phy.c revision 203c4805e91786f9a010bc7945a0fde70c9da28e
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#define _ATH5K_PHY 24 25#include <linux/delay.h> 26 27#include "ath5k.h" 28#include "reg.h" 29#include "base.h" 30#include "rfbuffer.h" 31#include "rfgain.h" 32 33/* 34 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 35 */ 36static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 37 const struct ath5k_rf_reg *rf_regs, 38 u32 val, u8 reg_id, bool set) 39{ 40 const struct ath5k_rf_reg *rfreg = NULL; 41 u8 offset, bank, num_bits, col, position; 42 u16 entry; 43 u32 mask, data, last_bit, bits_shifted, first_bit; 44 u32 *rfb; 45 s32 bits_left; 46 int i; 47 48 data = 0; 49 rfb = ah->ah_rf_banks; 50 51 for (i = 0; i < ah->ah_rf_regs_count; i++) { 52 if (rf_regs[i].index == reg_id) { 53 rfreg = &rf_regs[i]; 54 break; 55 } 56 } 57 58 if (rfb == NULL || rfreg == NULL) { 59 ATH5K_PRINTF("Rf register not found!\n"); 60 /* should not happen */ 61 return 0; 62 } 63 64 bank = rfreg->bank; 65 num_bits = rfreg->field.len; 66 first_bit = rfreg->field.pos; 67 col = rfreg->field.col; 68 69 /* first_bit is an offset from bank's 70 * start. Since we have all banks on 71 * the same array, we use this offset 72 * to mark each bank's start */ 73 offset = ah->ah_offset[bank]; 74 75 /* Boundary check */ 76 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 77 ATH5K_PRINTF("invalid values at offset %u\n", offset); 78 return 0; 79 } 80 81 entry = ((first_bit - 1) / 8) + offset; 82 position = (first_bit - 1) % 8; 83 84 if (set) 85 data = ath5k_hw_bitswap(val, num_bits); 86 87 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 88 position = 0, entry++) { 89 90 last_bit = (position + bits_left > 8) ? 8 : 91 position + bits_left; 92 93 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 94 (col * 8); 95 96 if (set) { 97 rfb[entry] &= ~mask; 98 rfb[entry] |= ((data << position) << (col * 8)) & mask; 99 data >>= (8 - position); 100 } else { 101 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 102 << bits_shifted; 103 bits_shifted += last_bit - position; 104 } 105 106 bits_left -= 8 - position; 107 } 108 109 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 110 111 return data; 112} 113 114/**********************\ 115* RF Gain optimization * 116\**********************/ 117 118/* 119 * This code is used to optimize rf gain on different environments 120 * (temprature mostly) based on feedback from a power detector. 121 * 122 * It's only used on RF5111 and RF5112, later RF chips seem to have 123 * auto adjustment on hw -notice they have a much smaller BANK 7 and 124 * no gain optimization ladder-. 125 * 126 * For more infos check out this patent doc 127 * http://www.freepatentsonline.com/7400691.html 128 * 129 * This paper describes power drops as seen on the receiver due to 130 * probe packets 131 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 132 * %20of%20Power%20Control.pdf 133 * 134 * And this is the MadWiFi bug entry related to the above 135 * http://madwifi-project.org/ticket/1659 136 * with various measurements and diagrams 137 * 138 * TODO: Deal with power drops due to probes by setting an apropriate 139 * tx power on the probe packets ! Make this part of the calibration process. 140 */ 141 142/* Initialize ah_gain durring attach */ 143int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 144{ 145 /* Initialize the gain optimization values */ 146 switch (ah->ah_radio) { 147 case AR5K_RF5111: 148 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 149 ah->ah_gain.g_low = 20; 150 ah->ah_gain.g_high = 35; 151 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 152 break; 153 case AR5K_RF5112: 154 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 155 ah->ah_gain.g_low = 20; 156 ah->ah_gain.g_high = 85; 157 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 return 0; 164} 165 166/* Schedule a gain probe check on the next transmited packet. 167 * That means our next packet is going to be sent with lower 168 * tx power and a Peak to Average Power Detector (PAPD) will try 169 * to measure the gain. 170 * 171 * TODO: Use propper tx power setting for the probe packet so 172 * that we don't observe a serious power drop on the receiver 173 * 174 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 175 * just after we enable the probe so that we don't mess with 176 * standard traffic ? Maybe it's time to use sw interrupts and 177 * a probe tasklet !!! 178 */ 179static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 180{ 181 182 /* Skip if gain calibration is inactive or 183 * we already handle a probe request */ 184 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 185 return; 186 187 /* Send the packet with 2dB below max power as 188 * patent doc suggest */ 189 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4, 190 AR5K_PHY_PAPD_PROBE_TXPOWER) | 191 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 192 193 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 194 195} 196 197/* Calculate gain_F measurement correction 198 * based on the current step for RF5112 rev. 2 */ 199static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 200{ 201 u32 mix, step; 202 u32 *rf; 203 const struct ath5k_gain_opt *go; 204 const struct ath5k_gain_opt_step *g_step; 205 const struct ath5k_rf_reg *rf_regs; 206 207 /* Only RF5112 Rev. 2 supports it */ 208 if ((ah->ah_radio != AR5K_RF5112) || 209 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 210 return 0; 211 212 go = &rfgain_opt_5112; 213 rf_regs = rf_regs_5112a; 214 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 215 216 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 217 218 if (ah->ah_rf_banks == NULL) 219 return 0; 220 221 rf = ah->ah_rf_banks; 222 ah->ah_gain.g_f_corr = 0; 223 224 /* No VGA (Variable Gain Amplifier) override, skip */ 225 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 226 return 0; 227 228 /* Mix gain stepping */ 229 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 230 231 /* Mix gain override */ 232 mix = g_step->gos_param[0]; 233 234 switch (mix) { 235 case 3: 236 ah->ah_gain.g_f_corr = step * 2; 237 break; 238 case 2: 239 ah->ah_gain.g_f_corr = (step - 5) * 2; 240 break; 241 case 1: 242 ah->ah_gain.g_f_corr = step; 243 break; 244 default: 245 ah->ah_gain.g_f_corr = 0; 246 break; 247 } 248 249 return ah->ah_gain.g_f_corr; 250} 251 252/* Check if current gain_F measurement is in the range of our 253 * power detector windows. If we get a measurement outside range 254 * we know it's not accurate (detectors can't measure anything outside 255 * their detection window) so we must ignore it */ 256static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 257{ 258 const struct ath5k_rf_reg *rf_regs; 259 u32 step, mix_ovr, level[4]; 260 u32 *rf; 261 262 if (ah->ah_rf_banks == NULL) 263 return false; 264 265 rf = ah->ah_rf_banks; 266 267 if (ah->ah_radio == AR5K_RF5111) { 268 269 rf_regs = rf_regs_5111; 270 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 271 272 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 273 false); 274 275 level[0] = 0; 276 level[1] = (step == 63) ? 50 : step + 4; 277 level[2] = (step != 63) ? 64 : level[0]; 278 level[3] = level[2] + 50 ; 279 280 ah->ah_gain.g_high = level[3] - 281 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 282 ah->ah_gain.g_low = level[0] + 283 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 284 } else { 285 286 rf_regs = rf_regs_5112; 287 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 288 289 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 290 false); 291 292 level[0] = level[2] = 0; 293 294 if (mix_ovr == 1) { 295 level[1] = level[3] = 83; 296 } else { 297 level[1] = level[3] = 107; 298 ah->ah_gain.g_high = 55; 299 } 300 } 301 302 return (ah->ah_gain.g_current >= level[0] && 303 ah->ah_gain.g_current <= level[1]) || 304 (ah->ah_gain.g_current >= level[2] && 305 ah->ah_gain.g_current <= level[3]); 306} 307 308/* Perform gain_F adjustment by choosing the right set 309 * of parameters from rf gain optimization ladder */ 310static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 311{ 312 const struct ath5k_gain_opt *go; 313 const struct ath5k_gain_opt_step *g_step; 314 int ret = 0; 315 316 switch (ah->ah_radio) { 317 case AR5K_RF5111: 318 go = &rfgain_opt_5111; 319 break; 320 case AR5K_RF5112: 321 go = &rfgain_opt_5112; 322 break; 323 default: 324 return 0; 325 } 326 327 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 328 329 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 330 331 /* Reached maximum */ 332 if (ah->ah_gain.g_step_idx == 0) 333 return -1; 334 335 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 336 ah->ah_gain.g_target >= ah->ah_gain.g_high && 337 ah->ah_gain.g_step_idx > 0; 338 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 339 ah->ah_gain.g_target -= 2 * 340 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 341 g_step->gos_gain); 342 343 ret = 1; 344 goto done; 345 } 346 347 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 348 349 /* Reached minimum */ 350 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 351 return -2; 352 353 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 354 ah->ah_gain.g_target <= ah->ah_gain.g_low && 355 ah->ah_gain.g_step_idx < go->go_steps_count-1; 356 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 357 ah->ah_gain.g_target -= 2 * 358 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 359 g_step->gos_gain); 360 361 ret = 2; 362 goto done; 363 } 364 365done: 366 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 367 "ret %d, gain step %u, current gain %u, target gain %u\n", 368 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 369 ah->ah_gain.g_target); 370 371 return ret; 372} 373 374/* Main callback for thermal rf gain calibration engine 375 * Check for a new gain reading and schedule an adjustment 376 * if needed. 377 * 378 * TODO: Use sw interrupt to schedule reset if gain_F needs 379 * adjustment */ 380enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 381{ 382 u32 data, type; 383 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 384 385 ATH5K_TRACE(ah->ah_sc); 386 387 if (ah->ah_rf_banks == NULL || 388 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 389 return AR5K_RFGAIN_INACTIVE; 390 391 /* No check requested, either engine is inactive 392 * or an adjustment is already requested */ 393 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 394 goto done; 395 396 /* Read the PAPD (Peak to Average Power Detector) 397 * register */ 398 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 399 400 /* No probe is scheduled, read gain_F measurement */ 401 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 402 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 403 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 404 405 /* If tx packet is CCK correct the gain_F measurement 406 * by cck ofdm gain delta */ 407 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 408 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 409 ah->ah_gain.g_current += 410 ee->ee_cck_ofdm_gain_delta; 411 else 412 ah->ah_gain.g_current += 413 AR5K_GAIN_CCK_PROBE_CORR; 414 } 415 416 /* Further correct gain_F measurement for 417 * RF5112A radios */ 418 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 419 ath5k_hw_rf_gainf_corr(ah); 420 ah->ah_gain.g_current = 421 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 422 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 423 0; 424 } 425 426 /* Check if measurement is ok and if we need 427 * to adjust gain, schedule a gain adjustment, 428 * else switch back to the acive state */ 429 if (ath5k_hw_rf_check_gainf_readback(ah) && 430 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 431 ath5k_hw_rf_gainf_adjust(ah)) { 432 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 433 } else { 434 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 435 } 436 } 437 438done: 439 return ah->ah_gain.g_state; 440} 441 442/* Write initial rf gain table to set the RF sensitivity 443 * this one works on all RF chips and has nothing to do 444 * with gain_F calibration */ 445int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 446{ 447 const struct ath5k_ini_rfgain *ath5k_rfg; 448 unsigned int i, size; 449 450 switch (ah->ah_radio) { 451 case AR5K_RF5111: 452 ath5k_rfg = rfgain_5111; 453 size = ARRAY_SIZE(rfgain_5111); 454 break; 455 case AR5K_RF5112: 456 ath5k_rfg = rfgain_5112; 457 size = ARRAY_SIZE(rfgain_5112); 458 break; 459 case AR5K_RF2413: 460 ath5k_rfg = rfgain_2413; 461 size = ARRAY_SIZE(rfgain_2413); 462 break; 463 case AR5K_RF2316: 464 ath5k_rfg = rfgain_2316; 465 size = ARRAY_SIZE(rfgain_2316); 466 break; 467 case AR5K_RF5413: 468 ath5k_rfg = rfgain_5413; 469 size = ARRAY_SIZE(rfgain_5413); 470 break; 471 case AR5K_RF2317: 472 case AR5K_RF2425: 473 ath5k_rfg = rfgain_2425; 474 size = ARRAY_SIZE(rfgain_2425); 475 break; 476 default: 477 return -EINVAL; 478 } 479 480 switch (freq) { 481 case AR5K_INI_RFGAIN_2GHZ: 482 case AR5K_INI_RFGAIN_5GHZ: 483 break; 484 default: 485 return -EINVAL; 486 } 487 488 for (i = 0; i < size; i++) { 489 AR5K_REG_WAIT(i); 490 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 491 (u32)ath5k_rfg[i].rfg_register); 492 } 493 494 return 0; 495} 496 497 498 499/********************\ 500* RF Registers setup * 501\********************/ 502 503 504/* 505 * Setup RF registers by writing rf buffer on hw 506 */ 507int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 508 unsigned int mode) 509{ 510 const struct ath5k_rf_reg *rf_regs; 511 const struct ath5k_ini_rfbuffer *ini_rfb; 512 const struct ath5k_gain_opt *go = NULL; 513 const struct ath5k_gain_opt_step *g_step; 514 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 515 u8 ee_mode = 0; 516 u32 *rfb; 517 int i, obdb = -1, bank = -1; 518 519 switch (ah->ah_radio) { 520 case AR5K_RF5111: 521 rf_regs = rf_regs_5111; 522 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 523 ini_rfb = rfb_5111; 524 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 525 go = &rfgain_opt_5111; 526 break; 527 case AR5K_RF5112: 528 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 529 rf_regs = rf_regs_5112a; 530 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 531 ini_rfb = rfb_5112a; 532 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 533 } else { 534 rf_regs = rf_regs_5112; 535 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 536 ini_rfb = rfb_5112; 537 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 538 } 539 go = &rfgain_opt_5112; 540 break; 541 case AR5K_RF2413: 542 rf_regs = rf_regs_2413; 543 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 544 ini_rfb = rfb_2413; 545 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 546 break; 547 case AR5K_RF2316: 548 rf_regs = rf_regs_2316; 549 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 550 ini_rfb = rfb_2316; 551 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 552 break; 553 case AR5K_RF5413: 554 rf_regs = rf_regs_5413; 555 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 556 ini_rfb = rfb_5413; 557 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 558 break; 559 case AR5K_RF2317: 560 rf_regs = rf_regs_2425; 561 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 562 ini_rfb = rfb_2317; 563 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 564 break; 565 case AR5K_RF2425: 566 rf_regs = rf_regs_2425; 567 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 568 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 569 ini_rfb = rfb_2425; 570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 571 } else { 572 ini_rfb = rfb_2417; 573 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 574 } 575 break; 576 default: 577 return -EINVAL; 578 } 579 580 /* If it's the first time we set rf buffer, allocate 581 * ah->ah_rf_banks based on ah->ah_rf_banks_size 582 * we set above */ 583 if (ah->ah_rf_banks == NULL) { 584 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 585 GFP_KERNEL); 586 if (ah->ah_rf_banks == NULL) { 587 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 588 return -ENOMEM; 589 } 590 } 591 592 /* Copy values to modify them */ 593 rfb = ah->ah_rf_banks; 594 595 for (i = 0; i < ah->ah_rf_banks_size; i++) { 596 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 597 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 598 return -EINVAL; 599 } 600 601 /* Bank changed, write down the offset */ 602 if (bank != ini_rfb[i].rfb_bank) { 603 bank = ini_rfb[i].rfb_bank; 604 ah->ah_offset[bank] = i; 605 } 606 607 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 608 } 609 610 /* Set Output and Driver bias current (OB/DB) */ 611 if (channel->hw_value & CHANNEL_2GHZ) { 612 613 if (channel->hw_value & CHANNEL_CCK) 614 ee_mode = AR5K_EEPROM_MODE_11B; 615 else 616 ee_mode = AR5K_EEPROM_MODE_11G; 617 618 /* For RF511X/RF211X combination we 619 * use b_OB and b_DB parameters stored 620 * in eeprom on ee->ee_ob[ee_mode][0] 621 * 622 * For all other chips we use OB/DB for 2Ghz 623 * stored in the b/g modal section just like 624 * 802.11a on ee->ee_ob[ee_mode][1] */ 625 if ((ah->ah_radio == AR5K_RF5111) || 626 (ah->ah_radio == AR5K_RF5112)) 627 obdb = 0; 628 else 629 obdb = 1; 630 631 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 632 AR5K_RF_OB_2GHZ, true); 633 634 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 635 AR5K_RF_DB_2GHZ, true); 636 637 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 638 } else if ((channel->hw_value & CHANNEL_5GHZ) || 639 (ah->ah_radio == AR5K_RF5111)) { 640 641 /* For 11a, Turbo and XR we need to choose 642 * OB/DB based on frequency range */ 643 ee_mode = AR5K_EEPROM_MODE_11A; 644 obdb = channel->center_freq >= 5725 ? 3 : 645 (channel->center_freq >= 5500 ? 2 : 646 (channel->center_freq >= 5260 ? 1 : 647 (channel->center_freq > 4000 ? 0 : -1))); 648 649 if (obdb < 0) 650 return -EINVAL; 651 652 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 653 AR5K_RF_OB_5GHZ, true); 654 655 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 656 AR5K_RF_DB_5GHZ, true); 657 } 658 659 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 660 661 /* Bank Modifications (chip-specific) */ 662 if (ah->ah_radio == AR5K_RF5111) { 663 664 /* Set gain_F settings according to current step */ 665 if (channel->hw_value & CHANNEL_OFDM) { 666 667 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 668 AR5K_PHY_FRAME_CTL_TX_CLIP, 669 g_step->gos_param[0]); 670 671 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 672 AR5K_RF_PWD_90, true); 673 674 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 675 AR5K_RF_PWD_84, true); 676 677 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 678 AR5K_RF_RFGAIN_SEL, true); 679 680 /* We programmed gain_F parameters, switch back 681 * to active state */ 682 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 683 684 } 685 686 /* Bank 6/7 setup */ 687 688 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 689 AR5K_RF_PWD_XPD, true); 690 691 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 692 AR5K_RF_XPD_GAIN, true); 693 694 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 695 AR5K_RF_GAIN_I, true); 696 697 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 698 AR5K_RF_PLO_SEL, true); 699 700 /* TODO: Half/quarter channel support */ 701 } 702 703 if (ah->ah_radio == AR5K_RF5112) { 704 705 /* Set gain_F settings according to current step */ 706 if (channel->hw_value & CHANNEL_OFDM) { 707 708 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 709 AR5K_RF_MIXGAIN_OVR, true); 710 711 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 712 AR5K_RF_PWD_138, true); 713 714 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 715 AR5K_RF_PWD_137, true); 716 717 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 718 AR5K_RF_PWD_136, true); 719 720 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 721 AR5K_RF_PWD_132, true); 722 723 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 724 AR5K_RF_PWD_131, true); 725 726 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 727 AR5K_RF_PWD_130, true); 728 729 /* We programmed gain_F parameters, switch back 730 * to active state */ 731 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 732 } 733 734 /* Bank 6/7 setup */ 735 736 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 737 AR5K_RF_XPD_SEL, true); 738 739 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 740 /* Rev. 1 supports only one xpd */ 741 ath5k_hw_rfb_op(ah, rf_regs, 742 ee->ee_x_gain[ee_mode], 743 AR5K_RF_XPD_GAIN, true); 744 745 } else { 746 /* TODO: Set high and low gain bits */ 747 ath5k_hw_rfb_op(ah, rf_regs, 748 ee->ee_x_gain[ee_mode], 749 AR5K_RF_PD_GAIN_LO, true); 750 ath5k_hw_rfb_op(ah, rf_regs, 751 ee->ee_x_gain[ee_mode], 752 AR5K_RF_PD_GAIN_HI, true); 753 754 /* Lower synth voltage on Rev 2 */ 755 ath5k_hw_rfb_op(ah, rf_regs, 2, 756 AR5K_RF_HIGH_VC_CP, true); 757 758 ath5k_hw_rfb_op(ah, rf_regs, 2, 759 AR5K_RF_MID_VC_CP, true); 760 761 ath5k_hw_rfb_op(ah, rf_regs, 2, 762 AR5K_RF_LOW_VC_CP, true); 763 764 ath5k_hw_rfb_op(ah, rf_regs, 2, 765 AR5K_RF_PUSH_UP, true); 766 767 /* Decrease power consumption on 5213+ BaseBand */ 768 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 769 ath5k_hw_rfb_op(ah, rf_regs, 1, 770 AR5K_RF_PAD2GND, true); 771 772 ath5k_hw_rfb_op(ah, rf_regs, 1, 773 AR5K_RF_XB2_LVL, true); 774 775 ath5k_hw_rfb_op(ah, rf_regs, 1, 776 AR5K_RF_XB5_LVL, true); 777 778 ath5k_hw_rfb_op(ah, rf_regs, 1, 779 AR5K_RF_PWD_167, true); 780 781 ath5k_hw_rfb_op(ah, rf_regs, 1, 782 AR5K_RF_PWD_166, true); 783 } 784 } 785 786 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 787 AR5K_RF_GAIN_I, true); 788 789 /* TODO: Half/quarter channel support */ 790 791 } 792 793 if (ah->ah_radio == AR5K_RF5413 && 794 channel->hw_value & CHANNEL_2GHZ) { 795 796 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 797 true); 798 799 /* Set optimum value for early revisions (on pci-e chips) */ 800 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 801 ah->ah_mac_srev < AR5K_SREV_AR5413) 802 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 803 AR5K_RF_PWD_ICLOBUF_2G, true); 804 805 } 806 807 /* Write RF banks on hw */ 808 for (i = 0; i < ah->ah_rf_banks_size; i++) { 809 AR5K_REG_WAIT(i); 810 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 811 } 812 813 return 0; 814} 815 816 817/**************************\ 818 PHY/RF channel functions 819\**************************/ 820 821/* 822 * Check if a channel is supported 823 */ 824bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 825{ 826 /* Check if the channel is in our supported range */ 827 if (flags & CHANNEL_2GHZ) { 828 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 829 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 830 return true; 831 } else if (flags & CHANNEL_5GHZ) 832 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 833 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 834 return true; 835 836 return false; 837} 838 839/* 840 * Convertion needed for RF5110 841 */ 842static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 843{ 844 u32 athchan; 845 846 /* 847 * Convert IEEE channel/MHz to an internal channel value used 848 * by the AR5210 chipset. This has not been verified with 849 * newer chipsets like the AR5212A who have a completely 850 * different RF/PHY part. 851 */ 852 athchan = (ath5k_hw_bitswap( 853 (ieee80211_frequency_to_channel( 854 channel->center_freq) - 24) / 2, 5) 855 << 1) | (1 << 6) | 0x1; 856 return athchan; 857} 858 859/* 860 * Set channel on RF5110 861 */ 862static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 863 struct ieee80211_channel *channel) 864{ 865 u32 data; 866 867 /* 868 * Set the channel and wait 869 */ 870 data = ath5k_hw_rf5110_chan2athchan(channel); 871 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 872 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 873 mdelay(1); 874 875 return 0; 876} 877 878/* 879 * Convertion needed for 5111 880 */ 881static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 882 struct ath5k_athchan_2ghz *athchan) 883{ 884 int channel; 885 886 /* Cast this value to catch negative channel numbers (>= -19) */ 887 channel = (int)ieee; 888 889 /* 890 * Map 2GHz IEEE channel to 5GHz Atheros channel 891 */ 892 if (channel <= 13) { 893 athchan->a2_athchan = 115 + channel; 894 athchan->a2_flags = 0x46; 895 } else if (channel == 14) { 896 athchan->a2_athchan = 124; 897 athchan->a2_flags = 0x44; 898 } else if (channel >= 15 && channel <= 26) { 899 athchan->a2_athchan = ((channel - 14) * 4) + 132; 900 athchan->a2_flags = 0x46; 901 } else 902 return -EINVAL; 903 904 return 0; 905} 906 907/* 908 * Set channel on 5111 909 */ 910static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 911 struct ieee80211_channel *channel) 912{ 913 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 914 unsigned int ath5k_channel = 915 ieee80211_frequency_to_channel(channel->center_freq); 916 u32 data0, data1, clock; 917 int ret; 918 919 /* 920 * Set the channel on the RF5111 radio 921 */ 922 data0 = data1 = 0; 923 924 if (channel->hw_value & CHANNEL_2GHZ) { 925 /* Map 2GHz channel to 5GHz Atheros channel ID */ 926 ret = ath5k_hw_rf5111_chan2athchan( 927 ieee80211_frequency_to_channel(channel->center_freq), 928 &ath5k_channel_2ghz); 929 if (ret) 930 return ret; 931 932 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 933 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 934 << 5) | (1 << 4); 935 } 936 937 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 938 clock = 1; 939 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 940 (clock << 1) | (1 << 10) | 1; 941 } else { 942 clock = 0; 943 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 944 << 2) | (clock << 1) | (1 << 10) | 1; 945 } 946 947 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 948 AR5K_RF_BUFFER); 949 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 950 AR5K_RF_BUFFER_CONTROL_3); 951 952 return 0; 953} 954 955/* 956 * Set channel on 5112 and newer 957 */ 958static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 959 struct ieee80211_channel *channel) 960{ 961 u32 data, data0, data1, data2; 962 u16 c; 963 964 data = data0 = data1 = data2 = 0; 965 c = channel->center_freq; 966 967 if (c < 4800) { 968 if (!((c - 2224) % 5)) { 969 data0 = ((2 * (c - 704)) - 3040) / 10; 970 data1 = 1; 971 } else if (!((c - 2192) % 5)) { 972 data0 = ((2 * (c - 672)) - 3040) / 10; 973 data1 = 0; 974 } else 975 return -EINVAL; 976 977 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 978 } else if ((c - (c % 5)) != 2 || c > 5435) { 979 if (!(c % 20) && c >= 5120) { 980 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 981 data2 = ath5k_hw_bitswap(3, 2); 982 } else if (!(c % 10)) { 983 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 984 data2 = ath5k_hw_bitswap(2, 2); 985 } else if (!(c % 5)) { 986 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 987 data2 = ath5k_hw_bitswap(1, 2); 988 } else 989 return -EINVAL; 990 } else { 991 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 992 data2 = ath5k_hw_bitswap(0, 2); 993 } 994 995 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 996 997 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 998 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 999 1000 return 0; 1001} 1002 1003/* 1004 * Set the channel on the RF2425 1005 */ 1006static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1007 struct ieee80211_channel *channel) 1008{ 1009 u32 data, data0, data2; 1010 u16 c; 1011 1012 data = data0 = data2 = 0; 1013 c = channel->center_freq; 1014 1015 if (c < 4800) { 1016 data0 = ath5k_hw_bitswap((c - 2272), 8); 1017 data2 = 0; 1018 /* ? 5GHz ? */ 1019 } else if ((c - (c % 5)) != 2 || c > 5435) { 1020 if (!(c % 20) && c < 5120) 1021 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1022 else if (!(c % 10)) 1023 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1024 else if (!(c % 5)) 1025 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1026 else 1027 return -EINVAL; 1028 data2 = ath5k_hw_bitswap(1, 2); 1029 } else { 1030 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 1031 data2 = ath5k_hw_bitswap(0, 2); 1032 } 1033 1034 data = (data0 << 4) | data2 << 2 | 0x1001; 1035 1036 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1037 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1038 1039 return 0; 1040} 1041 1042/* 1043 * Set a channel on the radio chip 1044 */ 1045int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) 1046{ 1047 int ret; 1048 /* 1049 * Check bounds supported by the PHY (we don't care about regultory 1050 * restrictions at this point). Note: hw_value already has the band 1051 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1052 * of the band by that */ 1053 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1054 ATH5K_ERR(ah->ah_sc, 1055 "channel frequency (%u MHz) out of supported " 1056 "band range\n", 1057 channel->center_freq); 1058 return -EINVAL; 1059 } 1060 1061 /* 1062 * Set the channel and wait 1063 */ 1064 switch (ah->ah_radio) { 1065 case AR5K_RF5110: 1066 ret = ath5k_hw_rf5110_channel(ah, channel); 1067 break; 1068 case AR5K_RF5111: 1069 ret = ath5k_hw_rf5111_channel(ah, channel); 1070 break; 1071 case AR5K_RF2425: 1072 ret = ath5k_hw_rf2425_channel(ah, channel); 1073 break; 1074 default: 1075 ret = ath5k_hw_rf5112_channel(ah, channel); 1076 break; 1077 } 1078 1079 if (ret) 1080 return ret; 1081 1082 /* Set JAPAN setting for channel 14 */ 1083 if (channel->center_freq == 2484) { 1084 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1085 AR5K_PHY_CCKTXCTL_JAPAN); 1086 } else { 1087 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1088 AR5K_PHY_CCKTXCTL_WORLD); 1089 } 1090 1091 ah->ah_current_channel.center_freq = channel->center_freq; 1092 ah->ah_current_channel.hw_value = channel->hw_value; 1093 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; 1094 1095 return 0; 1096} 1097 1098/*****************\ 1099 PHY calibration 1100\*****************/ 1101 1102/** 1103 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration 1104 * 1105 * @ah: struct ath5k_hw pointer we are operating on 1106 * @freq: the channel frequency, just used for error logging 1107 * 1108 * This function performs a noise floor calibration of the PHY and waits for 1109 * it to complete. Then the noise floor value is compared to some maximum 1110 * noise floor we consider valid. 1111 * 1112 * Note that this is different from what the madwifi HAL does: it reads the 1113 * noise floor and afterwards initiates the calibration. Since the noise floor 1114 * calibration can take some time to finish, depending on the current channel 1115 * use, that avoids the occasional timeout warnings we are seeing now. 1116 * 1117 * See the following link for an Atheros patent on noise floor calibration: 1118 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ 1119 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 1120 * 1121 * XXX: Since during noise floor calibration antennas are detached according to 1122 * the patent, we should stop tx queues here. 1123 */ 1124int 1125ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) 1126{ 1127 int ret; 1128 unsigned int i; 1129 s32 noise_floor; 1130 1131 /* 1132 * Enable noise floor calibration 1133 */ 1134 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1135 AR5K_PHY_AGCCTL_NF); 1136 1137 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1138 AR5K_PHY_AGCCTL_NF, 0, false); 1139 if (ret) { 1140 ATH5K_ERR(ah->ah_sc, 1141 "noise floor calibration timeout (%uMHz)\n", freq); 1142 return -EAGAIN; 1143 } 1144 1145 /* Wait until the noise floor is calibrated and read the value */ 1146 for (i = 20; i > 0; i--) { 1147 mdelay(1); 1148 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1149 noise_floor = AR5K_PHY_NF_RVAL(noise_floor); 1150 if (noise_floor & AR5K_PHY_NF_ACTIVE) { 1151 noise_floor = AR5K_PHY_NF_AVAL(noise_floor); 1152 1153 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) 1154 break; 1155 } 1156 } 1157 1158 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1159 "noise floor %d\n", noise_floor); 1160 1161 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { 1162 ATH5K_ERR(ah->ah_sc, 1163 "noise floor calibration failed (%uMHz)\n", freq); 1164 return -EAGAIN; 1165 } 1166 1167 ah->ah_noise_floor = noise_floor; 1168 1169 return 0; 1170} 1171 1172/* 1173 * Perform a PHY calibration on RF5110 1174 * -Fix BPSK/QAM Constellation (I/Q correction) 1175 * -Calculate Noise Floor 1176 */ 1177static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1178 struct ieee80211_channel *channel) 1179{ 1180 u32 phy_sig, phy_agc, phy_sat, beacon; 1181 int ret; 1182 1183 /* 1184 * Disable beacons and RX/TX queues, wait 1185 */ 1186 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1187 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1188 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1189 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1190 1191 mdelay(2); 1192 1193 /* 1194 * Set the channel (with AGC turned off) 1195 */ 1196 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1197 udelay(10); 1198 ret = ath5k_hw_channel(ah, channel); 1199 1200 /* 1201 * Activate PHY and wait 1202 */ 1203 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1204 mdelay(1); 1205 1206 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1207 1208 if (ret) 1209 return ret; 1210 1211 /* 1212 * Calibrate the radio chip 1213 */ 1214 1215 /* Remember normal state */ 1216 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1217 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1218 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1219 1220 /* Update radio registers */ 1221 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1222 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1223 1224 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1225 AR5K_PHY_AGCCOARSE_LO)) | 1226 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1227 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1228 1229 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1230 AR5K_PHY_ADCSAT_THR)) | 1231 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1232 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1233 1234 udelay(20); 1235 1236 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1237 udelay(10); 1238 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1239 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1240 1241 mdelay(1); 1242 1243 /* 1244 * Enable calibration and wait until completion 1245 */ 1246 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1247 1248 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1249 AR5K_PHY_AGCCTL_CAL, 0, false); 1250 1251 /* Reset to normal state */ 1252 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1253 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1254 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1255 1256 if (ret) { 1257 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1258 channel->center_freq); 1259 return ret; 1260 } 1261 1262 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1263 1264 /* 1265 * Re-enable RX/TX and beacons 1266 */ 1267 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1268 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1269 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1270 1271 return 0; 1272} 1273 1274/* 1275 * Perform a PHY calibration on RF5111/5112 and newer chips 1276 */ 1277static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, 1278 struct ieee80211_channel *channel) 1279{ 1280 u32 i_pwr, q_pwr; 1281 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1282 int i; 1283 ATH5K_TRACE(ah->ah_sc); 1284 1285 if (!ah->ah_calibration || 1286 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1287 goto done; 1288 1289 /* Calibration has finished, get the results and re-run */ 1290 for (i = 0; i <= 10; i++) { 1291 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1292 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1293 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1294 } 1295 1296 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1297 q_coffd = q_pwr >> 7; 1298 1299 /* No correction */ 1300 if (i_coffd == 0 || q_coffd == 0) 1301 goto done; 1302 1303 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 1304 1305 /* Boundary check */ 1306 if (i_coff > 31) 1307 i_coff = 31; 1308 if (i_coff < -32) 1309 i_coff = -32; 1310 1311 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; 1312 1313 /* Boundary check */ 1314 if (q_coff > 15) 1315 q_coff = 15; 1316 if (q_coff < -16) 1317 q_coff = -16; 1318 1319 /* Commit new I/Q value */ 1320 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | 1321 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); 1322 1323 /* Re-enable calibration -if we don't we'll commit 1324 * the same values again and again */ 1325 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1326 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1327 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1328 1329done: 1330 1331 /* TODO: Separate noise floor calibration from I/Q calibration 1332 * since noise floor calibration interrupts rx path while I/Q 1333 * calibration doesn't. We don't need to run noise floor calibration 1334 * as often as I/Q calibration.*/ 1335 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1336 1337 /* Initiate a gain_F calibration */ 1338 ath5k_hw_request_rfgain_probe(ah); 1339 1340 return 0; 1341} 1342 1343/* 1344 * Perform a PHY calibration 1345 */ 1346int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1347 struct ieee80211_channel *channel) 1348{ 1349 int ret; 1350 1351 if (ah->ah_radio == AR5K_RF5110) 1352 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1353 else 1354 ret = ath5k_hw_rf511x_calibrate(ah, channel); 1355 1356 return ret; 1357} 1358 1359int ath5k_hw_phy_disable(struct ath5k_hw *ah) 1360{ 1361 ATH5K_TRACE(ah->ah_sc); 1362 /*Just a try M.F.*/ 1363 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1364 1365 return 0; 1366} 1367 1368/********************\ 1369 Misc PHY functions 1370\********************/ 1371 1372/* 1373 * Get the PHY Chip revision 1374 */ 1375u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 1376{ 1377 unsigned int i; 1378 u32 srev; 1379 u16 ret; 1380 1381 ATH5K_TRACE(ah->ah_sc); 1382 1383 /* 1384 * Set the radio chip access register 1385 */ 1386 switch (chan) { 1387 case CHANNEL_2GHZ: 1388 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 1389 break; 1390 case CHANNEL_5GHZ: 1391 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1392 break; 1393 default: 1394 return 0; 1395 } 1396 1397 mdelay(2); 1398 1399 /* ...wait until PHY is ready and read the selected radio revision */ 1400 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 1401 1402 for (i = 0; i < 8; i++) 1403 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 1404 1405 if (ah->ah_version == AR5K_AR5210) { 1406 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 1407 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 1408 } else { 1409 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 1410 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 1411 ((srev & 0x0f) << 4), 8); 1412 } 1413 1414 /* Reset to the 5GHz mode */ 1415 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1416 1417 return ret; 1418} 1419 1420void /*TODO:Boundary check*/ 1421ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant) 1422{ 1423 ATH5K_TRACE(ah->ah_sc); 1424 /*Just a try M.F.*/ 1425 if (ah->ah_version != AR5K_AR5210) 1426 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA); 1427} 1428 1429unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) 1430{ 1431 ATH5K_TRACE(ah->ah_sc); 1432 /*Just a try M.F.*/ 1433 if (ah->ah_version != AR5K_AR5210) 1434 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 1435 1436 return false; /*XXX: What do we return for 5210 ?*/ 1437} 1438 1439 1440/****************\ 1441* TX power setup * 1442\****************/ 1443 1444/* 1445 * Helper functions 1446 */ 1447 1448/* 1449 * Do linear interpolation between two given (x, y) points 1450 */ 1451static s16 1452ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 1453 s16 y_left, s16 y_right) 1454{ 1455 s16 ratio, result; 1456 1457 /* Avoid divide by zero and skip interpolation 1458 * if we have the same point */ 1459 if ((x_left == x_right) || (y_left == y_right)) 1460 return y_left; 1461 1462 /* 1463 * Since we use ints and not fps, we need to scale up in 1464 * order to get a sane ratio value (or else we 'll eg. get 1465 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 1466 * to have some accuracy both for 0.5 and 0.25 steps. 1467 */ 1468 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 1469 1470 /* Now scale down to be in range */ 1471 result = y_left + (ratio * (target - x_left) / 100); 1472 1473 return result; 1474} 1475 1476/* 1477 * Find vertical boundary (min pwr) for the linear PCDAC curve. 1478 * 1479 * Since we have the top of the curve and we draw the line below 1480 * until we reach 1 (1 pcdac step) we need to know which point 1481 * (x value) that is so that we don't go below y axis and have negative 1482 * pcdac values when creating the curve, or fill the table with zeroes. 1483 */ 1484static s16 1485ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 1486 const s16 *pwrL, const s16 *pwrR) 1487{ 1488 s8 tmp; 1489 s16 min_pwrL, min_pwrR; 1490 s16 pwr_i = pwrL[0]; 1491 1492 do { 1493 pwr_i--; 1494 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1495 pwrL[0], pwrL[1], 1496 stepL[0], stepL[1]); 1497 1498 } while (tmp > 1); 1499 1500 min_pwrL = pwr_i; 1501 1502 pwr_i = pwrR[0]; 1503 do { 1504 pwr_i--; 1505 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1506 pwrR[0], pwrR[1], 1507 stepR[0], stepR[1]); 1508 1509 } while (tmp > 1); 1510 1511 min_pwrR = pwr_i; 1512 1513 /* Keep the right boundary so that it works for both curves */ 1514 return max(min_pwrL, min_pwrR); 1515} 1516 1517/* 1518 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 1519 * Power to PCDAC curve. 1520 * 1521 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 1522 * steps (offsets) on y axis. Power can go up to 31.5dB and max 1523 * PCDAC/PDADC step for each curve is 64 but we can write more than 1524 * one curves on hw so we can go up to 128 (which is the max step we 1525 * can write on the final table). 1526 * 1527 * We write y values (PCDAC/PDADC steps) on hw. 1528 */ 1529static void 1530ath5k_create_power_curve(s16 pmin, s16 pmax, 1531 const s16 *pwr, const u8 *vpd, 1532 u8 num_points, 1533 u8 *vpd_table, u8 type) 1534{ 1535 u8 idx[2] = { 0, 1 }; 1536 s16 pwr_i = 2*pmin; 1537 int i; 1538 1539 if (num_points < 2) 1540 return; 1541 1542 /* We want the whole line, so adjust boundaries 1543 * to cover the entire power range. Note that 1544 * power values are already 0.25dB so no need 1545 * to multiply pwr_i by 2 */ 1546 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 1547 pwr_i = pmin; 1548 pmin = 0; 1549 pmax = 63; 1550 } 1551 1552 /* Find surrounding turning points (TPs) 1553 * and interpolate between them */ 1554 for (i = 0; (i <= (u16) (pmax - pmin)) && 1555 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 1556 1557 /* We passed the right TP, move to the next set of TPs 1558 * if we pass the last TP, extrapolate above using the last 1559 * two TPs for ratio */ 1560 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 1561 idx[0]++; 1562 idx[1]++; 1563 } 1564 1565 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 1566 pwr[idx[0]], pwr[idx[1]], 1567 vpd[idx[0]], vpd[idx[1]]); 1568 1569 /* Increase by 0.5dB 1570 * (0.25 dB units) */ 1571 pwr_i += 2; 1572 } 1573} 1574 1575/* 1576 * Get the surrounding per-channel power calibration piers 1577 * for a given frequency so that we can interpolate between 1578 * them and come up with an apropriate dataset for our current 1579 * channel. 1580 */ 1581static void 1582ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 1583 struct ieee80211_channel *channel, 1584 struct ath5k_chan_pcal_info **pcinfo_l, 1585 struct ath5k_chan_pcal_info **pcinfo_r) 1586{ 1587 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1588 struct ath5k_chan_pcal_info *pcinfo; 1589 u8 idx_l, idx_r; 1590 u8 mode, max, i; 1591 u32 target = channel->center_freq; 1592 1593 idx_l = 0; 1594 idx_r = 0; 1595 1596 if (!(channel->hw_value & CHANNEL_OFDM)) { 1597 pcinfo = ee->ee_pwr_cal_b; 1598 mode = AR5K_EEPROM_MODE_11B; 1599 } else if (channel->hw_value & CHANNEL_2GHZ) { 1600 pcinfo = ee->ee_pwr_cal_g; 1601 mode = AR5K_EEPROM_MODE_11G; 1602 } else { 1603 pcinfo = ee->ee_pwr_cal_a; 1604 mode = AR5K_EEPROM_MODE_11A; 1605 } 1606 max = ee->ee_n_piers[mode] - 1; 1607 1608 /* Frequency is below our calibrated 1609 * range. Use the lowest power curve 1610 * we have */ 1611 if (target < pcinfo[0].freq) { 1612 idx_l = idx_r = 0; 1613 goto done; 1614 } 1615 1616 /* Frequency is above our calibrated 1617 * range. Use the highest power curve 1618 * we have */ 1619 if (target > pcinfo[max].freq) { 1620 idx_l = idx_r = max; 1621 goto done; 1622 } 1623 1624 /* Frequency is inside our calibrated 1625 * channel range. Pick the surrounding 1626 * calibration piers so that we can 1627 * interpolate */ 1628 for (i = 0; i <= max; i++) { 1629 1630 /* Frequency matches one of our calibration 1631 * piers, no need to interpolate, just use 1632 * that calibration pier */ 1633 if (pcinfo[i].freq == target) { 1634 idx_l = idx_r = i; 1635 goto done; 1636 } 1637 1638 /* We found a calibration pier that's above 1639 * frequency, use this pier and the previous 1640 * one to interpolate */ 1641 if (target < pcinfo[i].freq) { 1642 idx_r = i; 1643 idx_l = idx_r - 1; 1644 goto done; 1645 } 1646 } 1647 1648done: 1649 *pcinfo_l = &pcinfo[idx_l]; 1650 *pcinfo_r = &pcinfo[idx_r]; 1651 1652 return; 1653} 1654 1655/* 1656 * Get the surrounding per-rate power calibration data 1657 * for a given frequency and interpolate between power 1658 * values to set max target power supported by hw for 1659 * each rate. 1660 */ 1661static void 1662ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 1663 struct ieee80211_channel *channel, 1664 struct ath5k_rate_pcal_info *rates) 1665{ 1666 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1667 struct ath5k_rate_pcal_info *rpinfo; 1668 u8 idx_l, idx_r; 1669 u8 mode, max, i; 1670 u32 target = channel->center_freq; 1671 1672 idx_l = 0; 1673 idx_r = 0; 1674 1675 if (!(channel->hw_value & CHANNEL_OFDM)) { 1676 rpinfo = ee->ee_rate_tpwr_b; 1677 mode = AR5K_EEPROM_MODE_11B; 1678 } else if (channel->hw_value & CHANNEL_2GHZ) { 1679 rpinfo = ee->ee_rate_tpwr_g; 1680 mode = AR5K_EEPROM_MODE_11G; 1681 } else { 1682 rpinfo = ee->ee_rate_tpwr_a; 1683 mode = AR5K_EEPROM_MODE_11A; 1684 } 1685 max = ee->ee_rate_target_pwr_num[mode] - 1; 1686 1687 /* Get the surrounding calibration 1688 * piers - same as above */ 1689 if (target < rpinfo[0].freq) { 1690 idx_l = idx_r = 0; 1691 goto done; 1692 } 1693 1694 if (target > rpinfo[max].freq) { 1695 idx_l = idx_r = max; 1696 goto done; 1697 } 1698 1699 for (i = 0; i <= max; i++) { 1700 1701 if (rpinfo[i].freq == target) { 1702 idx_l = idx_r = i; 1703 goto done; 1704 } 1705 1706 if (target < rpinfo[i].freq) { 1707 idx_r = i; 1708 idx_l = idx_r - 1; 1709 goto done; 1710 } 1711 } 1712 1713done: 1714 /* Now interpolate power value, based on the frequency */ 1715 rates->freq = target; 1716 1717 rates->target_power_6to24 = 1718 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1719 rpinfo[idx_r].freq, 1720 rpinfo[idx_l].target_power_6to24, 1721 rpinfo[idx_r].target_power_6to24); 1722 1723 rates->target_power_36 = 1724 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1725 rpinfo[idx_r].freq, 1726 rpinfo[idx_l].target_power_36, 1727 rpinfo[idx_r].target_power_36); 1728 1729 rates->target_power_48 = 1730 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1731 rpinfo[idx_r].freq, 1732 rpinfo[idx_l].target_power_48, 1733 rpinfo[idx_r].target_power_48); 1734 1735 rates->target_power_54 = 1736 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1737 rpinfo[idx_r].freq, 1738 rpinfo[idx_l].target_power_54, 1739 rpinfo[idx_r].target_power_54); 1740} 1741 1742/* 1743 * Get the max edge power for this channel if 1744 * we have such data from EEPROM's Conformance Test 1745 * Limits (CTL), and limit max power if needed. 1746 * 1747 * FIXME: Only works for world regulatory domains 1748 */ 1749static void 1750ath5k_get_max_ctl_power(struct ath5k_hw *ah, 1751 struct ieee80211_channel *channel) 1752{ 1753 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1754 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 1755 u8 *ctl_val = ee->ee_ctl; 1756 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 1757 s16 edge_pwr = 0; 1758 u8 rep_idx; 1759 u8 i, ctl_mode; 1760 u8 ctl_idx = 0xFF; 1761 u32 target = channel->center_freq; 1762 1763 /* Find out a CTL for our mode that's not mapped 1764 * on a specific reg domain. 1765 * 1766 * TODO: Map our current reg domain to one of the 3 available 1767 * reg domain ids so that we can support more CTLs. */ 1768 switch (channel->hw_value & CHANNEL_MODES) { 1769 case CHANNEL_A: 1770 ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN; 1771 break; 1772 case CHANNEL_G: 1773 ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN; 1774 break; 1775 case CHANNEL_B: 1776 ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN; 1777 break; 1778 case CHANNEL_T: 1779 ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN; 1780 break; 1781 case CHANNEL_TG: 1782 ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN; 1783 break; 1784 case CHANNEL_XR: 1785 /* Fall through */ 1786 default: 1787 return; 1788 } 1789 1790 for (i = 0; i < ee->ee_ctls; i++) { 1791 if (ctl_val[i] == ctl_mode) { 1792 ctl_idx = i; 1793 break; 1794 } 1795 } 1796 1797 /* If we have a CTL dataset available grab it and find the 1798 * edge power for our frequency */ 1799 if (ctl_idx == 0xFF) 1800 return; 1801 1802 /* Edge powers are sorted by frequency from lower 1803 * to higher. Each CTL corresponds to 8 edge power 1804 * measurements. */ 1805 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 1806 1807 /* Don't do boundaries check because we 1808 * might have more that one bands defined 1809 * for this mode */ 1810 1811 /* Get the edge power that's closer to our 1812 * frequency */ 1813 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 1814 rep_idx += i; 1815 if (target <= rep[rep_idx].freq) 1816 edge_pwr = (s16) rep[rep_idx].edge; 1817 } 1818 1819 if (edge_pwr) 1820 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 1821} 1822 1823 1824/* 1825 * Power to PCDAC table functions 1826 */ 1827 1828/* 1829 * Fill Power to PCDAC table on RF5111 1830 * 1831 * No further processing is needed for RF5111, the only thing we have to 1832 * do is fill the values below and above calibration range since eeprom data 1833 * may not cover the entire PCDAC table. 1834 */ 1835static void 1836ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 1837 s16 *table_max) 1838{ 1839 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1840 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 1841 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 1842 s16 min_pwr, max_pwr; 1843 1844 /* Get table boundaries */ 1845 min_pwr = table_min[0]; 1846 pcdac_0 = pcdac_tmp[0]; 1847 1848 max_pwr = table_max[0]; 1849 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 1850 1851 /* Extrapolate below minimum using pcdac_0 */ 1852 pcdac_i = 0; 1853 for (i = 0; i < min_pwr; i++) 1854 pcdac_out[pcdac_i++] = pcdac_0; 1855 1856 /* Copy values from pcdac_tmp */ 1857 pwr_idx = min_pwr; 1858 for (i = 0 ; pwr_idx <= max_pwr && 1859 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 1860 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 1861 pwr_idx++; 1862 } 1863 1864 /* Extrapolate above maximum */ 1865 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 1866 pcdac_out[pcdac_i++] = pcdac_n; 1867 1868} 1869 1870/* 1871 * Combine available XPD Curves and fill Linear Power to PCDAC table 1872 * on RF5112 1873 * 1874 * RFX112 can have up to 2 curves (one for low txpower range and one for 1875 * higher txpower range). We need to put them both on pcdac_out and place 1876 * them in the correct location. In case we only have one curve available 1877 * just fit it on pcdac_out (it's supposed to cover the entire range of 1878 * available pwr levels since it's always the higher power curve). Extrapolate 1879 * below and above final table if needed. 1880 */ 1881static void 1882ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 1883 s16 *table_max, u8 pdcurves) 1884{ 1885 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1886 u8 *pcdac_low_pwr; 1887 u8 *pcdac_high_pwr; 1888 u8 *pcdac_tmp; 1889 u8 pwr; 1890 s16 max_pwr_idx; 1891 s16 min_pwr_idx; 1892 s16 mid_pwr_idx = 0; 1893 /* Edge flag turs on the 7nth bit on the PCDAC 1894 * to delcare the higher power curve (force values 1895 * to be greater than 64). If we only have one curve 1896 * we don't need to set this, if we have 2 curves and 1897 * fill the table backwards this can also be used to 1898 * switch from higher power curve to lower power curve */ 1899 u8 edge_flag; 1900 int i; 1901 1902 /* When we have only one curve available 1903 * that's the higher power curve. If we have 1904 * two curves the first is the high power curve 1905 * and the next is the low power curve. */ 1906 if (pdcurves > 1) { 1907 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 1908 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 1909 mid_pwr_idx = table_max[1] - table_min[1] - 1; 1910 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 1911 1912 /* If table size goes beyond 31.5dB, keep the 1913 * upper 31.5dB range when setting tx power. 1914 * Note: 126 = 31.5 dB in quarter dB steps */ 1915 if (table_max[0] - table_min[1] > 126) 1916 min_pwr_idx = table_max[0] - 126; 1917 else 1918 min_pwr_idx = table_min[1]; 1919 1920 /* Since we fill table backwards 1921 * start from high power curve */ 1922 pcdac_tmp = pcdac_high_pwr; 1923 1924 edge_flag = 0x40; 1925#if 0 1926 /* If both min and max power limits are in lower 1927 * power curve's range, only use the low power curve. 1928 * TODO: min/max levels are related to target 1929 * power values requested from driver/user 1930 * XXX: Is this really needed ? */ 1931 if (min_pwr < table_max[1] && 1932 max_pwr < table_max[1]) { 1933 edge_flag = 0; 1934 pcdac_tmp = pcdac_low_pwr; 1935 max_pwr_idx = (table_max[1] - table_min[1])/2; 1936 } 1937#endif 1938 } else { 1939 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 1940 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 1941 min_pwr_idx = table_min[0]; 1942 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 1943 pcdac_tmp = pcdac_high_pwr; 1944 edge_flag = 0; 1945 } 1946 1947 /* This is used when setting tx power*/ 1948 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 1949 1950 /* Fill Power to PCDAC table backwards */ 1951 pwr = max_pwr_idx; 1952 for (i = 63; i >= 0; i--) { 1953 /* Entering lower power range, reset 1954 * edge flag and set pcdac_tmp to lower 1955 * power curve.*/ 1956 if (edge_flag == 0x40 && 1957 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 1958 edge_flag = 0x00; 1959 pcdac_tmp = pcdac_low_pwr; 1960 pwr = mid_pwr_idx/2; 1961 } 1962 1963 /* Don't go below 1, extrapolate below if we have 1964 * already swithced to the lower power curve -or 1965 * we only have one curve and edge_flag is zero 1966 * anyway */ 1967 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 1968 while (i >= 0) { 1969 pcdac_out[i] = pcdac_out[i + 1]; 1970 i--; 1971 } 1972 break; 1973 } 1974 1975 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 1976 1977 /* Extrapolate above if pcdac is greater than 1978 * 126 -this can happen because we OR pcdac_out 1979 * value with edge_flag on high power curve */ 1980 if (pcdac_out[i] > 126) 1981 pcdac_out[i] = 126; 1982 1983 /* Decrease by a 0.5dB step */ 1984 pwr--; 1985 } 1986} 1987 1988/* Write PCDAC values on hw */ 1989static void 1990ath5k_setup_pcdac_table(struct ath5k_hw *ah) 1991{ 1992 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1993 int i; 1994 1995 /* 1996 * Write TX power values 1997 */ 1998 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 1999 ath5k_hw_reg_write(ah, 2000 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2001 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2002 AR5K_PHY_PCDAC_TXPOWER(i)); 2003 } 2004} 2005 2006 2007/* 2008 * Power to PDADC table functions 2009 */ 2010 2011/* 2012 * Set the gain boundaries and create final Power to PDADC table 2013 * 2014 * We can have up to 4 pd curves, we need to do a simmilar process 2015 * as we do for RF5112. This time we don't have an edge_flag but we 2016 * set the gain boundaries on a separate register. 2017 */ 2018static void 2019ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2020 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2021{ 2022 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2023 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2024 u8 *pdadc_tmp; 2025 s16 pdadc_0; 2026 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2027 u8 pd_gain_overlap; 2028 2029 /* Note: Register value is initialized on initvals 2030 * there is no feedback from hw. 2031 * XXX: What about pd_gain_overlap from EEPROM ? */ 2032 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2033 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2034 2035 /* Create final PDADC table */ 2036 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2037 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2038 2039 if (pdg == pdcurves - 1) 2040 /* 2 dB boundary stretch for last 2041 * (higher power) curve */ 2042 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2043 else 2044 /* Set gain boundary in the middle 2045 * between this curve and the next one */ 2046 gain_boundaries[pdg] = 2047 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2048 2049 /* Sanity check in case our 2 db stretch got out of 2050 * range. */ 2051 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2052 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2053 2054 /* For the first curve (lower power) 2055 * start from 0 dB */ 2056 if (pdg == 0) 2057 pdadc_0 = 0; 2058 else 2059 /* For the other curves use the gain overlap */ 2060 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2061 pd_gain_overlap; 2062 2063 /* Force each power step to be at least 0.5 dB */ 2064 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2065 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2066 else 2067 pwr_step = 1; 2068 2069 /* If pdadc_0 is negative, we need to extrapolate 2070 * below this pdgain by a number of pwr_steps */ 2071 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2072 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2073 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2074 pdadc_0++; 2075 } 2076 2077 /* Set last pwr level, using gain boundaries */ 2078 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2079 /* Limit it to be inside pwr range */ 2080 table_size = pwr_max[pdg] - pwr_min[pdg]; 2081 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2082 2083 /* Fill pdadc_out table */ 2084 while (pdadc_0 < max_idx) 2085 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2086 2087 /* Need to extrapolate above this pdgain? */ 2088 if (pdadc_n <= max_idx) 2089 continue; 2090 2091 /* Force each power step to be at least 0.5 dB */ 2092 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2093 pwr_step = pdadc_tmp[table_size - 1] - 2094 pdadc_tmp[table_size - 2]; 2095 else 2096 pwr_step = 1; 2097 2098 /* Extrapolate above */ 2099 while ((pdadc_0 < (s16) pdadc_n) && 2100 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2101 s16 tmp = pdadc_tmp[table_size - 1] + 2102 (pdadc_0 - max_idx) * pwr_step; 2103 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2104 pdadc_0++; 2105 } 2106 } 2107 2108 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2109 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2110 pdg++; 2111 } 2112 2113 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2114 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2115 pdadc_i++; 2116 } 2117 2118 /* Set gain boundaries */ 2119 ath5k_hw_reg_write(ah, 2120 AR5K_REG_SM(pd_gain_overlap, 2121 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2122 AR5K_REG_SM(gain_boundaries[0], 2123 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2124 AR5K_REG_SM(gain_boundaries[1], 2125 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2126 AR5K_REG_SM(gain_boundaries[2], 2127 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2128 AR5K_REG_SM(gain_boundaries[3], 2129 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2130 AR5K_PHY_TPC_RG5); 2131 2132 /* Used for setting rate power table */ 2133 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2134 2135} 2136 2137/* Write PDADC values on hw */ 2138static void 2139ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2140 u8 pdcurves, u8 *pdg_to_idx) 2141{ 2142 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2143 u32 reg; 2144 u8 i; 2145 2146 /* Select the right pdgain curves */ 2147 2148 /* Clear current settings */ 2149 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2150 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2151 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2152 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2153 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2154 2155 /* 2156 * Use pd_gains curve from eeprom 2157 * 2158 * This overrides the default setting from initvals 2159 * in case some vendors (e.g. Zcomax) don't use the default 2160 * curves. If we don't honor their settings we 'll get a 2161 * 5dB (1 * gain overlap ?) drop. 2162 */ 2163 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2164 2165 switch (pdcurves) { 2166 case 3: 2167 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2168 /* Fall through */ 2169 case 2: 2170 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2171 /* Fall through */ 2172 case 1: 2173 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2174 break; 2175 } 2176 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2177 2178 /* 2179 * Write TX power values 2180 */ 2181 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2182 ath5k_hw_reg_write(ah, 2183 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2184 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2185 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2186 ((pdadc_out[4*i + 3] & 0xff) << 24), 2187 AR5K_PHY_PDADC_TXPOWER(i)); 2188 } 2189} 2190 2191 2192/* 2193 * Common code for PCDAC/PDADC tables 2194 */ 2195 2196/* 2197 * This is the main function that uses all of the above 2198 * to set PCDAC/PDADC table on hw for the current channel. 2199 * This table is used for tx power calibration on the basband, 2200 * without it we get weird tx power levels and in some cases 2201 * distorted spectral mask 2202 */ 2203static int 2204ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2205 struct ieee80211_channel *channel, 2206 u8 ee_mode, u8 type) 2207{ 2208 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2209 struct ath5k_chan_pcal_info *pcinfo_L; 2210 struct ath5k_chan_pcal_info *pcinfo_R; 2211 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2212 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2213 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2214 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2215 u8 *tmpL; 2216 u8 *tmpR; 2217 u32 target = channel->center_freq; 2218 int pdg, i; 2219 2220 /* Get surounding freq piers for this channel */ 2221 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2222 &pcinfo_L, 2223 &pcinfo_R); 2224 2225 /* Loop over pd gain curves on 2226 * surounding freq piers by index */ 2227 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2228 2229 /* Fill curves in reverse order 2230 * from lower power (max gain) 2231 * to higher power. Use curve -> idx 2232 * backmaping we did on eeprom init */ 2233 u8 idx = pdg_curve_to_idx[pdg]; 2234 2235 /* Grab the needed curves by index */ 2236 pdg_L = &pcinfo_L->pd_curves[idx]; 2237 pdg_R = &pcinfo_R->pd_curves[idx]; 2238 2239 /* Initialize the temp tables */ 2240 tmpL = ah->ah_txpower.tmpL[pdg]; 2241 tmpR = ah->ah_txpower.tmpR[pdg]; 2242 2243 /* Set curve's x boundaries and create 2244 * curves so that they cover the same 2245 * range (if we don't do that one table 2246 * will have values on some range and the 2247 * other one won't have any so interpolation 2248 * will fail) */ 2249 table_min[pdg] = min(pdg_L->pd_pwr[0], 2250 pdg_R->pd_pwr[0]) / 2; 2251 2252 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2253 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2254 2255 /* Now create the curves on surrounding channels 2256 * and interpolate if needed to get the final 2257 * curve for this gain on this channel */ 2258 switch (type) { 2259 case AR5K_PWRTABLE_LINEAR_PCDAC: 2260 /* Override min/max so that we don't loose 2261 * accuracy (don't divide by 2) */ 2262 table_min[pdg] = min(pdg_L->pd_pwr[0], 2263 pdg_R->pd_pwr[0]); 2264 2265 table_max[pdg] = 2266 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2267 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2268 2269 /* Override minimum so that we don't get 2270 * out of bounds while extrapolating 2271 * below. Don't do this when we have 2 2272 * curves and we are on the high power curve 2273 * because table_min is ok in this case */ 2274 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2275 2276 table_min[pdg] = 2277 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2278 pdg_R->pd_step, 2279 pdg_L->pd_pwr, 2280 pdg_R->pd_pwr); 2281 2282 /* Don't go too low because we will 2283 * miss the upper part of the curve. 2284 * Note: 126 = 31.5dB (max power supported) 2285 * in 0.25dB units */ 2286 if (table_max[pdg] - table_min[pdg] > 126) 2287 table_min[pdg] = table_max[pdg] - 126; 2288 } 2289 2290 /* Fall through */ 2291 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2292 case AR5K_PWRTABLE_PWR_TO_PDADC: 2293 2294 ath5k_create_power_curve(table_min[pdg], 2295 table_max[pdg], 2296 pdg_L->pd_pwr, 2297 pdg_L->pd_step, 2298 pdg_L->pd_points, tmpL, type); 2299 2300 /* We are in a calibration 2301 * pier, no need to interpolate 2302 * between freq piers */ 2303 if (pcinfo_L == pcinfo_R) 2304 continue; 2305 2306 ath5k_create_power_curve(table_min[pdg], 2307 table_max[pdg], 2308 pdg_R->pd_pwr, 2309 pdg_R->pd_step, 2310 pdg_R->pd_points, tmpR, type); 2311 break; 2312 default: 2313 return -EINVAL; 2314 } 2315 2316 /* Interpolate between curves 2317 * of surounding freq piers to 2318 * get the final curve for this 2319 * pd gain. Re-use tmpL for interpolation 2320 * output */ 2321 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2322 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2323 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2324 (s16) pcinfo_L->freq, 2325 (s16) pcinfo_R->freq, 2326 (s16) tmpL[i], 2327 (s16) tmpR[i]); 2328 } 2329 } 2330 2331 /* Now we have a set of curves for this 2332 * channel on tmpL (x range is table_max - table_min 2333 * and y values are tmpL[pdg][]) sorted in the same 2334 * order as EEPROM (because we've used the backmaping). 2335 * So for RF5112 it's from higher power to lower power 2336 * and for RF2413 it's from lower power to higher power. 2337 * For RF5111 we only have one curve. */ 2338 2339 /* Fill min and max power levels for this 2340 * channel by interpolating the values on 2341 * surounding channels to complete the dataset */ 2342 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2343 (s16) pcinfo_L->freq, 2344 (s16) pcinfo_R->freq, 2345 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2346 2347 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2348 (s16) pcinfo_L->freq, 2349 (s16) pcinfo_R->freq, 2350 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2351 2352 /* We are ready to go, fill PCDAC/PDADC 2353 * table and write settings on hardware */ 2354 switch (type) { 2355 case AR5K_PWRTABLE_LINEAR_PCDAC: 2356 /* For RF5112 we can have one or two curves 2357 * and each curve covers a certain power lvl 2358 * range so we need to do some more processing */ 2359 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2360 ee->ee_pd_gains[ee_mode]); 2361 2362 /* Set txp.offset so that we can 2363 * match max power value with max 2364 * table index */ 2365 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2366 2367 /* Write settings on hw */ 2368 ath5k_setup_pcdac_table(ah); 2369 break; 2370 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2371 /* We are done for RF5111 since it has only 2372 * one curve, just fit the curve on the table */ 2373 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2374 2375 /* No rate powertable adjustment for RF5111 */ 2376 ah->ah_txpower.txp_min_idx = 0; 2377 ah->ah_txpower.txp_offset = 0; 2378 2379 /* Write settings on hw */ 2380 ath5k_setup_pcdac_table(ah); 2381 break; 2382 case AR5K_PWRTABLE_PWR_TO_PDADC: 2383 /* Set PDADC boundaries and fill 2384 * final PDADC table */ 2385 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2386 ee->ee_pd_gains[ee_mode]); 2387 2388 /* Write settings on hw */ 2389 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2390 2391 /* Set txp.offset, note that table_min 2392 * can be negative */ 2393 ah->ah_txpower.txp_offset = table_min[0]; 2394 break; 2395 default: 2396 return -EINVAL; 2397 } 2398 2399 return 0; 2400} 2401 2402 2403/* 2404 * Per-rate tx power setting 2405 * 2406 * This is the code that sets the desired tx power (below 2407 * maximum) on hw for each rate (we also have TPC that sets 2408 * power per packet). We do that by providing an index on the 2409 * PCDAC/PDADC table we set up. 2410 */ 2411 2412/* 2413 * Set rate power table 2414 * 2415 * For now we only limit txpower based on maximum tx power 2416 * supported by hw (what's inside rate_info). We need to limit 2417 * this even more, based on regulatory domain etc. 2418 * 2419 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2420 * and is indexed as follows: 2421 * rates[0] - rates[7] -> OFDM rates 2422 * rates[8] - rates[14] -> CCK rates 2423 * rates[15] -> XR rates (they all have the same power) 2424 */ 2425static void 2426ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2427 struct ath5k_rate_pcal_info *rate_info, 2428 u8 ee_mode) 2429{ 2430 unsigned int i; 2431 u16 *rates; 2432 2433 /* max_pwr is power level we got from driver/user in 0.5dB 2434 * units, switch to 0.25dB units so we can compare */ 2435 max_pwr *= 2; 2436 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2437 2438 /* apply rate limits */ 2439 rates = ah->ah_txpower.txp_rates_power_table; 2440 2441 /* OFDM rates 6 to 24Mb/s */ 2442 for (i = 0; i < 5; i++) 2443 rates[i] = min(max_pwr, rate_info->target_power_6to24); 2444 2445 /* Rest OFDM rates */ 2446 rates[5] = min(rates[0], rate_info->target_power_36); 2447 rates[6] = min(rates[0], rate_info->target_power_48); 2448 rates[7] = min(rates[0], rate_info->target_power_54); 2449 2450 /* CCK rates */ 2451 /* 1L */ 2452 rates[8] = min(rates[0], rate_info->target_power_6to24); 2453 /* 2L */ 2454 rates[9] = min(rates[0], rate_info->target_power_36); 2455 /* 2S */ 2456 rates[10] = min(rates[0], rate_info->target_power_36); 2457 /* 5L */ 2458 rates[11] = min(rates[0], rate_info->target_power_48); 2459 /* 5S */ 2460 rates[12] = min(rates[0], rate_info->target_power_48); 2461 /* 11L */ 2462 rates[13] = min(rates[0], rate_info->target_power_54); 2463 /* 11S */ 2464 rates[14] = min(rates[0], rate_info->target_power_54); 2465 2466 /* XR rates */ 2467 rates[15] = min(rates[0], rate_info->target_power_6to24); 2468 2469 /* CCK rates have different peak to average ratio 2470 * so we have to tweak their power so that gainf 2471 * correction works ok. For this we use OFDM to 2472 * CCK delta from eeprom */ 2473 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 2474 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 2475 for (i = 8; i <= 15; i++) 2476 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 2477 2478 ah->ah_txpower.txp_min_pwr = rates[7]; 2479 ah->ah_txpower.txp_max_pwr = rates[0]; 2480 ah->ah_txpower.txp_ofdm = rates[7]; 2481} 2482 2483 2484/* 2485 * Set transmition power 2486 */ 2487int 2488ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 2489 u8 ee_mode, u8 txpower) 2490{ 2491 struct ath5k_rate_pcal_info rate_info; 2492 u8 type; 2493 int ret; 2494 2495 ATH5K_TRACE(ah->ah_sc); 2496 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2497 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 2498 return -EINVAL; 2499 } 2500 if (txpower == 0) 2501 txpower = AR5K_TUNE_DEFAULT_TXPOWER; 2502 2503 /* Reset TX power values */ 2504 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 2505 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 2506 ah->ah_txpower.txp_min_pwr = 0; 2507 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 2508 2509 /* Initialize TX power table */ 2510 switch (ah->ah_radio) { 2511 case AR5K_RF5111: 2512 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 2513 break; 2514 case AR5K_RF5112: 2515 type = AR5K_PWRTABLE_LINEAR_PCDAC; 2516 break; 2517 case AR5K_RF2413: 2518 case AR5K_RF5413: 2519 case AR5K_RF2316: 2520 case AR5K_RF2317: 2521 case AR5K_RF2425: 2522 type = AR5K_PWRTABLE_PWR_TO_PDADC; 2523 break; 2524 default: 2525 return -EINVAL; 2526 } 2527 2528 /* FIXME: Only on channel/mode change */ 2529 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 2530 if (ret) 2531 return ret; 2532 2533 /* Limit max power if we have a CTL available */ 2534 ath5k_get_max_ctl_power(ah, channel); 2535 2536 /* FIXME: Tx power limit for this regdomain 2537 * XXX: Mac80211/CRDA will do that anyway ? */ 2538 2539 /* FIXME: Antenna reduction stuff */ 2540 2541 /* FIXME: Limit power on turbo modes */ 2542 2543 /* FIXME: TPC scale reduction */ 2544 2545 /* Get surounding channels for per-rate power table 2546 * calibration */ 2547 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 2548 2549 /* Setup rate power table */ 2550 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 2551 2552 /* Write rate power table on hw */ 2553 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 2554 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 2555 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 2556 2557 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 2558 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 2559 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 2560 2561 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 2562 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 2563 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 2564 2565 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 2566 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 2567 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 2568 2569 /* FIXME: TPC support */ 2570 if (ah->ah_txpower.txp_tpc) { 2571 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 2572 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2573 2574 ath5k_hw_reg_write(ah, 2575 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 2576 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 2577 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 2578 AR5K_TPC); 2579 } else { 2580 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 2581 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2582 } 2583 2584 return 0; 2585} 2586 2587int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower) 2588{ 2589 /*Just a try M.F.*/ 2590 struct ieee80211_channel *channel = &ah->ah_current_channel; 2591 2592 ATH5K_TRACE(ah->ah_sc); 2593 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 2594 "changing txpower to %d\n", txpower); 2595 2596 return ath5k_hw_txpower(ah, channel, mode, txpower); 2597} 2598 2599#undef _ATH5K_PHY 2600