phy.c revision 6752ee90aa7c933294a10dbd9ea51f12dece7eb1
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#define _ATH5K_PHY 24 25#include <linux/delay.h> 26 27#include "ath5k.h" 28#include "reg.h" 29#include "base.h" 30#include "rfbuffer.h" 31#include "rfgain.h" 32 33/* 34 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 35 */ 36static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 37 const struct ath5k_rf_reg *rf_regs, 38 u32 val, u8 reg_id, bool set) 39{ 40 const struct ath5k_rf_reg *rfreg = NULL; 41 u8 offset, bank, num_bits, col, position; 42 u16 entry; 43 u32 mask, data, last_bit, bits_shifted, first_bit; 44 u32 *rfb; 45 s32 bits_left; 46 int i; 47 48 data = 0; 49 rfb = ah->ah_rf_banks; 50 51 for (i = 0; i < ah->ah_rf_regs_count; i++) { 52 if (rf_regs[i].index == reg_id) { 53 rfreg = &rf_regs[i]; 54 break; 55 } 56 } 57 58 if (rfb == NULL || rfreg == NULL) { 59 ATH5K_PRINTF("Rf register not found!\n"); 60 /* should not happen */ 61 return 0; 62 } 63 64 bank = rfreg->bank; 65 num_bits = rfreg->field.len; 66 first_bit = rfreg->field.pos; 67 col = rfreg->field.col; 68 69 /* first_bit is an offset from bank's 70 * start. Since we have all banks on 71 * the same array, we use this offset 72 * to mark each bank's start */ 73 offset = ah->ah_offset[bank]; 74 75 /* Boundary check */ 76 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 77 ATH5K_PRINTF("invalid values at offset %u\n", offset); 78 return 0; 79 } 80 81 entry = ((first_bit - 1) / 8) + offset; 82 position = (first_bit - 1) % 8; 83 84 if (set) 85 data = ath5k_hw_bitswap(val, num_bits); 86 87 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 88 position = 0, entry++) { 89 90 last_bit = (position + bits_left > 8) ? 8 : 91 position + bits_left; 92 93 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 94 (col * 8); 95 96 if (set) { 97 rfb[entry] &= ~mask; 98 rfb[entry] |= ((data << position) << (col * 8)) & mask; 99 data >>= (8 - position); 100 } else { 101 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 102 << bits_shifted; 103 bits_shifted += last_bit - position; 104 } 105 106 bits_left -= 8 - position; 107 } 108 109 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 110 111 return data; 112} 113 114/**********************\ 115* RF Gain optimization * 116\**********************/ 117 118/* 119 * This code is used to optimize rf gain on different environments 120 * (temprature mostly) based on feedback from a power detector. 121 * 122 * It's only used on RF5111 and RF5112, later RF chips seem to have 123 * auto adjustment on hw -notice they have a much smaller BANK 7 and 124 * no gain optimization ladder-. 125 * 126 * For more infos check out this patent doc 127 * http://www.freepatentsonline.com/7400691.html 128 * 129 * This paper describes power drops as seen on the receiver due to 130 * probe packets 131 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 132 * %20of%20Power%20Control.pdf 133 * 134 * And this is the MadWiFi bug entry related to the above 135 * http://madwifi-project.org/ticket/1659 136 * with various measurements and diagrams 137 * 138 * TODO: Deal with power drops due to probes by setting an apropriate 139 * tx power on the probe packets ! Make this part of the calibration process. 140 */ 141 142/* Initialize ah_gain durring attach */ 143int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 144{ 145 /* Initialize the gain optimization values */ 146 switch (ah->ah_radio) { 147 case AR5K_RF5111: 148 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 149 ah->ah_gain.g_low = 20; 150 ah->ah_gain.g_high = 35; 151 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 152 break; 153 case AR5K_RF5112: 154 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 155 ah->ah_gain.g_low = 20; 156 ah->ah_gain.g_high = 85; 157 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 return 0; 164} 165 166/* Schedule a gain probe check on the next transmited packet. 167 * That means our next packet is going to be sent with lower 168 * tx power and a Peak to Average Power Detector (PAPD) will try 169 * to measure the gain. 170 * 171 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 172 * just after we enable the probe so that we don't mess with 173 * standard traffic ? Maybe it's time to use sw interrupts and 174 * a probe tasklet !!! 175 */ 176static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 177{ 178 179 /* Skip if gain calibration is inactive or 180 * we already handle a probe request */ 181 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 182 return; 183 184 /* Send the packet with 2dB below max power as 185 * patent doc suggest */ 186 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 187 AR5K_PHY_PAPD_PROBE_TXPOWER) | 188 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 189 190 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 191 192} 193 194/* Calculate gain_F measurement correction 195 * based on the current step for RF5112 rev. 2 */ 196static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 197{ 198 u32 mix, step; 199 u32 *rf; 200 const struct ath5k_gain_opt *go; 201 const struct ath5k_gain_opt_step *g_step; 202 const struct ath5k_rf_reg *rf_regs; 203 204 /* Only RF5112 Rev. 2 supports it */ 205 if ((ah->ah_radio != AR5K_RF5112) || 206 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 207 return 0; 208 209 go = &rfgain_opt_5112; 210 rf_regs = rf_regs_5112a; 211 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 212 213 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 214 215 if (ah->ah_rf_banks == NULL) 216 return 0; 217 218 rf = ah->ah_rf_banks; 219 ah->ah_gain.g_f_corr = 0; 220 221 /* No VGA (Variable Gain Amplifier) override, skip */ 222 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 223 return 0; 224 225 /* Mix gain stepping */ 226 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 227 228 /* Mix gain override */ 229 mix = g_step->gos_param[0]; 230 231 switch (mix) { 232 case 3: 233 ah->ah_gain.g_f_corr = step * 2; 234 break; 235 case 2: 236 ah->ah_gain.g_f_corr = (step - 5) * 2; 237 break; 238 case 1: 239 ah->ah_gain.g_f_corr = step; 240 break; 241 default: 242 ah->ah_gain.g_f_corr = 0; 243 break; 244 } 245 246 return ah->ah_gain.g_f_corr; 247} 248 249/* Check if current gain_F measurement is in the range of our 250 * power detector windows. If we get a measurement outside range 251 * we know it's not accurate (detectors can't measure anything outside 252 * their detection window) so we must ignore it */ 253static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 254{ 255 const struct ath5k_rf_reg *rf_regs; 256 u32 step, mix_ovr, level[4]; 257 u32 *rf; 258 259 if (ah->ah_rf_banks == NULL) 260 return false; 261 262 rf = ah->ah_rf_banks; 263 264 if (ah->ah_radio == AR5K_RF5111) { 265 266 rf_regs = rf_regs_5111; 267 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 268 269 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 270 false); 271 272 level[0] = 0; 273 level[1] = (step == 63) ? 50 : step + 4; 274 level[2] = (step != 63) ? 64 : level[0]; 275 level[3] = level[2] + 50 ; 276 277 ah->ah_gain.g_high = level[3] - 278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 279 ah->ah_gain.g_low = level[0] + 280 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 281 } else { 282 283 rf_regs = rf_regs_5112; 284 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 285 286 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 287 false); 288 289 level[0] = level[2] = 0; 290 291 if (mix_ovr == 1) { 292 level[1] = level[3] = 83; 293 } else { 294 level[1] = level[3] = 107; 295 ah->ah_gain.g_high = 55; 296 } 297 } 298 299 return (ah->ah_gain.g_current >= level[0] && 300 ah->ah_gain.g_current <= level[1]) || 301 (ah->ah_gain.g_current >= level[2] && 302 ah->ah_gain.g_current <= level[3]); 303} 304 305/* Perform gain_F adjustment by choosing the right set 306 * of parameters from rf gain optimization ladder */ 307static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 308{ 309 const struct ath5k_gain_opt *go; 310 const struct ath5k_gain_opt_step *g_step; 311 int ret = 0; 312 313 switch (ah->ah_radio) { 314 case AR5K_RF5111: 315 go = &rfgain_opt_5111; 316 break; 317 case AR5K_RF5112: 318 go = &rfgain_opt_5112; 319 break; 320 default: 321 return 0; 322 } 323 324 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 325 326 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 327 328 /* Reached maximum */ 329 if (ah->ah_gain.g_step_idx == 0) 330 return -1; 331 332 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 333 ah->ah_gain.g_target >= ah->ah_gain.g_high && 334 ah->ah_gain.g_step_idx > 0; 335 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 336 ah->ah_gain.g_target -= 2 * 337 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 338 g_step->gos_gain); 339 340 ret = 1; 341 goto done; 342 } 343 344 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 345 346 /* Reached minimum */ 347 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 348 return -2; 349 350 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 351 ah->ah_gain.g_target <= ah->ah_gain.g_low && 352 ah->ah_gain.g_step_idx < go->go_steps_count-1; 353 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 354 ah->ah_gain.g_target -= 2 * 355 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 356 g_step->gos_gain); 357 358 ret = 2; 359 goto done; 360 } 361 362done: 363 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 364 "ret %d, gain step %u, current gain %u, target gain %u\n", 365 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 366 ah->ah_gain.g_target); 367 368 return ret; 369} 370 371/* Main callback for thermal rf gain calibration engine 372 * Check for a new gain reading and schedule an adjustment 373 * if needed. 374 * 375 * TODO: Use sw interrupt to schedule reset if gain_F needs 376 * adjustment */ 377enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 378{ 379 u32 data, type; 380 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 381 382 ATH5K_TRACE(ah->ah_sc); 383 384 if (ah->ah_rf_banks == NULL || 385 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 386 return AR5K_RFGAIN_INACTIVE; 387 388 /* No check requested, either engine is inactive 389 * or an adjustment is already requested */ 390 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 391 goto done; 392 393 /* Read the PAPD (Peak to Average Power Detector) 394 * register */ 395 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 396 397 /* No probe is scheduled, read gain_F measurement */ 398 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 399 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 400 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 401 402 /* If tx packet is CCK correct the gain_F measurement 403 * by cck ofdm gain delta */ 404 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 405 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 406 ah->ah_gain.g_current += 407 ee->ee_cck_ofdm_gain_delta; 408 else 409 ah->ah_gain.g_current += 410 AR5K_GAIN_CCK_PROBE_CORR; 411 } 412 413 /* Further correct gain_F measurement for 414 * RF5112A radios */ 415 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 416 ath5k_hw_rf_gainf_corr(ah); 417 ah->ah_gain.g_current = 418 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 419 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 420 0; 421 } 422 423 /* Check if measurement is ok and if we need 424 * to adjust gain, schedule a gain adjustment, 425 * else switch back to the acive state */ 426 if (ath5k_hw_rf_check_gainf_readback(ah) && 427 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 428 ath5k_hw_rf_gainf_adjust(ah)) { 429 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 430 } else { 431 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 432 } 433 } 434 435done: 436 return ah->ah_gain.g_state; 437} 438 439/* Write initial rf gain table to set the RF sensitivity 440 * this one works on all RF chips and has nothing to do 441 * with gain_F calibration */ 442int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 443{ 444 const struct ath5k_ini_rfgain *ath5k_rfg; 445 unsigned int i, size; 446 447 switch (ah->ah_radio) { 448 case AR5K_RF5111: 449 ath5k_rfg = rfgain_5111; 450 size = ARRAY_SIZE(rfgain_5111); 451 break; 452 case AR5K_RF5112: 453 ath5k_rfg = rfgain_5112; 454 size = ARRAY_SIZE(rfgain_5112); 455 break; 456 case AR5K_RF2413: 457 ath5k_rfg = rfgain_2413; 458 size = ARRAY_SIZE(rfgain_2413); 459 break; 460 case AR5K_RF2316: 461 ath5k_rfg = rfgain_2316; 462 size = ARRAY_SIZE(rfgain_2316); 463 break; 464 case AR5K_RF5413: 465 ath5k_rfg = rfgain_5413; 466 size = ARRAY_SIZE(rfgain_5413); 467 break; 468 case AR5K_RF2317: 469 case AR5K_RF2425: 470 ath5k_rfg = rfgain_2425; 471 size = ARRAY_SIZE(rfgain_2425); 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 switch (freq) { 478 case AR5K_INI_RFGAIN_2GHZ: 479 case AR5K_INI_RFGAIN_5GHZ: 480 break; 481 default: 482 return -EINVAL; 483 } 484 485 for (i = 0; i < size; i++) { 486 AR5K_REG_WAIT(i); 487 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 488 (u32)ath5k_rfg[i].rfg_register); 489 } 490 491 return 0; 492} 493 494 495 496/********************\ 497* RF Registers setup * 498\********************/ 499 500 501/* 502 * Setup RF registers by writing rf buffer on hw 503 */ 504int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 505 unsigned int mode) 506{ 507 const struct ath5k_rf_reg *rf_regs; 508 const struct ath5k_ini_rfbuffer *ini_rfb; 509 const struct ath5k_gain_opt *go = NULL; 510 const struct ath5k_gain_opt_step *g_step; 511 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 512 u8 ee_mode = 0; 513 u32 *rfb; 514 int i, obdb = -1, bank = -1; 515 516 switch (ah->ah_radio) { 517 case AR5K_RF5111: 518 rf_regs = rf_regs_5111; 519 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 520 ini_rfb = rfb_5111; 521 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 522 go = &rfgain_opt_5111; 523 break; 524 case AR5K_RF5112: 525 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 526 rf_regs = rf_regs_5112a; 527 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 528 ini_rfb = rfb_5112a; 529 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 530 } else { 531 rf_regs = rf_regs_5112; 532 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 533 ini_rfb = rfb_5112; 534 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 535 } 536 go = &rfgain_opt_5112; 537 break; 538 case AR5K_RF2413: 539 rf_regs = rf_regs_2413; 540 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 541 ini_rfb = rfb_2413; 542 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 543 break; 544 case AR5K_RF2316: 545 rf_regs = rf_regs_2316; 546 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 547 ini_rfb = rfb_2316; 548 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 549 break; 550 case AR5K_RF5413: 551 rf_regs = rf_regs_5413; 552 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 553 ini_rfb = rfb_5413; 554 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 555 break; 556 case AR5K_RF2317: 557 rf_regs = rf_regs_2425; 558 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 559 ini_rfb = rfb_2317; 560 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 561 break; 562 case AR5K_RF2425: 563 rf_regs = rf_regs_2425; 564 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 565 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 566 ini_rfb = rfb_2425; 567 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 568 } else { 569 ini_rfb = rfb_2417; 570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 571 } 572 break; 573 default: 574 return -EINVAL; 575 } 576 577 /* If it's the first time we set rf buffer, allocate 578 * ah->ah_rf_banks based on ah->ah_rf_banks_size 579 * we set above */ 580 if (ah->ah_rf_banks == NULL) { 581 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 582 GFP_KERNEL); 583 if (ah->ah_rf_banks == NULL) { 584 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 585 return -ENOMEM; 586 } 587 } 588 589 /* Copy values to modify them */ 590 rfb = ah->ah_rf_banks; 591 592 for (i = 0; i < ah->ah_rf_banks_size; i++) { 593 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 594 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 595 return -EINVAL; 596 } 597 598 /* Bank changed, write down the offset */ 599 if (bank != ini_rfb[i].rfb_bank) { 600 bank = ini_rfb[i].rfb_bank; 601 ah->ah_offset[bank] = i; 602 } 603 604 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 605 } 606 607 /* Set Output and Driver bias current (OB/DB) */ 608 if (channel->hw_value & CHANNEL_2GHZ) { 609 610 if (channel->hw_value & CHANNEL_CCK) 611 ee_mode = AR5K_EEPROM_MODE_11B; 612 else 613 ee_mode = AR5K_EEPROM_MODE_11G; 614 615 /* For RF511X/RF211X combination we 616 * use b_OB and b_DB parameters stored 617 * in eeprom on ee->ee_ob[ee_mode][0] 618 * 619 * For all other chips we use OB/DB for 2Ghz 620 * stored in the b/g modal section just like 621 * 802.11a on ee->ee_ob[ee_mode][1] */ 622 if ((ah->ah_radio == AR5K_RF5111) || 623 (ah->ah_radio == AR5K_RF5112)) 624 obdb = 0; 625 else 626 obdb = 1; 627 628 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 629 AR5K_RF_OB_2GHZ, true); 630 631 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 632 AR5K_RF_DB_2GHZ, true); 633 634 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 635 } else if ((channel->hw_value & CHANNEL_5GHZ) || 636 (ah->ah_radio == AR5K_RF5111)) { 637 638 /* For 11a, Turbo and XR we need to choose 639 * OB/DB based on frequency range */ 640 ee_mode = AR5K_EEPROM_MODE_11A; 641 obdb = channel->center_freq >= 5725 ? 3 : 642 (channel->center_freq >= 5500 ? 2 : 643 (channel->center_freq >= 5260 ? 1 : 644 (channel->center_freq > 4000 ? 0 : -1))); 645 646 if (obdb < 0) 647 return -EINVAL; 648 649 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 650 AR5K_RF_OB_5GHZ, true); 651 652 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 653 AR5K_RF_DB_5GHZ, true); 654 } 655 656 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 657 658 /* Bank Modifications (chip-specific) */ 659 if (ah->ah_radio == AR5K_RF5111) { 660 661 /* Set gain_F settings according to current step */ 662 if (channel->hw_value & CHANNEL_OFDM) { 663 664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 665 AR5K_PHY_FRAME_CTL_TX_CLIP, 666 g_step->gos_param[0]); 667 668 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 669 AR5K_RF_PWD_90, true); 670 671 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 672 AR5K_RF_PWD_84, true); 673 674 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 675 AR5K_RF_RFGAIN_SEL, true); 676 677 /* We programmed gain_F parameters, switch back 678 * to active state */ 679 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 680 681 } 682 683 /* Bank 6/7 setup */ 684 685 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 686 AR5K_RF_PWD_XPD, true); 687 688 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 689 AR5K_RF_XPD_GAIN, true); 690 691 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 692 AR5K_RF_GAIN_I, true); 693 694 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 695 AR5K_RF_PLO_SEL, true); 696 697 /* TODO: Half/quarter channel support */ 698 } 699 700 if (ah->ah_radio == AR5K_RF5112) { 701 702 /* Set gain_F settings according to current step */ 703 if (channel->hw_value & CHANNEL_OFDM) { 704 705 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 706 AR5K_RF_MIXGAIN_OVR, true); 707 708 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 709 AR5K_RF_PWD_138, true); 710 711 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 712 AR5K_RF_PWD_137, true); 713 714 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 715 AR5K_RF_PWD_136, true); 716 717 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 718 AR5K_RF_PWD_132, true); 719 720 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 721 AR5K_RF_PWD_131, true); 722 723 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 724 AR5K_RF_PWD_130, true); 725 726 /* We programmed gain_F parameters, switch back 727 * to active state */ 728 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 729 } 730 731 /* Bank 6/7 setup */ 732 733 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 734 AR5K_RF_XPD_SEL, true); 735 736 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 737 /* Rev. 1 supports only one xpd */ 738 ath5k_hw_rfb_op(ah, rf_regs, 739 ee->ee_x_gain[ee_mode], 740 AR5K_RF_XPD_GAIN, true); 741 742 } else { 743 /* TODO: Set high and low gain bits */ 744 ath5k_hw_rfb_op(ah, rf_regs, 745 ee->ee_x_gain[ee_mode], 746 AR5K_RF_PD_GAIN_LO, true); 747 ath5k_hw_rfb_op(ah, rf_regs, 748 ee->ee_x_gain[ee_mode], 749 AR5K_RF_PD_GAIN_HI, true); 750 751 /* Lower synth voltage on Rev 2 */ 752 ath5k_hw_rfb_op(ah, rf_regs, 2, 753 AR5K_RF_HIGH_VC_CP, true); 754 755 ath5k_hw_rfb_op(ah, rf_regs, 2, 756 AR5K_RF_MID_VC_CP, true); 757 758 ath5k_hw_rfb_op(ah, rf_regs, 2, 759 AR5K_RF_LOW_VC_CP, true); 760 761 ath5k_hw_rfb_op(ah, rf_regs, 2, 762 AR5K_RF_PUSH_UP, true); 763 764 /* Decrease power consumption on 5213+ BaseBand */ 765 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 766 ath5k_hw_rfb_op(ah, rf_regs, 1, 767 AR5K_RF_PAD2GND, true); 768 769 ath5k_hw_rfb_op(ah, rf_regs, 1, 770 AR5K_RF_XB2_LVL, true); 771 772 ath5k_hw_rfb_op(ah, rf_regs, 1, 773 AR5K_RF_XB5_LVL, true); 774 775 ath5k_hw_rfb_op(ah, rf_regs, 1, 776 AR5K_RF_PWD_167, true); 777 778 ath5k_hw_rfb_op(ah, rf_regs, 1, 779 AR5K_RF_PWD_166, true); 780 } 781 } 782 783 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 784 AR5K_RF_GAIN_I, true); 785 786 /* TODO: Half/quarter channel support */ 787 788 } 789 790 if (ah->ah_radio == AR5K_RF5413 && 791 channel->hw_value & CHANNEL_2GHZ) { 792 793 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 794 true); 795 796 /* Set optimum value for early revisions (on pci-e chips) */ 797 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 798 ah->ah_mac_srev < AR5K_SREV_AR5413) 799 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 800 AR5K_RF_PWD_ICLOBUF_2G, true); 801 802 } 803 804 /* Write RF banks on hw */ 805 for (i = 0; i < ah->ah_rf_banks_size; i++) { 806 AR5K_REG_WAIT(i); 807 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 808 } 809 810 return 0; 811} 812 813 814/**************************\ 815 PHY/RF channel functions 816\**************************/ 817 818/* 819 * Check if a channel is supported 820 */ 821bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 822{ 823 /* Check if the channel is in our supported range */ 824 if (flags & CHANNEL_2GHZ) { 825 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 826 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 827 return true; 828 } else if (flags & CHANNEL_5GHZ) 829 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 830 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 831 return true; 832 833 return false; 834} 835 836/* 837 * Convertion needed for RF5110 838 */ 839static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 840{ 841 u32 athchan; 842 843 /* 844 * Convert IEEE channel/MHz to an internal channel value used 845 * by the AR5210 chipset. This has not been verified with 846 * newer chipsets like the AR5212A who have a completely 847 * different RF/PHY part. 848 */ 849 athchan = (ath5k_hw_bitswap( 850 (ieee80211_frequency_to_channel( 851 channel->center_freq) - 24) / 2, 5) 852 << 1) | (1 << 6) | 0x1; 853 return athchan; 854} 855 856/* 857 * Set channel on RF5110 858 */ 859static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 860 struct ieee80211_channel *channel) 861{ 862 u32 data; 863 864 /* 865 * Set the channel and wait 866 */ 867 data = ath5k_hw_rf5110_chan2athchan(channel); 868 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 869 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 870 mdelay(1); 871 872 return 0; 873} 874 875/* 876 * Convertion needed for 5111 877 */ 878static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 879 struct ath5k_athchan_2ghz *athchan) 880{ 881 int channel; 882 883 /* Cast this value to catch negative channel numbers (>= -19) */ 884 channel = (int)ieee; 885 886 /* 887 * Map 2GHz IEEE channel to 5GHz Atheros channel 888 */ 889 if (channel <= 13) { 890 athchan->a2_athchan = 115 + channel; 891 athchan->a2_flags = 0x46; 892 } else if (channel == 14) { 893 athchan->a2_athchan = 124; 894 athchan->a2_flags = 0x44; 895 } else if (channel >= 15 && channel <= 26) { 896 athchan->a2_athchan = ((channel - 14) * 4) + 132; 897 athchan->a2_flags = 0x46; 898 } else 899 return -EINVAL; 900 901 return 0; 902} 903 904/* 905 * Set channel on 5111 906 */ 907static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 908 struct ieee80211_channel *channel) 909{ 910 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 911 unsigned int ath5k_channel = 912 ieee80211_frequency_to_channel(channel->center_freq); 913 u32 data0, data1, clock; 914 int ret; 915 916 /* 917 * Set the channel on the RF5111 radio 918 */ 919 data0 = data1 = 0; 920 921 if (channel->hw_value & CHANNEL_2GHZ) { 922 /* Map 2GHz channel to 5GHz Atheros channel ID */ 923 ret = ath5k_hw_rf5111_chan2athchan( 924 ieee80211_frequency_to_channel(channel->center_freq), 925 &ath5k_channel_2ghz); 926 if (ret) 927 return ret; 928 929 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 930 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 931 << 5) | (1 << 4); 932 } 933 934 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 935 clock = 1; 936 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 937 (clock << 1) | (1 << 10) | 1; 938 } else { 939 clock = 0; 940 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 941 << 2) | (clock << 1) | (1 << 10) | 1; 942 } 943 944 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 945 AR5K_RF_BUFFER); 946 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 947 AR5K_RF_BUFFER_CONTROL_3); 948 949 return 0; 950} 951 952/* 953 * Set channel on 5112 and newer 954 */ 955static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 956 struct ieee80211_channel *channel) 957{ 958 u32 data, data0, data1, data2; 959 u16 c; 960 961 data = data0 = data1 = data2 = 0; 962 c = channel->center_freq; 963 964 if (c < 4800) { 965 if (!((c - 2224) % 5)) { 966 data0 = ((2 * (c - 704)) - 3040) / 10; 967 data1 = 1; 968 } else if (!((c - 2192) % 5)) { 969 data0 = ((2 * (c - 672)) - 3040) / 10; 970 data1 = 0; 971 } else 972 return -EINVAL; 973 974 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 975 } else if ((c - (c % 5)) != 2 || c > 5435) { 976 if (!(c % 20) && c >= 5120) { 977 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 978 data2 = ath5k_hw_bitswap(3, 2); 979 } else if (!(c % 10)) { 980 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 981 data2 = ath5k_hw_bitswap(2, 2); 982 } else if (!(c % 5)) { 983 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 984 data2 = ath5k_hw_bitswap(1, 2); 985 } else 986 return -EINVAL; 987 } else { 988 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 989 data2 = ath5k_hw_bitswap(0, 2); 990 } 991 992 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 993 994 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 995 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 996 997 return 0; 998} 999 1000/* 1001 * Set the channel on the RF2425 1002 */ 1003static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1004 struct ieee80211_channel *channel) 1005{ 1006 u32 data, data0, data2; 1007 u16 c; 1008 1009 data = data0 = data2 = 0; 1010 c = channel->center_freq; 1011 1012 if (c < 4800) { 1013 data0 = ath5k_hw_bitswap((c - 2272), 8); 1014 data2 = 0; 1015 /* ? 5GHz ? */ 1016 } else if ((c - (c % 5)) != 2 || c > 5435) { 1017 if (!(c % 20) && c < 5120) 1018 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1019 else if (!(c % 10)) 1020 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1021 else if (!(c % 5)) 1022 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1023 else 1024 return -EINVAL; 1025 data2 = ath5k_hw_bitswap(1, 2); 1026 } else { 1027 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 1028 data2 = ath5k_hw_bitswap(0, 2); 1029 } 1030 1031 data = (data0 << 4) | data2 << 2 | 0x1001; 1032 1033 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1034 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1035 1036 return 0; 1037} 1038 1039/* 1040 * Set a channel on the radio chip 1041 */ 1042int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) 1043{ 1044 int ret; 1045 /* 1046 * Check bounds supported by the PHY (we don't care about regultory 1047 * restrictions at this point). Note: hw_value already has the band 1048 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1049 * of the band by that */ 1050 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1051 ATH5K_ERR(ah->ah_sc, 1052 "channel frequency (%u MHz) out of supported " 1053 "band range\n", 1054 channel->center_freq); 1055 return -EINVAL; 1056 } 1057 1058 /* 1059 * Set the channel and wait 1060 */ 1061 switch (ah->ah_radio) { 1062 case AR5K_RF5110: 1063 ret = ath5k_hw_rf5110_channel(ah, channel); 1064 break; 1065 case AR5K_RF5111: 1066 ret = ath5k_hw_rf5111_channel(ah, channel); 1067 break; 1068 case AR5K_RF2425: 1069 ret = ath5k_hw_rf2425_channel(ah, channel); 1070 break; 1071 default: 1072 ret = ath5k_hw_rf5112_channel(ah, channel); 1073 break; 1074 } 1075 1076 if (ret) 1077 return ret; 1078 1079 /* Set JAPAN setting for channel 14 */ 1080 if (channel->center_freq == 2484) { 1081 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1082 AR5K_PHY_CCKTXCTL_JAPAN); 1083 } else { 1084 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1085 AR5K_PHY_CCKTXCTL_WORLD); 1086 } 1087 1088 ah->ah_current_channel.center_freq = channel->center_freq; 1089 ah->ah_current_channel.hw_value = channel->hw_value; 1090 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; 1091 1092 return 0; 1093} 1094 1095/*****************\ 1096 PHY calibration 1097\*****************/ 1098 1099/** 1100 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration 1101 * 1102 * @ah: struct ath5k_hw pointer we are operating on 1103 * @freq: the channel frequency, just used for error logging 1104 * 1105 * This function performs a noise floor calibration of the PHY and waits for 1106 * it to complete. Then the noise floor value is compared to some maximum 1107 * noise floor we consider valid. 1108 * 1109 * Note that this is different from what the madwifi HAL does: it reads the 1110 * noise floor and afterwards initiates the calibration. Since the noise floor 1111 * calibration can take some time to finish, depending on the current channel 1112 * use, that avoids the occasional timeout warnings we are seeing now. 1113 * 1114 * See the following link for an Atheros patent on noise floor calibration: 1115 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ 1116 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 1117 * 1118 * XXX: Since during noise floor calibration antennas are detached according to 1119 * the patent, we should stop tx queues here. 1120 */ 1121int 1122ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) 1123{ 1124 int ret; 1125 unsigned int i; 1126 s32 noise_floor; 1127 1128 /* 1129 * Enable noise floor calibration 1130 */ 1131 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1132 AR5K_PHY_AGCCTL_NF); 1133 1134 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1135 AR5K_PHY_AGCCTL_NF, 0, false); 1136 if (ret) { 1137 ATH5K_ERR(ah->ah_sc, 1138 "noise floor calibration timeout (%uMHz)\n", freq); 1139 return -EAGAIN; 1140 } 1141 1142 /* Wait until the noise floor is calibrated and read the value */ 1143 for (i = 20; i > 0; i--) { 1144 mdelay(1); 1145 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1146 noise_floor = AR5K_PHY_NF_RVAL(noise_floor); 1147 if (noise_floor & AR5K_PHY_NF_ACTIVE) { 1148 noise_floor = AR5K_PHY_NF_AVAL(noise_floor); 1149 1150 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) 1151 break; 1152 } 1153 } 1154 1155 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1156 "noise floor %d\n", noise_floor); 1157 1158 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { 1159 ATH5K_ERR(ah->ah_sc, 1160 "noise floor calibration failed (%uMHz)\n", freq); 1161 return -EAGAIN; 1162 } 1163 1164 ah->ah_noise_floor = noise_floor; 1165 1166 return 0; 1167} 1168 1169/* 1170 * Perform a PHY calibration on RF5110 1171 * -Fix BPSK/QAM Constellation (I/Q correction) 1172 * -Calculate Noise Floor 1173 */ 1174static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1175 struct ieee80211_channel *channel) 1176{ 1177 u32 phy_sig, phy_agc, phy_sat, beacon; 1178 int ret; 1179 1180 /* 1181 * Disable beacons and RX/TX queues, wait 1182 */ 1183 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1184 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1185 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1186 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1187 1188 mdelay(2); 1189 1190 /* 1191 * Set the channel (with AGC turned off) 1192 */ 1193 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1194 udelay(10); 1195 ret = ath5k_hw_channel(ah, channel); 1196 1197 /* 1198 * Activate PHY and wait 1199 */ 1200 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1201 mdelay(1); 1202 1203 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1204 1205 if (ret) 1206 return ret; 1207 1208 /* 1209 * Calibrate the radio chip 1210 */ 1211 1212 /* Remember normal state */ 1213 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1214 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1215 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1216 1217 /* Update radio registers */ 1218 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1219 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1220 1221 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1222 AR5K_PHY_AGCCOARSE_LO)) | 1223 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1224 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1225 1226 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1227 AR5K_PHY_ADCSAT_THR)) | 1228 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1229 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1230 1231 udelay(20); 1232 1233 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1234 udelay(10); 1235 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1236 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1237 1238 mdelay(1); 1239 1240 /* 1241 * Enable calibration and wait until completion 1242 */ 1243 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1244 1245 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1246 AR5K_PHY_AGCCTL_CAL, 0, false); 1247 1248 /* Reset to normal state */ 1249 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1250 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1251 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1252 1253 if (ret) { 1254 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1255 channel->center_freq); 1256 return ret; 1257 } 1258 1259 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1260 1261 /* 1262 * Re-enable RX/TX and beacons 1263 */ 1264 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1265 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1266 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1267 1268 return 0; 1269} 1270 1271/* 1272 * Perform a PHY calibration on RF5111/5112 and newer chips 1273 */ 1274static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, 1275 struct ieee80211_channel *channel) 1276{ 1277 u32 i_pwr, q_pwr; 1278 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1279 int i; 1280 ATH5K_TRACE(ah->ah_sc); 1281 1282 if (!ah->ah_calibration || 1283 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1284 goto done; 1285 1286 /* Calibration has finished, get the results and re-run */ 1287 for (i = 0; i <= 10; i++) { 1288 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1289 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1290 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1291 } 1292 1293 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1294 q_coffd = q_pwr >> 7; 1295 1296 /* No correction */ 1297 if (i_coffd == 0 || q_coffd == 0) 1298 goto done; 1299 1300 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 1301 1302 /* Boundary check */ 1303 if (i_coff > 31) 1304 i_coff = 31; 1305 if (i_coff < -32) 1306 i_coff = -32; 1307 1308 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; 1309 1310 /* Boundary check */ 1311 if (q_coff > 15) 1312 q_coff = 15; 1313 if (q_coff < -16) 1314 q_coff = -16; 1315 1316 /* Commit new I/Q value */ 1317 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | 1318 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); 1319 1320 /* Re-enable calibration -if we don't we'll commit 1321 * the same values again and again */ 1322 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1323 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1324 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1325 1326done: 1327 1328 /* TODO: Separate noise floor calibration from I/Q calibration 1329 * since noise floor calibration interrupts rx path while I/Q 1330 * calibration doesn't. We don't need to run noise floor calibration 1331 * as often as I/Q calibration.*/ 1332 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1333 1334 /* Initiate a gain_F calibration */ 1335 ath5k_hw_request_rfgain_probe(ah); 1336 1337 return 0; 1338} 1339 1340/* 1341 * Perform a PHY calibration 1342 */ 1343int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1344 struct ieee80211_channel *channel) 1345{ 1346 int ret; 1347 1348 if (ah->ah_radio == AR5K_RF5110) 1349 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1350 else 1351 ret = ath5k_hw_rf511x_calibrate(ah, channel); 1352 1353 return ret; 1354} 1355 1356/***************************\ 1357* Spur mitigation functions * 1358\***************************/ 1359 1360bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1361 struct ieee80211_channel *channel) 1362{ 1363 u8 refclk_freq; 1364 1365 if ((ah->ah_radio == AR5K_RF5112) || 1366 (ah->ah_radio == AR5K_RF5413) || 1367 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 1368 refclk_freq = 40; 1369 else 1370 refclk_freq = 32; 1371 1372 if ((channel->center_freq % refclk_freq != 0) && 1373 ((channel->center_freq % refclk_freq < 10) || 1374 (channel->center_freq % refclk_freq > 22))) 1375 return true; 1376 else 1377 return false; 1378} 1379 1380void 1381ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1382 struct ieee80211_channel *channel) 1383{ 1384 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1385 u32 mag_mask[4] = {0, 0, 0, 0}; 1386 u32 pilot_mask[2] = {0, 0}; 1387 /* Note: fbin values are scaled up by 2 */ 1388 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1389 s32 spur_delta_phase, spur_freq_sigma_delta; 1390 s32 spur_offset, num_symbols_x16; 1391 u8 num_symbol_offsets, i, freq_band; 1392 1393 /* Convert current frequency to fbin value (the same way channels 1394 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1395 * up by 2 so we can compare it later */ 1396 if (channel->hw_value & CHANNEL_2GHZ) { 1397 chan_fbin = (channel->center_freq - 2300) * 10; 1398 freq_band = AR5K_EEPROM_BAND_2GHZ; 1399 } else { 1400 chan_fbin = (channel->center_freq - 4900) * 10; 1401 freq_band = AR5K_EEPROM_BAND_5GHZ; 1402 } 1403 1404 /* Check if any spur_chan_fbin from EEPROM is 1405 * within our current channel's spur detection range */ 1406 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1407 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1408 /* XXX: Half/Quarter channels ?*/ 1409 if (channel->hw_value & CHANNEL_TURBO) 1410 spur_detection_window *= 2; 1411 1412 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1413 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1414 1415 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1416 * so it's zero if we got nothing from EEPROM */ 1417 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1418 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1419 break; 1420 } 1421 1422 if ((chan_fbin - spur_detection_window <= 1423 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1424 (chan_fbin + spur_detection_window >= 1425 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1426 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1427 break; 1428 } 1429 } 1430 1431 /* We need to enable spur filter for this channel */ 1432 if (spur_chan_fbin) { 1433 spur_offset = spur_chan_fbin - chan_fbin; 1434 /* 1435 * Calculate deltas: 1436 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1437 * spur_delta_phase -> spur_offset / chip_freq << 11 1438 * Note: Both values have 100KHz resolution 1439 */ 1440 /* XXX: Half/Quarter rate channels ? */ 1441 switch (channel->hw_value) { 1442 case CHANNEL_A: 1443 /* Both sample_freq and chip_freq are 40MHz */ 1444 spur_delta_phase = (spur_offset << 17) / 25; 1445 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1446 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1447 break; 1448 case CHANNEL_G: 1449 /* sample_freq -> 40MHz chip_freq -> 44MHz 1450 * (for b compatibility) */ 1451 spur_freq_sigma_delta = (spur_offset << 8) / 55; 1452 spur_delta_phase = (spur_offset << 17) / 25; 1453 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1454 break; 1455 case CHANNEL_T: 1456 case CHANNEL_TG: 1457 /* Both sample_freq and chip_freq are 80MHz */ 1458 spur_delta_phase = (spur_offset << 16) / 25; 1459 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1460 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; 1461 break; 1462 default: 1463 return; 1464 } 1465 1466 /* Calculate pilot and magnitude masks */ 1467 1468 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1469 * and divide by symbol_width to find how many symbols we have 1470 * Note: number of symbols is scaled up by 16 */ 1471 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1472 1473 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1474 if (!(num_symbols_x16 & 0xF)) 1475 /* _X_ */ 1476 num_symbol_offsets = 3; 1477 else 1478 /* _xx_ */ 1479 num_symbol_offsets = 4; 1480 1481 for (i = 0; i < num_symbol_offsets; i++) { 1482 1483 /* Calculate pilot mask */ 1484 s32 curr_sym_off = 1485 (num_symbols_x16 / 16) + i + 25; 1486 1487 /* Pilot magnitude mask seems to be a way to 1488 * declare the boundaries for our detection 1489 * window or something, it's 2 for the middle 1490 * value(s) where the symbol is expected to be 1491 * and 1 on the boundary values */ 1492 u8 plt_mag_map = 1493 (i == 0 || i == (num_symbol_offsets - 1)) 1494 ? 1 : 2; 1495 1496 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1497 if (curr_sym_off <= 25) 1498 pilot_mask[0] |= 1 << curr_sym_off; 1499 else if (curr_sym_off >= 27) 1500 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1501 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1502 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1503 1504 /* Calculate magnitude mask (for viterbi decoder) */ 1505 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1506 mag_mask[0] |= 1507 plt_mag_map << (curr_sym_off + 1) * 2; 1508 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1509 mag_mask[1] |= 1510 plt_mag_map << (curr_sym_off - 15) * 2; 1511 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1512 mag_mask[2] |= 1513 plt_mag_map << (curr_sym_off - 31) * 2; 1514 else if (curr_sym_off >= 46 && curr_sym_off <= 53) 1515 mag_mask[3] |= 1516 plt_mag_map << (curr_sym_off - 47) * 2; 1517 1518 } 1519 1520 /* Write settings on hw to enable spur filter */ 1521 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1522 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1523 /* XXX: Self correlator also ? */ 1524 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1525 AR5K_PHY_IQ_PILOT_MASK_EN | 1526 AR5K_PHY_IQ_CHAN_MASK_EN | 1527 AR5K_PHY_IQ_SPUR_FILT_EN); 1528 1529 /* Set delta phase and freq sigma delta */ 1530 ath5k_hw_reg_write(ah, 1531 AR5K_REG_SM(spur_delta_phase, 1532 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1533 AR5K_REG_SM(spur_freq_sigma_delta, 1534 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1535 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1536 AR5K_PHY_TIMING_11); 1537 1538 /* Write pilot masks */ 1539 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1540 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1541 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1542 pilot_mask[1]); 1543 1544 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1545 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1546 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1547 pilot_mask[1]); 1548 1549 /* Write magnitude masks */ 1550 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1551 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1552 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1553 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1554 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1555 mag_mask[3]); 1556 1557 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1558 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1559 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1560 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1561 AR5K_PHY_BIN_MASK2_4_MASK_4, 1562 mag_mask[3]); 1563 1564 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1565 AR5K_PHY_IQ_SPUR_FILT_EN) { 1566 /* Clean up spur mitigation settings and disable fliter */ 1567 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1568 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1569 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1570 AR5K_PHY_IQ_PILOT_MASK_EN | 1571 AR5K_PHY_IQ_CHAN_MASK_EN | 1572 AR5K_PHY_IQ_SPUR_FILT_EN); 1573 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1574 1575 /* Clear pilot masks */ 1576 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1577 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1578 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1579 0); 1580 1581 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1582 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1583 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1584 0); 1585 1586 /* Clear magnitude masks */ 1587 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1588 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1589 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1590 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1591 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1592 0); 1593 1594 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1595 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1596 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1597 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1598 AR5K_PHY_BIN_MASK2_4_MASK_4, 1599 0); 1600 } 1601} 1602 1603/********************\ 1604 Misc PHY functions 1605\********************/ 1606 1607int ath5k_hw_phy_disable(struct ath5k_hw *ah) 1608{ 1609 ATH5K_TRACE(ah->ah_sc); 1610 /*Just a try M.F.*/ 1611 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1612 1613 return 0; 1614} 1615 1616/* 1617 * Get the PHY Chip revision 1618 */ 1619u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 1620{ 1621 unsigned int i; 1622 u32 srev; 1623 u16 ret; 1624 1625 ATH5K_TRACE(ah->ah_sc); 1626 1627 /* 1628 * Set the radio chip access register 1629 */ 1630 switch (chan) { 1631 case CHANNEL_2GHZ: 1632 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 1633 break; 1634 case CHANNEL_5GHZ: 1635 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1636 break; 1637 default: 1638 return 0; 1639 } 1640 1641 mdelay(2); 1642 1643 /* ...wait until PHY is ready and read the selected radio revision */ 1644 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 1645 1646 for (i = 0; i < 8; i++) 1647 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 1648 1649 if (ah->ah_version == AR5K_AR5210) { 1650 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 1651 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 1652 } else { 1653 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 1654 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 1655 ((srev & 0x0f) << 4), 8); 1656 } 1657 1658 /* Reset to the 5GHz mode */ 1659 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1660 1661 return ret; 1662} 1663 1664/*****************\ 1665* Antenna control * 1666\*****************/ 1667 1668void /*TODO:Boundary check*/ 1669ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1670{ 1671 ATH5K_TRACE(ah->ah_sc); 1672 1673 if (ah->ah_version != AR5K_AR5210) 1674 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1675} 1676 1677unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) 1678{ 1679 ATH5K_TRACE(ah->ah_sc); 1680 1681 if (ah->ah_version != AR5K_AR5210) 1682 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7; 1683 1684 return false; /*XXX: What do we return for 5210 ?*/ 1685} 1686 1687/* 1688 * Enable/disable fast rx antenna diversity 1689 */ 1690static void 1691ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1692{ 1693 switch (ee_mode) { 1694 case AR5K_EEPROM_MODE_11G: 1695 /* XXX: This is set to 1696 * disabled on initvals !!! */ 1697 case AR5K_EEPROM_MODE_11A: 1698 if (enable) 1699 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1700 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1701 else 1702 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1703 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1704 break; 1705 case AR5K_EEPROM_MODE_11B: 1706 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1707 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1708 break; 1709 default: 1710 return; 1711 } 1712 1713 if (enable) { 1714 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1715 AR5K_PHY_RESTART_DIV_GC, 0xc); 1716 1717 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1718 AR5K_PHY_FAST_ANT_DIV_EN); 1719 } else { 1720 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1721 AR5K_PHY_RESTART_DIV_GC, 0x8); 1722 1723 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1724 AR5K_PHY_FAST_ANT_DIV_EN); 1725 } 1726} 1727 1728/* 1729 * Set antenna operating mode 1730 */ 1731void 1732ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1733{ 1734 struct ieee80211_channel *channel = &ah->ah_current_channel; 1735 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1736 bool use_def_for_sg; 1737 u8 def_ant, tx_ant, ee_mode; 1738 u32 sta_id1 = 0; 1739 1740 def_ant = ah->ah_def_ant; 1741 1742 ATH5K_TRACE(ah->ah_sc); 1743 1744 switch (channel->hw_value & CHANNEL_MODES) { 1745 case CHANNEL_A: 1746 case CHANNEL_T: 1747 case CHANNEL_XR: 1748 ee_mode = AR5K_EEPROM_MODE_11A; 1749 break; 1750 case CHANNEL_G: 1751 case CHANNEL_TG: 1752 ee_mode = AR5K_EEPROM_MODE_11G; 1753 break; 1754 case CHANNEL_B: 1755 ee_mode = AR5K_EEPROM_MODE_11B; 1756 break; 1757 default: 1758 ATH5K_ERR(ah->ah_sc, 1759 "invalid channel: %d\n", channel->center_freq); 1760 return; 1761 } 1762 1763 switch (ant_mode) { 1764 case AR5K_ANTMODE_DEFAULT: 1765 tx_ant = 0; 1766 use_def_for_tx = false; 1767 update_def_on_tx = false; 1768 use_def_for_rts = false; 1769 use_def_for_sg = false; 1770 fast_div = true; 1771 break; 1772 case AR5K_ANTMODE_FIXED_A: 1773 def_ant = 1; 1774 tx_ant = 0; 1775 use_def_for_tx = true; 1776 update_def_on_tx = false; 1777 use_def_for_rts = true; 1778 use_def_for_sg = true; 1779 fast_div = false; 1780 break; 1781 case AR5K_ANTMODE_FIXED_B: 1782 def_ant = 2; 1783 tx_ant = 0; 1784 use_def_for_tx = true; 1785 update_def_on_tx = false; 1786 use_def_for_rts = true; 1787 use_def_for_sg = true; 1788 fast_div = false; 1789 break; 1790 case AR5K_ANTMODE_SINGLE_AP: 1791 def_ant = 1; /* updated on tx */ 1792 tx_ant = 0; 1793 use_def_for_tx = true; 1794 update_def_on_tx = true; 1795 use_def_for_rts = true; 1796 use_def_for_sg = true; 1797 fast_div = true; 1798 break; 1799 case AR5K_ANTMODE_SECTOR_AP: 1800 tx_ant = 1; /* variable */ 1801 use_def_for_tx = false; 1802 update_def_on_tx = false; 1803 use_def_for_rts = true; 1804 use_def_for_sg = false; 1805 fast_div = false; 1806 break; 1807 case AR5K_ANTMODE_SECTOR_STA: 1808 tx_ant = 1; /* variable */ 1809 use_def_for_tx = true; 1810 update_def_on_tx = false; 1811 use_def_for_rts = true; 1812 use_def_for_sg = false; 1813 fast_div = true; 1814 break; 1815 case AR5K_ANTMODE_DEBUG: 1816 def_ant = 1; 1817 tx_ant = 2; 1818 use_def_for_tx = false; 1819 update_def_on_tx = false; 1820 use_def_for_rts = false; 1821 use_def_for_sg = false; 1822 fast_div = false; 1823 break; 1824 default: 1825 return; 1826 } 1827 1828 ah->ah_tx_ant = tx_ant; 1829 ah->ah_ant_mode = ant_mode; 1830 1831 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 1832 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 1833 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 1834 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 1835 1836 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 1837 1838 if (sta_id1) 1839 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 1840 1841 /* Note: set diversity before default antenna 1842 * because it won't work correctly */ 1843 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 1844 ath5k_hw_set_def_antenna(ah, def_ant); 1845} 1846 1847 1848/****************\ 1849* TX power setup * 1850\****************/ 1851 1852/* 1853 * Helper functions 1854 */ 1855 1856/* 1857 * Do linear interpolation between two given (x, y) points 1858 */ 1859static s16 1860ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 1861 s16 y_left, s16 y_right) 1862{ 1863 s16 ratio, result; 1864 1865 /* Avoid divide by zero and skip interpolation 1866 * if we have the same point */ 1867 if ((x_left == x_right) || (y_left == y_right)) 1868 return y_left; 1869 1870 /* 1871 * Since we use ints and not fps, we need to scale up in 1872 * order to get a sane ratio value (or else we 'll eg. get 1873 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 1874 * to have some accuracy both for 0.5 and 0.25 steps. 1875 */ 1876 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 1877 1878 /* Now scale down to be in range */ 1879 result = y_left + (ratio * (target - x_left) / 100); 1880 1881 return result; 1882} 1883 1884/* 1885 * Find vertical boundary (min pwr) for the linear PCDAC curve. 1886 * 1887 * Since we have the top of the curve and we draw the line below 1888 * until we reach 1 (1 pcdac step) we need to know which point 1889 * (x value) that is so that we don't go below y axis and have negative 1890 * pcdac values when creating the curve, or fill the table with zeroes. 1891 */ 1892static s16 1893ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 1894 const s16 *pwrL, const s16 *pwrR) 1895{ 1896 s8 tmp; 1897 s16 min_pwrL, min_pwrR; 1898 s16 pwr_i; 1899 1900 if (pwrL[0] == pwrL[1]) 1901 min_pwrL = pwrL[0]; 1902 else { 1903 pwr_i = pwrL[0]; 1904 do { 1905 pwr_i--; 1906 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1907 pwrL[0], pwrL[1], 1908 stepL[0], stepL[1]); 1909 } while (tmp > 1); 1910 1911 min_pwrL = pwr_i; 1912 } 1913 1914 if (pwrR[0] == pwrR[1]) 1915 min_pwrR = pwrR[0]; 1916 else { 1917 pwr_i = pwrR[0]; 1918 do { 1919 pwr_i--; 1920 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1921 pwrR[0], pwrR[1], 1922 stepR[0], stepR[1]); 1923 } while (tmp > 1); 1924 1925 min_pwrR = pwr_i; 1926 } 1927 1928 /* Keep the right boundary so that it works for both curves */ 1929 return max(min_pwrL, min_pwrR); 1930} 1931 1932/* 1933 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 1934 * Power to PCDAC curve. 1935 * 1936 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 1937 * steps (offsets) on y axis. Power can go up to 31.5dB and max 1938 * PCDAC/PDADC step for each curve is 64 but we can write more than 1939 * one curves on hw so we can go up to 128 (which is the max step we 1940 * can write on the final table). 1941 * 1942 * We write y values (PCDAC/PDADC steps) on hw. 1943 */ 1944static void 1945ath5k_create_power_curve(s16 pmin, s16 pmax, 1946 const s16 *pwr, const u8 *vpd, 1947 u8 num_points, 1948 u8 *vpd_table, u8 type) 1949{ 1950 u8 idx[2] = { 0, 1 }; 1951 s16 pwr_i = 2*pmin; 1952 int i; 1953 1954 if (num_points < 2) 1955 return; 1956 1957 /* We want the whole line, so adjust boundaries 1958 * to cover the entire power range. Note that 1959 * power values are already 0.25dB so no need 1960 * to multiply pwr_i by 2 */ 1961 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 1962 pwr_i = pmin; 1963 pmin = 0; 1964 pmax = 63; 1965 } 1966 1967 /* Find surrounding turning points (TPs) 1968 * and interpolate between them */ 1969 for (i = 0; (i <= (u16) (pmax - pmin)) && 1970 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 1971 1972 /* We passed the right TP, move to the next set of TPs 1973 * if we pass the last TP, extrapolate above using the last 1974 * two TPs for ratio */ 1975 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 1976 idx[0]++; 1977 idx[1]++; 1978 } 1979 1980 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 1981 pwr[idx[0]], pwr[idx[1]], 1982 vpd[idx[0]], vpd[idx[1]]); 1983 1984 /* Increase by 0.5dB 1985 * (0.25 dB units) */ 1986 pwr_i += 2; 1987 } 1988} 1989 1990/* 1991 * Get the surrounding per-channel power calibration piers 1992 * for a given frequency so that we can interpolate between 1993 * them and come up with an apropriate dataset for our current 1994 * channel. 1995 */ 1996static void 1997ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 1998 struct ieee80211_channel *channel, 1999 struct ath5k_chan_pcal_info **pcinfo_l, 2000 struct ath5k_chan_pcal_info **pcinfo_r) 2001{ 2002 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2003 struct ath5k_chan_pcal_info *pcinfo; 2004 u8 idx_l, idx_r; 2005 u8 mode, max, i; 2006 u32 target = channel->center_freq; 2007 2008 idx_l = 0; 2009 idx_r = 0; 2010 2011 if (!(channel->hw_value & CHANNEL_OFDM)) { 2012 pcinfo = ee->ee_pwr_cal_b; 2013 mode = AR5K_EEPROM_MODE_11B; 2014 } else if (channel->hw_value & CHANNEL_2GHZ) { 2015 pcinfo = ee->ee_pwr_cal_g; 2016 mode = AR5K_EEPROM_MODE_11G; 2017 } else { 2018 pcinfo = ee->ee_pwr_cal_a; 2019 mode = AR5K_EEPROM_MODE_11A; 2020 } 2021 max = ee->ee_n_piers[mode] - 1; 2022 2023 /* Frequency is below our calibrated 2024 * range. Use the lowest power curve 2025 * we have */ 2026 if (target < pcinfo[0].freq) { 2027 idx_l = idx_r = 0; 2028 goto done; 2029 } 2030 2031 /* Frequency is above our calibrated 2032 * range. Use the highest power curve 2033 * we have */ 2034 if (target > pcinfo[max].freq) { 2035 idx_l = idx_r = max; 2036 goto done; 2037 } 2038 2039 /* Frequency is inside our calibrated 2040 * channel range. Pick the surrounding 2041 * calibration piers so that we can 2042 * interpolate */ 2043 for (i = 0; i <= max; i++) { 2044 2045 /* Frequency matches one of our calibration 2046 * piers, no need to interpolate, just use 2047 * that calibration pier */ 2048 if (pcinfo[i].freq == target) { 2049 idx_l = idx_r = i; 2050 goto done; 2051 } 2052 2053 /* We found a calibration pier that's above 2054 * frequency, use this pier and the previous 2055 * one to interpolate */ 2056 if (target < pcinfo[i].freq) { 2057 idx_r = i; 2058 idx_l = idx_r - 1; 2059 goto done; 2060 } 2061 } 2062 2063done: 2064 *pcinfo_l = &pcinfo[idx_l]; 2065 *pcinfo_r = &pcinfo[idx_r]; 2066 2067 return; 2068} 2069 2070/* 2071 * Get the surrounding per-rate power calibration data 2072 * for a given frequency and interpolate between power 2073 * values to set max target power supported by hw for 2074 * each rate. 2075 */ 2076static void 2077ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2078 struct ieee80211_channel *channel, 2079 struct ath5k_rate_pcal_info *rates) 2080{ 2081 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2082 struct ath5k_rate_pcal_info *rpinfo; 2083 u8 idx_l, idx_r; 2084 u8 mode, max, i; 2085 u32 target = channel->center_freq; 2086 2087 idx_l = 0; 2088 idx_r = 0; 2089 2090 if (!(channel->hw_value & CHANNEL_OFDM)) { 2091 rpinfo = ee->ee_rate_tpwr_b; 2092 mode = AR5K_EEPROM_MODE_11B; 2093 } else if (channel->hw_value & CHANNEL_2GHZ) { 2094 rpinfo = ee->ee_rate_tpwr_g; 2095 mode = AR5K_EEPROM_MODE_11G; 2096 } else { 2097 rpinfo = ee->ee_rate_tpwr_a; 2098 mode = AR5K_EEPROM_MODE_11A; 2099 } 2100 max = ee->ee_rate_target_pwr_num[mode] - 1; 2101 2102 /* Get the surrounding calibration 2103 * piers - same as above */ 2104 if (target < rpinfo[0].freq) { 2105 idx_l = idx_r = 0; 2106 goto done; 2107 } 2108 2109 if (target > rpinfo[max].freq) { 2110 idx_l = idx_r = max; 2111 goto done; 2112 } 2113 2114 for (i = 0; i <= max; i++) { 2115 2116 if (rpinfo[i].freq == target) { 2117 idx_l = idx_r = i; 2118 goto done; 2119 } 2120 2121 if (target < rpinfo[i].freq) { 2122 idx_r = i; 2123 idx_l = idx_r - 1; 2124 goto done; 2125 } 2126 } 2127 2128done: 2129 /* Now interpolate power value, based on the frequency */ 2130 rates->freq = target; 2131 2132 rates->target_power_6to24 = 2133 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2134 rpinfo[idx_r].freq, 2135 rpinfo[idx_l].target_power_6to24, 2136 rpinfo[idx_r].target_power_6to24); 2137 2138 rates->target_power_36 = 2139 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2140 rpinfo[idx_r].freq, 2141 rpinfo[idx_l].target_power_36, 2142 rpinfo[idx_r].target_power_36); 2143 2144 rates->target_power_48 = 2145 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2146 rpinfo[idx_r].freq, 2147 rpinfo[idx_l].target_power_48, 2148 rpinfo[idx_r].target_power_48); 2149 2150 rates->target_power_54 = 2151 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2152 rpinfo[idx_r].freq, 2153 rpinfo[idx_l].target_power_54, 2154 rpinfo[idx_r].target_power_54); 2155} 2156 2157/* 2158 * Get the max edge power for this channel if 2159 * we have such data from EEPROM's Conformance Test 2160 * Limits (CTL), and limit max power if needed. 2161 */ 2162static void 2163ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2164 struct ieee80211_channel *channel) 2165{ 2166 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2167 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2168 u8 *ctl_val = ee->ee_ctl; 2169 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2170 s16 edge_pwr = 0; 2171 u8 rep_idx; 2172 u8 i, ctl_mode; 2173 u8 ctl_idx = 0xFF; 2174 u32 target = channel->center_freq; 2175 2176 ctl_mode = ath_regd_get_band_ctl(&ah->ah_regulatory, channel->band); 2177 2178 switch (channel->hw_value & CHANNEL_MODES) { 2179 case CHANNEL_A: 2180 ctl_mode |= AR5K_CTL_11A; 2181 break; 2182 case CHANNEL_G: 2183 ctl_mode |= AR5K_CTL_11G; 2184 break; 2185 case CHANNEL_B: 2186 ctl_mode |= AR5K_CTL_11B; 2187 break; 2188 case CHANNEL_T: 2189 ctl_mode |= AR5K_CTL_TURBO; 2190 break; 2191 case CHANNEL_TG: 2192 ctl_mode |= AR5K_CTL_TURBOG; 2193 break; 2194 case CHANNEL_XR: 2195 /* Fall through */ 2196 default: 2197 return; 2198 } 2199 2200 for (i = 0; i < ee->ee_ctls; i++) { 2201 if (ctl_val[i] == ctl_mode) { 2202 ctl_idx = i; 2203 break; 2204 } 2205 } 2206 2207 /* If we have a CTL dataset available grab it and find the 2208 * edge power for our frequency */ 2209 if (ctl_idx == 0xFF) 2210 return; 2211 2212 /* Edge powers are sorted by frequency from lower 2213 * to higher. Each CTL corresponds to 8 edge power 2214 * measurements. */ 2215 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2216 2217 /* Don't do boundaries check because we 2218 * might have more that one bands defined 2219 * for this mode */ 2220 2221 /* Get the edge power that's closer to our 2222 * frequency */ 2223 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2224 rep_idx += i; 2225 if (target <= rep[rep_idx].freq) 2226 edge_pwr = (s16) rep[rep_idx].edge; 2227 } 2228 2229 if (edge_pwr) 2230 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2231} 2232 2233 2234/* 2235 * Power to PCDAC table functions 2236 */ 2237 2238/* 2239 * Fill Power to PCDAC table on RF5111 2240 * 2241 * No further processing is needed for RF5111, the only thing we have to 2242 * do is fill the values below and above calibration range since eeprom data 2243 * may not cover the entire PCDAC table. 2244 */ 2245static void 2246ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2247 s16 *table_max) 2248{ 2249 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2250 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2251 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2252 s16 min_pwr, max_pwr; 2253 2254 /* Get table boundaries */ 2255 min_pwr = table_min[0]; 2256 pcdac_0 = pcdac_tmp[0]; 2257 2258 max_pwr = table_max[0]; 2259 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2260 2261 /* Extrapolate below minimum using pcdac_0 */ 2262 pcdac_i = 0; 2263 for (i = 0; i < min_pwr; i++) 2264 pcdac_out[pcdac_i++] = pcdac_0; 2265 2266 /* Copy values from pcdac_tmp */ 2267 pwr_idx = min_pwr; 2268 for (i = 0 ; pwr_idx <= max_pwr && 2269 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2270 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2271 pwr_idx++; 2272 } 2273 2274 /* Extrapolate above maximum */ 2275 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2276 pcdac_out[pcdac_i++] = pcdac_n; 2277 2278} 2279 2280/* 2281 * Combine available XPD Curves and fill Linear Power to PCDAC table 2282 * on RF5112 2283 * 2284 * RFX112 can have up to 2 curves (one for low txpower range and one for 2285 * higher txpower range). We need to put them both on pcdac_out and place 2286 * them in the correct location. In case we only have one curve available 2287 * just fit it on pcdac_out (it's supposed to cover the entire range of 2288 * available pwr levels since it's always the higher power curve). Extrapolate 2289 * below and above final table if needed. 2290 */ 2291static void 2292ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2293 s16 *table_max, u8 pdcurves) 2294{ 2295 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2296 u8 *pcdac_low_pwr; 2297 u8 *pcdac_high_pwr; 2298 u8 *pcdac_tmp; 2299 u8 pwr; 2300 s16 max_pwr_idx; 2301 s16 min_pwr_idx; 2302 s16 mid_pwr_idx = 0; 2303 /* Edge flag turs on the 7nth bit on the PCDAC 2304 * to delcare the higher power curve (force values 2305 * to be greater than 64). If we only have one curve 2306 * we don't need to set this, if we have 2 curves and 2307 * fill the table backwards this can also be used to 2308 * switch from higher power curve to lower power curve */ 2309 u8 edge_flag; 2310 int i; 2311 2312 /* When we have only one curve available 2313 * that's the higher power curve. If we have 2314 * two curves the first is the high power curve 2315 * and the next is the low power curve. */ 2316 if (pdcurves > 1) { 2317 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2318 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2319 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2320 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2321 2322 /* If table size goes beyond 31.5dB, keep the 2323 * upper 31.5dB range when setting tx power. 2324 * Note: 126 = 31.5 dB in quarter dB steps */ 2325 if (table_max[0] - table_min[1] > 126) 2326 min_pwr_idx = table_max[0] - 126; 2327 else 2328 min_pwr_idx = table_min[1]; 2329 2330 /* Since we fill table backwards 2331 * start from high power curve */ 2332 pcdac_tmp = pcdac_high_pwr; 2333 2334 edge_flag = 0x40; 2335#if 0 2336 /* If both min and max power limits are in lower 2337 * power curve's range, only use the low power curve. 2338 * TODO: min/max levels are related to target 2339 * power values requested from driver/user 2340 * XXX: Is this really needed ? */ 2341 if (min_pwr < table_max[1] && 2342 max_pwr < table_max[1]) { 2343 edge_flag = 0; 2344 pcdac_tmp = pcdac_low_pwr; 2345 max_pwr_idx = (table_max[1] - table_min[1])/2; 2346 } 2347#endif 2348 } else { 2349 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2350 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2351 min_pwr_idx = table_min[0]; 2352 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2353 pcdac_tmp = pcdac_high_pwr; 2354 edge_flag = 0; 2355 } 2356 2357 /* This is used when setting tx power*/ 2358 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2359 2360 /* Fill Power to PCDAC table backwards */ 2361 pwr = max_pwr_idx; 2362 for (i = 63; i >= 0; i--) { 2363 /* Entering lower power range, reset 2364 * edge flag and set pcdac_tmp to lower 2365 * power curve.*/ 2366 if (edge_flag == 0x40 && 2367 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2368 edge_flag = 0x00; 2369 pcdac_tmp = pcdac_low_pwr; 2370 pwr = mid_pwr_idx/2; 2371 } 2372 2373 /* Don't go below 1, extrapolate below if we have 2374 * already swithced to the lower power curve -or 2375 * we only have one curve and edge_flag is zero 2376 * anyway */ 2377 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2378 while (i >= 0) { 2379 pcdac_out[i] = pcdac_out[i + 1]; 2380 i--; 2381 } 2382 break; 2383 } 2384 2385 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2386 2387 /* Extrapolate above if pcdac is greater than 2388 * 126 -this can happen because we OR pcdac_out 2389 * value with edge_flag on high power curve */ 2390 if (pcdac_out[i] > 126) 2391 pcdac_out[i] = 126; 2392 2393 /* Decrease by a 0.5dB step */ 2394 pwr--; 2395 } 2396} 2397 2398/* Write PCDAC values on hw */ 2399static void 2400ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2401{ 2402 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2403 int i; 2404 2405 /* 2406 * Write TX power values 2407 */ 2408 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2409 ath5k_hw_reg_write(ah, 2410 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2411 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2412 AR5K_PHY_PCDAC_TXPOWER(i)); 2413 } 2414} 2415 2416 2417/* 2418 * Power to PDADC table functions 2419 */ 2420 2421/* 2422 * Set the gain boundaries and create final Power to PDADC table 2423 * 2424 * We can have up to 4 pd curves, we need to do a simmilar process 2425 * as we do for RF5112. This time we don't have an edge_flag but we 2426 * set the gain boundaries on a separate register. 2427 */ 2428static void 2429ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2430 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2431{ 2432 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2433 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2434 u8 *pdadc_tmp; 2435 s16 pdadc_0; 2436 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2437 u8 pd_gain_overlap; 2438 2439 /* Note: Register value is initialized on initvals 2440 * there is no feedback from hw. 2441 * XXX: What about pd_gain_overlap from EEPROM ? */ 2442 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2443 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2444 2445 /* Create final PDADC table */ 2446 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2447 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2448 2449 if (pdg == pdcurves - 1) 2450 /* 2 dB boundary stretch for last 2451 * (higher power) curve */ 2452 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2453 else 2454 /* Set gain boundary in the middle 2455 * between this curve and the next one */ 2456 gain_boundaries[pdg] = 2457 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2458 2459 /* Sanity check in case our 2 db stretch got out of 2460 * range. */ 2461 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2462 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2463 2464 /* For the first curve (lower power) 2465 * start from 0 dB */ 2466 if (pdg == 0) 2467 pdadc_0 = 0; 2468 else 2469 /* For the other curves use the gain overlap */ 2470 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2471 pd_gain_overlap; 2472 2473 /* Force each power step to be at least 0.5 dB */ 2474 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2475 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2476 else 2477 pwr_step = 1; 2478 2479 /* If pdadc_0 is negative, we need to extrapolate 2480 * below this pdgain by a number of pwr_steps */ 2481 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2482 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2483 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2484 pdadc_0++; 2485 } 2486 2487 /* Set last pwr level, using gain boundaries */ 2488 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2489 /* Limit it to be inside pwr range */ 2490 table_size = pwr_max[pdg] - pwr_min[pdg]; 2491 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2492 2493 /* Fill pdadc_out table */ 2494 while (pdadc_0 < max_idx) 2495 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2496 2497 /* Need to extrapolate above this pdgain? */ 2498 if (pdadc_n <= max_idx) 2499 continue; 2500 2501 /* Force each power step to be at least 0.5 dB */ 2502 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2503 pwr_step = pdadc_tmp[table_size - 1] - 2504 pdadc_tmp[table_size - 2]; 2505 else 2506 pwr_step = 1; 2507 2508 /* Extrapolate above */ 2509 while ((pdadc_0 < (s16) pdadc_n) && 2510 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2511 s16 tmp = pdadc_tmp[table_size - 1] + 2512 (pdadc_0 - max_idx) * pwr_step; 2513 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2514 pdadc_0++; 2515 } 2516 } 2517 2518 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2519 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2520 pdg++; 2521 } 2522 2523 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2524 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2525 pdadc_i++; 2526 } 2527 2528 /* Set gain boundaries */ 2529 ath5k_hw_reg_write(ah, 2530 AR5K_REG_SM(pd_gain_overlap, 2531 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2532 AR5K_REG_SM(gain_boundaries[0], 2533 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2534 AR5K_REG_SM(gain_boundaries[1], 2535 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2536 AR5K_REG_SM(gain_boundaries[2], 2537 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2538 AR5K_REG_SM(gain_boundaries[3], 2539 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2540 AR5K_PHY_TPC_RG5); 2541 2542 /* Used for setting rate power table */ 2543 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2544 2545} 2546 2547/* Write PDADC values on hw */ 2548static void 2549ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2550 u8 pdcurves, u8 *pdg_to_idx) 2551{ 2552 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2553 u32 reg; 2554 u8 i; 2555 2556 /* Select the right pdgain curves */ 2557 2558 /* Clear current settings */ 2559 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2560 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2561 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2562 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2563 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2564 2565 /* 2566 * Use pd_gains curve from eeprom 2567 * 2568 * This overrides the default setting from initvals 2569 * in case some vendors (e.g. Zcomax) don't use the default 2570 * curves. If we don't honor their settings we 'll get a 2571 * 5dB (1 * gain overlap ?) drop. 2572 */ 2573 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2574 2575 switch (pdcurves) { 2576 case 3: 2577 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2578 /* Fall through */ 2579 case 2: 2580 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2581 /* Fall through */ 2582 case 1: 2583 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2584 break; 2585 } 2586 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2587 2588 /* 2589 * Write TX power values 2590 */ 2591 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2592 ath5k_hw_reg_write(ah, 2593 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2594 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2595 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2596 ((pdadc_out[4*i + 3] & 0xff) << 24), 2597 AR5K_PHY_PDADC_TXPOWER(i)); 2598 } 2599} 2600 2601 2602/* 2603 * Common code for PCDAC/PDADC tables 2604 */ 2605 2606/* 2607 * This is the main function that uses all of the above 2608 * to set PCDAC/PDADC table on hw for the current channel. 2609 * This table is used for tx power calibration on the basband, 2610 * without it we get weird tx power levels and in some cases 2611 * distorted spectral mask 2612 */ 2613static int 2614ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2615 struct ieee80211_channel *channel, 2616 u8 ee_mode, u8 type) 2617{ 2618 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2619 struct ath5k_chan_pcal_info *pcinfo_L; 2620 struct ath5k_chan_pcal_info *pcinfo_R; 2621 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2622 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2623 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2624 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2625 u8 *tmpL; 2626 u8 *tmpR; 2627 u32 target = channel->center_freq; 2628 int pdg, i; 2629 2630 /* Get surounding freq piers for this channel */ 2631 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2632 &pcinfo_L, 2633 &pcinfo_R); 2634 2635 /* Loop over pd gain curves on 2636 * surounding freq piers by index */ 2637 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2638 2639 /* Fill curves in reverse order 2640 * from lower power (max gain) 2641 * to higher power. Use curve -> idx 2642 * backmaping we did on eeprom init */ 2643 u8 idx = pdg_curve_to_idx[pdg]; 2644 2645 /* Grab the needed curves by index */ 2646 pdg_L = &pcinfo_L->pd_curves[idx]; 2647 pdg_R = &pcinfo_R->pd_curves[idx]; 2648 2649 /* Initialize the temp tables */ 2650 tmpL = ah->ah_txpower.tmpL[pdg]; 2651 tmpR = ah->ah_txpower.tmpR[pdg]; 2652 2653 /* Set curve's x boundaries and create 2654 * curves so that they cover the same 2655 * range (if we don't do that one table 2656 * will have values on some range and the 2657 * other one won't have any so interpolation 2658 * will fail) */ 2659 table_min[pdg] = min(pdg_L->pd_pwr[0], 2660 pdg_R->pd_pwr[0]) / 2; 2661 2662 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2663 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2664 2665 /* Now create the curves on surrounding channels 2666 * and interpolate if needed to get the final 2667 * curve for this gain on this channel */ 2668 switch (type) { 2669 case AR5K_PWRTABLE_LINEAR_PCDAC: 2670 /* Override min/max so that we don't loose 2671 * accuracy (don't divide by 2) */ 2672 table_min[pdg] = min(pdg_L->pd_pwr[0], 2673 pdg_R->pd_pwr[0]); 2674 2675 table_max[pdg] = 2676 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2677 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2678 2679 /* Override minimum so that we don't get 2680 * out of bounds while extrapolating 2681 * below. Don't do this when we have 2 2682 * curves and we are on the high power curve 2683 * because table_min is ok in this case */ 2684 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2685 2686 table_min[pdg] = 2687 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2688 pdg_R->pd_step, 2689 pdg_L->pd_pwr, 2690 pdg_R->pd_pwr); 2691 2692 /* Don't go too low because we will 2693 * miss the upper part of the curve. 2694 * Note: 126 = 31.5dB (max power supported) 2695 * in 0.25dB units */ 2696 if (table_max[pdg] - table_min[pdg] > 126) 2697 table_min[pdg] = table_max[pdg] - 126; 2698 } 2699 2700 /* Fall through */ 2701 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2702 case AR5K_PWRTABLE_PWR_TO_PDADC: 2703 2704 ath5k_create_power_curve(table_min[pdg], 2705 table_max[pdg], 2706 pdg_L->pd_pwr, 2707 pdg_L->pd_step, 2708 pdg_L->pd_points, tmpL, type); 2709 2710 /* We are in a calibration 2711 * pier, no need to interpolate 2712 * between freq piers */ 2713 if (pcinfo_L == pcinfo_R) 2714 continue; 2715 2716 ath5k_create_power_curve(table_min[pdg], 2717 table_max[pdg], 2718 pdg_R->pd_pwr, 2719 pdg_R->pd_step, 2720 pdg_R->pd_points, tmpR, type); 2721 break; 2722 default: 2723 return -EINVAL; 2724 } 2725 2726 /* Interpolate between curves 2727 * of surounding freq piers to 2728 * get the final curve for this 2729 * pd gain. Re-use tmpL for interpolation 2730 * output */ 2731 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2732 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2733 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2734 (s16) pcinfo_L->freq, 2735 (s16) pcinfo_R->freq, 2736 (s16) tmpL[i], 2737 (s16) tmpR[i]); 2738 } 2739 } 2740 2741 /* Now we have a set of curves for this 2742 * channel on tmpL (x range is table_max - table_min 2743 * and y values are tmpL[pdg][]) sorted in the same 2744 * order as EEPROM (because we've used the backmaping). 2745 * So for RF5112 it's from higher power to lower power 2746 * and for RF2413 it's from lower power to higher power. 2747 * For RF5111 we only have one curve. */ 2748 2749 /* Fill min and max power levels for this 2750 * channel by interpolating the values on 2751 * surounding channels to complete the dataset */ 2752 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2753 (s16) pcinfo_L->freq, 2754 (s16) pcinfo_R->freq, 2755 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2756 2757 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2758 (s16) pcinfo_L->freq, 2759 (s16) pcinfo_R->freq, 2760 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2761 2762 /* We are ready to go, fill PCDAC/PDADC 2763 * table and write settings on hardware */ 2764 switch (type) { 2765 case AR5K_PWRTABLE_LINEAR_PCDAC: 2766 /* For RF5112 we can have one or two curves 2767 * and each curve covers a certain power lvl 2768 * range so we need to do some more processing */ 2769 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2770 ee->ee_pd_gains[ee_mode]); 2771 2772 /* Set txp.offset so that we can 2773 * match max power value with max 2774 * table index */ 2775 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2776 2777 /* Write settings on hw */ 2778 ath5k_setup_pcdac_table(ah); 2779 break; 2780 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2781 /* We are done for RF5111 since it has only 2782 * one curve, just fit the curve on the table */ 2783 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2784 2785 /* No rate powertable adjustment for RF5111 */ 2786 ah->ah_txpower.txp_min_idx = 0; 2787 ah->ah_txpower.txp_offset = 0; 2788 2789 /* Write settings on hw */ 2790 ath5k_setup_pcdac_table(ah); 2791 break; 2792 case AR5K_PWRTABLE_PWR_TO_PDADC: 2793 /* Set PDADC boundaries and fill 2794 * final PDADC table */ 2795 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2796 ee->ee_pd_gains[ee_mode]); 2797 2798 /* Write settings on hw */ 2799 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2800 2801 /* Set txp.offset, note that table_min 2802 * can be negative */ 2803 ah->ah_txpower.txp_offset = table_min[0]; 2804 break; 2805 default: 2806 return -EINVAL; 2807 } 2808 2809 return 0; 2810} 2811 2812 2813/* 2814 * Per-rate tx power setting 2815 * 2816 * This is the code that sets the desired tx power (below 2817 * maximum) on hw for each rate (we also have TPC that sets 2818 * power per packet). We do that by providing an index on the 2819 * PCDAC/PDADC table we set up. 2820 */ 2821 2822/* 2823 * Set rate power table 2824 * 2825 * For now we only limit txpower based on maximum tx power 2826 * supported by hw (what's inside rate_info). We need to limit 2827 * this even more, based on regulatory domain etc. 2828 * 2829 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2830 * and is indexed as follows: 2831 * rates[0] - rates[7] -> OFDM rates 2832 * rates[8] - rates[14] -> CCK rates 2833 * rates[15] -> XR rates (they all have the same power) 2834 */ 2835static void 2836ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2837 struct ath5k_rate_pcal_info *rate_info, 2838 u8 ee_mode) 2839{ 2840 unsigned int i; 2841 u16 *rates; 2842 2843 /* max_pwr is power level we got from driver/user in 0.5dB 2844 * units, switch to 0.25dB units so we can compare */ 2845 max_pwr *= 2; 2846 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2847 2848 /* apply rate limits */ 2849 rates = ah->ah_txpower.txp_rates_power_table; 2850 2851 /* OFDM rates 6 to 24Mb/s */ 2852 for (i = 0; i < 5; i++) 2853 rates[i] = min(max_pwr, rate_info->target_power_6to24); 2854 2855 /* Rest OFDM rates */ 2856 rates[5] = min(rates[0], rate_info->target_power_36); 2857 rates[6] = min(rates[0], rate_info->target_power_48); 2858 rates[7] = min(rates[0], rate_info->target_power_54); 2859 2860 /* CCK rates */ 2861 /* 1L */ 2862 rates[8] = min(rates[0], rate_info->target_power_6to24); 2863 /* 2L */ 2864 rates[9] = min(rates[0], rate_info->target_power_36); 2865 /* 2S */ 2866 rates[10] = min(rates[0], rate_info->target_power_36); 2867 /* 5L */ 2868 rates[11] = min(rates[0], rate_info->target_power_48); 2869 /* 5S */ 2870 rates[12] = min(rates[0], rate_info->target_power_48); 2871 /* 11L */ 2872 rates[13] = min(rates[0], rate_info->target_power_54); 2873 /* 11S */ 2874 rates[14] = min(rates[0], rate_info->target_power_54); 2875 2876 /* XR rates */ 2877 rates[15] = min(rates[0], rate_info->target_power_6to24); 2878 2879 /* CCK rates have different peak to average ratio 2880 * so we have to tweak their power so that gainf 2881 * correction works ok. For this we use OFDM to 2882 * CCK delta from eeprom */ 2883 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 2884 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 2885 for (i = 8; i <= 15; i++) 2886 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 2887 2888 /* Now that we have all rates setup use table offset to 2889 * match the power range set by user with the power indices 2890 * on PCDAC/PDADC table */ 2891 for (i = 0; i < 16; i++) { 2892 rates[i] += ah->ah_txpower.txp_offset; 2893 /* Don't get out of bounds */ 2894 if (rates[i] > 63) 2895 rates[i] = 63; 2896 } 2897 2898 /* Min/max in 0.25dB units */ 2899 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 2900 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 2901 ah->ah_txpower.txp_ofdm = rates[7]; 2902} 2903 2904 2905/* 2906 * Set transmition power 2907 */ 2908int 2909ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 2910 u8 ee_mode, u8 txpower) 2911{ 2912 struct ath5k_rate_pcal_info rate_info; 2913 u8 type; 2914 int ret; 2915 2916 ATH5K_TRACE(ah->ah_sc); 2917 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2918 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 2919 return -EINVAL; 2920 } 2921 if (txpower == 0) 2922 txpower = AR5K_TUNE_DEFAULT_TXPOWER; 2923 2924 /* Reset TX power values */ 2925 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 2926 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 2927 ah->ah_txpower.txp_min_pwr = 0; 2928 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 2929 2930 /* Initialize TX power table */ 2931 switch (ah->ah_radio) { 2932 case AR5K_RF5111: 2933 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 2934 break; 2935 case AR5K_RF5112: 2936 type = AR5K_PWRTABLE_LINEAR_PCDAC; 2937 break; 2938 case AR5K_RF2413: 2939 case AR5K_RF5413: 2940 case AR5K_RF2316: 2941 case AR5K_RF2317: 2942 case AR5K_RF2425: 2943 type = AR5K_PWRTABLE_PWR_TO_PDADC; 2944 break; 2945 default: 2946 return -EINVAL; 2947 } 2948 2949 /* FIXME: Only on channel/mode change */ 2950 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 2951 if (ret) 2952 return ret; 2953 2954 /* Limit max power if we have a CTL available */ 2955 ath5k_get_max_ctl_power(ah, channel); 2956 2957 /* FIXME: Tx power limit for this regdomain 2958 * XXX: Mac80211/CRDA will do that anyway ? */ 2959 2960 /* FIXME: Antenna reduction stuff */ 2961 2962 /* FIXME: Limit power on turbo modes */ 2963 2964 /* FIXME: TPC scale reduction */ 2965 2966 /* Get surounding channels for per-rate power table 2967 * calibration */ 2968 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 2969 2970 /* Setup rate power table */ 2971 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 2972 2973 /* Write rate power table on hw */ 2974 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 2975 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 2976 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 2977 2978 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 2979 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 2980 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 2981 2982 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 2983 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 2984 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 2985 2986 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 2987 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 2988 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 2989 2990 /* FIXME: TPC support */ 2991 if (ah->ah_txpower.txp_tpc) { 2992 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 2993 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2994 2995 ath5k_hw_reg_write(ah, 2996 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 2997 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 2998 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 2999 AR5K_TPC); 3000 } else { 3001 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3002 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3003 } 3004 3005 return 0; 3006} 3007 3008int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3009{ 3010 /*Just a try M.F.*/ 3011 struct ieee80211_channel *channel = &ah->ah_current_channel; 3012 u8 ee_mode; 3013 3014 ATH5K_TRACE(ah->ah_sc); 3015 3016 switch (channel->hw_value & CHANNEL_MODES) { 3017 case CHANNEL_A: 3018 case CHANNEL_T: 3019 case CHANNEL_XR: 3020 ee_mode = AR5K_EEPROM_MODE_11A; 3021 break; 3022 case CHANNEL_G: 3023 case CHANNEL_TG: 3024 ee_mode = AR5K_EEPROM_MODE_11G; 3025 break; 3026 case CHANNEL_B: 3027 ee_mode = AR5K_EEPROM_MODE_11B; 3028 break; 3029 default: 3030 ATH5K_ERR(ah->ah_sc, 3031 "invalid channel: %d\n", channel->center_freq); 3032 return -EINVAL; 3033 } 3034 3035 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3036 "changing txpower to %d\n", txpower); 3037 3038 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3039} 3040 3041#undef _ATH5K_PHY 3042