phy.c revision 73a06a683455f472cc09ad249064c66a41e29e39
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32 33/******************\ 34* Helper functions * 35\******************/ 36 37/* 38 * Get the PHY Chip revision 39 */ 40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41{ 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81} 82 83/* 84 * Check if a channel is supported 85 */ 86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87{ 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99} 100 101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103{ 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119} 120 121/* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127{ 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200} 201 202/** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219{ 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 switch (ah->ah_bwmode) { 232 case AR5K_BWMODE_40MHZ: 233 clock = 40 * 2; 234 break; 235 case AR5K_BWMODE_10MHZ: 236 clock = 40 / 2; 237 break; 238 case AR5K_BWMODE_5MHZ: 239 clock = 40 / 4; 240 break; 241 default: 242 clock = 40; 243 break; 244 } 245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 246 247 /* Get exponent 248 * ALGO: coef_exp = 14 - highest set bit position */ 249 coef_exp = ilog2(coef_scaled); 250 251 /* Doesn't make sense if it's zero*/ 252 if (!coef_scaled || !coef_exp) 253 return -EINVAL; 254 255 /* Note: we've shifted coef_scaled by 24 */ 256 coef_exp = 14 - (coef_exp - 24); 257 258 259 /* Get mantissa (significant digits) 260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 261 coef_man = coef_scaled + 262 (1 << (24 - coef_exp - 1)); 263 264 /* Calculate delta slope coefficient exponent 265 * and mantissa (remove scaling) and set them on hw */ 266 ds_coef_man = coef_man >> (24 - coef_exp); 267 ds_coef_exp = coef_exp - 16; 268 269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 273 274 return 0; 275} 276 277int ath5k_hw_phy_disable(struct ath5k_hw *ah) 278{ 279 /*Just a try M.F.*/ 280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 281 282 return 0; 283} 284 285 286/**********************\ 287* RF Gain optimization * 288\**********************/ 289 290/* 291 * This code is used to optimize RF gain on different environments 292 * (temperature mostly) based on feedback from a power detector. 293 * 294 * It's only used on RF5111 and RF5112, later RF chips seem to have 295 * auto adjustment on hw -notice they have a much smaller BANK 7 and 296 * no gain optimization ladder-. 297 * 298 * For more infos check out this patent doc 299 * http://www.freepatentsonline.com/7400691.html 300 * 301 * This paper describes power drops as seen on the receiver due to 302 * probe packets 303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 304 * %20of%20Power%20Control.pdf 305 * 306 * And this is the MadWiFi bug entry related to the above 307 * http://madwifi-project.org/ticket/1659 308 * with various measurements and diagrams 309 * 310 * TODO: Deal with power drops due to probes by setting an apropriate 311 * tx power on the probe packets ! Make this part of the calibration process. 312 */ 313 314/* Initialize ah_gain durring attach */ 315int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 316{ 317 /* Initialize the gain optimization values */ 318 switch (ah->ah_radio) { 319 case AR5K_RF5111: 320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 321 ah->ah_gain.g_low = 20; 322 ah->ah_gain.g_high = 35; 323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 324 break; 325 case AR5K_RF5112: 326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 327 ah->ah_gain.g_low = 20; 328 ah->ah_gain.g_high = 85; 329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 330 break; 331 default: 332 return -EINVAL; 333 } 334 335 return 0; 336} 337 338/* Schedule a gain probe check on the next transmited packet. 339 * That means our next packet is going to be sent with lower 340 * tx power and a Peak to Average Power Detector (PAPD) will try 341 * to measure the gain. 342 * 343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 344 * just after we enable the probe so that we don't mess with 345 * standard traffic ? Maybe it's time to use sw interrupts and 346 * a probe tasklet !!! 347 */ 348static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 349{ 350 351 /* Skip if gain calibration is inactive or 352 * we already handle a probe request */ 353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 354 return; 355 356 /* Send the packet with 2dB below max power as 357 * patent doc suggest */ 358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 359 AR5K_PHY_PAPD_PROBE_TXPOWER) | 360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 361 362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 363 364} 365 366/* Calculate gain_F measurement correction 367 * based on the current step for RF5112 rev. 2 */ 368static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 369{ 370 u32 mix, step; 371 u32 *rf; 372 const struct ath5k_gain_opt *go; 373 const struct ath5k_gain_opt_step *g_step; 374 const struct ath5k_rf_reg *rf_regs; 375 376 /* Only RF5112 Rev. 2 supports it */ 377 if ((ah->ah_radio != AR5K_RF5112) || 378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 379 return 0; 380 381 go = &rfgain_opt_5112; 382 rf_regs = rf_regs_5112a; 383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 384 385 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 386 387 if (ah->ah_rf_banks == NULL) 388 return 0; 389 390 rf = ah->ah_rf_banks; 391 ah->ah_gain.g_f_corr = 0; 392 393 /* No VGA (Variable Gain Amplifier) override, skip */ 394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 395 return 0; 396 397 /* Mix gain stepping */ 398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 399 400 /* Mix gain override */ 401 mix = g_step->gos_param[0]; 402 403 switch (mix) { 404 case 3: 405 ah->ah_gain.g_f_corr = step * 2; 406 break; 407 case 2: 408 ah->ah_gain.g_f_corr = (step - 5) * 2; 409 break; 410 case 1: 411 ah->ah_gain.g_f_corr = step; 412 break; 413 default: 414 ah->ah_gain.g_f_corr = 0; 415 break; 416 } 417 418 return ah->ah_gain.g_f_corr; 419} 420 421/* Check if current gain_F measurement is in the range of our 422 * power detector windows. If we get a measurement outside range 423 * we know it's not accurate (detectors can't measure anything outside 424 * their detection window) so we must ignore it */ 425static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 426{ 427 const struct ath5k_rf_reg *rf_regs; 428 u32 step, mix_ovr, level[4]; 429 u32 *rf; 430 431 if (ah->ah_rf_banks == NULL) 432 return false; 433 434 rf = ah->ah_rf_banks; 435 436 if (ah->ah_radio == AR5K_RF5111) { 437 438 rf_regs = rf_regs_5111; 439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 440 441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 442 false); 443 444 level[0] = 0; 445 level[1] = (step == 63) ? 50 : step + 4; 446 level[2] = (step != 63) ? 64 : level[0]; 447 level[3] = level[2] + 50 ; 448 449 ah->ah_gain.g_high = level[3] - 450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 451 ah->ah_gain.g_low = level[0] + 452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 453 } else { 454 455 rf_regs = rf_regs_5112; 456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 457 458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 459 false); 460 461 level[0] = level[2] = 0; 462 463 if (mix_ovr == 1) { 464 level[1] = level[3] = 83; 465 } else { 466 level[1] = level[3] = 107; 467 ah->ah_gain.g_high = 55; 468 } 469 } 470 471 return (ah->ah_gain.g_current >= level[0] && 472 ah->ah_gain.g_current <= level[1]) || 473 (ah->ah_gain.g_current >= level[2] && 474 ah->ah_gain.g_current <= level[3]); 475} 476 477/* Perform gain_F adjustment by choosing the right set 478 * of parameters from RF gain optimization ladder */ 479static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 480{ 481 const struct ath5k_gain_opt *go; 482 const struct ath5k_gain_opt_step *g_step; 483 int ret = 0; 484 485 switch (ah->ah_radio) { 486 case AR5K_RF5111: 487 go = &rfgain_opt_5111; 488 break; 489 case AR5K_RF5112: 490 go = &rfgain_opt_5112; 491 break; 492 default: 493 return 0; 494 } 495 496 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 497 498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 499 500 /* Reached maximum */ 501 if (ah->ah_gain.g_step_idx == 0) 502 return -1; 503 504 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 505 ah->ah_gain.g_target >= ah->ah_gain.g_high && 506 ah->ah_gain.g_step_idx > 0; 507 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 508 ah->ah_gain.g_target -= 2 * 509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 510 g_step->gos_gain); 511 512 ret = 1; 513 goto done; 514 } 515 516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 517 518 /* Reached minimum */ 519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 520 return -2; 521 522 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 523 ah->ah_gain.g_target <= ah->ah_gain.g_low && 524 ah->ah_gain.g_step_idx < go->go_steps_count-1; 525 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 526 ah->ah_gain.g_target -= 2 * 527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 528 g_step->gos_gain); 529 530 ret = 2; 531 goto done; 532 } 533 534done: 535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 536 "ret %d, gain step %u, current gain %u, target gain %u\n", 537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 538 ah->ah_gain.g_target); 539 540 return ret; 541} 542 543/* Main callback for thermal RF gain calibration engine 544 * Check for a new gain reading and schedule an adjustment 545 * if needed. 546 * 547 * TODO: Use sw interrupt to schedule reset if gain_F needs 548 * adjustment */ 549enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 550{ 551 u32 data, type; 552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 553 554 if (ah->ah_rf_banks == NULL || 555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 556 return AR5K_RFGAIN_INACTIVE; 557 558 /* No check requested, either engine is inactive 559 * or an adjustment is already requested */ 560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 561 goto done; 562 563 /* Read the PAPD (Peak to Average Power Detector) 564 * register */ 565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 566 567 /* No probe is scheduled, read gain_F measurement */ 568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 571 572 /* If tx packet is CCK correct the gain_F measurement 573 * by cck ofdm gain delta */ 574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 576 ah->ah_gain.g_current += 577 ee->ee_cck_ofdm_gain_delta; 578 else 579 ah->ah_gain.g_current += 580 AR5K_GAIN_CCK_PROBE_CORR; 581 } 582 583 /* Further correct gain_F measurement for 584 * RF5112A radios */ 585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 586 ath5k_hw_rf_gainf_corr(ah); 587 ah->ah_gain.g_current = 588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 590 0; 591 } 592 593 /* Check if measurement is ok and if we need 594 * to adjust gain, schedule a gain adjustment, 595 * else switch back to the acive state */ 596 if (ath5k_hw_rf_check_gainf_readback(ah) && 597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 598 ath5k_hw_rf_gainf_adjust(ah)) { 599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 600 } else { 601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 602 } 603 } 604 605done: 606 return ah->ah_gain.g_state; 607} 608 609/* Write initial RF gain table to set the RF sensitivity 610 * this one works on all RF chips and has nothing to do 611 * with gain_F calibration */ 612static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 613{ 614 const struct ath5k_ini_rfgain *ath5k_rfg; 615 unsigned int i, size; 616 617 switch (ah->ah_radio) { 618 case AR5K_RF5111: 619 ath5k_rfg = rfgain_5111; 620 size = ARRAY_SIZE(rfgain_5111); 621 break; 622 case AR5K_RF5112: 623 ath5k_rfg = rfgain_5112; 624 size = ARRAY_SIZE(rfgain_5112); 625 break; 626 case AR5K_RF2413: 627 ath5k_rfg = rfgain_2413; 628 size = ARRAY_SIZE(rfgain_2413); 629 break; 630 case AR5K_RF2316: 631 ath5k_rfg = rfgain_2316; 632 size = ARRAY_SIZE(rfgain_2316); 633 break; 634 case AR5K_RF5413: 635 ath5k_rfg = rfgain_5413; 636 size = ARRAY_SIZE(rfgain_5413); 637 break; 638 case AR5K_RF2317: 639 case AR5K_RF2425: 640 ath5k_rfg = rfgain_2425; 641 size = ARRAY_SIZE(rfgain_2425); 642 break; 643 default: 644 return -EINVAL; 645 } 646 647 switch (freq) { 648 case AR5K_INI_RFGAIN_2GHZ: 649 case AR5K_INI_RFGAIN_5GHZ: 650 break; 651 default: 652 return -EINVAL; 653 } 654 655 for (i = 0; i < size; i++) { 656 AR5K_REG_WAIT(i); 657 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 658 (u32)ath5k_rfg[i].rfg_register); 659 } 660 661 return 0; 662} 663 664 665 666/********************\ 667* RF Registers setup * 668\********************/ 669 670/* 671 * Setup RF registers by writing RF buffer on hw 672 */ 673static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 674 struct ieee80211_channel *channel, unsigned int mode) 675{ 676 const struct ath5k_rf_reg *rf_regs; 677 const struct ath5k_ini_rfbuffer *ini_rfb; 678 const struct ath5k_gain_opt *go = NULL; 679 const struct ath5k_gain_opt_step *g_step; 680 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 681 u8 ee_mode = 0; 682 u32 *rfb; 683 int i, obdb = -1, bank = -1; 684 685 switch (ah->ah_radio) { 686 case AR5K_RF5111: 687 rf_regs = rf_regs_5111; 688 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 689 ini_rfb = rfb_5111; 690 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 691 go = &rfgain_opt_5111; 692 break; 693 case AR5K_RF5112: 694 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 695 rf_regs = rf_regs_5112a; 696 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 697 ini_rfb = rfb_5112a; 698 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 699 } else { 700 rf_regs = rf_regs_5112; 701 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 702 ini_rfb = rfb_5112; 703 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 704 } 705 go = &rfgain_opt_5112; 706 break; 707 case AR5K_RF2413: 708 rf_regs = rf_regs_2413; 709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 710 ini_rfb = rfb_2413; 711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 712 break; 713 case AR5K_RF2316: 714 rf_regs = rf_regs_2316; 715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 716 ini_rfb = rfb_2316; 717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 718 break; 719 case AR5K_RF5413: 720 rf_regs = rf_regs_5413; 721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 722 ini_rfb = rfb_5413; 723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 724 break; 725 case AR5K_RF2317: 726 rf_regs = rf_regs_2425; 727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 728 ini_rfb = rfb_2317; 729 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 730 break; 731 case AR5K_RF2425: 732 rf_regs = rf_regs_2425; 733 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 734 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 735 ini_rfb = rfb_2425; 736 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 737 } else { 738 ini_rfb = rfb_2417; 739 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 740 } 741 break; 742 default: 743 return -EINVAL; 744 } 745 746 /* If it's the first time we set RF buffer, allocate 747 * ah->ah_rf_banks based on ah->ah_rf_banks_size 748 * we set above */ 749 if (ah->ah_rf_banks == NULL) { 750 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 751 GFP_KERNEL); 752 if (ah->ah_rf_banks == NULL) { 753 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 754 return -ENOMEM; 755 } 756 } 757 758 /* Copy values to modify them */ 759 rfb = ah->ah_rf_banks; 760 761 for (i = 0; i < ah->ah_rf_banks_size; i++) { 762 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 763 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 764 return -EINVAL; 765 } 766 767 /* Bank changed, write down the offset */ 768 if (bank != ini_rfb[i].rfb_bank) { 769 bank = ini_rfb[i].rfb_bank; 770 ah->ah_offset[bank] = i; 771 } 772 773 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 774 } 775 776 /* Set Output and Driver bias current (OB/DB) */ 777 if (channel->hw_value & CHANNEL_2GHZ) { 778 779 if (channel->hw_value & CHANNEL_CCK) 780 ee_mode = AR5K_EEPROM_MODE_11B; 781 else 782 ee_mode = AR5K_EEPROM_MODE_11G; 783 784 /* For RF511X/RF211X combination we 785 * use b_OB and b_DB parameters stored 786 * in eeprom on ee->ee_ob[ee_mode][0] 787 * 788 * For all other chips we use OB/DB for 2Ghz 789 * stored in the b/g modal section just like 790 * 802.11a on ee->ee_ob[ee_mode][1] */ 791 if ((ah->ah_radio == AR5K_RF5111) || 792 (ah->ah_radio == AR5K_RF5112)) 793 obdb = 0; 794 else 795 obdb = 1; 796 797 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 798 AR5K_RF_OB_2GHZ, true); 799 800 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 801 AR5K_RF_DB_2GHZ, true); 802 803 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 804 } else if ((channel->hw_value & CHANNEL_5GHZ) || 805 (ah->ah_radio == AR5K_RF5111)) { 806 807 /* For 11a, Turbo and XR we need to choose 808 * OB/DB based on frequency range */ 809 ee_mode = AR5K_EEPROM_MODE_11A; 810 obdb = channel->center_freq >= 5725 ? 3 : 811 (channel->center_freq >= 5500 ? 2 : 812 (channel->center_freq >= 5260 ? 1 : 813 (channel->center_freq > 4000 ? 0 : -1))); 814 815 if (obdb < 0) 816 return -EINVAL; 817 818 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 819 AR5K_RF_OB_5GHZ, true); 820 821 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 822 AR5K_RF_DB_5GHZ, true); 823 } 824 825 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 826 827 /* Bank Modifications (chip-specific) */ 828 if (ah->ah_radio == AR5K_RF5111) { 829 830 /* Set gain_F settings according to current step */ 831 if (channel->hw_value & CHANNEL_OFDM) { 832 833 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 834 AR5K_PHY_FRAME_CTL_TX_CLIP, 835 g_step->gos_param[0]); 836 837 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 838 AR5K_RF_PWD_90, true); 839 840 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 841 AR5K_RF_PWD_84, true); 842 843 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 844 AR5K_RF_RFGAIN_SEL, true); 845 846 /* We programmed gain_F parameters, switch back 847 * to active state */ 848 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 849 850 } 851 852 /* Bank 6/7 setup */ 853 854 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 855 AR5K_RF_PWD_XPD, true); 856 857 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 858 AR5K_RF_XPD_GAIN, true); 859 860 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 861 AR5K_RF_GAIN_I, true); 862 863 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 864 AR5K_RF_PLO_SEL, true); 865 866 /* Tweak power detectors for half/quarter rate support */ 867 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 868 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 869 u8 wait_i; 870 871 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 872 AR5K_RF_WAIT_S, true); 873 874 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 875 0x1f : 0x10; 876 877 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 878 AR5K_RF_WAIT_I, true); 879 ath5k_hw_rfb_op(ah, rf_regs, 3, 880 AR5K_RF_MAX_TIME, true); 881 882 } 883 } 884 885 if (ah->ah_radio == AR5K_RF5112) { 886 887 /* Set gain_F settings according to current step */ 888 if (channel->hw_value & CHANNEL_OFDM) { 889 890 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 891 AR5K_RF_MIXGAIN_OVR, true); 892 893 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 894 AR5K_RF_PWD_138, true); 895 896 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 897 AR5K_RF_PWD_137, true); 898 899 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 900 AR5K_RF_PWD_136, true); 901 902 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 903 AR5K_RF_PWD_132, true); 904 905 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 906 AR5K_RF_PWD_131, true); 907 908 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 909 AR5K_RF_PWD_130, true); 910 911 /* We programmed gain_F parameters, switch back 912 * to active state */ 913 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 914 } 915 916 /* Bank 6/7 setup */ 917 918 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 919 AR5K_RF_XPD_SEL, true); 920 921 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 922 /* Rev. 1 supports only one xpd */ 923 ath5k_hw_rfb_op(ah, rf_regs, 924 ee->ee_x_gain[ee_mode], 925 AR5K_RF_XPD_GAIN, true); 926 927 } else { 928 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 929 if (ee->ee_pd_gains[ee_mode] > 1) { 930 ath5k_hw_rfb_op(ah, rf_regs, 931 pdg_curve_to_idx[0], 932 AR5K_RF_PD_GAIN_LO, true); 933 ath5k_hw_rfb_op(ah, rf_regs, 934 pdg_curve_to_idx[1], 935 AR5K_RF_PD_GAIN_HI, true); 936 } else { 937 ath5k_hw_rfb_op(ah, rf_regs, 938 pdg_curve_to_idx[0], 939 AR5K_RF_PD_GAIN_LO, true); 940 ath5k_hw_rfb_op(ah, rf_regs, 941 pdg_curve_to_idx[0], 942 AR5K_RF_PD_GAIN_HI, true); 943 } 944 945 /* Lower synth voltage on Rev 2 */ 946 ath5k_hw_rfb_op(ah, rf_regs, 2, 947 AR5K_RF_HIGH_VC_CP, true); 948 949 ath5k_hw_rfb_op(ah, rf_regs, 2, 950 AR5K_RF_MID_VC_CP, true); 951 952 ath5k_hw_rfb_op(ah, rf_regs, 2, 953 AR5K_RF_LOW_VC_CP, true); 954 955 ath5k_hw_rfb_op(ah, rf_regs, 2, 956 AR5K_RF_PUSH_UP, true); 957 958 /* Decrease power consumption on 5213+ BaseBand */ 959 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 960 ath5k_hw_rfb_op(ah, rf_regs, 1, 961 AR5K_RF_PAD2GND, true); 962 963 ath5k_hw_rfb_op(ah, rf_regs, 1, 964 AR5K_RF_XB2_LVL, true); 965 966 ath5k_hw_rfb_op(ah, rf_regs, 1, 967 AR5K_RF_XB5_LVL, true); 968 969 ath5k_hw_rfb_op(ah, rf_regs, 1, 970 AR5K_RF_PWD_167, true); 971 972 ath5k_hw_rfb_op(ah, rf_regs, 1, 973 AR5K_RF_PWD_166, true); 974 } 975 } 976 977 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 978 AR5K_RF_GAIN_I, true); 979 980 /* Tweak power detector for half/quarter rates */ 981 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 982 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 983 u8 pd_delay; 984 985 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 986 0xf : 0x8; 987 988 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 989 AR5K_RF_PD_PERIOD_A, true); 990 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 991 AR5K_RF_PD_DELAY_A, true); 992 993 } 994 } 995 996 if (ah->ah_radio == AR5K_RF5413 && 997 channel->hw_value & CHANNEL_2GHZ) { 998 999 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1000 true); 1001 1002 /* Set optimum value for early revisions (on pci-e chips) */ 1003 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1004 ah->ah_mac_srev < AR5K_SREV_AR5413) 1005 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1006 AR5K_RF_PWD_ICLOBUF_2G, true); 1007 1008 } 1009 1010 /* Write RF banks on hw */ 1011 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1012 AR5K_REG_WAIT(i); 1013 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1014 } 1015 1016 return 0; 1017} 1018 1019 1020/**************************\ 1021 PHY/RF channel functions 1022\**************************/ 1023 1024/* 1025 * Convertion needed for RF5110 1026 */ 1027static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1028{ 1029 u32 athchan; 1030 1031 /* 1032 * Convert IEEE channel/MHz to an internal channel value used 1033 * by the AR5210 chipset. This has not been verified with 1034 * newer chipsets like the AR5212A who have a completely 1035 * different RF/PHY part. 1036 */ 1037 athchan = (ath5k_hw_bitswap( 1038 (ieee80211_frequency_to_channel( 1039 channel->center_freq) - 24) / 2, 5) 1040 << 1) | (1 << 6) | 0x1; 1041 return athchan; 1042} 1043 1044/* 1045 * Set channel on RF5110 1046 */ 1047static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1048 struct ieee80211_channel *channel) 1049{ 1050 u32 data; 1051 1052 /* 1053 * Set the channel and wait 1054 */ 1055 data = ath5k_hw_rf5110_chan2athchan(channel); 1056 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1057 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1058 mdelay(1); 1059 1060 return 0; 1061} 1062 1063/* 1064 * Convertion needed for 5111 1065 */ 1066static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1067 struct ath5k_athchan_2ghz *athchan) 1068{ 1069 int channel; 1070 1071 /* Cast this value to catch negative channel numbers (>= -19) */ 1072 channel = (int)ieee; 1073 1074 /* 1075 * Map 2GHz IEEE channel to 5GHz Atheros channel 1076 */ 1077 if (channel <= 13) { 1078 athchan->a2_athchan = 115 + channel; 1079 athchan->a2_flags = 0x46; 1080 } else if (channel == 14) { 1081 athchan->a2_athchan = 124; 1082 athchan->a2_flags = 0x44; 1083 } else if (channel >= 15 && channel <= 26) { 1084 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1085 athchan->a2_flags = 0x46; 1086 } else 1087 return -EINVAL; 1088 1089 return 0; 1090} 1091 1092/* 1093 * Set channel on 5111 1094 */ 1095static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1096 struct ieee80211_channel *channel) 1097{ 1098 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1099 unsigned int ath5k_channel = 1100 ieee80211_frequency_to_channel(channel->center_freq); 1101 u32 data0, data1, clock; 1102 int ret; 1103 1104 /* 1105 * Set the channel on the RF5111 radio 1106 */ 1107 data0 = data1 = 0; 1108 1109 if (channel->hw_value & CHANNEL_2GHZ) { 1110 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1111 ret = ath5k_hw_rf5111_chan2athchan( 1112 ieee80211_frequency_to_channel(channel->center_freq), 1113 &ath5k_channel_2ghz); 1114 if (ret) 1115 return ret; 1116 1117 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1118 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1119 << 5) | (1 << 4); 1120 } 1121 1122 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1123 clock = 1; 1124 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1125 (clock << 1) | (1 << 10) | 1; 1126 } else { 1127 clock = 0; 1128 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1129 << 2) | (clock << 1) | (1 << 10) | 1; 1130 } 1131 1132 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1133 AR5K_RF_BUFFER); 1134 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1135 AR5K_RF_BUFFER_CONTROL_3); 1136 1137 return 0; 1138} 1139 1140/* 1141 * Set channel on 5112 and newer 1142 */ 1143static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1144 struct ieee80211_channel *channel) 1145{ 1146 u32 data, data0, data1, data2; 1147 u16 c; 1148 1149 data = data0 = data1 = data2 = 0; 1150 c = channel->center_freq; 1151 1152 if (c < 4800) { 1153 if (!((c - 2224) % 5)) { 1154 data0 = ((2 * (c - 704)) - 3040) / 10; 1155 data1 = 1; 1156 } else if (!((c - 2192) % 5)) { 1157 data0 = ((2 * (c - 672)) - 3040) / 10; 1158 data1 = 0; 1159 } else 1160 return -EINVAL; 1161 1162 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1163 } else if ((c % 5) != 2 || c > 5435) { 1164 if (!(c % 20) && c >= 5120) { 1165 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1166 data2 = ath5k_hw_bitswap(3, 2); 1167 } else if (!(c % 10)) { 1168 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1169 data2 = ath5k_hw_bitswap(2, 2); 1170 } else if (!(c % 5)) { 1171 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1172 data2 = ath5k_hw_bitswap(1, 2); 1173 } else 1174 return -EINVAL; 1175 } else { 1176 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1177 data2 = ath5k_hw_bitswap(0, 2); 1178 } 1179 1180 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1181 1182 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1183 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1184 1185 return 0; 1186} 1187 1188/* 1189 * Set the channel on the RF2425 1190 */ 1191static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1192 struct ieee80211_channel *channel) 1193{ 1194 u32 data, data0, data2; 1195 u16 c; 1196 1197 data = data0 = data2 = 0; 1198 c = channel->center_freq; 1199 1200 if (c < 4800) { 1201 data0 = ath5k_hw_bitswap((c - 2272), 8); 1202 data2 = 0; 1203 /* ? 5GHz ? */ 1204 } else if ((c % 5) != 2 || c > 5435) { 1205 if (!(c % 20) && c < 5120) 1206 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1207 else if (!(c % 10)) 1208 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1209 else if (!(c % 5)) 1210 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1211 else 1212 return -EINVAL; 1213 data2 = ath5k_hw_bitswap(1, 2); 1214 } else { 1215 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1216 data2 = ath5k_hw_bitswap(0, 2); 1217 } 1218 1219 data = (data0 << 4) | data2 << 2 | 0x1001; 1220 1221 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1222 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1223 1224 return 0; 1225} 1226 1227/* 1228 * Set a channel on the radio chip 1229 */ 1230static int ath5k_hw_channel(struct ath5k_hw *ah, 1231 struct ieee80211_channel *channel) 1232{ 1233 int ret; 1234 /* 1235 * Check bounds supported by the PHY (we don't care about regultory 1236 * restrictions at this point). Note: hw_value already has the band 1237 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1238 * of the band by that */ 1239 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1240 ATH5K_ERR(ah->ah_sc, 1241 "channel frequency (%u MHz) out of supported " 1242 "band range\n", 1243 channel->center_freq); 1244 return -EINVAL; 1245 } 1246 1247 /* 1248 * Set the channel and wait 1249 */ 1250 switch (ah->ah_radio) { 1251 case AR5K_RF5110: 1252 ret = ath5k_hw_rf5110_channel(ah, channel); 1253 break; 1254 case AR5K_RF5111: 1255 ret = ath5k_hw_rf5111_channel(ah, channel); 1256 break; 1257 case AR5K_RF2425: 1258 ret = ath5k_hw_rf2425_channel(ah, channel); 1259 break; 1260 default: 1261 ret = ath5k_hw_rf5112_channel(ah, channel); 1262 break; 1263 } 1264 1265 if (ret) 1266 return ret; 1267 1268 /* Set JAPAN setting for channel 14 */ 1269 if (channel->center_freq == 2484) { 1270 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1271 AR5K_PHY_CCKTXCTL_JAPAN); 1272 } else { 1273 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1274 AR5K_PHY_CCKTXCTL_WORLD); 1275 } 1276 1277 ah->ah_current_channel = channel; 1278 1279 return 0; 1280} 1281 1282/*****************\ 1283 PHY calibration 1284\*****************/ 1285 1286static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1287{ 1288 s32 val; 1289 1290 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1291 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1292} 1293 1294void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1295{ 1296 int i; 1297 1298 ah->ah_nfcal_hist.index = 0; 1299 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1300 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1301} 1302 1303static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1304{ 1305 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1306 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1307 hist->nfval[hist->index] = noise_floor; 1308} 1309 1310static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1311{ 1312 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1313 s16 tmp; 1314 int i, j; 1315 1316 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1317 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1318 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1319 if (sort[j] > sort[j-1]) { 1320 tmp = sort[j]; 1321 sort[j] = sort[j-1]; 1322 sort[j-1] = tmp; 1323 } 1324 } 1325 } 1326 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1327 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1328 "cal %d:%d\n", i, sort[i]); 1329 } 1330 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1331} 1332 1333/* 1334 * When we tell the hardware to perform a noise floor calibration 1335 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1336 * sample-and-hold the minimum noise level seen at the antennas. 1337 * This value is then stored in a ring buffer of recently measured 1338 * noise floor values so we have a moving window of the last few 1339 * samples. 1340 * 1341 * The median of the values in the history is then loaded into the 1342 * hardware for its own use for RSSI and CCA measurements. 1343 */ 1344void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1345{ 1346 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1347 u32 val; 1348 s16 nf, threshold; 1349 u8 ee_mode; 1350 1351 /* keep last value if calibration hasn't completed */ 1352 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1353 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1354 "NF did not complete in calibration window\n"); 1355 1356 return; 1357 } 1358 1359 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { 1360 case CHANNEL_A: 1361 case CHANNEL_T: 1362 case CHANNEL_XR: 1363 ee_mode = AR5K_EEPROM_MODE_11A; 1364 break; 1365 case CHANNEL_G: 1366 case CHANNEL_TG: 1367 ee_mode = AR5K_EEPROM_MODE_11G; 1368 break; 1369 default: 1370 case CHANNEL_B: 1371 ee_mode = AR5K_EEPROM_MODE_11B; 1372 break; 1373 } 1374 1375 1376 /* completed NF calibration, test threshold */ 1377 nf = ath5k_hw_read_measured_noise_floor(ah); 1378 threshold = ee->ee_noise_floor_thr[ee_mode]; 1379 1380 if (nf > threshold) { 1381 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1382 "noise floor failure detected; " 1383 "read %d, threshold %d\n", 1384 nf, threshold); 1385 1386 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1387 } 1388 1389 ath5k_hw_update_nfcal_hist(ah, nf); 1390 nf = ath5k_hw_get_median_noise_floor(ah); 1391 1392 /* load noise floor (in .5 dBm) so the hardware will use it */ 1393 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1394 val |= (nf * 2) & AR5K_PHY_NF_M; 1395 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1396 1397 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1398 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1399 1400 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1401 0, false); 1402 1403 /* 1404 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1405 * so that we're not capped by the median we just loaded. 1406 * This will be used as the initial value for the next noise 1407 * floor calibration. 1408 */ 1409 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1410 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1411 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1412 AR5K_PHY_AGCCTL_NF_EN | 1413 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1414 AR5K_PHY_AGCCTL_NF); 1415 1416 ah->ah_noise_floor = nf; 1417 1418 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1419 "noise floor calibrated: %d\n", nf); 1420} 1421 1422/* 1423 * Perform a PHY calibration on RF5110 1424 * -Fix BPSK/QAM Constellation (I/Q correction) 1425 */ 1426static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1427 struct ieee80211_channel *channel) 1428{ 1429 u32 phy_sig, phy_agc, phy_sat, beacon; 1430 int ret; 1431 1432 /* 1433 * Disable beacons and RX/TX queues, wait 1434 */ 1435 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1436 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1437 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1438 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1439 1440 mdelay(2); 1441 1442 /* 1443 * Set the channel (with AGC turned off) 1444 */ 1445 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1446 udelay(10); 1447 ret = ath5k_hw_channel(ah, channel); 1448 1449 /* 1450 * Activate PHY and wait 1451 */ 1452 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1453 mdelay(1); 1454 1455 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1456 1457 if (ret) 1458 return ret; 1459 1460 /* 1461 * Calibrate the radio chip 1462 */ 1463 1464 /* Remember normal state */ 1465 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1466 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1467 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1468 1469 /* Update radio registers */ 1470 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1471 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1472 1473 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1474 AR5K_PHY_AGCCOARSE_LO)) | 1475 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1476 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1477 1478 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1479 AR5K_PHY_ADCSAT_THR)) | 1480 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1481 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1482 1483 udelay(20); 1484 1485 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1486 udelay(10); 1487 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1488 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1489 1490 mdelay(1); 1491 1492 /* 1493 * Enable calibration and wait until completion 1494 */ 1495 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1496 1497 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1498 AR5K_PHY_AGCCTL_CAL, 0, false); 1499 1500 /* Reset to normal state */ 1501 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1502 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1503 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1504 1505 if (ret) { 1506 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1507 channel->center_freq); 1508 return ret; 1509 } 1510 1511 /* 1512 * Re-enable RX/TX and beacons 1513 */ 1514 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1515 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1516 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1517 1518 return 0; 1519} 1520 1521/* 1522 * Perform I/Q calibration on RF5111/5112 and newer chips 1523 */ 1524static int 1525ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1526{ 1527 u32 i_pwr, q_pwr; 1528 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1529 int i; 1530 1531 if (!ah->ah_calibration || 1532 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1533 return 0; 1534 1535 /* Calibration has finished, get the results and re-run */ 1536 /* work around empty results which can apparently happen on 5212 */ 1537 for (i = 0; i <= 10; i++) { 1538 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1539 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1540 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1541 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1542 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1543 if (i_pwr && q_pwr) 1544 break; 1545 } 1546 1547 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1548 1549 if (ah->ah_version == AR5K_AR5211) 1550 q_coffd = q_pwr >> 6; 1551 else 1552 q_coffd = q_pwr >> 7; 1553 1554 /* protect against divide by 0 and loss of sign bits */ 1555 if (i_coffd == 0 || q_coffd < 2) 1556 return 0; 1557 1558 i_coff = (-iq_corr) / i_coffd; 1559 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1560 1561 if (ah->ah_version == AR5K_AR5211) 1562 q_coff = (i_pwr / q_coffd) - 64; 1563 else 1564 q_coff = (i_pwr / q_coffd) - 128; 1565 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1566 1567 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1568 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1569 i_coff, q_coff, i_coffd, q_coffd); 1570 1571 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1572 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1573 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1574 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1575 1576 /* Re-enable calibration -if we don't we'll commit 1577 * the same values again and again */ 1578 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1579 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1580 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1581 1582 return 0; 1583} 1584 1585/* 1586 * Perform a PHY calibration 1587 */ 1588int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1589 struct ieee80211_channel *channel) 1590{ 1591 int ret; 1592 1593 if (ah->ah_radio == AR5K_RF5110) 1594 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1595 else { 1596 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1597 ath5k_hw_request_rfgain_probe(ah); 1598 } 1599 1600 return ret; 1601} 1602 1603 1604/***************************\ 1605* Spur mitigation functions * 1606\***************************/ 1607 1608static void 1609ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1610 struct ieee80211_channel *channel) 1611{ 1612 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1613 u32 mag_mask[4] = {0, 0, 0, 0}; 1614 u32 pilot_mask[2] = {0, 0}; 1615 /* Note: fbin values are scaled up by 2 */ 1616 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1617 s32 spur_delta_phase, spur_freq_sigma_delta; 1618 s32 spur_offset, num_symbols_x16; 1619 u8 num_symbol_offsets, i, freq_band; 1620 1621 /* Convert current frequency to fbin value (the same way channels 1622 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1623 * up by 2 so we can compare it later */ 1624 if (channel->hw_value & CHANNEL_2GHZ) { 1625 chan_fbin = (channel->center_freq - 2300) * 10; 1626 freq_band = AR5K_EEPROM_BAND_2GHZ; 1627 } else { 1628 chan_fbin = (channel->center_freq - 4900) * 10; 1629 freq_band = AR5K_EEPROM_BAND_5GHZ; 1630 } 1631 1632 /* Check if any spur_chan_fbin from EEPROM is 1633 * within our current channel's spur detection range */ 1634 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1635 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1636 /* XXX: Half/Quarter channels ?*/ 1637 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1638 spur_detection_window *= 2; 1639 1640 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1641 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1642 1643 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1644 * so it's zero if we got nothing from EEPROM */ 1645 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1646 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1647 break; 1648 } 1649 1650 if ((chan_fbin - spur_detection_window <= 1651 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1652 (chan_fbin + spur_detection_window >= 1653 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1654 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1655 break; 1656 } 1657 } 1658 1659 /* We need to enable spur filter for this channel */ 1660 if (spur_chan_fbin) { 1661 spur_offset = spur_chan_fbin - chan_fbin; 1662 /* 1663 * Calculate deltas: 1664 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1665 * spur_delta_phase -> spur_offset / chip_freq << 11 1666 * Note: Both values have 100Hz resolution 1667 */ 1668 switch (ah->ah_bwmode) { 1669 case AR5K_BWMODE_40MHZ: 1670 /* Both sample_freq and chip_freq are 80MHz */ 1671 spur_delta_phase = (spur_offset << 16) / 25; 1672 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1673 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1674 break; 1675 case AR5K_BWMODE_10MHZ: 1676 /* Both sample_freq and chip_freq are 20MHz (?) */ 1677 spur_delta_phase = (spur_offset << 18) / 25; 1678 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1679 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1680 case AR5K_BWMODE_5MHZ: 1681 /* Both sample_freq and chip_freq are 10MHz (?) */ 1682 spur_delta_phase = (spur_offset << 19) / 25; 1683 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1684 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1685 default: 1686 if (channel->hw_value == CHANNEL_A) { 1687 /* Both sample_freq and chip_freq are 40MHz */ 1688 spur_delta_phase = (spur_offset << 17) / 25; 1689 spur_freq_sigma_delta = 1690 (spur_delta_phase >> 10); 1691 symbol_width = 1692 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1693 } else { 1694 /* sample_freq -> 40MHz chip_freq -> 44MHz 1695 * (for b compatibility) */ 1696 spur_delta_phase = (spur_offset << 17) / 25; 1697 spur_freq_sigma_delta = 1698 (spur_offset << 8) / 55; 1699 symbol_width = 1700 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1701 } 1702 break; 1703 } 1704 1705 /* Calculate pilot and magnitude masks */ 1706 1707 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1708 * and divide by symbol_width to find how many symbols we have 1709 * Note: number of symbols is scaled up by 16 */ 1710 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1711 1712 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1713 if (!(num_symbols_x16 & 0xF)) 1714 /* _X_ */ 1715 num_symbol_offsets = 3; 1716 else 1717 /* _xx_ */ 1718 num_symbol_offsets = 4; 1719 1720 for (i = 0; i < num_symbol_offsets; i++) { 1721 1722 /* Calculate pilot mask */ 1723 s32 curr_sym_off = 1724 (num_symbols_x16 / 16) + i + 25; 1725 1726 /* Pilot magnitude mask seems to be a way to 1727 * declare the boundaries for our detection 1728 * window or something, it's 2 for the middle 1729 * value(s) where the symbol is expected to be 1730 * and 1 on the boundary values */ 1731 u8 plt_mag_map = 1732 (i == 0 || i == (num_symbol_offsets - 1)) 1733 ? 1 : 2; 1734 1735 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1736 if (curr_sym_off <= 25) 1737 pilot_mask[0] |= 1 << curr_sym_off; 1738 else if (curr_sym_off >= 27) 1739 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1740 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1741 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1742 1743 /* Calculate magnitude mask (for viterbi decoder) */ 1744 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1745 mag_mask[0] |= 1746 plt_mag_map << (curr_sym_off + 1) * 2; 1747 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1748 mag_mask[1] |= 1749 plt_mag_map << (curr_sym_off - 15) * 2; 1750 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1751 mag_mask[2] |= 1752 plt_mag_map << (curr_sym_off - 31) * 2; 1753 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1754 mag_mask[3] |= 1755 plt_mag_map << (curr_sym_off - 47) * 2; 1756 1757 } 1758 1759 /* Write settings on hw to enable spur filter */ 1760 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1761 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1762 /* XXX: Self correlator also ? */ 1763 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1764 AR5K_PHY_IQ_PILOT_MASK_EN | 1765 AR5K_PHY_IQ_CHAN_MASK_EN | 1766 AR5K_PHY_IQ_SPUR_FILT_EN); 1767 1768 /* Set delta phase and freq sigma delta */ 1769 ath5k_hw_reg_write(ah, 1770 AR5K_REG_SM(spur_delta_phase, 1771 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1772 AR5K_REG_SM(spur_freq_sigma_delta, 1773 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1774 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1775 AR5K_PHY_TIMING_11); 1776 1777 /* Write pilot masks */ 1778 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1779 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1780 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1781 pilot_mask[1]); 1782 1783 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1784 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1785 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1786 pilot_mask[1]); 1787 1788 /* Write magnitude masks */ 1789 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1790 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1791 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1792 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1793 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1794 mag_mask[3]); 1795 1796 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1797 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1798 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1799 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1800 AR5K_PHY_BIN_MASK2_4_MASK_4, 1801 mag_mask[3]); 1802 1803 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1804 AR5K_PHY_IQ_SPUR_FILT_EN) { 1805 /* Clean up spur mitigation settings and disable fliter */ 1806 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1807 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1808 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1809 AR5K_PHY_IQ_PILOT_MASK_EN | 1810 AR5K_PHY_IQ_CHAN_MASK_EN | 1811 AR5K_PHY_IQ_SPUR_FILT_EN); 1812 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1813 1814 /* Clear pilot masks */ 1815 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1816 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1817 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1818 0); 1819 1820 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1822 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1823 0); 1824 1825 /* Clear magnitude masks */ 1826 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1827 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1828 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1829 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1830 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1831 0); 1832 1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1834 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1835 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1837 AR5K_PHY_BIN_MASK2_4_MASK_4, 1838 0); 1839 } 1840} 1841 1842 1843/*****************\ 1844* Antenna control * 1845\*****************/ 1846 1847static void /*TODO:Boundary check*/ 1848ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1849{ 1850 if (ah->ah_version != AR5K_AR5210) 1851 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1852} 1853 1854/* 1855 * Enable/disable fast rx antenna diversity 1856 */ 1857static void 1858ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1859{ 1860 switch (ee_mode) { 1861 case AR5K_EEPROM_MODE_11G: 1862 /* XXX: This is set to 1863 * disabled on initvals !!! */ 1864 case AR5K_EEPROM_MODE_11A: 1865 if (enable) 1866 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1867 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1868 else 1869 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1870 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1871 break; 1872 case AR5K_EEPROM_MODE_11B: 1873 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1874 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1875 break; 1876 default: 1877 return; 1878 } 1879 1880 if (enable) { 1881 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1882 AR5K_PHY_RESTART_DIV_GC, 4); 1883 1884 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1885 AR5K_PHY_FAST_ANT_DIV_EN); 1886 } else { 1887 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1888 AR5K_PHY_RESTART_DIV_GC, 0); 1889 1890 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1891 AR5K_PHY_FAST_ANT_DIV_EN); 1892 } 1893} 1894 1895void 1896ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1897{ 1898 u8 ant0, ant1; 1899 1900 /* 1901 * In case a fixed antenna was set as default 1902 * use the same switch table twice. 1903 */ 1904 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1905 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1906 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1907 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1908 else { 1909 ant0 = AR5K_ANT_SWTABLE_A; 1910 ant1 = AR5K_ANT_SWTABLE_B; 1911 } 1912 1913 /* Set antenna idle switch table */ 1914 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1915 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1916 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1917 AR5K_PHY_ANT_CTL_TXRX_EN)); 1918 1919 /* Set antenna switch tables */ 1920 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1921 AR5K_PHY_ANT_SWITCH_TABLE_0); 1922 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1923 AR5K_PHY_ANT_SWITCH_TABLE_1); 1924} 1925 1926/* 1927 * Set antenna operating mode 1928 */ 1929void 1930ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1931{ 1932 struct ieee80211_channel *channel = ah->ah_current_channel; 1933 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1934 bool use_def_for_sg; 1935 u8 def_ant, tx_ant, ee_mode; 1936 u32 sta_id1 = 0; 1937 1938 /* if channel is not initialized yet we can't set the antennas 1939 * so just store the mode. it will be set on the next reset */ 1940 if (channel == NULL) { 1941 ah->ah_ant_mode = ant_mode; 1942 return; 1943 } 1944 1945 def_ant = ah->ah_def_ant; 1946 1947 switch (channel->hw_value & CHANNEL_MODES) { 1948 case CHANNEL_A: 1949 case CHANNEL_T: 1950 case CHANNEL_XR: 1951 ee_mode = AR5K_EEPROM_MODE_11A; 1952 break; 1953 case CHANNEL_G: 1954 case CHANNEL_TG: 1955 ee_mode = AR5K_EEPROM_MODE_11G; 1956 break; 1957 case CHANNEL_B: 1958 ee_mode = AR5K_EEPROM_MODE_11B; 1959 break; 1960 default: 1961 ATH5K_ERR(ah->ah_sc, 1962 "invalid channel: %d\n", channel->center_freq); 1963 return; 1964 } 1965 1966 switch (ant_mode) { 1967 case AR5K_ANTMODE_DEFAULT: 1968 tx_ant = 0; 1969 use_def_for_tx = false; 1970 update_def_on_tx = false; 1971 use_def_for_rts = false; 1972 use_def_for_sg = false; 1973 fast_div = true; 1974 break; 1975 case AR5K_ANTMODE_FIXED_A: 1976 def_ant = 1; 1977 tx_ant = 1; 1978 use_def_for_tx = true; 1979 update_def_on_tx = false; 1980 use_def_for_rts = true; 1981 use_def_for_sg = true; 1982 fast_div = false; 1983 break; 1984 case AR5K_ANTMODE_FIXED_B: 1985 def_ant = 2; 1986 tx_ant = 2; 1987 use_def_for_tx = true; 1988 update_def_on_tx = false; 1989 use_def_for_rts = true; 1990 use_def_for_sg = true; 1991 fast_div = false; 1992 break; 1993 case AR5K_ANTMODE_SINGLE_AP: 1994 def_ant = 1; /* updated on tx */ 1995 tx_ant = 0; 1996 use_def_for_tx = true; 1997 update_def_on_tx = true; 1998 use_def_for_rts = true; 1999 use_def_for_sg = true; 2000 fast_div = true; 2001 break; 2002 case AR5K_ANTMODE_SECTOR_AP: 2003 tx_ant = 1; /* variable */ 2004 use_def_for_tx = false; 2005 update_def_on_tx = false; 2006 use_def_for_rts = true; 2007 use_def_for_sg = false; 2008 fast_div = false; 2009 break; 2010 case AR5K_ANTMODE_SECTOR_STA: 2011 tx_ant = 1; /* variable */ 2012 use_def_for_tx = true; 2013 update_def_on_tx = false; 2014 use_def_for_rts = true; 2015 use_def_for_sg = false; 2016 fast_div = true; 2017 break; 2018 case AR5K_ANTMODE_DEBUG: 2019 def_ant = 1; 2020 tx_ant = 2; 2021 use_def_for_tx = false; 2022 update_def_on_tx = false; 2023 use_def_for_rts = false; 2024 use_def_for_sg = false; 2025 fast_div = false; 2026 break; 2027 default: 2028 return; 2029 } 2030 2031 ah->ah_tx_ant = tx_ant; 2032 ah->ah_ant_mode = ant_mode; 2033 ah->ah_def_ant = def_ant; 2034 2035 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2036 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2037 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2038 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2039 2040 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2041 2042 if (sta_id1) 2043 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2044 2045 ath5k_hw_set_antenna_switch(ah, ee_mode); 2046 /* Note: set diversity before default antenna 2047 * because it won't work correctly */ 2048 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2049 ath5k_hw_set_def_antenna(ah, def_ant); 2050} 2051 2052 2053/****************\ 2054* TX power setup * 2055\****************/ 2056 2057/* 2058 * Helper functions 2059 */ 2060 2061/* 2062 * Do linear interpolation between two given (x, y) points 2063 */ 2064static s16 2065ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2066 s16 y_left, s16 y_right) 2067{ 2068 s16 ratio, result; 2069 2070 /* Avoid divide by zero and skip interpolation 2071 * if we have the same point */ 2072 if ((x_left == x_right) || (y_left == y_right)) 2073 return y_left; 2074 2075 /* 2076 * Since we use ints and not fps, we need to scale up in 2077 * order to get a sane ratio value (or else we 'll eg. get 2078 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2079 * to have some accuracy both for 0.5 and 0.25 steps. 2080 */ 2081 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2082 2083 /* Now scale down to be in range */ 2084 result = y_left + (ratio * (target - x_left) / 100); 2085 2086 return result; 2087} 2088 2089/* 2090 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2091 * 2092 * Since we have the top of the curve and we draw the line below 2093 * until we reach 1 (1 pcdac step) we need to know which point 2094 * (x value) that is so that we don't go below y axis and have negative 2095 * pcdac values when creating the curve, or fill the table with zeroes. 2096 */ 2097static s16 2098ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2099 const s16 *pwrL, const s16 *pwrR) 2100{ 2101 s8 tmp; 2102 s16 min_pwrL, min_pwrR; 2103 s16 pwr_i; 2104 2105 /* Some vendors write the same pcdac value twice !!! */ 2106 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2107 return max(pwrL[0], pwrR[0]); 2108 2109 if (pwrL[0] == pwrL[1]) 2110 min_pwrL = pwrL[0]; 2111 else { 2112 pwr_i = pwrL[0]; 2113 do { 2114 pwr_i--; 2115 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2116 pwrL[0], pwrL[1], 2117 stepL[0], stepL[1]); 2118 } while (tmp > 1); 2119 2120 min_pwrL = pwr_i; 2121 } 2122 2123 if (pwrR[0] == pwrR[1]) 2124 min_pwrR = pwrR[0]; 2125 else { 2126 pwr_i = pwrR[0]; 2127 do { 2128 pwr_i--; 2129 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2130 pwrR[0], pwrR[1], 2131 stepR[0], stepR[1]); 2132 } while (tmp > 1); 2133 2134 min_pwrR = pwr_i; 2135 } 2136 2137 /* Keep the right boundary so that it works for both curves */ 2138 return max(min_pwrL, min_pwrR); 2139} 2140 2141/* 2142 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2143 * Power to PCDAC curve. 2144 * 2145 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2146 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2147 * PCDAC/PDADC step for each curve is 64 but we can write more than 2148 * one curves on hw so we can go up to 128 (which is the max step we 2149 * can write on the final table). 2150 * 2151 * We write y values (PCDAC/PDADC steps) on hw. 2152 */ 2153static void 2154ath5k_create_power_curve(s16 pmin, s16 pmax, 2155 const s16 *pwr, const u8 *vpd, 2156 u8 num_points, 2157 u8 *vpd_table, u8 type) 2158{ 2159 u8 idx[2] = { 0, 1 }; 2160 s16 pwr_i = 2*pmin; 2161 int i; 2162 2163 if (num_points < 2) 2164 return; 2165 2166 /* We want the whole line, so adjust boundaries 2167 * to cover the entire power range. Note that 2168 * power values are already 0.25dB so no need 2169 * to multiply pwr_i by 2 */ 2170 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2171 pwr_i = pmin; 2172 pmin = 0; 2173 pmax = 63; 2174 } 2175 2176 /* Find surrounding turning points (TPs) 2177 * and interpolate between them */ 2178 for (i = 0; (i <= (u16) (pmax - pmin)) && 2179 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2180 2181 /* We passed the right TP, move to the next set of TPs 2182 * if we pass the last TP, extrapolate above using the last 2183 * two TPs for ratio */ 2184 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2185 idx[0]++; 2186 idx[1]++; 2187 } 2188 2189 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2190 pwr[idx[0]], pwr[idx[1]], 2191 vpd[idx[0]], vpd[idx[1]]); 2192 2193 /* Increase by 0.5dB 2194 * (0.25 dB units) */ 2195 pwr_i += 2; 2196 } 2197} 2198 2199/* 2200 * Get the surrounding per-channel power calibration piers 2201 * for a given frequency so that we can interpolate between 2202 * them and come up with an apropriate dataset for our current 2203 * channel. 2204 */ 2205static void 2206ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2207 struct ieee80211_channel *channel, 2208 struct ath5k_chan_pcal_info **pcinfo_l, 2209 struct ath5k_chan_pcal_info **pcinfo_r) 2210{ 2211 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2212 struct ath5k_chan_pcal_info *pcinfo; 2213 u8 idx_l, idx_r; 2214 u8 mode, max, i; 2215 u32 target = channel->center_freq; 2216 2217 idx_l = 0; 2218 idx_r = 0; 2219 2220 if (!(channel->hw_value & CHANNEL_OFDM)) { 2221 pcinfo = ee->ee_pwr_cal_b; 2222 mode = AR5K_EEPROM_MODE_11B; 2223 } else if (channel->hw_value & CHANNEL_2GHZ) { 2224 pcinfo = ee->ee_pwr_cal_g; 2225 mode = AR5K_EEPROM_MODE_11G; 2226 } else { 2227 pcinfo = ee->ee_pwr_cal_a; 2228 mode = AR5K_EEPROM_MODE_11A; 2229 } 2230 max = ee->ee_n_piers[mode] - 1; 2231 2232 /* Frequency is below our calibrated 2233 * range. Use the lowest power curve 2234 * we have */ 2235 if (target < pcinfo[0].freq) { 2236 idx_l = idx_r = 0; 2237 goto done; 2238 } 2239 2240 /* Frequency is above our calibrated 2241 * range. Use the highest power curve 2242 * we have */ 2243 if (target > pcinfo[max].freq) { 2244 idx_l = idx_r = max; 2245 goto done; 2246 } 2247 2248 /* Frequency is inside our calibrated 2249 * channel range. Pick the surrounding 2250 * calibration piers so that we can 2251 * interpolate */ 2252 for (i = 0; i <= max; i++) { 2253 2254 /* Frequency matches one of our calibration 2255 * piers, no need to interpolate, just use 2256 * that calibration pier */ 2257 if (pcinfo[i].freq == target) { 2258 idx_l = idx_r = i; 2259 goto done; 2260 } 2261 2262 /* We found a calibration pier that's above 2263 * frequency, use this pier and the previous 2264 * one to interpolate */ 2265 if (target < pcinfo[i].freq) { 2266 idx_r = i; 2267 idx_l = idx_r - 1; 2268 goto done; 2269 } 2270 } 2271 2272done: 2273 *pcinfo_l = &pcinfo[idx_l]; 2274 *pcinfo_r = &pcinfo[idx_r]; 2275} 2276 2277/* 2278 * Get the surrounding per-rate power calibration data 2279 * for a given frequency and interpolate between power 2280 * values to set max target power supported by hw for 2281 * each rate. 2282 */ 2283static void 2284ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2285 struct ieee80211_channel *channel, 2286 struct ath5k_rate_pcal_info *rates) 2287{ 2288 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2289 struct ath5k_rate_pcal_info *rpinfo; 2290 u8 idx_l, idx_r; 2291 u8 mode, max, i; 2292 u32 target = channel->center_freq; 2293 2294 idx_l = 0; 2295 idx_r = 0; 2296 2297 if (!(channel->hw_value & CHANNEL_OFDM)) { 2298 rpinfo = ee->ee_rate_tpwr_b; 2299 mode = AR5K_EEPROM_MODE_11B; 2300 } else if (channel->hw_value & CHANNEL_2GHZ) { 2301 rpinfo = ee->ee_rate_tpwr_g; 2302 mode = AR5K_EEPROM_MODE_11G; 2303 } else { 2304 rpinfo = ee->ee_rate_tpwr_a; 2305 mode = AR5K_EEPROM_MODE_11A; 2306 } 2307 max = ee->ee_rate_target_pwr_num[mode] - 1; 2308 2309 /* Get the surrounding calibration 2310 * piers - same as above */ 2311 if (target < rpinfo[0].freq) { 2312 idx_l = idx_r = 0; 2313 goto done; 2314 } 2315 2316 if (target > rpinfo[max].freq) { 2317 idx_l = idx_r = max; 2318 goto done; 2319 } 2320 2321 for (i = 0; i <= max; i++) { 2322 2323 if (rpinfo[i].freq == target) { 2324 idx_l = idx_r = i; 2325 goto done; 2326 } 2327 2328 if (target < rpinfo[i].freq) { 2329 idx_r = i; 2330 idx_l = idx_r - 1; 2331 goto done; 2332 } 2333 } 2334 2335done: 2336 /* Now interpolate power value, based on the frequency */ 2337 rates->freq = target; 2338 2339 rates->target_power_6to24 = 2340 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2341 rpinfo[idx_r].freq, 2342 rpinfo[idx_l].target_power_6to24, 2343 rpinfo[idx_r].target_power_6to24); 2344 2345 rates->target_power_36 = 2346 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2347 rpinfo[idx_r].freq, 2348 rpinfo[idx_l].target_power_36, 2349 rpinfo[idx_r].target_power_36); 2350 2351 rates->target_power_48 = 2352 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2353 rpinfo[idx_r].freq, 2354 rpinfo[idx_l].target_power_48, 2355 rpinfo[idx_r].target_power_48); 2356 2357 rates->target_power_54 = 2358 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2359 rpinfo[idx_r].freq, 2360 rpinfo[idx_l].target_power_54, 2361 rpinfo[idx_r].target_power_54); 2362} 2363 2364/* 2365 * Get the max edge power for this channel if 2366 * we have such data from EEPROM's Conformance Test 2367 * Limits (CTL), and limit max power if needed. 2368 */ 2369static void 2370ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2371 struct ieee80211_channel *channel) 2372{ 2373 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2374 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2375 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2376 u8 *ctl_val = ee->ee_ctl; 2377 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2378 s16 edge_pwr = 0; 2379 u8 rep_idx; 2380 u8 i, ctl_mode; 2381 u8 ctl_idx = 0xFF; 2382 u32 target = channel->center_freq; 2383 2384 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2385 2386 switch (channel->hw_value & CHANNEL_MODES) { 2387 case CHANNEL_A: 2388 ctl_mode |= AR5K_CTL_11A; 2389 break; 2390 case CHANNEL_G: 2391 ctl_mode |= AR5K_CTL_11G; 2392 break; 2393 case CHANNEL_B: 2394 ctl_mode |= AR5K_CTL_11B; 2395 break; 2396 case CHANNEL_T: 2397 ctl_mode |= AR5K_CTL_TURBO; 2398 break; 2399 case CHANNEL_TG: 2400 ctl_mode |= AR5K_CTL_TURBOG; 2401 break; 2402 case CHANNEL_XR: 2403 /* Fall through */ 2404 default: 2405 return; 2406 } 2407 2408 for (i = 0; i < ee->ee_ctls; i++) { 2409 if (ctl_val[i] == ctl_mode) { 2410 ctl_idx = i; 2411 break; 2412 } 2413 } 2414 2415 /* If we have a CTL dataset available grab it and find the 2416 * edge power for our frequency */ 2417 if (ctl_idx == 0xFF) 2418 return; 2419 2420 /* Edge powers are sorted by frequency from lower 2421 * to higher. Each CTL corresponds to 8 edge power 2422 * measurements. */ 2423 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2424 2425 /* Don't do boundaries check because we 2426 * might have more that one bands defined 2427 * for this mode */ 2428 2429 /* Get the edge power that's closer to our 2430 * frequency */ 2431 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2432 rep_idx += i; 2433 if (target <= rep[rep_idx].freq) 2434 edge_pwr = (s16) rep[rep_idx].edge; 2435 } 2436 2437 if (edge_pwr) 2438 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2439} 2440 2441 2442/* 2443 * Power to PCDAC table functions 2444 */ 2445 2446/* 2447 * Fill Power to PCDAC table on RF5111 2448 * 2449 * No further processing is needed for RF5111, the only thing we have to 2450 * do is fill the values below and above calibration range since eeprom data 2451 * may not cover the entire PCDAC table. 2452 */ 2453static void 2454ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2455 s16 *table_max) 2456{ 2457 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2458 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2459 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2460 s16 min_pwr, max_pwr; 2461 2462 /* Get table boundaries */ 2463 min_pwr = table_min[0]; 2464 pcdac_0 = pcdac_tmp[0]; 2465 2466 max_pwr = table_max[0]; 2467 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2468 2469 /* Extrapolate below minimum using pcdac_0 */ 2470 pcdac_i = 0; 2471 for (i = 0; i < min_pwr; i++) 2472 pcdac_out[pcdac_i++] = pcdac_0; 2473 2474 /* Copy values from pcdac_tmp */ 2475 pwr_idx = min_pwr; 2476 for (i = 0 ; pwr_idx <= max_pwr && 2477 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2478 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2479 pwr_idx++; 2480 } 2481 2482 /* Extrapolate above maximum */ 2483 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2484 pcdac_out[pcdac_i++] = pcdac_n; 2485 2486} 2487 2488/* 2489 * Combine available XPD Curves and fill Linear Power to PCDAC table 2490 * on RF5112 2491 * 2492 * RFX112 can have up to 2 curves (one for low txpower range and one for 2493 * higher txpower range). We need to put them both on pcdac_out and place 2494 * them in the correct location. In case we only have one curve available 2495 * just fit it on pcdac_out (it's supposed to cover the entire range of 2496 * available pwr levels since it's always the higher power curve). Extrapolate 2497 * below and above final table if needed. 2498 */ 2499static void 2500ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2501 s16 *table_max, u8 pdcurves) 2502{ 2503 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2504 u8 *pcdac_low_pwr; 2505 u8 *pcdac_high_pwr; 2506 u8 *pcdac_tmp; 2507 u8 pwr; 2508 s16 max_pwr_idx; 2509 s16 min_pwr_idx; 2510 s16 mid_pwr_idx = 0; 2511 /* Edge flag turs on the 7nth bit on the PCDAC 2512 * to delcare the higher power curve (force values 2513 * to be greater than 64). If we only have one curve 2514 * we don't need to set this, if we have 2 curves and 2515 * fill the table backwards this can also be used to 2516 * switch from higher power curve to lower power curve */ 2517 u8 edge_flag; 2518 int i; 2519 2520 /* When we have only one curve available 2521 * that's the higher power curve. If we have 2522 * two curves the first is the high power curve 2523 * and the next is the low power curve. */ 2524 if (pdcurves > 1) { 2525 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2526 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2527 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2528 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2529 2530 /* If table size goes beyond 31.5dB, keep the 2531 * upper 31.5dB range when setting tx power. 2532 * Note: 126 = 31.5 dB in quarter dB steps */ 2533 if (table_max[0] - table_min[1] > 126) 2534 min_pwr_idx = table_max[0] - 126; 2535 else 2536 min_pwr_idx = table_min[1]; 2537 2538 /* Since we fill table backwards 2539 * start from high power curve */ 2540 pcdac_tmp = pcdac_high_pwr; 2541 2542 edge_flag = 0x40; 2543 } else { 2544 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2545 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2546 min_pwr_idx = table_min[0]; 2547 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2548 pcdac_tmp = pcdac_high_pwr; 2549 edge_flag = 0; 2550 } 2551 2552 /* This is used when setting tx power*/ 2553 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2554 2555 /* Fill Power to PCDAC table backwards */ 2556 pwr = max_pwr_idx; 2557 for (i = 63; i >= 0; i--) { 2558 /* Entering lower power range, reset 2559 * edge flag and set pcdac_tmp to lower 2560 * power curve.*/ 2561 if (edge_flag == 0x40 && 2562 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2563 edge_flag = 0x00; 2564 pcdac_tmp = pcdac_low_pwr; 2565 pwr = mid_pwr_idx/2; 2566 } 2567 2568 /* Don't go below 1, extrapolate below if we have 2569 * already swithced to the lower power curve -or 2570 * we only have one curve and edge_flag is zero 2571 * anyway */ 2572 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2573 while (i >= 0) { 2574 pcdac_out[i] = pcdac_out[i + 1]; 2575 i--; 2576 } 2577 break; 2578 } 2579 2580 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2581 2582 /* Extrapolate above if pcdac is greater than 2583 * 126 -this can happen because we OR pcdac_out 2584 * value with edge_flag on high power curve */ 2585 if (pcdac_out[i] > 126) 2586 pcdac_out[i] = 126; 2587 2588 /* Decrease by a 0.5dB step */ 2589 pwr--; 2590 } 2591} 2592 2593/* Write PCDAC values on hw */ 2594static void 2595ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2596{ 2597 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2598 int i; 2599 2600 /* 2601 * Write TX power values 2602 */ 2603 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2604 ath5k_hw_reg_write(ah, 2605 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2606 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2607 AR5K_PHY_PCDAC_TXPOWER(i)); 2608 } 2609} 2610 2611 2612/* 2613 * Power to PDADC table functions 2614 */ 2615 2616/* 2617 * Set the gain boundaries and create final Power to PDADC table 2618 * 2619 * We can have up to 4 pd curves, we need to do a simmilar process 2620 * as we do for RF5112. This time we don't have an edge_flag but we 2621 * set the gain boundaries on a separate register. 2622 */ 2623static void 2624ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2625 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2626{ 2627 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2628 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2629 u8 *pdadc_tmp; 2630 s16 pdadc_0; 2631 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2632 u8 pd_gain_overlap; 2633 2634 /* Note: Register value is initialized on initvals 2635 * there is no feedback from hw. 2636 * XXX: What about pd_gain_overlap from EEPROM ? */ 2637 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2638 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2639 2640 /* Create final PDADC table */ 2641 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2642 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2643 2644 if (pdg == pdcurves - 1) 2645 /* 2 dB boundary stretch for last 2646 * (higher power) curve */ 2647 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2648 else 2649 /* Set gain boundary in the middle 2650 * between this curve and the next one */ 2651 gain_boundaries[pdg] = 2652 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2653 2654 /* Sanity check in case our 2 db stretch got out of 2655 * range. */ 2656 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2657 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2658 2659 /* For the first curve (lower power) 2660 * start from 0 dB */ 2661 if (pdg == 0) 2662 pdadc_0 = 0; 2663 else 2664 /* For the other curves use the gain overlap */ 2665 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2666 pd_gain_overlap; 2667 2668 /* Force each power step to be at least 0.5 dB */ 2669 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2670 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2671 else 2672 pwr_step = 1; 2673 2674 /* If pdadc_0 is negative, we need to extrapolate 2675 * below this pdgain by a number of pwr_steps */ 2676 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2677 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2678 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2679 pdadc_0++; 2680 } 2681 2682 /* Set last pwr level, using gain boundaries */ 2683 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2684 /* Limit it to be inside pwr range */ 2685 table_size = pwr_max[pdg] - pwr_min[pdg]; 2686 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2687 2688 /* Fill pdadc_out table */ 2689 while (pdadc_0 < max_idx && pdadc_i < 128) 2690 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2691 2692 /* Need to extrapolate above this pdgain? */ 2693 if (pdadc_n <= max_idx) 2694 continue; 2695 2696 /* Force each power step to be at least 0.5 dB */ 2697 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2698 pwr_step = pdadc_tmp[table_size - 1] - 2699 pdadc_tmp[table_size - 2]; 2700 else 2701 pwr_step = 1; 2702 2703 /* Extrapolate above */ 2704 while ((pdadc_0 < (s16) pdadc_n) && 2705 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2706 s16 tmp = pdadc_tmp[table_size - 1] + 2707 (pdadc_0 - max_idx) * pwr_step; 2708 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2709 pdadc_0++; 2710 } 2711 } 2712 2713 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2714 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2715 pdg++; 2716 } 2717 2718 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2719 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2720 pdadc_i++; 2721 } 2722 2723 /* Set gain boundaries */ 2724 ath5k_hw_reg_write(ah, 2725 AR5K_REG_SM(pd_gain_overlap, 2726 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2727 AR5K_REG_SM(gain_boundaries[0], 2728 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2729 AR5K_REG_SM(gain_boundaries[1], 2730 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2731 AR5K_REG_SM(gain_boundaries[2], 2732 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2733 AR5K_REG_SM(gain_boundaries[3], 2734 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2735 AR5K_PHY_TPC_RG5); 2736 2737 /* Used for setting rate power table */ 2738 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2739 2740} 2741 2742/* Write PDADC values on hw */ 2743static void 2744ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2745 u8 pdcurves, u8 *pdg_to_idx) 2746{ 2747 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2748 u32 reg; 2749 u8 i; 2750 2751 /* Select the right pdgain curves */ 2752 2753 /* Clear current settings */ 2754 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2755 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2756 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2757 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2758 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2759 2760 /* 2761 * Use pd_gains curve from eeprom 2762 * 2763 * This overrides the default setting from initvals 2764 * in case some vendors (e.g. Zcomax) don't use the default 2765 * curves. If we don't honor their settings we 'll get a 2766 * 5dB (1 * gain overlap ?) drop. 2767 */ 2768 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2769 2770 switch (pdcurves) { 2771 case 3: 2772 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2773 /* Fall through */ 2774 case 2: 2775 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2776 /* Fall through */ 2777 case 1: 2778 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2779 break; 2780 } 2781 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2782 2783 /* 2784 * Write TX power values 2785 */ 2786 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2787 ath5k_hw_reg_write(ah, 2788 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2789 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2790 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2791 ((pdadc_out[4*i + 3] & 0xff) << 24), 2792 AR5K_PHY_PDADC_TXPOWER(i)); 2793 } 2794} 2795 2796 2797/* 2798 * Common code for PCDAC/PDADC tables 2799 */ 2800 2801/* 2802 * This is the main function that uses all of the above 2803 * to set PCDAC/PDADC table on hw for the current channel. 2804 * This table is used for tx power calibration on the basband, 2805 * without it we get weird tx power levels and in some cases 2806 * distorted spectral mask 2807 */ 2808static int 2809ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2810 struct ieee80211_channel *channel, 2811 u8 ee_mode, u8 type) 2812{ 2813 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2814 struct ath5k_chan_pcal_info *pcinfo_L; 2815 struct ath5k_chan_pcal_info *pcinfo_R; 2816 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2817 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2818 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2819 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2820 u8 *tmpL; 2821 u8 *tmpR; 2822 u32 target = channel->center_freq; 2823 int pdg, i; 2824 2825 /* Get surounding freq piers for this channel */ 2826 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2827 &pcinfo_L, 2828 &pcinfo_R); 2829 2830 /* Loop over pd gain curves on 2831 * surounding freq piers by index */ 2832 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2833 2834 /* Fill curves in reverse order 2835 * from lower power (max gain) 2836 * to higher power. Use curve -> idx 2837 * backmapping we did on eeprom init */ 2838 u8 idx = pdg_curve_to_idx[pdg]; 2839 2840 /* Grab the needed curves by index */ 2841 pdg_L = &pcinfo_L->pd_curves[idx]; 2842 pdg_R = &pcinfo_R->pd_curves[idx]; 2843 2844 /* Initialize the temp tables */ 2845 tmpL = ah->ah_txpower.tmpL[pdg]; 2846 tmpR = ah->ah_txpower.tmpR[pdg]; 2847 2848 /* Set curve's x boundaries and create 2849 * curves so that they cover the same 2850 * range (if we don't do that one table 2851 * will have values on some range and the 2852 * other one won't have any so interpolation 2853 * will fail) */ 2854 table_min[pdg] = min(pdg_L->pd_pwr[0], 2855 pdg_R->pd_pwr[0]) / 2; 2856 2857 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2858 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2859 2860 /* Now create the curves on surrounding channels 2861 * and interpolate if needed to get the final 2862 * curve for this gain on this channel */ 2863 switch (type) { 2864 case AR5K_PWRTABLE_LINEAR_PCDAC: 2865 /* Override min/max so that we don't loose 2866 * accuracy (don't divide by 2) */ 2867 table_min[pdg] = min(pdg_L->pd_pwr[0], 2868 pdg_R->pd_pwr[0]); 2869 2870 table_max[pdg] = 2871 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2872 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2873 2874 /* Override minimum so that we don't get 2875 * out of bounds while extrapolating 2876 * below. Don't do this when we have 2 2877 * curves and we are on the high power curve 2878 * because table_min is ok in this case */ 2879 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2880 2881 table_min[pdg] = 2882 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2883 pdg_R->pd_step, 2884 pdg_L->pd_pwr, 2885 pdg_R->pd_pwr); 2886 2887 /* Don't go too low because we will 2888 * miss the upper part of the curve. 2889 * Note: 126 = 31.5dB (max power supported) 2890 * in 0.25dB units */ 2891 if (table_max[pdg] - table_min[pdg] > 126) 2892 table_min[pdg] = table_max[pdg] - 126; 2893 } 2894 2895 /* Fall through */ 2896 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2897 case AR5K_PWRTABLE_PWR_TO_PDADC: 2898 2899 ath5k_create_power_curve(table_min[pdg], 2900 table_max[pdg], 2901 pdg_L->pd_pwr, 2902 pdg_L->pd_step, 2903 pdg_L->pd_points, tmpL, type); 2904 2905 /* We are in a calibration 2906 * pier, no need to interpolate 2907 * between freq piers */ 2908 if (pcinfo_L == pcinfo_R) 2909 continue; 2910 2911 ath5k_create_power_curve(table_min[pdg], 2912 table_max[pdg], 2913 pdg_R->pd_pwr, 2914 pdg_R->pd_step, 2915 pdg_R->pd_points, tmpR, type); 2916 break; 2917 default: 2918 return -EINVAL; 2919 } 2920 2921 /* Interpolate between curves 2922 * of surounding freq piers to 2923 * get the final curve for this 2924 * pd gain. Re-use tmpL for interpolation 2925 * output */ 2926 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2927 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2928 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2929 (s16) pcinfo_L->freq, 2930 (s16) pcinfo_R->freq, 2931 (s16) tmpL[i], 2932 (s16) tmpR[i]); 2933 } 2934 } 2935 2936 /* Now we have a set of curves for this 2937 * channel on tmpL (x range is table_max - table_min 2938 * and y values are tmpL[pdg][]) sorted in the same 2939 * order as EEPROM (because we've used the backmapping). 2940 * So for RF5112 it's from higher power to lower power 2941 * and for RF2413 it's from lower power to higher power. 2942 * For RF5111 we only have one curve. */ 2943 2944 /* Fill min and max power levels for this 2945 * channel by interpolating the values on 2946 * surounding channels to complete the dataset */ 2947 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2948 (s16) pcinfo_L->freq, 2949 (s16) pcinfo_R->freq, 2950 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2951 2952 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2953 (s16) pcinfo_L->freq, 2954 (s16) pcinfo_R->freq, 2955 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2956 2957 /* We are ready to go, fill PCDAC/PDADC 2958 * table and write settings on hardware */ 2959 switch (type) { 2960 case AR5K_PWRTABLE_LINEAR_PCDAC: 2961 /* For RF5112 we can have one or two curves 2962 * and each curve covers a certain power lvl 2963 * range so we need to do some more processing */ 2964 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2965 ee->ee_pd_gains[ee_mode]); 2966 2967 /* Set txp.offset so that we can 2968 * match max power value with max 2969 * table index */ 2970 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2971 2972 /* Write settings on hw */ 2973 ath5k_setup_pcdac_table(ah); 2974 break; 2975 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2976 /* We are done for RF5111 since it has only 2977 * one curve, just fit the curve on the table */ 2978 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2979 2980 /* No rate powertable adjustment for RF5111 */ 2981 ah->ah_txpower.txp_min_idx = 0; 2982 ah->ah_txpower.txp_offset = 0; 2983 2984 /* Write settings on hw */ 2985 ath5k_setup_pcdac_table(ah); 2986 break; 2987 case AR5K_PWRTABLE_PWR_TO_PDADC: 2988 /* Set PDADC boundaries and fill 2989 * final PDADC table */ 2990 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2991 ee->ee_pd_gains[ee_mode]); 2992 2993 /* Write settings on hw */ 2994 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2995 2996 /* Set txp.offset, note that table_min 2997 * can be negative */ 2998 ah->ah_txpower.txp_offset = table_min[0]; 2999 break; 3000 default: 3001 return -EINVAL; 3002 } 3003 3004 return 0; 3005} 3006 3007 3008/* 3009 * Per-rate tx power setting 3010 * 3011 * This is the code that sets the desired tx power (below 3012 * maximum) on hw for each rate (we also have TPC that sets 3013 * power per packet). We do that by providing an index on the 3014 * PCDAC/PDADC table we set up. 3015 */ 3016 3017/* 3018 * Set rate power table 3019 * 3020 * For now we only limit txpower based on maximum tx power 3021 * supported by hw (what's inside rate_info). We need to limit 3022 * this even more, based on regulatory domain etc. 3023 * 3024 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3025 * and is indexed as follows: 3026 * rates[0] - rates[7] -> OFDM rates 3027 * rates[8] - rates[14] -> CCK rates 3028 * rates[15] -> XR rates (they all have the same power) 3029 */ 3030static void 3031ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3032 struct ath5k_rate_pcal_info *rate_info, 3033 u8 ee_mode) 3034{ 3035 unsigned int i; 3036 u16 *rates; 3037 3038 /* max_pwr is power level we got from driver/user in 0.5dB 3039 * units, switch to 0.25dB units so we can compare */ 3040 max_pwr *= 2; 3041 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3042 3043 /* apply rate limits */ 3044 rates = ah->ah_txpower.txp_rates_power_table; 3045 3046 /* OFDM rates 6 to 24Mb/s */ 3047 for (i = 0; i < 5; i++) 3048 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3049 3050 /* Rest OFDM rates */ 3051 rates[5] = min(rates[0], rate_info->target_power_36); 3052 rates[6] = min(rates[0], rate_info->target_power_48); 3053 rates[7] = min(rates[0], rate_info->target_power_54); 3054 3055 /* CCK rates */ 3056 /* 1L */ 3057 rates[8] = min(rates[0], rate_info->target_power_6to24); 3058 /* 2L */ 3059 rates[9] = min(rates[0], rate_info->target_power_36); 3060 /* 2S */ 3061 rates[10] = min(rates[0], rate_info->target_power_36); 3062 /* 5L */ 3063 rates[11] = min(rates[0], rate_info->target_power_48); 3064 /* 5S */ 3065 rates[12] = min(rates[0], rate_info->target_power_48); 3066 /* 11L */ 3067 rates[13] = min(rates[0], rate_info->target_power_54); 3068 /* 11S */ 3069 rates[14] = min(rates[0], rate_info->target_power_54); 3070 3071 /* XR rates */ 3072 rates[15] = min(rates[0], rate_info->target_power_6to24); 3073 3074 /* CCK rates have different peak to average ratio 3075 * so we have to tweak their power so that gainf 3076 * correction works ok. For this we use OFDM to 3077 * CCK delta from eeprom */ 3078 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3079 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3080 for (i = 8; i <= 15; i++) 3081 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3082 3083 /* Now that we have all rates setup use table offset to 3084 * match the power range set by user with the power indices 3085 * on PCDAC/PDADC table */ 3086 for (i = 0; i < 16; i++) { 3087 rates[i] += ah->ah_txpower.txp_offset; 3088 /* Don't get out of bounds */ 3089 if (rates[i] > 63) 3090 rates[i] = 63; 3091 } 3092 3093 /* Min/max in 0.25dB units */ 3094 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3095 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 3096 ah->ah_txpower.txp_ofdm = rates[7]; 3097} 3098 3099 3100/* 3101 * Set transmission power 3102 */ 3103static int 3104ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3105 u8 ee_mode, u8 txpower, bool fast) 3106{ 3107 struct ath5k_rate_pcal_info rate_info; 3108 u8 type; 3109 int ret; 3110 3111 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3112 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3113 return -EINVAL; 3114 } 3115 3116 /* Reset TX power values */ 3117 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3118 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3119 ah->ah_txpower.txp_min_pwr = 0; 3120 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 3121 3122 /* Initialize TX power table */ 3123 switch (ah->ah_radio) { 3124 case AR5K_RF5110: 3125 /* TODO */ 3126 return 0; 3127 case AR5K_RF5111: 3128 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3129 break; 3130 case AR5K_RF5112: 3131 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3132 break; 3133 case AR5K_RF2413: 3134 case AR5K_RF5413: 3135 case AR5K_RF2316: 3136 case AR5K_RF2317: 3137 case AR5K_RF2425: 3138 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3139 break; 3140 default: 3141 return -EINVAL; 3142 } 3143 3144 /* If fast is set it means we are on the same channel/mode 3145 * so there is no need to recalculate the powertable, we 'll 3146 * just use the cached one */ 3147 if (!fast) { 3148 ret = ath5k_setup_channel_powertable(ah, channel, 3149 ee_mode, type); 3150 if (ret) 3151 return ret; 3152 } 3153 3154 /* Limit max power if we have a CTL available */ 3155 ath5k_get_max_ctl_power(ah, channel); 3156 3157 /* FIXME: Antenna reduction stuff */ 3158 3159 /* FIXME: Limit power on turbo modes */ 3160 3161 /* FIXME: TPC scale reduction */ 3162 3163 /* Get surounding channels for per-rate power table 3164 * calibration */ 3165 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3166 3167 /* Setup rate power table */ 3168 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3169 3170 /* Write rate power table on hw */ 3171 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3172 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3173 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3174 3175 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3176 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3177 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3178 3179 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3180 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3181 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3182 3183 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3184 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3185 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3186 3187 /* FIXME: TPC support */ 3188 if (ah->ah_txpower.txp_tpc) { 3189 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3190 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3191 3192 ath5k_hw_reg_write(ah, 3193 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3194 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3195 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3196 AR5K_TPC); 3197 } else { 3198 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3199 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3200 } 3201 3202 return 0; 3203} 3204 3205int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3206{ 3207 /*Just a try M.F.*/ 3208 struct ieee80211_channel *channel = ah->ah_current_channel; 3209 u8 ee_mode; 3210 3211 switch (channel->hw_value & CHANNEL_MODES) { 3212 case CHANNEL_A: 3213 case CHANNEL_T: 3214 case CHANNEL_XR: 3215 ee_mode = AR5K_EEPROM_MODE_11A; 3216 break; 3217 case CHANNEL_G: 3218 case CHANNEL_TG: 3219 ee_mode = AR5K_EEPROM_MODE_11G; 3220 break; 3221 case CHANNEL_B: 3222 ee_mode = AR5K_EEPROM_MODE_11B; 3223 break; 3224 default: 3225 ATH5K_ERR(ah->ah_sc, 3226 "invalid channel: %d\n", channel->center_freq); 3227 return -EINVAL; 3228 } 3229 3230 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3231 "changing txpower to %d\n", txpower); 3232 3233 return ath5k_hw_txpower(ah, channel, ee_mode, txpower, true); 3234} 3235 3236/*************\ 3237 Init function 3238\*************/ 3239 3240int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3241 u8 mode, u8 ee_mode, u8 freq, bool fast) 3242{ 3243 struct ieee80211_channel *curr_channel; 3244 int ret, i; 3245 u32 phy_tst1; 3246 bool fast_txp; 3247 ret = 0; 3248 3249 /* 3250 * Sanity check for fast flag 3251 * Don't try fast channel change when changing modulation 3252 * mode/band. We check for chip compatibility on 3253 * ath5k_hw_reset. 3254 */ 3255 curr_channel = ah->ah_current_channel; 3256 if (fast && (channel->hw_value != curr_channel->hw_value)) 3257 return -EINVAL; 3258 3259 /* 3260 * On fast channel change we only set the synth parameters 3261 * while PHY is running, enable calibration and skip the rest. 3262 */ 3263 if (fast) { 3264 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3265 AR5K_PHY_RFBUS_REQ_REQUEST); 3266 for (i = 0; i < 100; i++) { 3267 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3268 break; 3269 udelay(5); 3270 } 3271 /* Failed */ 3272 if (i >= 100) 3273 return -EIO; 3274 } 3275 3276 /* 3277 * If we don't change channel/mode skip 3278 * tx powertable calculation and use the 3279 * cached one. 3280 */ 3281 if ((channel->hw_value == curr_channel->hw_value) && 3282 (channel->center_freq == curr_channel->center_freq)) 3283 fast_txp = true; 3284 else 3285 fast_txp = false; 3286 3287 /* 3288 * Set TX power 3289 * 3290 * Note: We need to do that before we set 3291 * RF buffer settings on 5211/5212+ so that we 3292 * properly set curve indices. 3293 */ 3294 ret = ath5k_hw_txpower(ah, channel, ee_mode, 3295 ah->ah_txpower.txp_max_pwr / 2, 3296 fast_txp); 3297 if (ret) 3298 return ret; 3299 3300 /* 3301 * For 5210 we do all initialization using 3302 * initvals, so we don't have to modify 3303 * any settings (5210 also only supports 3304 * a/aturbo modes) 3305 */ 3306 if ((ah->ah_version != AR5K_AR5210) && !fast) { 3307 3308 /* 3309 * Write initial RF gain settings 3310 * This should work for both 5111/5112 3311 */ 3312 ret = ath5k_hw_rfgain_init(ah, freq); 3313 if (ret) 3314 return ret; 3315 3316 mdelay(1); 3317 3318 /* 3319 * Write RF buffer 3320 */ 3321 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3322 if (ret) 3323 return ret; 3324 3325 /* Write OFDM timings on 5212*/ 3326 if (ah->ah_version == AR5K_AR5212 && 3327 channel->hw_value & CHANNEL_OFDM) { 3328 3329 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3330 if (ret) 3331 return ret; 3332 3333 /* Spur info is available only from EEPROM versions 3334 * greater than 5.3, but the EEPROM routines will use 3335 * static values for older versions */ 3336 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3337 ath5k_hw_set_spur_mitigation_filter(ah, 3338 channel); 3339 } 3340 3341 /*Enable/disable 802.11b mode on 5111 3342 (enable 2111 frequency converter + CCK)*/ 3343 if (ah->ah_radio == AR5K_RF5111) { 3344 if (mode == AR5K_MODE_11B) 3345 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3346 AR5K_TXCFG_B_MODE); 3347 else 3348 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3349 AR5K_TXCFG_B_MODE); 3350 } 3351 3352 } else if (ah->ah_version == AR5K_AR5210) { 3353 mdelay(1); 3354 /* Disable phy and wait */ 3355 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3356 mdelay(1); 3357 } 3358 3359 /* Set channel on PHY */ 3360 ret = ath5k_hw_channel(ah, channel); 3361 if (ret) 3362 return ret; 3363 3364 /* 3365 * Enable the PHY and wait until completion 3366 * This includes BaseBand and Synthesizer 3367 * activation. 3368 */ 3369 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3370 3371 /* 3372 * On 5211+ read activation -> rx delay 3373 * and use it. 3374 */ 3375 if (ah->ah_version != AR5K_AR5210) { 3376 u32 delay; 3377 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 3378 AR5K_PHY_RX_DELAY_M; 3379 delay = (channel->hw_value & CHANNEL_CCK) ? 3380 ((delay << 2) / 22) : (delay / 10); 3381 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 3382 delay = delay << 1; 3383 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 3384 delay = delay << 2; 3385 /* XXX: /2 on turbo ? Let's be safe 3386 * for now */ 3387 udelay(100 + delay); 3388 } else { 3389 mdelay(1); 3390 } 3391 3392 if (fast) 3393 /* 3394 * Release RF Bus grant 3395 */ 3396 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3397 AR5K_PHY_RFBUS_REQ_REQUEST); 3398 else { 3399 /* 3400 * Perform ADC test to see if baseband is ready 3401 * Set tx hold and check adc test register 3402 */ 3403 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3404 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3405 for (i = 0; i <= 20; i++) { 3406 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3407 break; 3408 udelay(200); 3409 } 3410 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3411 } 3412 3413 /* 3414 * Start automatic gain control calibration 3415 * 3416 * During AGC calibration RX path is re-routed to 3417 * a power detector so we don't receive anything. 3418 * 3419 * This method is used to calibrate some static offsets 3420 * used together with on-the fly I/Q calibration (the 3421 * one performed via ath5k_hw_phy_calibrate), which doesn't 3422 * interrupt rx path. 3423 * 3424 * While rx path is re-routed to the power detector we also 3425 * start a noise floor calibration to measure the 3426 * card's noise floor (the noise we measure when we are not 3427 * transmitting or receiving anything). 3428 * 3429 * If we are in a noisy environment, AGC calibration may time 3430 * out and/or noise floor calibration might timeout. 3431 */ 3432 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3433 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3434 3435 /* At the same time start I/Q calibration for QAM constellation 3436 * -no need for CCK- */ 3437 ah->ah_calibration = false; 3438 if (!(mode == AR5K_MODE_11B)) { 3439 ah->ah_calibration = true; 3440 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3441 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3442 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3443 AR5K_PHY_IQ_RUN); 3444 } 3445 3446 /* Wait for gain calibration to finish (we check for I/Q calibration 3447 * during ath5k_phy_calibrate) */ 3448 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3449 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3450 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3451 channel->center_freq); 3452 } 3453 3454 /* Restore antenna mode */ 3455 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3456 3457 return ret; 3458} 3459