phy.c revision 9320b5c4a7260d9593102f378201d17e3f030739
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32 33/******************\ 34* Helper functions * 35\******************/ 36 37/* 38 * Get the PHY Chip revision 39 */ 40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41{ 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81} 82 83/* 84 * Check if a channel is supported 85 */ 86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87{ 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99} 100 101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103{ 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119} 120 121/* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127{ 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200} 201 202/** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219{ 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 /* TODO: Half/quarter rate */ 232 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40; 233 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 234 235 /* Get exponent 236 * ALGO: coef_exp = 14 - highest set bit position */ 237 coef_exp = ilog2(coef_scaled); 238 239 /* Doesn't make sense if it's zero*/ 240 if (!coef_scaled || !coef_exp) 241 return -EINVAL; 242 243 /* Note: we've shifted coef_scaled by 24 */ 244 coef_exp = 14 - (coef_exp - 24); 245 246 247 /* Get mantissa (significant digits) 248 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 249 coef_man = coef_scaled + 250 (1 << (24 - coef_exp - 1)); 251 252 /* Calculate delta slope coefficient exponent 253 * and mantissa (remove scaling) and set them on hw */ 254 ds_coef_man = coef_man >> (24 - coef_exp); 255 ds_coef_exp = coef_exp - 16; 256 257 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 258 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 259 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 260 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 261 262 return 0; 263} 264 265int ath5k_hw_phy_disable(struct ath5k_hw *ah) 266{ 267 /*Just a try M.F.*/ 268 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 269 270 return 0; 271} 272 273 274/**********************\ 275* RF Gain optimization * 276\**********************/ 277 278/* 279 * This code is used to optimize RF gain on different environments 280 * (temperature mostly) based on feedback from a power detector. 281 * 282 * It's only used on RF5111 and RF5112, later RF chips seem to have 283 * auto adjustment on hw -notice they have a much smaller BANK 7 and 284 * no gain optimization ladder-. 285 * 286 * For more infos check out this patent doc 287 * http://www.freepatentsonline.com/7400691.html 288 * 289 * This paper describes power drops as seen on the receiver due to 290 * probe packets 291 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 292 * %20of%20Power%20Control.pdf 293 * 294 * And this is the MadWiFi bug entry related to the above 295 * http://madwifi-project.org/ticket/1659 296 * with various measurements and diagrams 297 * 298 * TODO: Deal with power drops due to probes by setting an apropriate 299 * tx power on the probe packets ! Make this part of the calibration process. 300 */ 301 302/* Initialize ah_gain durring attach */ 303int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 304{ 305 /* Initialize the gain optimization values */ 306 switch (ah->ah_radio) { 307 case AR5K_RF5111: 308 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 309 ah->ah_gain.g_low = 20; 310 ah->ah_gain.g_high = 35; 311 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 312 break; 313 case AR5K_RF5112: 314 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 315 ah->ah_gain.g_low = 20; 316 ah->ah_gain.g_high = 85; 317 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 318 break; 319 default: 320 return -EINVAL; 321 } 322 323 return 0; 324} 325 326/* Schedule a gain probe check on the next transmited packet. 327 * That means our next packet is going to be sent with lower 328 * tx power and a Peak to Average Power Detector (PAPD) will try 329 * to measure the gain. 330 * 331 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 332 * just after we enable the probe so that we don't mess with 333 * standard traffic ? Maybe it's time to use sw interrupts and 334 * a probe tasklet !!! 335 */ 336static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 337{ 338 339 /* Skip if gain calibration is inactive or 340 * we already handle a probe request */ 341 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 342 return; 343 344 /* Send the packet with 2dB below max power as 345 * patent doc suggest */ 346 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 347 AR5K_PHY_PAPD_PROBE_TXPOWER) | 348 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 349 350 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 351 352} 353 354/* Calculate gain_F measurement correction 355 * based on the current step for RF5112 rev. 2 */ 356static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 357{ 358 u32 mix, step; 359 u32 *rf; 360 const struct ath5k_gain_opt *go; 361 const struct ath5k_gain_opt_step *g_step; 362 const struct ath5k_rf_reg *rf_regs; 363 364 /* Only RF5112 Rev. 2 supports it */ 365 if ((ah->ah_radio != AR5K_RF5112) || 366 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 367 return 0; 368 369 go = &rfgain_opt_5112; 370 rf_regs = rf_regs_5112a; 371 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 372 373 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 374 375 if (ah->ah_rf_banks == NULL) 376 return 0; 377 378 rf = ah->ah_rf_banks; 379 ah->ah_gain.g_f_corr = 0; 380 381 /* No VGA (Variable Gain Amplifier) override, skip */ 382 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 383 return 0; 384 385 /* Mix gain stepping */ 386 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 387 388 /* Mix gain override */ 389 mix = g_step->gos_param[0]; 390 391 switch (mix) { 392 case 3: 393 ah->ah_gain.g_f_corr = step * 2; 394 break; 395 case 2: 396 ah->ah_gain.g_f_corr = (step - 5) * 2; 397 break; 398 case 1: 399 ah->ah_gain.g_f_corr = step; 400 break; 401 default: 402 ah->ah_gain.g_f_corr = 0; 403 break; 404 } 405 406 return ah->ah_gain.g_f_corr; 407} 408 409/* Check if current gain_F measurement is in the range of our 410 * power detector windows. If we get a measurement outside range 411 * we know it's not accurate (detectors can't measure anything outside 412 * their detection window) so we must ignore it */ 413static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 414{ 415 const struct ath5k_rf_reg *rf_regs; 416 u32 step, mix_ovr, level[4]; 417 u32 *rf; 418 419 if (ah->ah_rf_banks == NULL) 420 return false; 421 422 rf = ah->ah_rf_banks; 423 424 if (ah->ah_radio == AR5K_RF5111) { 425 426 rf_regs = rf_regs_5111; 427 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 428 429 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 430 false); 431 432 level[0] = 0; 433 level[1] = (step == 63) ? 50 : step + 4; 434 level[2] = (step != 63) ? 64 : level[0]; 435 level[3] = level[2] + 50 ; 436 437 ah->ah_gain.g_high = level[3] - 438 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 439 ah->ah_gain.g_low = level[0] + 440 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 441 } else { 442 443 rf_regs = rf_regs_5112; 444 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 445 446 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 447 false); 448 449 level[0] = level[2] = 0; 450 451 if (mix_ovr == 1) { 452 level[1] = level[3] = 83; 453 } else { 454 level[1] = level[3] = 107; 455 ah->ah_gain.g_high = 55; 456 } 457 } 458 459 return (ah->ah_gain.g_current >= level[0] && 460 ah->ah_gain.g_current <= level[1]) || 461 (ah->ah_gain.g_current >= level[2] && 462 ah->ah_gain.g_current <= level[3]); 463} 464 465/* Perform gain_F adjustment by choosing the right set 466 * of parameters from RF gain optimization ladder */ 467static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 468{ 469 const struct ath5k_gain_opt *go; 470 const struct ath5k_gain_opt_step *g_step; 471 int ret = 0; 472 473 switch (ah->ah_radio) { 474 case AR5K_RF5111: 475 go = &rfgain_opt_5111; 476 break; 477 case AR5K_RF5112: 478 go = &rfgain_opt_5112; 479 break; 480 default: 481 return 0; 482 } 483 484 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 485 486 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 487 488 /* Reached maximum */ 489 if (ah->ah_gain.g_step_idx == 0) 490 return -1; 491 492 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 493 ah->ah_gain.g_target >= ah->ah_gain.g_high && 494 ah->ah_gain.g_step_idx > 0; 495 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 496 ah->ah_gain.g_target -= 2 * 497 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 498 g_step->gos_gain); 499 500 ret = 1; 501 goto done; 502 } 503 504 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 505 506 /* Reached minimum */ 507 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 508 return -2; 509 510 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 511 ah->ah_gain.g_target <= ah->ah_gain.g_low && 512 ah->ah_gain.g_step_idx < go->go_steps_count-1; 513 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 514 ah->ah_gain.g_target -= 2 * 515 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 516 g_step->gos_gain); 517 518 ret = 2; 519 goto done; 520 } 521 522done: 523 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 524 "ret %d, gain step %u, current gain %u, target gain %u\n", 525 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 526 ah->ah_gain.g_target); 527 528 return ret; 529} 530 531/* Main callback for thermal RF gain calibration engine 532 * Check for a new gain reading and schedule an adjustment 533 * if needed. 534 * 535 * TODO: Use sw interrupt to schedule reset if gain_F needs 536 * adjustment */ 537enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 538{ 539 u32 data, type; 540 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 541 542 if (ah->ah_rf_banks == NULL || 543 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 544 return AR5K_RFGAIN_INACTIVE; 545 546 /* No check requested, either engine is inactive 547 * or an adjustment is already requested */ 548 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 549 goto done; 550 551 /* Read the PAPD (Peak to Average Power Detector) 552 * register */ 553 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 554 555 /* No probe is scheduled, read gain_F measurement */ 556 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 557 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 558 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 559 560 /* If tx packet is CCK correct the gain_F measurement 561 * by cck ofdm gain delta */ 562 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 563 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 564 ah->ah_gain.g_current += 565 ee->ee_cck_ofdm_gain_delta; 566 else 567 ah->ah_gain.g_current += 568 AR5K_GAIN_CCK_PROBE_CORR; 569 } 570 571 /* Further correct gain_F measurement for 572 * RF5112A radios */ 573 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 574 ath5k_hw_rf_gainf_corr(ah); 575 ah->ah_gain.g_current = 576 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 577 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 578 0; 579 } 580 581 /* Check if measurement is ok and if we need 582 * to adjust gain, schedule a gain adjustment, 583 * else switch back to the acive state */ 584 if (ath5k_hw_rf_check_gainf_readback(ah) && 585 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 586 ath5k_hw_rf_gainf_adjust(ah)) { 587 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 588 } else { 589 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 590 } 591 } 592 593done: 594 return ah->ah_gain.g_state; 595} 596 597/* Write initial RF gain table to set the RF sensitivity 598 * this one works on all RF chips and has nothing to do 599 * with gain_F calibration */ 600static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 601{ 602 const struct ath5k_ini_rfgain *ath5k_rfg; 603 unsigned int i, size; 604 605 switch (ah->ah_radio) { 606 case AR5K_RF5111: 607 ath5k_rfg = rfgain_5111; 608 size = ARRAY_SIZE(rfgain_5111); 609 break; 610 case AR5K_RF5112: 611 ath5k_rfg = rfgain_5112; 612 size = ARRAY_SIZE(rfgain_5112); 613 break; 614 case AR5K_RF2413: 615 ath5k_rfg = rfgain_2413; 616 size = ARRAY_SIZE(rfgain_2413); 617 break; 618 case AR5K_RF2316: 619 ath5k_rfg = rfgain_2316; 620 size = ARRAY_SIZE(rfgain_2316); 621 break; 622 case AR5K_RF5413: 623 ath5k_rfg = rfgain_5413; 624 size = ARRAY_SIZE(rfgain_5413); 625 break; 626 case AR5K_RF2317: 627 case AR5K_RF2425: 628 ath5k_rfg = rfgain_2425; 629 size = ARRAY_SIZE(rfgain_2425); 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 switch (freq) { 636 case AR5K_INI_RFGAIN_2GHZ: 637 case AR5K_INI_RFGAIN_5GHZ: 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 for (i = 0; i < size; i++) { 644 AR5K_REG_WAIT(i); 645 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 646 (u32)ath5k_rfg[i].rfg_register); 647 } 648 649 return 0; 650} 651 652 653 654/********************\ 655* RF Registers setup * 656\********************/ 657 658/* 659 * Setup RF registers by writing RF buffer on hw 660 */ 661static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 662 struct ieee80211_channel *channel, unsigned int mode) 663{ 664 const struct ath5k_rf_reg *rf_regs; 665 const struct ath5k_ini_rfbuffer *ini_rfb; 666 const struct ath5k_gain_opt *go = NULL; 667 const struct ath5k_gain_opt_step *g_step; 668 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 669 u8 ee_mode = 0; 670 u32 *rfb; 671 int i, obdb = -1, bank = -1; 672 673 switch (ah->ah_radio) { 674 case AR5K_RF5111: 675 rf_regs = rf_regs_5111; 676 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 677 ini_rfb = rfb_5111; 678 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 679 go = &rfgain_opt_5111; 680 break; 681 case AR5K_RF5112: 682 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 683 rf_regs = rf_regs_5112a; 684 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 685 ini_rfb = rfb_5112a; 686 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 687 } else { 688 rf_regs = rf_regs_5112; 689 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 690 ini_rfb = rfb_5112; 691 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 692 } 693 go = &rfgain_opt_5112; 694 break; 695 case AR5K_RF2413: 696 rf_regs = rf_regs_2413; 697 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 698 ini_rfb = rfb_2413; 699 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 700 break; 701 case AR5K_RF2316: 702 rf_regs = rf_regs_2316; 703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 704 ini_rfb = rfb_2316; 705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 706 break; 707 case AR5K_RF5413: 708 rf_regs = rf_regs_5413; 709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 710 ini_rfb = rfb_5413; 711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 712 break; 713 case AR5K_RF2317: 714 rf_regs = rf_regs_2425; 715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 716 ini_rfb = rfb_2317; 717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 718 break; 719 case AR5K_RF2425: 720 rf_regs = rf_regs_2425; 721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 722 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 723 ini_rfb = rfb_2425; 724 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 725 } else { 726 ini_rfb = rfb_2417; 727 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 728 } 729 break; 730 default: 731 return -EINVAL; 732 } 733 734 /* If it's the first time we set RF buffer, allocate 735 * ah->ah_rf_banks based on ah->ah_rf_banks_size 736 * we set above */ 737 if (ah->ah_rf_banks == NULL) { 738 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 739 GFP_KERNEL); 740 if (ah->ah_rf_banks == NULL) { 741 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 742 return -ENOMEM; 743 } 744 } 745 746 /* Copy values to modify them */ 747 rfb = ah->ah_rf_banks; 748 749 for (i = 0; i < ah->ah_rf_banks_size; i++) { 750 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 751 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 752 return -EINVAL; 753 } 754 755 /* Bank changed, write down the offset */ 756 if (bank != ini_rfb[i].rfb_bank) { 757 bank = ini_rfb[i].rfb_bank; 758 ah->ah_offset[bank] = i; 759 } 760 761 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 762 } 763 764 /* Set Output and Driver bias current (OB/DB) */ 765 if (channel->hw_value & CHANNEL_2GHZ) { 766 767 if (channel->hw_value & CHANNEL_CCK) 768 ee_mode = AR5K_EEPROM_MODE_11B; 769 else 770 ee_mode = AR5K_EEPROM_MODE_11G; 771 772 /* For RF511X/RF211X combination we 773 * use b_OB and b_DB parameters stored 774 * in eeprom on ee->ee_ob[ee_mode][0] 775 * 776 * For all other chips we use OB/DB for 2Ghz 777 * stored in the b/g modal section just like 778 * 802.11a on ee->ee_ob[ee_mode][1] */ 779 if ((ah->ah_radio == AR5K_RF5111) || 780 (ah->ah_radio == AR5K_RF5112)) 781 obdb = 0; 782 else 783 obdb = 1; 784 785 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 786 AR5K_RF_OB_2GHZ, true); 787 788 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 789 AR5K_RF_DB_2GHZ, true); 790 791 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 792 } else if ((channel->hw_value & CHANNEL_5GHZ) || 793 (ah->ah_radio == AR5K_RF5111)) { 794 795 /* For 11a, Turbo and XR we need to choose 796 * OB/DB based on frequency range */ 797 ee_mode = AR5K_EEPROM_MODE_11A; 798 obdb = channel->center_freq >= 5725 ? 3 : 799 (channel->center_freq >= 5500 ? 2 : 800 (channel->center_freq >= 5260 ? 1 : 801 (channel->center_freq > 4000 ? 0 : -1))); 802 803 if (obdb < 0) 804 return -EINVAL; 805 806 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 807 AR5K_RF_OB_5GHZ, true); 808 809 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 810 AR5K_RF_DB_5GHZ, true); 811 } 812 813 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 814 815 /* Bank Modifications (chip-specific) */ 816 if (ah->ah_radio == AR5K_RF5111) { 817 818 /* Set gain_F settings according to current step */ 819 if (channel->hw_value & CHANNEL_OFDM) { 820 821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 822 AR5K_PHY_FRAME_CTL_TX_CLIP, 823 g_step->gos_param[0]); 824 825 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 826 AR5K_RF_PWD_90, true); 827 828 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 829 AR5K_RF_PWD_84, true); 830 831 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 832 AR5K_RF_RFGAIN_SEL, true); 833 834 /* We programmed gain_F parameters, switch back 835 * to active state */ 836 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 837 838 } 839 840 /* Bank 6/7 setup */ 841 842 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 843 AR5K_RF_PWD_XPD, true); 844 845 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 846 AR5K_RF_XPD_GAIN, true); 847 848 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 849 AR5K_RF_GAIN_I, true); 850 851 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 852 AR5K_RF_PLO_SEL, true); 853 854 /* TODO: Half/quarter channel support */ 855 } 856 857 if (ah->ah_radio == AR5K_RF5112) { 858 859 /* Set gain_F settings according to current step */ 860 if (channel->hw_value & CHANNEL_OFDM) { 861 862 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 863 AR5K_RF_MIXGAIN_OVR, true); 864 865 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 866 AR5K_RF_PWD_138, true); 867 868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 869 AR5K_RF_PWD_137, true); 870 871 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 872 AR5K_RF_PWD_136, true); 873 874 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 875 AR5K_RF_PWD_132, true); 876 877 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 878 AR5K_RF_PWD_131, true); 879 880 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 881 AR5K_RF_PWD_130, true); 882 883 /* We programmed gain_F parameters, switch back 884 * to active state */ 885 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 886 } 887 888 /* Bank 6/7 setup */ 889 890 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 891 AR5K_RF_XPD_SEL, true); 892 893 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 894 /* Rev. 1 supports only one xpd */ 895 ath5k_hw_rfb_op(ah, rf_regs, 896 ee->ee_x_gain[ee_mode], 897 AR5K_RF_XPD_GAIN, true); 898 899 } else { 900 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 901 if (ee->ee_pd_gains[ee_mode] > 1) { 902 ath5k_hw_rfb_op(ah, rf_regs, 903 pdg_curve_to_idx[0], 904 AR5K_RF_PD_GAIN_LO, true); 905 ath5k_hw_rfb_op(ah, rf_regs, 906 pdg_curve_to_idx[1], 907 AR5K_RF_PD_GAIN_HI, true); 908 } else { 909 ath5k_hw_rfb_op(ah, rf_regs, 910 pdg_curve_to_idx[0], 911 AR5K_RF_PD_GAIN_LO, true); 912 ath5k_hw_rfb_op(ah, rf_regs, 913 pdg_curve_to_idx[0], 914 AR5K_RF_PD_GAIN_HI, true); 915 } 916 917 /* Lower synth voltage on Rev 2 */ 918 ath5k_hw_rfb_op(ah, rf_regs, 2, 919 AR5K_RF_HIGH_VC_CP, true); 920 921 ath5k_hw_rfb_op(ah, rf_regs, 2, 922 AR5K_RF_MID_VC_CP, true); 923 924 ath5k_hw_rfb_op(ah, rf_regs, 2, 925 AR5K_RF_LOW_VC_CP, true); 926 927 ath5k_hw_rfb_op(ah, rf_regs, 2, 928 AR5K_RF_PUSH_UP, true); 929 930 /* Decrease power consumption on 5213+ BaseBand */ 931 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 932 ath5k_hw_rfb_op(ah, rf_regs, 1, 933 AR5K_RF_PAD2GND, true); 934 935 ath5k_hw_rfb_op(ah, rf_regs, 1, 936 AR5K_RF_XB2_LVL, true); 937 938 ath5k_hw_rfb_op(ah, rf_regs, 1, 939 AR5K_RF_XB5_LVL, true); 940 941 ath5k_hw_rfb_op(ah, rf_regs, 1, 942 AR5K_RF_PWD_167, true); 943 944 ath5k_hw_rfb_op(ah, rf_regs, 1, 945 AR5K_RF_PWD_166, true); 946 } 947 } 948 949 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 950 AR5K_RF_GAIN_I, true); 951 952 /* TODO: Half/quarter channel support */ 953 954 } 955 956 if (ah->ah_radio == AR5K_RF5413 && 957 channel->hw_value & CHANNEL_2GHZ) { 958 959 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 960 true); 961 962 /* Set optimum value for early revisions (on pci-e chips) */ 963 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 964 ah->ah_mac_srev < AR5K_SREV_AR5413) 965 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 966 AR5K_RF_PWD_ICLOBUF_2G, true); 967 968 } 969 970 /* Write RF banks on hw */ 971 for (i = 0; i < ah->ah_rf_banks_size; i++) { 972 AR5K_REG_WAIT(i); 973 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 974 } 975 976 return 0; 977} 978 979 980/**************************\ 981 PHY/RF channel functions 982\**************************/ 983 984/* 985 * Convertion needed for RF5110 986 */ 987static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 988{ 989 u32 athchan; 990 991 /* 992 * Convert IEEE channel/MHz to an internal channel value used 993 * by the AR5210 chipset. This has not been verified with 994 * newer chipsets like the AR5212A who have a completely 995 * different RF/PHY part. 996 */ 997 athchan = (ath5k_hw_bitswap( 998 (ieee80211_frequency_to_channel( 999 channel->center_freq) - 24) / 2, 5) 1000 << 1) | (1 << 6) | 0x1; 1001 return athchan; 1002} 1003 1004/* 1005 * Set channel on RF5110 1006 */ 1007static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1008 struct ieee80211_channel *channel) 1009{ 1010 u32 data; 1011 1012 /* 1013 * Set the channel and wait 1014 */ 1015 data = ath5k_hw_rf5110_chan2athchan(channel); 1016 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1017 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1018 mdelay(1); 1019 1020 return 0; 1021} 1022 1023/* 1024 * Convertion needed for 5111 1025 */ 1026static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1027 struct ath5k_athchan_2ghz *athchan) 1028{ 1029 int channel; 1030 1031 /* Cast this value to catch negative channel numbers (>= -19) */ 1032 channel = (int)ieee; 1033 1034 /* 1035 * Map 2GHz IEEE channel to 5GHz Atheros channel 1036 */ 1037 if (channel <= 13) { 1038 athchan->a2_athchan = 115 + channel; 1039 athchan->a2_flags = 0x46; 1040 } else if (channel == 14) { 1041 athchan->a2_athchan = 124; 1042 athchan->a2_flags = 0x44; 1043 } else if (channel >= 15 && channel <= 26) { 1044 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1045 athchan->a2_flags = 0x46; 1046 } else 1047 return -EINVAL; 1048 1049 return 0; 1050} 1051 1052/* 1053 * Set channel on 5111 1054 */ 1055static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1056 struct ieee80211_channel *channel) 1057{ 1058 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1059 unsigned int ath5k_channel = 1060 ieee80211_frequency_to_channel(channel->center_freq); 1061 u32 data0, data1, clock; 1062 int ret; 1063 1064 /* 1065 * Set the channel on the RF5111 radio 1066 */ 1067 data0 = data1 = 0; 1068 1069 if (channel->hw_value & CHANNEL_2GHZ) { 1070 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1071 ret = ath5k_hw_rf5111_chan2athchan( 1072 ieee80211_frequency_to_channel(channel->center_freq), 1073 &ath5k_channel_2ghz); 1074 if (ret) 1075 return ret; 1076 1077 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1078 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1079 << 5) | (1 << 4); 1080 } 1081 1082 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1083 clock = 1; 1084 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1085 (clock << 1) | (1 << 10) | 1; 1086 } else { 1087 clock = 0; 1088 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1089 << 2) | (clock << 1) | (1 << 10) | 1; 1090 } 1091 1092 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1093 AR5K_RF_BUFFER); 1094 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1095 AR5K_RF_BUFFER_CONTROL_3); 1096 1097 return 0; 1098} 1099 1100/* 1101 * Set channel on 5112 and newer 1102 */ 1103static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1104 struct ieee80211_channel *channel) 1105{ 1106 u32 data, data0, data1, data2; 1107 u16 c; 1108 1109 data = data0 = data1 = data2 = 0; 1110 c = channel->center_freq; 1111 1112 if (c < 4800) { 1113 if (!((c - 2224) % 5)) { 1114 data0 = ((2 * (c - 704)) - 3040) / 10; 1115 data1 = 1; 1116 } else if (!((c - 2192) % 5)) { 1117 data0 = ((2 * (c - 672)) - 3040) / 10; 1118 data1 = 0; 1119 } else 1120 return -EINVAL; 1121 1122 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1123 } else if ((c % 5) != 2 || c > 5435) { 1124 if (!(c % 20) && c >= 5120) { 1125 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1126 data2 = ath5k_hw_bitswap(3, 2); 1127 } else if (!(c % 10)) { 1128 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1129 data2 = ath5k_hw_bitswap(2, 2); 1130 } else if (!(c % 5)) { 1131 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1132 data2 = ath5k_hw_bitswap(1, 2); 1133 } else 1134 return -EINVAL; 1135 } else { 1136 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1137 data2 = ath5k_hw_bitswap(0, 2); 1138 } 1139 1140 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1141 1142 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1143 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1144 1145 return 0; 1146} 1147 1148/* 1149 * Set the channel on the RF2425 1150 */ 1151static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1152 struct ieee80211_channel *channel) 1153{ 1154 u32 data, data0, data2; 1155 u16 c; 1156 1157 data = data0 = data2 = 0; 1158 c = channel->center_freq; 1159 1160 if (c < 4800) { 1161 data0 = ath5k_hw_bitswap((c - 2272), 8); 1162 data2 = 0; 1163 /* ? 5GHz ? */ 1164 } else if ((c % 5) != 2 || c > 5435) { 1165 if (!(c % 20) && c < 5120) 1166 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1167 else if (!(c % 10)) 1168 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1169 else if (!(c % 5)) 1170 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1171 else 1172 return -EINVAL; 1173 data2 = ath5k_hw_bitswap(1, 2); 1174 } else { 1175 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1176 data2 = ath5k_hw_bitswap(0, 2); 1177 } 1178 1179 data = (data0 << 4) | data2 << 2 | 0x1001; 1180 1181 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1182 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1183 1184 return 0; 1185} 1186 1187/* 1188 * Set a channel on the radio chip 1189 */ 1190static int ath5k_hw_channel(struct ath5k_hw *ah, 1191 struct ieee80211_channel *channel) 1192{ 1193 int ret; 1194 /* 1195 * Check bounds supported by the PHY (we don't care about regultory 1196 * restrictions at this point). Note: hw_value already has the band 1197 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1198 * of the band by that */ 1199 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1200 ATH5K_ERR(ah->ah_sc, 1201 "channel frequency (%u MHz) out of supported " 1202 "band range\n", 1203 channel->center_freq); 1204 return -EINVAL; 1205 } 1206 1207 /* 1208 * Set the channel and wait 1209 */ 1210 switch (ah->ah_radio) { 1211 case AR5K_RF5110: 1212 ret = ath5k_hw_rf5110_channel(ah, channel); 1213 break; 1214 case AR5K_RF5111: 1215 ret = ath5k_hw_rf5111_channel(ah, channel); 1216 break; 1217 case AR5K_RF2425: 1218 ret = ath5k_hw_rf2425_channel(ah, channel); 1219 break; 1220 default: 1221 ret = ath5k_hw_rf5112_channel(ah, channel); 1222 break; 1223 } 1224 1225 if (ret) 1226 return ret; 1227 1228 /* Set JAPAN setting for channel 14 */ 1229 if (channel->center_freq == 2484) { 1230 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1231 AR5K_PHY_CCKTXCTL_JAPAN); 1232 } else { 1233 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1234 AR5K_PHY_CCKTXCTL_WORLD); 1235 } 1236 1237 ah->ah_current_channel = channel; 1238 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; 1239 ath5k_hw_set_clockrate(ah); 1240 1241 return 0; 1242} 1243 1244/*****************\ 1245 PHY calibration 1246\*****************/ 1247 1248static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1249{ 1250 s32 val; 1251 1252 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1253 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1254} 1255 1256void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1257{ 1258 int i; 1259 1260 ah->ah_nfcal_hist.index = 0; 1261 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1262 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1263} 1264 1265static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1266{ 1267 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1268 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1269 hist->nfval[hist->index] = noise_floor; 1270} 1271 1272static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1273{ 1274 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1275 s16 tmp; 1276 int i, j; 1277 1278 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1279 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1280 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1281 if (sort[j] > sort[j-1]) { 1282 tmp = sort[j]; 1283 sort[j] = sort[j-1]; 1284 sort[j-1] = tmp; 1285 } 1286 } 1287 } 1288 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1289 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1290 "cal %d:%d\n", i, sort[i]); 1291 } 1292 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1293} 1294 1295/* 1296 * When we tell the hardware to perform a noise floor calibration 1297 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1298 * sample-and-hold the minimum noise level seen at the antennas. 1299 * This value is then stored in a ring buffer of recently measured 1300 * noise floor values so we have a moving window of the last few 1301 * samples. 1302 * 1303 * The median of the values in the history is then loaded into the 1304 * hardware for its own use for RSSI and CCA measurements. 1305 */ 1306void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1307{ 1308 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1309 u32 val; 1310 s16 nf, threshold; 1311 u8 ee_mode; 1312 1313 /* keep last value if calibration hasn't completed */ 1314 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1315 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1316 "NF did not complete in calibration window\n"); 1317 1318 return; 1319 } 1320 1321 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { 1322 case CHANNEL_A: 1323 case CHANNEL_T: 1324 case CHANNEL_XR: 1325 ee_mode = AR5K_EEPROM_MODE_11A; 1326 break; 1327 case CHANNEL_G: 1328 case CHANNEL_TG: 1329 ee_mode = AR5K_EEPROM_MODE_11G; 1330 break; 1331 default: 1332 case CHANNEL_B: 1333 ee_mode = AR5K_EEPROM_MODE_11B; 1334 break; 1335 } 1336 1337 1338 /* completed NF calibration, test threshold */ 1339 nf = ath5k_hw_read_measured_noise_floor(ah); 1340 threshold = ee->ee_noise_floor_thr[ee_mode]; 1341 1342 if (nf > threshold) { 1343 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1344 "noise floor failure detected; " 1345 "read %d, threshold %d\n", 1346 nf, threshold); 1347 1348 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1349 } 1350 1351 ath5k_hw_update_nfcal_hist(ah, nf); 1352 nf = ath5k_hw_get_median_noise_floor(ah); 1353 1354 /* load noise floor (in .5 dBm) so the hardware will use it */ 1355 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1356 val |= (nf * 2) & AR5K_PHY_NF_M; 1357 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1358 1359 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1360 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1361 1362 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1363 0, false); 1364 1365 /* 1366 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1367 * so that we're not capped by the median we just loaded. 1368 * This will be used as the initial value for the next noise 1369 * floor calibration. 1370 */ 1371 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1372 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1373 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1374 AR5K_PHY_AGCCTL_NF_EN | 1375 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1376 AR5K_PHY_AGCCTL_NF); 1377 1378 ah->ah_noise_floor = nf; 1379 1380 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1381 "noise floor calibrated: %d\n", nf); 1382} 1383 1384/* 1385 * Perform a PHY calibration on RF5110 1386 * -Fix BPSK/QAM Constellation (I/Q correction) 1387 */ 1388static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1389 struct ieee80211_channel *channel) 1390{ 1391 u32 phy_sig, phy_agc, phy_sat, beacon; 1392 int ret; 1393 1394 /* 1395 * Disable beacons and RX/TX queues, wait 1396 */ 1397 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1398 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1399 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1400 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1401 1402 mdelay(2); 1403 1404 /* 1405 * Set the channel (with AGC turned off) 1406 */ 1407 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1408 udelay(10); 1409 ret = ath5k_hw_channel(ah, channel); 1410 1411 /* 1412 * Activate PHY and wait 1413 */ 1414 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1415 mdelay(1); 1416 1417 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1418 1419 if (ret) 1420 return ret; 1421 1422 /* 1423 * Calibrate the radio chip 1424 */ 1425 1426 /* Remember normal state */ 1427 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1428 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1429 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1430 1431 /* Update radio registers */ 1432 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1433 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1434 1435 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1436 AR5K_PHY_AGCCOARSE_LO)) | 1437 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1438 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1439 1440 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1441 AR5K_PHY_ADCSAT_THR)) | 1442 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1443 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1444 1445 udelay(20); 1446 1447 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1448 udelay(10); 1449 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1450 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1451 1452 mdelay(1); 1453 1454 /* 1455 * Enable calibration and wait until completion 1456 */ 1457 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1458 1459 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1460 AR5K_PHY_AGCCTL_CAL, 0, false); 1461 1462 /* Reset to normal state */ 1463 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1464 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1465 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1466 1467 if (ret) { 1468 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1469 channel->center_freq); 1470 return ret; 1471 } 1472 1473 /* 1474 * Re-enable RX/TX and beacons 1475 */ 1476 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1477 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1478 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1479 1480 return 0; 1481} 1482 1483/* 1484 * Perform I/Q calibration on RF5111/5112 and newer chips 1485 */ 1486static int 1487ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1488{ 1489 u32 i_pwr, q_pwr; 1490 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1491 int i; 1492 1493 if (!ah->ah_calibration || 1494 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1495 return 0; 1496 1497 /* Calibration has finished, get the results and re-run */ 1498 /* work around empty results which can apparently happen on 5212 */ 1499 for (i = 0; i <= 10; i++) { 1500 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1501 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1502 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1503 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1504 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1505 if (i_pwr && q_pwr) 1506 break; 1507 } 1508 1509 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1510 1511 if (ah->ah_version == AR5K_AR5211) 1512 q_coffd = q_pwr >> 6; 1513 else 1514 q_coffd = q_pwr >> 7; 1515 1516 /* protect against divide by 0 and loss of sign bits */ 1517 if (i_coffd == 0 || q_coffd < 2) 1518 return 0; 1519 1520 i_coff = (-iq_corr) / i_coffd; 1521 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1522 1523 if (ah->ah_version == AR5K_AR5211) 1524 q_coff = (i_pwr / q_coffd) - 64; 1525 else 1526 q_coff = (i_pwr / q_coffd) - 128; 1527 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1528 1529 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1530 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1531 i_coff, q_coff, i_coffd, q_coffd); 1532 1533 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1534 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1535 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1536 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1537 1538 /* Re-enable calibration -if we don't we'll commit 1539 * the same values again and again */ 1540 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1541 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1542 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1543 1544 return 0; 1545} 1546 1547/* 1548 * Perform a PHY calibration 1549 */ 1550int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1551 struct ieee80211_channel *channel) 1552{ 1553 int ret; 1554 1555 if (ah->ah_radio == AR5K_RF5110) 1556 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1557 else { 1558 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1559 ath5k_hw_request_rfgain_probe(ah); 1560 } 1561 1562 return ret; 1563} 1564 1565 1566/***************************\ 1567* Spur mitigation functions * 1568\***************************/ 1569 1570static void 1571ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1572 struct ieee80211_channel *channel) 1573{ 1574 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1575 u32 mag_mask[4] = {0, 0, 0, 0}; 1576 u32 pilot_mask[2] = {0, 0}; 1577 /* Note: fbin values are scaled up by 2 */ 1578 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1579 s32 spur_delta_phase, spur_freq_sigma_delta; 1580 s32 spur_offset, num_symbols_x16; 1581 u8 num_symbol_offsets, i, freq_band; 1582 1583 /* Convert current frequency to fbin value (the same way channels 1584 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1585 * up by 2 so we can compare it later */ 1586 if (channel->hw_value & CHANNEL_2GHZ) { 1587 chan_fbin = (channel->center_freq - 2300) * 10; 1588 freq_band = AR5K_EEPROM_BAND_2GHZ; 1589 } else { 1590 chan_fbin = (channel->center_freq - 4900) * 10; 1591 freq_band = AR5K_EEPROM_BAND_5GHZ; 1592 } 1593 1594 /* Check if any spur_chan_fbin from EEPROM is 1595 * within our current channel's spur detection range */ 1596 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1597 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1598 /* XXX: Half/Quarter channels ?*/ 1599 if (channel->hw_value & CHANNEL_TURBO) 1600 spur_detection_window *= 2; 1601 1602 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1603 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1604 1605 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1606 * so it's zero if we got nothing from EEPROM */ 1607 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1608 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1609 break; 1610 } 1611 1612 if ((chan_fbin - spur_detection_window <= 1613 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1614 (chan_fbin + spur_detection_window >= 1615 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1616 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1617 break; 1618 } 1619 } 1620 1621 /* We need to enable spur filter for this channel */ 1622 if (spur_chan_fbin) { 1623 spur_offset = spur_chan_fbin - chan_fbin; 1624 /* 1625 * Calculate deltas: 1626 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1627 * spur_delta_phase -> spur_offset / chip_freq << 11 1628 * Note: Both values have 100KHz resolution 1629 */ 1630 /* XXX: Half/Quarter rate channels ? */ 1631 switch (channel->hw_value) { 1632 case CHANNEL_A: 1633 /* Both sample_freq and chip_freq are 40MHz */ 1634 spur_delta_phase = (spur_offset << 17) / 25; 1635 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1636 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1637 break; 1638 case CHANNEL_G: 1639 /* sample_freq -> 40MHz chip_freq -> 44MHz 1640 * (for b compatibility) */ 1641 spur_freq_sigma_delta = (spur_offset << 8) / 55; 1642 spur_delta_phase = (spur_offset << 17) / 25; 1643 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1644 break; 1645 case CHANNEL_T: 1646 case CHANNEL_TG: 1647 /* Both sample_freq and chip_freq are 80MHz */ 1648 spur_delta_phase = (spur_offset << 16) / 25; 1649 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1650 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; 1651 break; 1652 default: 1653 return; 1654 } 1655 1656 /* Calculate pilot and magnitude masks */ 1657 1658 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1659 * and divide by symbol_width to find how many symbols we have 1660 * Note: number of symbols is scaled up by 16 */ 1661 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1662 1663 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1664 if (!(num_symbols_x16 & 0xF)) 1665 /* _X_ */ 1666 num_symbol_offsets = 3; 1667 else 1668 /* _xx_ */ 1669 num_symbol_offsets = 4; 1670 1671 for (i = 0; i < num_symbol_offsets; i++) { 1672 1673 /* Calculate pilot mask */ 1674 s32 curr_sym_off = 1675 (num_symbols_x16 / 16) + i + 25; 1676 1677 /* Pilot magnitude mask seems to be a way to 1678 * declare the boundaries for our detection 1679 * window or something, it's 2 for the middle 1680 * value(s) where the symbol is expected to be 1681 * and 1 on the boundary values */ 1682 u8 plt_mag_map = 1683 (i == 0 || i == (num_symbol_offsets - 1)) 1684 ? 1 : 2; 1685 1686 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1687 if (curr_sym_off <= 25) 1688 pilot_mask[0] |= 1 << curr_sym_off; 1689 else if (curr_sym_off >= 27) 1690 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1691 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1692 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1693 1694 /* Calculate magnitude mask (for viterbi decoder) */ 1695 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1696 mag_mask[0] |= 1697 plt_mag_map << (curr_sym_off + 1) * 2; 1698 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1699 mag_mask[1] |= 1700 plt_mag_map << (curr_sym_off - 15) * 2; 1701 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1702 mag_mask[2] |= 1703 plt_mag_map << (curr_sym_off - 31) * 2; 1704 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1705 mag_mask[3] |= 1706 plt_mag_map << (curr_sym_off - 47) * 2; 1707 1708 } 1709 1710 /* Write settings on hw to enable spur filter */ 1711 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1712 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1713 /* XXX: Self correlator also ? */ 1714 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1715 AR5K_PHY_IQ_PILOT_MASK_EN | 1716 AR5K_PHY_IQ_CHAN_MASK_EN | 1717 AR5K_PHY_IQ_SPUR_FILT_EN); 1718 1719 /* Set delta phase and freq sigma delta */ 1720 ath5k_hw_reg_write(ah, 1721 AR5K_REG_SM(spur_delta_phase, 1722 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1723 AR5K_REG_SM(spur_freq_sigma_delta, 1724 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1725 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1726 AR5K_PHY_TIMING_11); 1727 1728 /* Write pilot masks */ 1729 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1730 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1731 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1732 pilot_mask[1]); 1733 1734 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1735 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1736 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1737 pilot_mask[1]); 1738 1739 /* Write magnitude masks */ 1740 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1741 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1742 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1743 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1744 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1745 mag_mask[3]); 1746 1747 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1748 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1749 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1750 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1751 AR5K_PHY_BIN_MASK2_4_MASK_4, 1752 mag_mask[3]); 1753 1754 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1755 AR5K_PHY_IQ_SPUR_FILT_EN) { 1756 /* Clean up spur mitigation settings and disable fliter */ 1757 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1758 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1759 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1760 AR5K_PHY_IQ_PILOT_MASK_EN | 1761 AR5K_PHY_IQ_CHAN_MASK_EN | 1762 AR5K_PHY_IQ_SPUR_FILT_EN); 1763 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1764 1765 /* Clear pilot masks */ 1766 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1767 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1768 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1769 0); 1770 1771 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1772 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1773 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1774 0); 1775 1776 /* Clear magnitude masks */ 1777 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1778 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1779 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1780 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1781 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1782 0); 1783 1784 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1785 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1786 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1787 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1788 AR5K_PHY_BIN_MASK2_4_MASK_4, 1789 0); 1790 } 1791} 1792 1793 1794/*****************\ 1795* Antenna control * 1796\*****************/ 1797 1798static void /*TODO:Boundary check*/ 1799ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1800{ 1801 if (ah->ah_version != AR5K_AR5210) 1802 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1803} 1804 1805/* 1806 * Enable/disable fast rx antenna diversity 1807 */ 1808static void 1809ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1810{ 1811 switch (ee_mode) { 1812 case AR5K_EEPROM_MODE_11G: 1813 /* XXX: This is set to 1814 * disabled on initvals !!! */ 1815 case AR5K_EEPROM_MODE_11A: 1816 if (enable) 1817 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1818 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1819 else 1820 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1821 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1822 break; 1823 case AR5K_EEPROM_MODE_11B: 1824 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1825 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1826 break; 1827 default: 1828 return; 1829 } 1830 1831 if (enable) { 1832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1833 AR5K_PHY_RESTART_DIV_GC, 4); 1834 1835 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1836 AR5K_PHY_FAST_ANT_DIV_EN); 1837 } else { 1838 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1839 AR5K_PHY_RESTART_DIV_GC, 0); 1840 1841 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1842 AR5K_PHY_FAST_ANT_DIV_EN); 1843 } 1844} 1845 1846void 1847ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1848{ 1849 u8 ant0, ant1; 1850 1851 /* 1852 * In case a fixed antenna was set as default 1853 * use the same switch table twice. 1854 */ 1855 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1856 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1857 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1858 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1859 else { 1860 ant0 = AR5K_ANT_SWTABLE_A; 1861 ant1 = AR5K_ANT_SWTABLE_B; 1862 } 1863 1864 /* Set antenna idle switch table */ 1865 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1866 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1867 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1868 AR5K_PHY_ANT_CTL_TXRX_EN)); 1869 1870 /* Set antenna switch tables */ 1871 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1872 AR5K_PHY_ANT_SWITCH_TABLE_0); 1873 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1874 AR5K_PHY_ANT_SWITCH_TABLE_1); 1875} 1876 1877/* 1878 * Set antenna operating mode 1879 */ 1880void 1881ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1882{ 1883 struct ieee80211_channel *channel = ah->ah_current_channel; 1884 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1885 bool use_def_for_sg; 1886 u8 def_ant, tx_ant, ee_mode; 1887 u32 sta_id1 = 0; 1888 1889 /* if channel is not initialized yet we can't set the antennas 1890 * so just store the mode. it will be set on the next reset */ 1891 if (channel == NULL) { 1892 ah->ah_ant_mode = ant_mode; 1893 return; 1894 } 1895 1896 def_ant = ah->ah_def_ant; 1897 1898 switch (channel->hw_value & CHANNEL_MODES) { 1899 case CHANNEL_A: 1900 case CHANNEL_T: 1901 case CHANNEL_XR: 1902 ee_mode = AR5K_EEPROM_MODE_11A; 1903 break; 1904 case CHANNEL_G: 1905 case CHANNEL_TG: 1906 ee_mode = AR5K_EEPROM_MODE_11G; 1907 break; 1908 case CHANNEL_B: 1909 ee_mode = AR5K_EEPROM_MODE_11B; 1910 break; 1911 default: 1912 ATH5K_ERR(ah->ah_sc, 1913 "invalid channel: %d\n", channel->center_freq); 1914 return; 1915 } 1916 1917 switch (ant_mode) { 1918 case AR5K_ANTMODE_DEFAULT: 1919 tx_ant = 0; 1920 use_def_for_tx = false; 1921 update_def_on_tx = false; 1922 use_def_for_rts = false; 1923 use_def_for_sg = false; 1924 fast_div = true; 1925 break; 1926 case AR5K_ANTMODE_FIXED_A: 1927 def_ant = 1; 1928 tx_ant = 1; 1929 use_def_for_tx = true; 1930 update_def_on_tx = false; 1931 use_def_for_rts = true; 1932 use_def_for_sg = true; 1933 fast_div = false; 1934 break; 1935 case AR5K_ANTMODE_FIXED_B: 1936 def_ant = 2; 1937 tx_ant = 2; 1938 use_def_for_tx = true; 1939 update_def_on_tx = false; 1940 use_def_for_rts = true; 1941 use_def_for_sg = true; 1942 fast_div = false; 1943 break; 1944 case AR5K_ANTMODE_SINGLE_AP: 1945 def_ant = 1; /* updated on tx */ 1946 tx_ant = 0; 1947 use_def_for_tx = true; 1948 update_def_on_tx = true; 1949 use_def_for_rts = true; 1950 use_def_for_sg = true; 1951 fast_div = true; 1952 break; 1953 case AR5K_ANTMODE_SECTOR_AP: 1954 tx_ant = 1; /* variable */ 1955 use_def_for_tx = false; 1956 update_def_on_tx = false; 1957 use_def_for_rts = true; 1958 use_def_for_sg = false; 1959 fast_div = false; 1960 break; 1961 case AR5K_ANTMODE_SECTOR_STA: 1962 tx_ant = 1; /* variable */ 1963 use_def_for_tx = true; 1964 update_def_on_tx = false; 1965 use_def_for_rts = true; 1966 use_def_for_sg = false; 1967 fast_div = true; 1968 break; 1969 case AR5K_ANTMODE_DEBUG: 1970 def_ant = 1; 1971 tx_ant = 2; 1972 use_def_for_tx = false; 1973 update_def_on_tx = false; 1974 use_def_for_rts = false; 1975 use_def_for_sg = false; 1976 fast_div = false; 1977 break; 1978 default: 1979 return; 1980 } 1981 1982 ah->ah_tx_ant = tx_ant; 1983 ah->ah_ant_mode = ant_mode; 1984 ah->ah_def_ant = def_ant; 1985 1986 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 1987 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 1988 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 1989 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 1990 1991 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 1992 1993 if (sta_id1) 1994 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 1995 1996 ath5k_hw_set_antenna_switch(ah, ee_mode); 1997 /* Note: set diversity before default antenna 1998 * because it won't work correctly */ 1999 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2000 ath5k_hw_set_def_antenna(ah, def_ant); 2001} 2002 2003 2004/****************\ 2005* TX power setup * 2006\****************/ 2007 2008/* 2009 * Helper functions 2010 */ 2011 2012/* 2013 * Do linear interpolation between two given (x, y) points 2014 */ 2015static s16 2016ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2017 s16 y_left, s16 y_right) 2018{ 2019 s16 ratio, result; 2020 2021 /* Avoid divide by zero and skip interpolation 2022 * if we have the same point */ 2023 if ((x_left == x_right) || (y_left == y_right)) 2024 return y_left; 2025 2026 /* 2027 * Since we use ints and not fps, we need to scale up in 2028 * order to get a sane ratio value (or else we 'll eg. get 2029 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2030 * to have some accuracy both for 0.5 and 0.25 steps. 2031 */ 2032 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2033 2034 /* Now scale down to be in range */ 2035 result = y_left + (ratio * (target - x_left) / 100); 2036 2037 return result; 2038} 2039 2040/* 2041 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2042 * 2043 * Since we have the top of the curve and we draw the line below 2044 * until we reach 1 (1 pcdac step) we need to know which point 2045 * (x value) that is so that we don't go below y axis and have negative 2046 * pcdac values when creating the curve, or fill the table with zeroes. 2047 */ 2048static s16 2049ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2050 const s16 *pwrL, const s16 *pwrR) 2051{ 2052 s8 tmp; 2053 s16 min_pwrL, min_pwrR; 2054 s16 pwr_i; 2055 2056 /* Some vendors write the same pcdac value twice !!! */ 2057 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2058 return max(pwrL[0], pwrR[0]); 2059 2060 if (pwrL[0] == pwrL[1]) 2061 min_pwrL = pwrL[0]; 2062 else { 2063 pwr_i = pwrL[0]; 2064 do { 2065 pwr_i--; 2066 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2067 pwrL[0], pwrL[1], 2068 stepL[0], stepL[1]); 2069 } while (tmp > 1); 2070 2071 min_pwrL = pwr_i; 2072 } 2073 2074 if (pwrR[0] == pwrR[1]) 2075 min_pwrR = pwrR[0]; 2076 else { 2077 pwr_i = pwrR[0]; 2078 do { 2079 pwr_i--; 2080 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2081 pwrR[0], pwrR[1], 2082 stepR[0], stepR[1]); 2083 } while (tmp > 1); 2084 2085 min_pwrR = pwr_i; 2086 } 2087 2088 /* Keep the right boundary so that it works for both curves */ 2089 return max(min_pwrL, min_pwrR); 2090} 2091 2092/* 2093 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2094 * Power to PCDAC curve. 2095 * 2096 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2097 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2098 * PCDAC/PDADC step for each curve is 64 but we can write more than 2099 * one curves on hw so we can go up to 128 (which is the max step we 2100 * can write on the final table). 2101 * 2102 * We write y values (PCDAC/PDADC steps) on hw. 2103 */ 2104static void 2105ath5k_create_power_curve(s16 pmin, s16 pmax, 2106 const s16 *pwr, const u8 *vpd, 2107 u8 num_points, 2108 u8 *vpd_table, u8 type) 2109{ 2110 u8 idx[2] = { 0, 1 }; 2111 s16 pwr_i = 2*pmin; 2112 int i; 2113 2114 if (num_points < 2) 2115 return; 2116 2117 /* We want the whole line, so adjust boundaries 2118 * to cover the entire power range. Note that 2119 * power values are already 0.25dB so no need 2120 * to multiply pwr_i by 2 */ 2121 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2122 pwr_i = pmin; 2123 pmin = 0; 2124 pmax = 63; 2125 } 2126 2127 /* Find surrounding turning points (TPs) 2128 * and interpolate between them */ 2129 for (i = 0; (i <= (u16) (pmax - pmin)) && 2130 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2131 2132 /* We passed the right TP, move to the next set of TPs 2133 * if we pass the last TP, extrapolate above using the last 2134 * two TPs for ratio */ 2135 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2136 idx[0]++; 2137 idx[1]++; 2138 } 2139 2140 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2141 pwr[idx[0]], pwr[idx[1]], 2142 vpd[idx[0]], vpd[idx[1]]); 2143 2144 /* Increase by 0.5dB 2145 * (0.25 dB units) */ 2146 pwr_i += 2; 2147 } 2148} 2149 2150/* 2151 * Get the surrounding per-channel power calibration piers 2152 * for a given frequency so that we can interpolate between 2153 * them and come up with an apropriate dataset for our current 2154 * channel. 2155 */ 2156static void 2157ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2158 struct ieee80211_channel *channel, 2159 struct ath5k_chan_pcal_info **pcinfo_l, 2160 struct ath5k_chan_pcal_info **pcinfo_r) 2161{ 2162 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2163 struct ath5k_chan_pcal_info *pcinfo; 2164 u8 idx_l, idx_r; 2165 u8 mode, max, i; 2166 u32 target = channel->center_freq; 2167 2168 idx_l = 0; 2169 idx_r = 0; 2170 2171 if (!(channel->hw_value & CHANNEL_OFDM)) { 2172 pcinfo = ee->ee_pwr_cal_b; 2173 mode = AR5K_EEPROM_MODE_11B; 2174 } else if (channel->hw_value & CHANNEL_2GHZ) { 2175 pcinfo = ee->ee_pwr_cal_g; 2176 mode = AR5K_EEPROM_MODE_11G; 2177 } else { 2178 pcinfo = ee->ee_pwr_cal_a; 2179 mode = AR5K_EEPROM_MODE_11A; 2180 } 2181 max = ee->ee_n_piers[mode] - 1; 2182 2183 /* Frequency is below our calibrated 2184 * range. Use the lowest power curve 2185 * we have */ 2186 if (target < pcinfo[0].freq) { 2187 idx_l = idx_r = 0; 2188 goto done; 2189 } 2190 2191 /* Frequency is above our calibrated 2192 * range. Use the highest power curve 2193 * we have */ 2194 if (target > pcinfo[max].freq) { 2195 idx_l = idx_r = max; 2196 goto done; 2197 } 2198 2199 /* Frequency is inside our calibrated 2200 * channel range. Pick the surrounding 2201 * calibration piers so that we can 2202 * interpolate */ 2203 for (i = 0; i <= max; i++) { 2204 2205 /* Frequency matches one of our calibration 2206 * piers, no need to interpolate, just use 2207 * that calibration pier */ 2208 if (pcinfo[i].freq == target) { 2209 idx_l = idx_r = i; 2210 goto done; 2211 } 2212 2213 /* We found a calibration pier that's above 2214 * frequency, use this pier and the previous 2215 * one to interpolate */ 2216 if (target < pcinfo[i].freq) { 2217 idx_r = i; 2218 idx_l = idx_r - 1; 2219 goto done; 2220 } 2221 } 2222 2223done: 2224 *pcinfo_l = &pcinfo[idx_l]; 2225 *pcinfo_r = &pcinfo[idx_r]; 2226} 2227 2228/* 2229 * Get the surrounding per-rate power calibration data 2230 * for a given frequency and interpolate between power 2231 * values to set max target power supported by hw for 2232 * each rate. 2233 */ 2234static void 2235ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2236 struct ieee80211_channel *channel, 2237 struct ath5k_rate_pcal_info *rates) 2238{ 2239 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2240 struct ath5k_rate_pcal_info *rpinfo; 2241 u8 idx_l, idx_r; 2242 u8 mode, max, i; 2243 u32 target = channel->center_freq; 2244 2245 idx_l = 0; 2246 idx_r = 0; 2247 2248 if (!(channel->hw_value & CHANNEL_OFDM)) { 2249 rpinfo = ee->ee_rate_tpwr_b; 2250 mode = AR5K_EEPROM_MODE_11B; 2251 } else if (channel->hw_value & CHANNEL_2GHZ) { 2252 rpinfo = ee->ee_rate_tpwr_g; 2253 mode = AR5K_EEPROM_MODE_11G; 2254 } else { 2255 rpinfo = ee->ee_rate_tpwr_a; 2256 mode = AR5K_EEPROM_MODE_11A; 2257 } 2258 max = ee->ee_rate_target_pwr_num[mode] - 1; 2259 2260 /* Get the surrounding calibration 2261 * piers - same as above */ 2262 if (target < rpinfo[0].freq) { 2263 idx_l = idx_r = 0; 2264 goto done; 2265 } 2266 2267 if (target > rpinfo[max].freq) { 2268 idx_l = idx_r = max; 2269 goto done; 2270 } 2271 2272 for (i = 0; i <= max; i++) { 2273 2274 if (rpinfo[i].freq == target) { 2275 idx_l = idx_r = i; 2276 goto done; 2277 } 2278 2279 if (target < rpinfo[i].freq) { 2280 idx_r = i; 2281 idx_l = idx_r - 1; 2282 goto done; 2283 } 2284 } 2285 2286done: 2287 /* Now interpolate power value, based on the frequency */ 2288 rates->freq = target; 2289 2290 rates->target_power_6to24 = 2291 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2292 rpinfo[idx_r].freq, 2293 rpinfo[idx_l].target_power_6to24, 2294 rpinfo[idx_r].target_power_6to24); 2295 2296 rates->target_power_36 = 2297 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2298 rpinfo[idx_r].freq, 2299 rpinfo[idx_l].target_power_36, 2300 rpinfo[idx_r].target_power_36); 2301 2302 rates->target_power_48 = 2303 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2304 rpinfo[idx_r].freq, 2305 rpinfo[idx_l].target_power_48, 2306 rpinfo[idx_r].target_power_48); 2307 2308 rates->target_power_54 = 2309 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2310 rpinfo[idx_r].freq, 2311 rpinfo[idx_l].target_power_54, 2312 rpinfo[idx_r].target_power_54); 2313} 2314 2315/* 2316 * Get the max edge power for this channel if 2317 * we have such data from EEPROM's Conformance Test 2318 * Limits (CTL), and limit max power if needed. 2319 */ 2320static void 2321ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2322 struct ieee80211_channel *channel) 2323{ 2324 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2325 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2326 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2327 u8 *ctl_val = ee->ee_ctl; 2328 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2329 s16 edge_pwr = 0; 2330 u8 rep_idx; 2331 u8 i, ctl_mode; 2332 u8 ctl_idx = 0xFF; 2333 u32 target = channel->center_freq; 2334 2335 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2336 2337 switch (channel->hw_value & CHANNEL_MODES) { 2338 case CHANNEL_A: 2339 ctl_mode |= AR5K_CTL_11A; 2340 break; 2341 case CHANNEL_G: 2342 ctl_mode |= AR5K_CTL_11G; 2343 break; 2344 case CHANNEL_B: 2345 ctl_mode |= AR5K_CTL_11B; 2346 break; 2347 case CHANNEL_T: 2348 ctl_mode |= AR5K_CTL_TURBO; 2349 break; 2350 case CHANNEL_TG: 2351 ctl_mode |= AR5K_CTL_TURBOG; 2352 break; 2353 case CHANNEL_XR: 2354 /* Fall through */ 2355 default: 2356 return; 2357 } 2358 2359 for (i = 0; i < ee->ee_ctls; i++) { 2360 if (ctl_val[i] == ctl_mode) { 2361 ctl_idx = i; 2362 break; 2363 } 2364 } 2365 2366 /* If we have a CTL dataset available grab it and find the 2367 * edge power for our frequency */ 2368 if (ctl_idx == 0xFF) 2369 return; 2370 2371 /* Edge powers are sorted by frequency from lower 2372 * to higher. Each CTL corresponds to 8 edge power 2373 * measurements. */ 2374 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2375 2376 /* Don't do boundaries check because we 2377 * might have more that one bands defined 2378 * for this mode */ 2379 2380 /* Get the edge power that's closer to our 2381 * frequency */ 2382 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2383 rep_idx += i; 2384 if (target <= rep[rep_idx].freq) 2385 edge_pwr = (s16) rep[rep_idx].edge; 2386 } 2387 2388 if (edge_pwr) 2389 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2390} 2391 2392 2393/* 2394 * Power to PCDAC table functions 2395 */ 2396 2397/* 2398 * Fill Power to PCDAC table on RF5111 2399 * 2400 * No further processing is needed for RF5111, the only thing we have to 2401 * do is fill the values below and above calibration range since eeprom data 2402 * may not cover the entire PCDAC table. 2403 */ 2404static void 2405ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2406 s16 *table_max) 2407{ 2408 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2409 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2410 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2411 s16 min_pwr, max_pwr; 2412 2413 /* Get table boundaries */ 2414 min_pwr = table_min[0]; 2415 pcdac_0 = pcdac_tmp[0]; 2416 2417 max_pwr = table_max[0]; 2418 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2419 2420 /* Extrapolate below minimum using pcdac_0 */ 2421 pcdac_i = 0; 2422 for (i = 0; i < min_pwr; i++) 2423 pcdac_out[pcdac_i++] = pcdac_0; 2424 2425 /* Copy values from pcdac_tmp */ 2426 pwr_idx = min_pwr; 2427 for (i = 0 ; pwr_idx <= max_pwr && 2428 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2429 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2430 pwr_idx++; 2431 } 2432 2433 /* Extrapolate above maximum */ 2434 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2435 pcdac_out[pcdac_i++] = pcdac_n; 2436 2437} 2438 2439/* 2440 * Combine available XPD Curves and fill Linear Power to PCDAC table 2441 * on RF5112 2442 * 2443 * RFX112 can have up to 2 curves (one for low txpower range and one for 2444 * higher txpower range). We need to put them both on pcdac_out and place 2445 * them in the correct location. In case we only have one curve available 2446 * just fit it on pcdac_out (it's supposed to cover the entire range of 2447 * available pwr levels since it's always the higher power curve). Extrapolate 2448 * below and above final table if needed. 2449 */ 2450static void 2451ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2452 s16 *table_max, u8 pdcurves) 2453{ 2454 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2455 u8 *pcdac_low_pwr; 2456 u8 *pcdac_high_pwr; 2457 u8 *pcdac_tmp; 2458 u8 pwr; 2459 s16 max_pwr_idx; 2460 s16 min_pwr_idx; 2461 s16 mid_pwr_idx = 0; 2462 /* Edge flag turs on the 7nth bit on the PCDAC 2463 * to delcare the higher power curve (force values 2464 * to be greater than 64). If we only have one curve 2465 * we don't need to set this, if we have 2 curves and 2466 * fill the table backwards this can also be used to 2467 * switch from higher power curve to lower power curve */ 2468 u8 edge_flag; 2469 int i; 2470 2471 /* When we have only one curve available 2472 * that's the higher power curve. If we have 2473 * two curves the first is the high power curve 2474 * and the next is the low power curve. */ 2475 if (pdcurves > 1) { 2476 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2477 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2478 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2479 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2480 2481 /* If table size goes beyond 31.5dB, keep the 2482 * upper 31.5dB range when setting tx power. 2483 * Note: 126 = 31.5 dB in quarter dB steps */ 2484 if (table_max[0] - table_min[1] > 126) 2485 min_pwr_idx = table_max[0] - 126; 2486 else 2487 min_pwr_idx = table_min[1]; 2488 2489 /* Since we fill table backwards 2490 * start from high power curve */ 2491 pcdac_tmp = pcdac_high_pwr; 2492 2493 edge_flag = 0x40; 2494 } else { 2495 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2496 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2497 min_pwr_idx = table_min[0]; 2498 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2499 pcdac_tmp = pcdac_high_pwr; 2500 edge_flag = 0; 2501 } 2502 2503 /* This is used when setting tx power*/ 2504 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2505 2506 /* Fill Power to PCDAC table backwards */ 2507 pwr = max_pwr_idx; 2508 for (i = 63; i >= 0; i--) { 2509 /* Entering lower power range, reset 2510 * edge flag and set pcdac_tmp to lower 2511 * power curve.*/ 2512 if (edge_flag == 0x40 && 2513 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2514 edge_flag = 0x00; 2515 pcdac_tmp = pcdac_low_pwr; 2516 pwr = mid_pwr_idx/2; 2517 } 2518 2519 /* Don't go below 1, extrapolate below if we have 2520 * already swithced to the lower power curve -or 2521 * we only have one curve and edge_flag is zero 2522 * anyway */ 2523 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2524 while (i >= 0) { 2525 pcdac_out[i] = pcdac_out[i + 1]; 2526 i--; 2527 } 2528 break; 2529 } 2530 2531 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2532 2533 /* Extrapolate above if pcdac is greater than 2534 * 126 -this can happen because we OR pcdac_out 2535 * value with edge_flag on high power curve */ 2536 if (pcdac_out[i] > 126) 2537 pcdac_out[i] = 126; 2538 2539 /* Decrease by a 0.5dB step */ 2540 pwr--; 2541 } 2542} 2543 2544/* Write PCDAC values on hw */ 2545static void 2546ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2547{ 2548 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2549 int i; 2550 2551 /* 2552 * Write TX power values 2553 */ 2554 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2555 ath5k_hw_reg_write(ah, 2556 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2557 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2558 AR5K_PHY_PCDAC_TXPOWER(i)); 2559 } 2560} 2561 2562 2563/* 2564 * Power to PDADC table functions 2565 */ 2566 2567/* 2568 * Set the gain boundaries and create final Power to PDADC table 2569 * 2570 * We can have up to 4 pd curves, we need to do a simmilar process 2571 * as we do for RF5112. This time we don't have an edge_flag but we 2572 * set the gain boundaries on a separate register. 2573 */ 2574static void 2575ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2576 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2577{ 2578 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2579 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2580 u8 *pdadc_tmp; 2581 s16 pdadc_0; 2582 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2583 u8 pd_gain_overlap; 2584 2585 /* Note: Register value is initialized on initvals 2586 * there is no feedback from hw. 2587 * XXX: What about pd_gain_overlap from EEPROM ? */ 2588 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2589 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2590 2591 /* Create final PDADC table */ 2592 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2593 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2594 2595 if (pdg == pdcurves - 1) 2596 /* 2 dB boundary stretch for last 2597 * (higher power) curve */ 2598 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2599 else 2600 /* Set gain boundary in the middle 2601 * between this curve and the next one */ 2602 gain_boundaries[pdg] = 2603 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2604 2605 /* Sanity check in case our 2 db stretch got out of 2606 * range. */ 2607 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2608 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2609 2610 /* For the first curve (lower power) 2611 * start from 0 dB */ 2612 if (pdg == 0) 2613 pdadc_0 = 0; 2614 else 2615 /* For the other curves use the gain overlap */ 2616 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2617 pd_gain_overlap; 2618 2619 /* Force each power step to be at least 0.5 dB */ 2620 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2621 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2622 else 2623 pwr_step = 1; 2624 2625 /* If pdadc_0 is negative, we need to extrapolate 2626 * below this pdgain by a number of pwr_steps */ 2627 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2628 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2629 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2630 pdadc_0++; 2631 } 2632 2633 /* Set last pwr level, using gain boundaries */ 2634 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2635 /* Limit it to be inside pwr range */ 2636 table_size = pwr_max[pdg] - pwr_min[pdg]; 2637 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2638 2639 /* Fill pdadc_out table */ 2640 while (pdadc_0 < max_idx && pdadc_i < 128) 2641 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2642 2643 /* Need to extrapolate above this pdgain? */ 2644 if (pdadc_n <= max_idx) 2645 continue; 2646 2647 /* Force each power step to be at least 0.5 dB */ 2648 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2649 pwr_step = pdadc_tmp[table_size - 1] - 2650 pdadc_tmp[table_size - 2]; 2651 else 2652 pwr_step = 1; 2653 2654 /* Extrapolate above */ 2655 while ((pdadc_0 < (s16) pdadc_n) && 2656 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2657 s16 tmp = pdadc_tmp[table_size - 1] + 2658 (pdadc_0 - max_idx) * pwr_step; 2659 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2660 pdadc_0++; 2661 } 2662 } 2663 2664 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2665 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2666 pdg++; 2667 } 2668 2669 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2670 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2671 pdadc_i++; 2672 } 2673 2674 /* Set gain boundaries */ 2675 ath5k_hw_reg_write(ah, 2676 AR5K_REG_SM(pd_gain_overlap, 2677 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2678 AR5K_REG_SM(gain_boundaries[0], 2679 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2680 AR5K_REG_SM(gain_boundaries[1], 2681 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2682 AR5K_REG_SM(gain_boundaries[2], 2683 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2684 AR5K_REG_SM(gain_boundaries[3], 2685 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2686 AR5K_PHY_TPC_RG5); 2687 2688 /* Used for setting rate power table */ 2689 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2690 2691} 2692 2693/* Write PDADC values on hw */ 2694static void 2695ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2696 u8 pdcurves, u8 *pdg_to_idx) 2697{ 2698 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2699 u32 reg; 2700 u8 i; 2701 2702 /* Select the right pdgain curves */ 2703 2704 /* Clear current settings */ 2705 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2706 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2707 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2708 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2709 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2710 2711 /* 2712 * Use pd_gains curve from eeprom 2713 * 2714 * This overrides the default setting from initvals 2715 * in case some vendors (e.g. Zcomax) don't use the default 2716 * curves. If we don't honor their settings we 'll get a 2717 * 5dB (1 * gain overlap ?) drop. 2718 */ 2719 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2720 2721 switch (pdcurves) { 2722 case 3: 2723 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2724 /* Fall through */ 2725 case 2: 2726 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2727 /* Fall through */ 2728 case 1: 2729 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2730 break; 2731 } 2732 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2733 2734 /* 2735 * Write TX power values 2736 */ 2737 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2738 ath5k_hw_reg_write(ah, 2739 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2740 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2741 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2742 ((pdadc_out[4*i + 3] & 0xff) << 24), 2743 AR5K_PHY_PDADC_TXPOWER(i)); 2744 } 2745} 2746 2747 2748/* 2749 * Common code for PCDAC/PDADC tables 2750 */ 2751 2752/* 2753 * This is the main function that uses all of the above 2754 * to set PCDAC/PDADC table on hw for the current channel. 2755 * This table is used for tx power calibration on the basband, 2756 * without it we get weird tx power levels and in some cases 2757 * distorted spectral mask 2758 */ 2759static int 2760ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2761 struct ieee80211_channel *channel, 2762 u8 ee_mode, u8 type) 2763{ 2764 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2765 struct ath5k_chan_pcal_info *pcinfo_L; 2766 struct ath5k_chan_pcal_info *pcinfo_R; 2767 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2768 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2769 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2770 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2771 u8 *tmpL; 2772 u8 *tmpR; 2773 u32 target = channel->center_freq; 2774 int pdg, i; 2775 2776 /* Get surounding freq piers for this channel */ 2777 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2778 &pcinfo_L, 2779 &pcinfo_R); 2780 2781 /* Loop over pd gain curves on 2782 * surounding freq piers by index */ 2783 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2784 2785 /* Fill curves in reverse order 2786 * from lower power (max gain) 2787 * to higher power. Use curve -> idx 2788 * backmapping we did on eeprom init */ 2789 u8 idx = pdg_curve_to_idx[pdg]; 2790 2791 /* Grab the needed curves by index */ 2792 pdg_L = &pcinfo_L->pd_curves[idx]; 2793 pdg_R = &pcinfo_R->pd_curves[idx]; 2794 2795 /* Initialize the temp tables */ 2796 tmpL = ah->ah_txpower.tmpL[pdg]; 2797 tmpR = ah->ah_txpower.tmpR[pdg]; 2798 2799 /* Set curve's x boundaries and create 2800 * curves so that they cover the same 2801 * range (if we don't do that one table 2802 * will have values on some range and the 2803 * other one won't have any so interpolation 2804 * will fail) */ 2805 table_min[pdg] = min(pdg_L->pd_pwr[0], 2806 pdg_R->pd_pwr[0]) / 2; 2807 2808 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2809 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2810 2811 /* Now create the curves on surrounding channels 2812 * and interpolate if needed to get the final 2813 * curve for this gain on this channel */ 2814 switch (type) { 2815 case AR5K_PWRTABLE_LINEAR_PCDAC: 2816 /* Override min/max so that we don't loose 2817 * accuracy (don't divide by 2) */ 2818 table_min[pdg] = min(pdg_L->pd_pwr[0], 2819 pdg_R->pd_pwr[0]); 2820 2821 table_max[pdg] = 2822 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2823 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2824 2825 /* Override minimum so that we don't get 2826 * out of bounds while extrapolating 2827 * below. Don't do this when we have 2 2828 * curves and we are on the high power curve 2829 * because table_min is ok in this case */ 2830 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2831 2832 table_min[pdg] = 2833 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2834 pdg_R->pd_step, 2835 pdg_L->pd_pwr, 2836 pdg_R->pd_pwr); 2837 2838 /* Don't go too low because we will 2839 * miss the upper part of the curve. 2840 * Note: 126 = 31.5dB (max power supported) 2841 * in 0.25dB units */ 2842 if (table_max[pdg] - table_min[pdg] > 126) 2843 table_min[pdg] = table_max[pdg] - 126; 2844 } 2845 2846 /* Fall through */ 2847 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2848 case AR5K_PWRTABLE_PWR_TO_PDADC: 2849 2850 ath5k_create_power_curve(table_min[pdg], 2851 table_max[pdg], 2852 pdg_L->pd_pwr, 2853 pdg_L->pd_step, 2854 pdg_L->pd_points, tmpL, type); 2855 2856 /* We are in a calibration 2857 * pier, no need to interpolate 2858 * between freq piers */ 2859 if (pcinfo_L == pcinfo_R) 2860 continue; 2861 2862 ath5k_create_power_curve(table_min[pdg], 2863 table_max[pdg], 2864 pdg_R->pd_pwr, 2865 pdg_R->pd_step, 2866 pdg_R->pd_points, tmpR, type); 2867 break; 2868 default: 2869 return -EINVAL; 2870 } 2871 2872 /* Interpolate between curves 2873 * of surounding freq piers to 2874 * get the final curve for this 2875 * pd gain. Re-use tmpL for interpolation 2876 * output */ 2877 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2878 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2879 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2880 (s16) pcinfo_L->freq, 2881 (s16) pcinfo_R->freq, 2882 (s16) tmpL[i], 2883 (s16) tmpR[i]); 2884 } 2885 } 2886 2887 /* Now we have a set of curves for this 2888 * channel on tmpL (x range is table_max - table_min 2889 * and y values are tmpL[pdg][]) sorted in the same 2890 * order as EEPROM (because we've used the backmapping). 2891 * So for RF5112 it's from higher power to lower power 2892 * and for RF2413 it's from lower power to higher power. 2893 * For RF5111 we only have one curve. */ 2894 2895 /* Fill min and max power levels for this 2896 * channel by interpolating the values on 2897 * surounding channels to complete the dataset */ 2898 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2899 (s16) pcinfo_L->freq, 2900 (s16) pcinfo_R->freq, 2901 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2902 2903 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2904 (s16) pcinfo_L->freq, 2905 (s16) pcinfo_R->freq, 2906 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2907 2908 /* We are ready to go, fill PCDAC/PDADC 2909 * table and write settings on hardware */ 2910 switch (type) { 2911 case AR5K_PWRTABLE_LINEAR_PCDAC: 2912 /* For RF5112 we can have one or two curves 2913 * and each curve covers a certain power lvl 2914 * range so we need to do some more processing */ 2915 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2916 ee->ee_pd_gains[ee_mode]); 2917 2918 /* Set txp.offset so that we can 2919 * match max power value with max 2920 * table index */ 2921 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2922 2923 /* Write settings on hw */ 2924 ath5k_setup_pcdac_table(ah); 2925 break; 2926 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2927 /* We are done for RF5111 since it has only 2928 * one curve, just fit the curve on the table */ 2929 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2930 2931 /* No rate powertable adjustment for RF5111 */ 2932 ah->ah_txpower.txp_min_idx = 0; 2933 ah->ah_txpower.txp_offset = 0; 2934 2935 /* Write settings on hw */ 2936 ath5k_setup_pcdac_table(ah); 2937 break; 2938 case AR5K_PWRTABLE_PWR_TO_PDADC: 2939 /* Set PDADC boundaries and fill 2940 * final PDADC table */ 2941 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2942 ee->ee_pd_gains[ee_mode]); 2943 2944 /* Write settings on hw */ 2945 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2946 2947 /* Set txp.offset, note that table_min 2948 * can be negative */ 2949 ah->ah_txpower.txp_offset = table_min[0]; 2950 break; 2951 default: 2952 return -EINVAL; 2953 } 2954 2955 return 0; 2956} 2957 2958 2959/* 2960 * Per-rate tx power setting 2961 * 2962 * This is the code that sets the desired tx power (below 2963 * maximum) on hw for each rate (we also have TPC that sets 2964 * power per packet). We do that by providing an index on the 2965 * PCDAC/PDADC table we set up. 2966 */ 2967 2968/* 2969 * Set rate power table 2970 * 2971 * For now we only limit txpower based on maximum tx power 2972 * supported by hw (what's inside rate_info). We need to limit 2973 * this even more, based on regulatory domain etc. 2974 * 2975 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2976 * and is indexed as follows: 2977 * rates[0] - rates[7] -> OFDM rates 2978 * rates[8] - rates[14] -> CCK rates 2979 * rates[15] -> XR rates (they all have the same power) 2980 */ 2981static void 2982ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2983 struct ath5k_rate_pcal_info *rate_info, 2984 u8 ee_mode) 2985{ 2986 unsigned int i; 2987 u16 *rates; 2988 2989 /* max_pwr is power level we got from driver/user in 0.5dB 2990 * units, switch to 0.25dB units so we can compare */ 2991 max_pwr *= 2; 2992 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2993 2994 /* apply rate limits */ 2995 rates = ah->ah_txpower.txp_rates_power_table; 2996 2997 /* OFDM rates 6 to 24Mb/s */ 2998 for (i = 0; i < 5; i++) 2999 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3000 3001 /* Rest OFDM rates */ 3002 rates[5] = min(rates[0], rate_info->target_power_36); 3003 rates[6] = min(rates[0], rate_info->target_power_48); 3004 rates[7] = min(rates[0], rate_info->target_power_54); 3005 3006 /* CCK rates */ 3007 /* 1L */ 3008 rates[8] = min(rates[0], rate_info->target_power_6to24); 3009 /* 2L */ 3010 rates[9] = min(rates[0], rate_info->target_power_36); 3011 /* 2S */ 3012 rates[10] = min(rates[0], rate_info->target_power_36); 3013 /* 5L */ 3014 rates[11] = min(rates[0], rate_info->target_power_48); 3015 /* 5S */ 3016 rates[12] = min(rates[0], rate_info->target_power_48); 3017 /* 11L */ 3018 rates[13] = min(rates[0], rate_info->target_power_54); 3019 /* 11S */ 3020 rates[14] = min(rates[0], rate_info->target_power_54); 3021 3022 /* XR rates */ 3023 rates[15] = min(rates[0], rate_info->target_power_6to24); 3024 3025 /* CCK rates have different peak to average ratio 3026 * so we have to tweak their power so that gainf 3027 * correction works ok. For this we use OFDM to 3028 * CCK delta from eeprom */ 3029 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3030 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3031 for (i = 8; i <= 15; i++) 3032 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3033 3034 /* Now that we have all rates setup use table offset to 3035 * match the power range set by user with the power indices 3036 * on PCDAC/PDADC table */ 3037 for (i = 0; i < 16; i++) { 3038 rates[i] += ah->ah_txpower.txp_offset; 3039 /* Don't get out of bounds */ 3040 if (rates[i] > 63) 3041 rates[i] = 63; 3042 } 3043 3044 /* Min/max in 0.25dB units */ 3045 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3046 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 3047 ah->ah_txpower.txp_ofdm = rates[7]; 3048} 3049 3050 3051/* 3052 * Set transmission power 3053 */ 3054static int 3055ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3056 u8 ee_mode, u8 txpower) 3057{ 3058 struct ath5k_rate_pcal_info rate_info; 3059 u8 type; 3060 int ret; 3061 3062 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3063 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3064 return -EINVAL; 3065 } 3066 3067 /* Reset TX power values */ 3068 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3069 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3070 ah->ah_txpower.txp_min_pwr = 0; 3071 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 3072 3073 /* Initialize TX power table */ 3074 switch (ah->ah_radio) { 3075 case AR5K_RF5111: 3076 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3077 break; 3078 case AR5K_RF5112: 3079 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3080 break; 3081 case AR5K_RF2413: 3082 case AR5K_RF5413: 3083 case AR5K_RF2316: 3084 case AR5K_RF2317: 3085 case AR5K_RF2425: 3086 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3087 break; 3088 default: 3089 return -EINVAL; 3090 } 3091 3092 /* FIXME: Only on channel/mode change */ 3093 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 3094 if (ret) 3095 return ret; 3096 3097 /* Limit max power if we have a CTL available */ 3098 ath5k_get_max_ctl_power(ah, channel); 3099 3100 /* FIXME: Antenna reduction stuff */ 3101 3102 /* FIXME: Limit power on turbo modes */ 3103 3104 /* FIXME: TPC scale reduction */ 3105 3106 /* Get surounding channels for per-rate power table 3107 * calibration */ 3108 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3109 3110 /* Setup rate power table */ 3111 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3112 3113 /* Write rate power table on hw */ 3114 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3115 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3116 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3117 3118 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3119 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3120 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3121 3122 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3123 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3124 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3125 3126 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3127 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3128 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3129 3130 /* FIXME: TPC support */ 3131 if (ah->ah_txpower.txp_tpc) { 3132 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3133 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3134 3135 ath5k_hw_reg_write(ah, 3136 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3137 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3138 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3139 AR5K_TPC); 3140 } else { 3141 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3142 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3143 } 3144 3145 return 0; 3146} 3147 3148int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3149{ 3150 /*Just a try M.F.*/ 3151 struct ieee80211_channel *channel = ah->ah_current_channel; 3152 u8 ee_mode; 3153 3154 switch (channel->hw_value & CHANNEL_MODES) { 3155 case CHANNEL_A: 3156 case CHANNEL_T: 3157 case CHANNEL_XR: 3158 ee_mode = AR5K_EEPROM_MODE_11A; 3159 break; 3160 case CHANNEL_G: 3161 case CHANNEL_TG: 3162 ee_mode = AR5K_EEPROM_MODE_11G; 3163 break; 3164 case CHANNEL_B: 3165 ee_mode = AR5K_EEPROM_MODE_11B; 3166 break; 3167 default: 3168 ATH5K_ERR(ah->ah_sc, 3169 "invalid channel: %d\n", channel->center_freq); 3170 return -EINVAL; 3171 } 3172 3173 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3174 "changing txpower to %d\n", txpower); 3175 3176 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3177} 3178 3179/*************\ 3180 Init function 3181\*************/ 3182 3183int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3184 u8 mode, u8 ee_mode, u8 freq) 3185{ 3186 int ret, i; 3187 u32 phy_tst1; 3188 3189 ret = 0; 3190 3191 /* 3192 * 5211/5212 Specific 3193 */ 3194 if (ah->ah_version != AR5K_AR5210) { 3195 3196 /* 3197 * Write initial RF gain settings 3198 * This should work for both 5111/5112 3199 */ 3200 ret = ath5k_hw_rfgain_init(ah, freq); 3201 if (ret) 3202 return ret; 3203 3204 mdelay(1); 3205 3206 /* 3207 * Set TX power 3208 */ 3209 ret = ath5k_hw_txpower(ah, channel, ee_mode, 3210 ah->ah_txpower.txp_max_pwr / 2); 3211 if (ret) 3212 return ret; 3213 3214 /* 3215 * Write RF buffer 3216 */ 3217 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3218 if (ret) 3219 return ret; 3220 3221 3222 /* Write OFDM timings on 5212*/ 3223 if (ah->ah_version == AR5K_AR5212 && 3224 channel->hw_value & CHANNEL_OFDM) { 3225 3226 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3227 if (ret) 3228 return ret; 3229 3230 /* Spur info is available only from EEPROM versions 3231 * greater than 5.3, but the EEPROM routines will use 3232 * static values for older versions */ 3233 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3234 ath5k_hw_set_spur_mitigation_filter(ah, 3235 channel); 3236 } 3237 3238 /*Enable/disable 802.11b mode on 5111 3239 (enable 2111 frequency converter + CCK)*/ 3240 if (ah->ah_radio == AR5K_RF5111) { 3241 if (mode == AR5K_MODE_11B) 3242 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3243 AR5K_TXCFG_B_MODE); 3244 else 3245 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3246 AR5K_TXCFG_B_MODE); 3247 } 3248 3249 } else { 3250 /* 3251 * For 5210 we do all initialization using 3252 * initvals, so we don't have to modify 3253 * any settings (5210 also only supports 3254 * a/aturbo modes) 3255 */ 3256 mdelay(1); 3257 /* Disable phy and wait */ 3258 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3259 mdelay(1); 3260 } 3261 3262 /* Set channel on PHY */ 3263 ret = ath5k_hw_channel(ah, channel); 3264 if (ret) 3265 return ret; 3266 3267 /* 3268 * Enable the PHY and wait until completion 3269 * This includes BaseBand and Synthesizer 3270 * activation. 3271 */ 3272 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3273 3274 /* 3275 * On 5211+ read activation -> rx delay 3276 * and use it. 3277 * 3278 * TODO: Half/quarter rate support 3279 */ 3280 if (ah->ah_version != AR5K_AR5210) { 3281 u32 delay; 3282 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 3283 AR5K_PHY_RX_DELAY_M; 3284 delay = (channel->hw_value & CHANNEL_CCK) ? 3285 ((delay << 2) / 22) : (delay / 10); 3286 3287 udelay(100 + (2 * delay)); 3288 } else { 3289 mdelay(1); 3290 } 3291 3292 /* 3293 * Perform ADC test to see if baseband is ready 3294 * Set TX hold and check ADC test register 3295 */ 3296 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3297 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3298 for (i = 0; i <= 20; i++) { 3299 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3300 break; 3301 udelay(200); 3302 } 3303 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3304 3305 /* 3306 * Start automatic gain control calibration 3307 * 3308 * During AGC calibration RX path is re-routed to 3309 * a power detector so we don't receive anything. 3310 * 3311 * This method is used to calibrate some static offsets 3312 * used together with on-the fly I/Q calibration (the 3313 * one performed via ath5k_hw_phy_calibrate), which doesn't 3314 * interrupt rx path. 3315 * 3316 * While rx path is re-routed to the power detector we also 3317 * start a noise floor calibration to measure the 3318 * card's noise floor (the noise we measure when we are not 3319 * transmitting or receiving anything). 3320 * 3321 * If we are in a noisy environment, AGC calibration may time 3322 * out and/or noise floor calibration might timeout. 3323 */ 3324 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3325 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3326 3327 /* At the same time start I/Q calibration for QAM constellation 3328 * -no need for CCK- */ 3329 ah->ah_calibration = false; 3330 if (!(mode == AR5K_MODE_11B)) { 3331 ah->ah_calibration = true; 3332 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3333 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3334 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3335 AR5K_PHY_IQ_RUN); 3336 } 3337 3338 /* Wait for gain calibration to finish (we check for I/Q calibration 3339 * during ath5k_phy_calibrate) */ 3340 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3341 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3342 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3343 channel->center_freq); 3344 } 3345 3346 /* Restore antenna mode */ 3347 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3348 3349 return ret; 3350} 3351