phy.c revision a4b770972b8f819e408d7cc3ae9637e15bff62f6
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32/* 33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 34 */ 35static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 36 const struct ath5k_rf_reg *rf_regs, 37 u32 val, u8 reg_id, bool set) 38{ 39 const struct ath5k_rf_reg *rfreg = NULL; 40 u8 offset, bank, num_bits, col, position; 41 u16 entry; 42 u32 mask, data, last_bit, bits_shifted, first_bit; 43 u32 *rfb; 44 s32 bits_left; 45 int i; 46 47 data = 0; 48 rfb = ah->ah_rf_banks; 49 50 for (i = 0; i < ah->ah_rf_regs_count; i++) { 51 if (rf_regs[i].index == reg_id) { 52 rfreg = &rf_regs[i]; 53 break; 54 } 55 } 56 57 if (rfb == NULL || rfreg == NULL) { 58 ATH5K_PRINTF("Rf register not found!\n"); 59 /* should not happen */ 60 return 0; 61 } 62 63 bank = rfreg->bank; 64 num_bits = rfreg->field.len; 65 first_bit = rfreg->field.pos; 66 col = rfreg->field.col; 67 68 /* first_bit is an offset from bank's 69 * start. Since we have all banks on 70 * the same array, we use this offset 71 * to mark each bank's start */ 72 offset = ah->ah_offset[bank]; 73 74 /* Boundary check */ 75 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 76 ATH5K_PRINTF("invalid values at offset %u\n", offset); 77 return 0; 78 } 79 80 entry = ((first_bit - 1) / 8) + offset; 81 position = (first_bit - 1) % 8; 82 83 if (set) 84 data = ath5k_hw_bitswap(val, num_bits); 85 86 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 87 position = 0, entry++) { 88 89 last_bit = (position + bits_left > 8) ? 8 : 90 position + bits_left; 91 92 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 93 (col * 8); 94 95 if (set) { 96 rfb[entry] &= ~mask; 97 rfb[entry] |= ((data << position) << (col * 8)) & mask; 98 data >>= (8 - position); 99 } else { 100 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 101 << bits_shifted; 102 bits_shifted += last_bit - position; 103 } 104 105 bits_left -= 8 - position; 106 } 107 108 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 109 110 return data; 111} 112 113/**********************\ 114* RF Gain optimization * 115\**********************/ 116 117/* 118 * This code is used to optimize rf gain on different environments 119 * (temperature mostly) based on feedback from a power detector. 120 * 121 * It's only used on RF5111 and RF5112, later RF chips seem to have 122 * auto adjustment on hw -notice they have a much smaller BANK 7 and 123 * no gain optimization ladder-. 124 * 125 * For more infos check out this patent doc 126 * http://www.freepatentsonline.com/7400691.html 127 * 128 * This paper describes power drops as seen on the receiver due to 129 * probe packets 130 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 131 * %20of%20Power%20Control.pdf 132 * 133 * And this is the MadWiFi bug entry related to the above 134 * http://madwifi-project.org/ticket/1659 135 * with various measurements and diagrams 136 * 137 * TODO: Deal with power drops due to probes by setting an apropriate 138 * tx power on the probe packets ! Make this part of the calibration process. 139 */ 140 141/* Initialize ah_gain durring attach */ 142int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 143{ 144 /* Initialize the gain optimization values */ 145 switch (ah->ah_radio) { 146 case AR5K_RF5111: 147 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 148 ah->ah_gain.g_low = 20; 149 ah->ah_gain.g_high = 35; 150 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 151 break; 152 case AR5K_RF5112: 153 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 154 ah->ah_gain.g_low = 20; 155 ah->ah_gain.g_high = 85; 156 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 157 break; 158 default: 159 return -EINVAL; 160 } 161 162 return 0; 163} 164 165/* Schedule a gain probe check on the next transmited packet. 166 * That means our next packet is going to be sent with lower 167 * tx power and a Peak to Average Power Detector (PAPD) will try 168 * to measure the gain. 169 * 170 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 171 * just after we enable the probe so that we don't mess with 172 * standard traffic ? Maybe it's time to use sw interrupts and 173 * a probe tasklet !!! 174 */ 175static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 176{ 177 178 /* Skip if gain calibration is inactive or 179 * we already handle a probe request */ 180 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 181 return; 182 183 /* Send the packet with 2dB below max power as 184 * patent doc suggest */ 185 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 186 AR5K_PHY_PAPD_PROBE_TXPOWER) | 187 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 188 189 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 190 191} 192 193/* Calculate gain_F measurement correction 194 * based on the current step for RF5112 rev. 2 */ 195static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 196{ 197 u32 mix, step; 198 u32 *rf; 199 const struct ath5k_gain_opt *go; 200 const struct ath5k_gain_opt_step *g_step; 201 const struct ath5k_rf_reg *rf_regs; 202 203 /* Only RF5112 Rev. 2 supports it */ 204 if ((ah->ah_radio != AR5K_RF5112) || 205 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 206 return 0; 207 208 go = &rfgain_opt_5112; 209 rf_regs = rf_regs_5112a; 210 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 211 212 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 213 214 if (ah->ah_rf_banks == NULL) 215 return 0; 216 217 rf = ah->ah_rf_banks; 218 ah->ah_gain.g_f_corr = 0; 219 220 /* No VGA (Variable Gain Amplifier) override, skip */ 221 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 222 return 0; 223 224 /* Mix gain stepping */ 225 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 226 227 /* Mix gain override */ 228 mix = g_step->gos_param[0]; 229 230 switch (mix) { 231 case 3: 232 ah->ah_gain.g_f_corr = step * 2; 233 break; 234 case 2: 235 ah->ah_gain.g_f_corr = (step - 5) * 2; 236 break; 237 case 1: 238 ah->ah_gain.g_f_corr = step; 239 break; 240 default: 241 ah->ah_gain.g_f_corr = 0; 242 break; 243 } 244 245 return ah->ah_gain.g_f_corr; 246} 247 248/* Check if current gain_F measurement is in the range of our 249 * power detector windows. If we get a measurement outside range 250 * we know it's not accurate (detectors can't measure anything outside 251 * their detection window) so we must ignore it */ 252static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 253{ 254 const struct ath5k_rf_reg *rf_regs; 255 u32 step, mix_ovr, level[4]; 256 u32 *rf; 257 258 if (ah->ah_rf_banks == NULL) 259 return false; 260 261 rf = ah->ah_rf_banks; 262 263 if (ah->ah_radio == AR5K_RF5111) { 264 265 rf_regs = rf_regs_5111; 266 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 267 268 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 269 false); 270 271 level[0] = 0; 272 level[1] = (step == 63) ? 50 : step + 4; 273 level[2] = (step != 63) ? 64 : level[0]; 274 level[3] = level[2] + 50 ; 275 276 ah->ah_gain.g_high = level[3] - 277 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 278 ah->ah_gain.g_low = level[0] + 279 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 280 } else { 281 282 rf_regs = rf_regs_5112; 283 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 284 285 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 286 false); 287 288 level[0] = level[2] = 0; 289 290 if (mix_ovr == 1) { 291 level[1] = level[3] = 83; 292 } else { 293 level[1] = level[3] = 107; 294 ah->ah_gain.g_high = 55; 295 } 296 } 297 298 return (ah->ah_gain.g_current >= level[0] && 299 ah->ah_gain.g_current <= level[1]) || 300 (ah->ah_gain.g_current >= level[2] && 301 ah->ah_gain.g_current <= level[3]); 302} 303 304/* Perform gain_F adjustment by choosing the right set 305 * of parameters from rf gain optimization ladder */ 306static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 307{ 308 const struct ath5k_gain_opt *go; 309 const struct ath5k_gain_opt_step *g_step; 310 int ret = 0; 311 312 switch (ah->ah_radio) { 313 case AR5K_RF5111: 314 go = &rfgain_opt_5111; 315 break; 316 case AR5K_RF5112: 317 go = &rfgain_opt_5112; 318 break; 319 default: 320 return 0; 321 } 322 323 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 324 325 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 326 327 /* Reached maximum */ 328 if (ah->ah_gain.g_step_idx == 0) 329 return -1; 330 331 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 332 ah->ah_gain.g_target >= ah->ah_gain.g_high && 333 ah->ah_gain.g_step_idx > 0; 334 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 335 ah->ah_gain.g_target -= 2 * 336 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 337 g_step->gos_gain); 338 339 ret = 1; 340 goto done; 341 } 342 343 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 344 345 /* Reached minimum */ 346 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 347 return -2; 348 349 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 350 ah->ah_gain.g_target <= ah->ah_gain.g_low && 351 ah->ah_gain.g_step_idx < go->go_steps_count-1; 352 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 353 ah->ah_gain.g_target -= 2 * 354 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 355 g_step->gos_gain); 356 357 ret = 2; 358 goto done; 359 } 360 361done: 362 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 363 "ret %d, gain step %u, current gain %u, target gain %u\n", 364 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 365 ah->ah_gain.g_target); 366 367 return ret; 368} 369 370/* Main callback for thermal rf gain calibration engine 371 * Check for a new gain reading and schedule an adjustment 372 * if needed. 373 * 374 * TODO: Use sw interrupt to schedule reset if gain_F needs 375 * adjustment */ 376enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 377{ 378 u32 data, type; 379 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 380 381 ATH5K_TRACE(ah->ah_sc); 382 383 if (ah->ah_rf_banks == NULL || 384 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 385 return AR5K_RFGAIN_INACTIVE; 386 387 /* No check requested, either engine is inactive 388 * or an adjustment is already requested */ 389 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 390 goto done; 391 392 /* Read the PAPD (Peak to Average Power Detector) 393 * register */ 394 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 395 396 /* No probe is scheduled, read gain_F measurement */ 397 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 398 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 399 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 400 401 /* If tx packet is CCK correct the gain_F measurement 402 * by cck ofdm gain delta */ 403 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 404 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 405 ah->ah_gain.g_current += 406 ee->ee_cck_ofdm_gain_delta; 407 else 408 ah->ah_gain.g_current += 409 AR5K_GAIN_CCK_PROBE_CORR; 410 } 411 412 /* Further correct gain_F measurement for 413 * RF5112A radios */ 414 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 415 ath5k_hw_rf_gainf_corr(ah); 416 ah->ah_gain.g_current = 417 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 418 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 419 0; 420 } 421 422 /* Check if measurement is ok and if we need 423 * to adjust gain, schedule a gain adjustment, 424 * else switch back to the acive state */ 425 if (ath5k_hw_rf_check_gainf_readback(ah) && 426 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 427 ath5k_hw_rf_gainf_adjust(ah)) { 428 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 429 } else { 430 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 431 } 432 } 433 434done: 435 return ah->ah_gain.g_state; 436} 437 438/* Write initial rf gain table to set the RF sensitivity 439 * this one works on all RF chips and has nothing to do 440 * with gain_F calibration */ 441int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 442{ 443 const struct ath5k_ini_rfgain *ath5k_rfg; 444 unsigned int i, size; 445 446 switch (ah->ah_radio) { 447 case AR5K_RF5111: 448 ath5k_rfg = rfgain_5111; 449 size = ARRAY_SIZE(rfgain_5111); 450 break; 451 case AR5K_RF5112: 452 ath5k_rfg = rfgain_5112; 453 size = ARRAY_SIZE(rfgain_5112); 454 break; 455 case AR5K_RF2413: 456 ath5k_rfg = rfgain_2413; 457 size = ARRAY_SIZE(rfgain_2413); 458 break; 459 case AR5K_RF2316: 460 ath5k_rfg = rfgain_2316; 461 size = ARRAY_SIZE(rfgain_2316); 462 break; 463 case AR5K_RF5413: 464 ath5k_rfg = rfgain_5413; 465 size = ARRAY_SIZE(rfgain_5413); 466 break; 467 case AR5K_RF2317: 468 case AR5K_RF2425: 469 ath5k_rfg = rfgain_2425; 470 size = ARRAY_SIZE(rfgain_2425); 471 break; 472 default: 473 return -EINVAL; 474 } 475 476 switch (freq) { 477 case AR5K_INI_RFGAIN_2GHZ: 478 case AR5K_INI_RFGAIN_5GHZ: 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 for (i = 0; i < size; i++) { 485 AR5K_REG_WAIT(i); 486 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 487 (u32)ath5k_rfg[i].rfg_register); 488 } 489 490 return 0; 491} 492 493 494 495/********************\ 496* RF Registers setup * 497\********************/ 498 499 500/* 501 * Setup RF registers by writing rf buffer on hw 502 */ 503int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 504 unsigned int mode) 505{ 506 const struct ath5k_rf_reg *rf_regs; 507 const struct ath5k_ini_rfbuffer *ini_rfb; 508 const struct ath5k_gain_opt *go = NULL; 509 const struct ath5k_gain_opt_step *g_step; 510 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 511 u8 ee_mode = 0; 512 u32 *rfb; 513 int i, obdb = -1, bank = -1; 514 515 switch (ah->ah_radio) { 516 case AR5K_RF5111: 517 rf_regs = rf_regs_5111; 518 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 519 ini_rfb = rfb_5111; 520 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 521 go = &rfgain_opt_5111; 522 break; 523 case AR5K_RF5112: 524 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 525 rf_regs = rf_regs_5112a; 526 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 527 ini_rfb = rfb_5112a; 528 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 529 } else { 530 rf_regs = rf_regs_5112; 531 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 532 ini_rfb = rfb_5112; 533 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 534 } 535 go = &rfgain_opt_5112; 536 break; 537 case AR5K_RF2413: 538 rf_regs = rf_regs_2413; 539 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 540 ini_rfb = rfb_2413; 541 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 542 break; 543 case AR5K_RF2316: 544 rf_regs = rf_regs_2316; 545 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 546 ini_rfb = rfb_2316; 547 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 548 break; 549 case AR5K_RF5413: 550 rf_regs = rf_regs_5413; 551 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 552 ini_rfb = rfb_5413; 553 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 554 break; 555 case AR5K_RF2317: 556 rf_regs = rf_regs_2425; 557 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 558 ini_rfb = rfb_2317; 559 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 560 break; 561 case AR5K_RF2425: 562 rf_regs = rf_regs_2425; 563 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 564 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 565 ini_rfb = rfb_2425; 566 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 567 } else { 568 ini_rfb = rfb_2417; 569 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 570 } 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 /* If it's the first time we set rf buffer, allocate 577 * ah->ah_rf_banks based on ah->ah_rf_banks_size 578 * we set above */ 579 if (ah->ah_rf_banks == NULL) { 580 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 581 GFP_KERNEL); 582 if (ah->ah_rf_banks == NULL) { 583 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 584 return -ENOMEM; 585 } 586 } 587 588 /* Copy values to modify them */ 589 rfb = ah->ah_rf_banks; 590 591 for (i = 0; i < ah->ah_rf_banks_size; i++) { 592 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 593 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 594 return -EINVAL; 595 } 596 597 /* Bank changed, write down the offset */ 598 if (bank != ini_rfb[i].rfb_bank) { 599 bank = ini_rfb[i].rfb_bank; 600 ah->ah_offset[bank] = i; 601 } 602 603 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 604 } 605 606 /* Set Output and Driver bias current (OB/DB) */ 607 if (channel->hw_value & CHANNEL_2GHZ) { 608 609 if (channel->hw_value & CHANNEL_CCK) 610 ee_mode = AR5K_EEPROM_MODE_11B; 611 else 612 ee_mode = AR5K_EEPROM_MODE_11G; 613 614 /* For RF511X/RF211X combination we 615 * use b_OB and b_DB parameters stored 616 * in eeprom on ee->ee_ob[ee_mode][0] 617 * 618 * For all other chips we use OB/DB for 2Ghz 619 * stored in the b/g modal section just like 620 * 802.11a on ee->ee_ob[ee_mode][1] */ 621 if ((ah->ah_radio == AR5K_RF5111) || 622 (ah->ah_radio == AR5K_RF5112)) 623 obdb = 0; 624 else 625 obdb = 1; 626 627 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 628 AR5K_RF_OB_2GHZ, true); 629 630 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 631 AR5K_RF_DB_2GHZ, true); 632 633 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 634 } else if ((channel->hw_value & CHANNEL_5GHZ) || 635 (ah->ah_radio == AR5K_RF5111)) { 636 637 /* For 11a, Turbo and XR we need to choose 638 * OB/DB based on frequency range */ 639 ee_mode = AR5K_EEPROM_MODE_11A; 640 obdb = channel->center_freq >= 5725 ? 3 : 641 (channel->center_freq >= 5500 ? 2 : 642 (channel->center_freq >= 5260 ? 1 : 643 (channel->center_freq > 4000 ? 0 : -1))); 644 645 if (obdb < 0) 646 return -EINVAL; 647 648 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 649 AR5K_RF_OB_5GHZ, true); 650 651 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 652 AR5K_RF_DB_5GHZ, true); 653 } 654 655 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 656 657 /* Bank Modifications (chip-specific) */ 658 if (ah->ah_radio == AR5K_RF5111) { 659 660 /* Set gain_F settings according to current step */ 661 if (channel->hw_value & CHANNEL_OFDM) { 662 663 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 664 AR5K_PHY_FRAME_CTL_TX_CLIP, 665 g_step->gos_param[0]); 666 667 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 668 AR5K_RF_PWD_90, true); 669 670 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 671 AR5K_RF_PWD_84, true); 672 673 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 674 AR5K_RF_RFGAIN_SEL, true); 675 676 /* We programmed gain_F parameters, switch back 677 * to active state */ 678 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 679 680 } 681 682 /* Bank 6/7 setup */ 683 684 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 685 AR5K_RF_PWD_XPD, true); 686 687 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 688 AR5K_RF_XPD_GAIN, true); 689 690 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 691 AR5K_RF_GAIN_I, true); 692 693 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 694 AR5K_RF_PLO_SEL, true); 695 696 /* TODO: Half/quarter channel support */ 697 } 698 699 if (ah->ah_radio == AR5K_RF5112) { 700 701 /* Set gain_F settings according to current step */ 702 if (channel->hw_value & CHANNEL_OFDM) { 703 704 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 705 AR5K_RF_MIXGAIN_OVR, true); 706 707 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 708 AR5K_RF_PWD_138, true); 709 710 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 711 AR5K_RF_PWD_137, true); 712 713 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 714 AR5K_RF_PWD_136, true); 715 716 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 717 AR5K_RF_PWD_132, true); 718 719 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 720 AR5K_RF_PWD_131, true); 721 722 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 723 AR5K_RF_PWD_130, true); 724 725 /* We programmed gain_F parameters, switch back 726 * to active state */ 727 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 728 } 729 730 /* Bank 6/7 setup */ 731 732 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 733 AR5K_RF_XPD_SEL, true); 734 735 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 736 /* Rev. 1 supports only one xpd */ 737 ath5k_hw_rfb_op(ah, rf_regs, 738 ee->ee_x_gain[ee_mode], 739 AR5K_RF_XPD_GAIN, true); 740 741 } else { 742 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 743 if (ee->ee_pd_gains[ee_mode] > 1) { 744 ath5k_hw_rfb_op(ah, rf_regs, 745 pdg_curve_to_idx[0], 746 AR5K_RF_PD_GAIN_LO, true); 747 ath5k_hw_rfb_op(ah, rf_regs, 748 pdg_curve_to_idx[1], 749 AR5K_RF_PD_GAIN_HI, true); 750 } else { 751 ath5k_hw_rfb_op(ah, rf_regs, 752 pdg_curve_to_idx[0], 753 AR5K_RF_PD_GAIN_LO, true); 754 ath5k_hw_rfb_op(ah, rf_regs, 755 pdg_curve_to_idx[0], 756 AR5K_RF_PD_GAIN_HI, true); 757 } 758 759 /* Lower synth voltage on Rev 2 */ 760 ath5k_hw_rfb_op(ah, rf_regs, 2, 761 AR5K_RF_HIGH_VC_CP, true); 762 763 ath5k_hw_rfb_op(ah, rf_regs, 2, 764 AR5K_RF_MID_VC_CP, true); 765 766 ath5k_hw_rfb_op(ah, rf_regs, 2, 767 AR5K_RF_LOW_VC_CP, true); 768 769 ath5k_hw_rfb_op(ah, rf_regs, 2, 770 AR5K_RF_PUSH_UP, true); 771 772 /* Decrease power consumption on 5213+ BaseBand */ 773 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 774 ath5k_hw_rfb_op(ah, rf_regs, 1, 775 AR5K_RF_PAD2GND, true); 776 777 ath5k_hw_rfb_op(ah, rf_regs, 1, 778 AR5K_RF_XB2_LVL, true); 779 780 ath5k_hw_rfb_op(ah, rf_regs, 1, 781 AR5K_RF_XB5_LVL, true); 782 783 ath5k_hw_rfb_op(ah, rf_regs, 1, 784 AR5K_RF_PWD_167, true); 785 786 ath5k_hw_rfb_op(ah, rf_regs, 1, 787 AR5K_RF_PWD_166, true); 788 } 789 } 790 791 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 792 AR5K_RF_GAIN_I, true); 793 794 /* TODO: Half/quarter channel support */ 795 796 } 797 798 if (ah->ah_radio == AR5K_RF5413 && 799 channel->hw_value & CHANNEL_2GHZ) { 800 801 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 802 true); 803 804 /* Set optimum value for early revisions (on pci-e chips) */ 805 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 806 ah->ah_mac_srev < AR5K_SREV_AR5413) 807 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 808 AR5K_RF_PWD_ICLOBUF_2G, true); 809 810 } 811 812 /* Write RF banks on hw */ 813 for (i = 0; i < ah->ah_rf_banks_size; i++) { 814 AR5K_REG_WAIT(i); 815 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 816 } 817 818 return 0; 819} 820 821 822/**************************\ 823 PHY/RF channel functions 824\**************************/ 825 826/* 827 * Check if a channel is supported 828 */ 829bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 830{ 831 /* Check if the channel is in our supported range */ 832 if (flags & CHANNEL_2GHZ) { 833 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 834 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 835 return true; 836 } else if (flags & CHANNEL_5GHZ) 837 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 838 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 839 return true; 840 841 return false; 842} 843 844/* 845 * Convertion needed for RF5110 846 */ 847static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 848{ 849 u32 athchan; 850 851 /* 852 * Convert IEEE channel/MHz to an internal channel value used 853 * by the AR5210 chipset. This has not been verified with 854 * newer chipsets like the AR5212A who have a completely 855 * different RF/PHY part. 856 */ 857 athchan = (ath5k_hw_bitswap( 858 (ieee80211_frequency_to_channel( 859 channel->center_freq) - 24) / 2, 5) 860 << 1) | (1 << 6) | 0x1; 861 return athchan; 862} 863 864/* 865 * Set channel on RF5110 866 */ 867static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 868 struct ieee80211_channel *channel) 869{ 870 u32 data; 871 872 /* 873 * Set the channel and wait 874 */ 875 data = ath5k_hw_rf5110_chan2athchan(channel); 876 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 877 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 878 mdelay(1); 879 880 return 0; 881} 882 883/* 884 * Convertion needed for 5111 885 */ 886static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 887 struct ath5k_athchan_2ghz *athchan) 888{ 889 int channel; 890 891 /* Cast this value to catch negative channel numbers (>= -19) */ 892 channel = (int)ieee; 893 894 /* 895 * Map 2GHz IEEE channel to 5GHz Atheros channel 896 */ 897 if (channel <= 13) { 898 athchan->a2_athchan = 115 + channel; 899 athchan->a2_flags = 0x46; 900 } else if (channel == 14) { 901 athchan->a2_athchan = 124; 902 athchan->a2_flags = 0x44; 903 } else if (channel >= 15 && channel <= 26) { 904 athchan->a2_athchan = ((channel - 14) * 4) + 132; 905 athchan->a2_flags = 0x46; 906 } else 907 return -EINVAL; 908 909 return 0; 910} 911 912/* 913 * Set channel on 5111 914 */ 915static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 916 struct ieee80211_channel *channel) 917{ 918 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 919 unsigned int ath5k_channel = 920 ieee80211_frequency_to_channel(channel->center_freq); 921 u32 data0, data1, clock; 922 int ret; 923 924 /* 925 * Set the channel on the RF5111 radio 926 */ 927 data0 = data1 = 0; 928 929 if (channel->hw_value & CHANNEL_2GHZ) { 930 /* Map 2GHz channel to 5GHz Atheros channel ID */ 931 ret = ath5k_hw_rf5111_chan2athchan( 932 ieee80211_frequency_to_channel(channel->center_freq), 933 &ath5k_channel_2ghz); 934 if (ret) 935 return ret; 936 937 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 938 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 939 << 5) | (1 << 4); 940 } 941 942 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 943 clock = 1; 944 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 945 (clock << 1) | (1 << 10) | 1; 946 } else { 947 clock = 0; 948 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 949 << 2) | (clock << 1) | (1 << 10) | 1; 950 } 951 952 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 953 AR5K_RF_BUFFER); 954 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 955 AR5K_RF_BUFFER_CONTROL_3); 956 957 return 0; 958} 959 960/* 961 * Set channel on 5112 and newer 962 */ 963static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 964 struct ieee80211_channel *channel) 965{ 966 u32 data, data0, data1, data2; 967 u16 c; 968 969 data = data0 = data1 = data2 = 0; 970 c = channel->center_freq; 971 972 if (c < 4800) { 973 if (!((c - 2224) % 5)) { 974 data0 = ((2 * (c - 704)) - 3040) / 10; 975 data1 = 1; 976 } else if (!((c - 2192) % 5)) { 977 data0 = ((2 * (c - 672)) - 3040) / 10; 978 data1 = 0; 979 } else 980 return -EINVAL; 981 982 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 983 } else if ((c % 5) != 2 || c > 5435) { 984 if (!(c % 20) && c >= 5120) { 985 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 986 data2 = ath5k_hw_bitswap(3, 2); 987 } else if (!(c % 10)) { 988 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 989 data2 = ath5k_hw_bitswap(2, 2); 990 } else if (!(c % 5)) { 991 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 992 data2 = ath5k_hw_bitswap(1, 2); 993 } else 994 return -EINVAL; 995 } else { 996 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 997 data2 = ath5k_hw_bitswap(0, 2); 998 } 999 1000 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1001 1002 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1003 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1004 1005 return 0; 1006} 1007 1008/* 1009 * Set the channel on the RF2425 1010 */ 1011static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1012 struct ieee80211_channel *channel) 1013{ 1014 u32 data, data0, data2; 1015 u16 c; 1016 1017 data = data0 = data2 = 0; 1018 c = channel->center_freq; 1019 1020 if (c < 4800) { 1021 data0 = ath5k_hw_bitswap((c - 2272), 8); 1022 data2 = 0; 1023 /* ? 5GHz ? */ 1024 } else if ((c % 5) != 2 || c > 5435) { 1025 if (!(c % 20) && c < 5120) 1026 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1027 else if (!(c % 10)) 1028 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1029 else if (!(c % 5)) 1030 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1031 else 1032 return -EINVAL; 1033 data2 = ath5k_hw_bitswap(1, 2); 1034 } else { 1035 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1036 data2 = ath5k_hw_bitswap(0, 2); 1037 } 1038 1039 data = (data0 << 4) | data2 << 2 | 0x1001; 1040 1041 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1042 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1043 1044 return 0; 1045} 1046 1047/* 1048 * Set a channel on the radio chip 1049 */ 1050int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) 1051{ 1052 int ret; 1053 /* 1054 * Check bounds supported by the PHY (we don't care about regultory 1055 * restrictions at this point). Note: hw_value already has the band 1056 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1057 * of the band by that */ 1058 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1059 ATH5K_ERR(ah->ah_sc, 1060 "channel frequency (%u MHz) out of supported " 1061 "band range\n", 1062 channel->center_freq); 1063 return -EINVAL; 1064 } 1065 1066 /* 1067 * Set the channel and wait 1068 */ 1069 switch (ah->ah_radio) { 1070 case AR5K_RF5110: 1071 ret = ath5k_hw_rf5110_channel(ah, channel); 1072 break; 1073 case AR5K_RF5111: 1074 ret = ath5k_hw_rf5111_channel(ah, channel); 1075 break; 1076 case AR5K_RF2425: 1077 ret = ath5k_hw_rf2425_channel(ah, channel); 1078 break; 1079 default: 1080 ret = ath5k_hw_rf5112_channel(ah, channel); 1081 break; 1082 } 1083 1084 if (ret) 1085 return ret; 1086 1087 /* Set JAPAN setting for channel 14 */ 1088 if (channel->center_freq == 2484) { 1089 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1090 AR5K_PHY_CCKTXCTL_JAPAN); 1091 } else { 1092 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1093 AR5K_PHY_CCKTXCTL_WORLD); 1094 } 1095 1096 ah->ah_current_channel = channel; 1097 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; 1098 1099 return 0; 1100} 1101 1102/*****************\ 1103 PHY calibration 1104\*****************/ 1105 1106static int sign_extend(int val, const int nbits) 1107{ 1108 int order = BIT(nbits-1); 1109 return (val ^ order) - order; 1110} 1111 1112static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1113{ 1114 s32 val; 1115 1116 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1117 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9); 1118} 1119 1120void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1121{ 1122 int i; 1123 1124 ah->ah_nfcal_hist.index = 0; 1125 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1126 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1127} 1128 1129static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1130{ 1131 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1132 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1133 hist->nfval[hist->index] = noise_floor; 1134} 1135 1136static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1137{ 1138 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1139 s16 tmp; 1140 int i, j; 1141 1142 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1143 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1144 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1145 if (sort[j] > sort[j-1]) { 1146 tmp = sort[j]; 1147 sort[j] = sort[j-1]; 1148 sort[j-1] = tmp; 1149 } 1150 } 1151 } 1152 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1153 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1154 "cal %d:%d\n", i, sort[i]); 1155 } 1156 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1157} 1158 1159/* 1160 * When we tell the hardware to perform a noise floor calibration 1161 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1162 * sample-and-hold the minimum noise level seen at the antennas. 1163 * This value is then stored in a ring buffer of recently measured 1164 * noise floor values so we have a moving window of the last few 1165 * samples. 1166 * 1167 * The median of the values in the history is then loaded into the 1168 * hardware for its own use for RSSI and CCA measurements. 1169 */ 1170static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1171{ 1172 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1173 u32 val; 1174 s16 nf, threshold; 1175 u8 ee_mode; 1176 1177 /* keep last value if calibration hasn't completed */ 1178 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1179 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1180 "NF did not complete in calibration window\n"); 1181 1182 return; 1183 } 1184 1185 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { 1186 case CHANNEL_A: 1187 case CHANNEL_T: 1188 case CHANNEL_XR: 1189 ee_mode = AR5K_EEPROM_MODE_11A; 1190 break; 1191 case CHANNEL_G: 1192 case CHANNEL_TG: 1193 ee_mode = AR5K_EEPROM_MODE_11G; 1194 break; 1195 default: 1196 case CHANNEL_B: 1197 ee_mode = AR5K_EEPROM_MODE_11B; 1198 break; 1199 } 1200 1201 1202 /* completed NF calibration, test threshold */ 1203 nf = ath5k_hw_read_measured_noise_floor(ah); 1204 threshold = ee->ee_noise_floor_thr[ee_mode]; 1205 1206 if (nf > threshold) { 1207 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1208 "noise floor failure detected; " 1209 "read %d, threshold %d\n", 1210 nf, threshold); 1211 1212 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1213 } 1214 1215 ath5k_hw_update_nfcal_hist(ah, nf); 1216 nf = ath5k_hw_get_median_noise_floor(ah); 1217 1218 /* load noise floor (in .5 dBm) so the hardware will use it */ 1219 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1220 val |= (nf * 2) & AR5K_PHY_NF_M; 1221 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1222 1223 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1224 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1225 1226 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1227 0, false); 1228 1229 /* 1230 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1231 * so that we're not capped by the median we just loaded. 1232 * This will be used as the initial value for the next noise 1233 * floor calibration. 1234 */ 1235 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1236 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1237 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1238 AR5K_PHY_AGCCTL_NF_EN | 1239 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1240 AR5K_PHY_AGCCTL_NF); 1241 1242 ah->ah_noise_floor = nf; 1243 1244 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1245 "noise floor calibrated: %d\n", nf); 1246} 1247 1248/* 1249 * Perform a PHY calibration on RF5110 1250 * -Fix BPSK/QAM Constellation (I/Q correction) 1251 * -Calculate Noise Floor 1252 */ 1253static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1254 struct ieee80211_channel *channel) 1255{ 1256 u32 phy_sig, phy_agc, phy_sat, beacon; 1257 int ret; 1258 1259 /* 1260 * Disable beacons and RX/TX queues, wait 1261 */ 1262 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1263 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1264 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1265 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1266 1267 mdelay(2); 1268 1269 /* 1270 * Set the channel (with AGC turned off) 1271 */ 1272 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1273 udelay(10); 1274 ret = ath5k_hw_channel(ah, channel); 1275 1276 /* 1277 * Activate PHY and wait 1278 */ 1279 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1280 mdelay(1); 1281 1282 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1283 1284 if (ret) 1285 return ret; 1286 1287 /* 1288 * Calibrate the radio chip 1289 */ 1290 1291 /* Remember normal state */ 1292 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1293 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1294 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1295 1296 /* Update radio registers */ 1297 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1298 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1299 1300 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1301 AR5K_PHY_AGCCOARSE_LO)) | 1302 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1303 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1304 1305 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1306 AR5K_PHY_ADCSAT_THR)) | 1307 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1308 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1309 1310 udelay(20); 1311 1312 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1313 udelay(10); 1314 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1315 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1316 1317 mdelay(1); 1318 1319 /* 1320 * Enable calibration and wait until completion 1321 */ 1322 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1323 1324 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1325 AR5K_PHY_AGCCTL_CAL, 0, false); 1326 1327 /* Reset to normal state */ 1328 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1329 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1330 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1331 1332 if (ret) { 1333 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1334 channel->center_freq); 1335 return ret; 1336 } 1337 1338 ath5k_hw_update_noise_floor(ah); 1339 1340 /* 1341 * Re-enable RX/TX and beacons 1342 */ 1343 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1344 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1345 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1346 1347 return 0; 1348} 1349 1350/* 1351 * Perform a PHY calibration on RF5111/5112 and newer chips 1352 */ 1353static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, 1354 struct ieee80211_channel *channel) 1355{ 1356 u32 i_pwr, q_pwr; 1357 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1358 int i; 1359 ATH5K_TRACE(ah->ah_sc); 1360 1361 if (!ah->ah_calibration || 1362 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1363 goto done; 1364 1365 /* Calibration has finished, get the results and re-run */ 1366 1367 /* work around empty results which can apparently happen on 5212 */ 1368 for (i = 0; i <= 10; i++) { 1369 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1370 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1371 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1372 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1373 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1374 if (i_pwr && q_pwr) 1375 break; 1376 } 1377 1378 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1379 1380 if (ah->ah_version == AR5K_AR5211) 1381 q_coffd = q_pwr >> 6; 1382 else 1383 q_coffd = q_pwr >> 7; 1384 1385 /* protect against divide by 0 and loss of sign bits */ 1386 if (i_coffd == 0 || q_coffd < 2) 1387 goto done; 1388 1389 i_coff = (-iq_corr) / i_coffd; 1390 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1391 1392 if (ah->ah_version == AR5K_AR5211) 1393 q_coff = (i_pwr / q_coffd) - 64; 1394 else 1395 q_coff = (i_pwr / q_coffd) - 128; 1396 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1397 1398 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1399 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1400 i_coff, q_coff, i_coffd, q_coffd); 1401 1402 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1403 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1404 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1405 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1406 1407 /* Re-enable calibration -if we don't we'll commit 1408 * the same values again and again */ 1409 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1410 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1411 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1412 1413done: 1414 1415 /* TODO: Separate noise floor calibration from I/Q calibration 1416 * since noise floor calibration interrupts rx path while I/Q 1417 * calibration doesn't. We don't need to run noise floor calibration 1418 * as often as I/Q calibration.*/ 1419 ath5k_hw_update_noise_floor(ah); 1420 1421 /* Initiate a gain_F calibration */ 1422 ath5k_hw_request_rfgain_probe(ah); 1423 1424 return 0; 1425} 1426 1427/* 1428 * Perform a PHY calibration 1429 */ 1430int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1431 struct ieee80211_channel *channel) 1432{ 1433 int ret; 1434 1435 if (ah->ah_radio == AR5K_RF5110) 1436 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1437 else 1438 ret = ath5k_hw_rf511x_calibrate(ah, channel); 1439 1440 return ret; 1441} 1442 1443/***************************\ 1444* Spur mitigation functions * 1445\***************************/ 1446 1447bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1448 struct ieee80211_channel *channel) 1449{ 1450 u8 refclk_freq; 1451 1452 if ((ah->ah_radio == AR5K_RF5112) || 1453 (ah->ah_radio == AR5K_RF5413) || 1454 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 1455 refclk_freq = 40; 1456 else 1457 refclk_freq = 32; 1458 1459 if ((channel->center_freq % refclk_freq != 0) && 1460 ((channel->center_freq % refclk_freq < 10) || 1461 (channel->center_freq % refclk_freq > 22))) 1462 return true; 1463 else 1464 return false; 1465} 1466 1467void 1468ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1469 struct ieee80211_channel *channel) 1470{ 1471 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1472 u32 mag_mask[4] = {0, 0, 0, 0}; 1473 u32 pilot_mask[2] = {0, 0}; 1474 /* Note: fbin values are scaled up by 2 */ 1475 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1476 s32 spur_delta_phase, spur_freq_sigma_delta; 1477 s32 spur_offset, num_symbols_x16; 1478 u8 num_symbol_offsets, i, freq_band; 1479 1480 /* Convert current frequency to fbin value (the same way channels 1481 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1482 * up by 2 so we can compare it later */ 1483 if (channel->hw_value & CHANNEL_2GHZ) { 1484 chan_fbin = (channel->center_freq - 2300) * 10; 1485 freq_band = AR5K_EEPROM_BAND_2GHZ; 1486 } else { 1487 chan_fbin = (channel->center_freq - 4900) * 10; 1488 freq_band = AR5K_EEPROM_BAND_5GHZ; 1489 } 1490 1491 /* Check if any spur_chan_fbin from EEPROM is 1492 * within our current channel's spur detection range */ 1493 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1494 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1495 /* XXX: Half/Quarter channels ?*/ 1496 if (channel->hw_value & CHANNEL_TURBO) 1497 spur_detection_window *= 2; 1498 1499 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1500 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1501 1502 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1503 * so it's zero if we got nothing from EEPROM */ 1504 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1505 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1506 break; 1507 } 1508 1509 if ((chan_fbin - spur_detection_window <= 1510 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1511 (chan_fbin + spur_detection_window >= 1512 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1513 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1514 break; 1515 } 1516 } 1517 1518 /* We need to enable spur filter for this channel */ 1519 if (spur_chan_fbin) { 1520 spur_offset = spur_chan_fbin - chan_fbin; 1521 /* 1522 * Calculate deltas: 1523 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1524 * spur_delta_phase -> spur_offset / chip_freq << 11 1525 * Note: Both values have 100KHz resolution 1526 */ 1527 /* XXX: Half/Quarter rate channels ? */ 1528 switch (channel->hw_value) { 1529 case CHANNEL_A: 1530 /* Both sample_freq and chip_freq are 40MHz */ 1531 spur_delta_phase = (spur_offset << 17) / 25; 1532 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1533 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1534 break; 1535 case CHANNEL_G: 1536 /* sample_freq -> 40MHz chip_freq -> 44MHz 1537 * (for b compatibility) */ 1538 spur_freq_sigma_delta = (spur_offset << 8) / 55; 1539 spur_delta_phase = (spur_offset << 17) / 25; 1540 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1541 break; 1542 case CHANNEL_T: 1543 case CHANNEL_TG: 1544 /* Both sample_freq and chip_freq are 80MHz */ 1545 spur_delta_phase = (spur_offset << 16) / 25; 1546 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1547 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; 1548 break; 1549 default: 1550 return; 1551 } 1552 1553 /* Calculate pilot and magnitude masks */ 1554 1555 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1556 * and divide by symbol_width to find how many symbols we have 1557 * Note: number of symbols is scaled up by 16 */ 1558 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1559 1560 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1561 if (!(num_symbols_x16 & 0xF)) 1562 /* _X_ */ 1563 num_symbol_offsets = 3; 1564 else 1565 /* _xx_ */ 1566 num_symbol_offsets = 4; 1567 1568 for (i = 0; i < num_symbol_offsets; i++) { 1569 1570 /* Calculate pilot mask */ 1571 s32 curr_sym_off = 1572 (num_symbols_x16 / 16) + i + 25; 1573 1574 /* Pilot magnitude mask seems to be a way to 1575 * declare the boundaries for our detection 1576 * window or something, it's 2 for the middle 1577 * value(s) where the symbol is expected to be 1578 * and 1 on the boundary values */ 1579 u8 plt_mag_map = 1580 (i == 0 || i == (num_symbol_offsets - 1)) 1581 ? 1 : 2; 1582 1583 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1584 if (curr_sym_off <= 25) 1585 pilot_mask[0] |= 1 << curr_sym_off; 1586 else if (curr_sym_off >= 27) 1587 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1588 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1589 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1590 1591 /* Calculate magnitude mask (for viterbi decoder) */ 1592 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1593 mag_mask[0] |= 1594 plt_mag_map << (curr_sym_off + 1) * 2; 1595 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1596 mag_mask[1] |= 1597 plt_mag_map << (curr_sym_off - 15) * 2; 1598 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1599 mag_mask[2] |= 1600 plt_mag_map << (curr_sym_off - 31) * 2; 1601 else if (curr_sym_off >= 46 && curr_sym_off <= 53) 1602 mag_mask[3] |= 1603 plt_mag_map << (curr_sym_off - 47) * 2; 1604 1605 } 1606 1607 /* Write settings on hw to enable spur filter */ 1608 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1609 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1610 /* XXX: Self correlator also ? */ 1611 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1612 AR5K_PHY_IQ_PILOT_MASK_EN | 1613 AR5K_PHY_IQ_CHAN_MASK_EN | 1614 AR5K_PHY_IQ_SPUR_FILT_EN); 1615 1616 /* Set delta phase and freq sigma delta */ 1617 ath5k_hw_reg_write(ah, 1618 AR5K_REG_SM(spur_delta_phase, 1619 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1620 AR5K_REG_SM(spur_freq_sigma_delta, 1621 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1622 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1623 AR5K_PHY_TIMING_11); 1624 1625 /* Write pilot masks */ 1626 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1627 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1628 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1629 pilot_mask[1]); 1630 1631 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1632 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1633 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1634 pilot_mask[1]); 1635 1636 /* Write magnitude masks */ 1637 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1638 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1639 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1640 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1641 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1642 mag_mask[3]); 1643 1644 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1645 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1646 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1647 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1648 AR5K_PHY_BIN_MASK2_4_MASK_4, 1649 mag_mask[3]); 1650 1651 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1652 AR5K_PHY_IQ_SPUR_FILT_EN) { 1653 /* Clean up spur mitigation settings and disable fliter */ 1654 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1655 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1656 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1657 AR5K_PHY_IQ_PILOT_MASK_EN | 1658 AR5K_PHY_IQ_CHAN_MASK_EN | 1659 AR5K_PHY_IQ_SPUR_FILT_EN); 1660 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1661 1662 /* Clear pilot masks */ 1663 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1665 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1666 0); 1667 1668 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1669 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1670 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1671 0); 1672 1673 /* Clear magnitude masks */ 1674 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1675 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1676 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1677 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1678 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1679 0); 1680 1681 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1682 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1683 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1684 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1685 AR5K_PHY_BIN_MASK2_4_MASK_4, 1686 0); 1687 } 1688} 1689 1690/********************\ 1691 Misc PHY functions 1692\********************/ 1693 1694int ath5k_hw_phy_disable(struct ath5k_hw *ah) 1695{ 1696 ATH5K_TRACE(ah->ah_sc); 1697 /*Just a try M.F.*/ 1698 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1699 1700 return 0; 1701} 1702 1703/* 1704 * Get the PHY Chip revision 1705 */ 1706u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 1707{ 1708 unsigned int i; 1709 u32 srev; 1710 u16 ret; 1711 1712 ATH5K_TRACE(ah->ah_sc); 1713 1714 /* 1715 * Set the radio chip access register 1716 */ 1717 switch (chan) { 1718 case CHANNEL_2GHZ: 1719 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 1720 break; 1721 case CHANNEL_5GHZ: 1722 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1723 break; 1724 default: 1725 return 0; 1726 } 1727 1728 mdelay(2); 1729 1730 /* ...wait until PHY is ready and read the selected radio revision */ 1731 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 1732 1733 for (i = 0; i < 8; i++) 1734 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 1735 1736 if (ah->ah_version == AR5K_AR5210) { 1737 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 1738 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 1739 } else { 1740 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 1741 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 1742 ((srev & 0x0f) << 4), 8); 1743 } 1744 1745 /* Reset to the 5GHz mode */ 1746 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1747 1748 return ret; 1749} 1750 1751/*****************\ 1752* Antenna control * 1753\*****************/ 1754 1755static void /*TODO:Boundary check*/ 1756ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1757{ 1758 ATH5K_TRACE(ah->ah_sc); 1759 1760 if (ah->ah_version != AR5K_AR5210) 1761 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1762} 1763 1764/* 1765 * Enable/disable fast rx antenna diversity 1766 */ 1767static void 1768ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1769{ 1770 switch (ee_mode) { 1771 case AR5K_EEPROM_MODE_11G: 1772 /* XXX: This is set to 1773 * disabled on initvals !!! */ 1774 case AR5K_EEPROM_MODE_11A: 1775 if (enable) 1776 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1777 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1778 else 1779 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1780 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1781 break; 1782 case AR5K_EEPROM_MODE_11B: 1783 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1784 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1785 break; 1786 default: 1787 return; 1788 } 1789 1790 if (enable) { 1791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1792 AR5K_PHY_RESTART_DIV_GC, 0xc); 1793 1794 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1795 AR5K_PHY_FAST_ANT_DIV_EN); 1796 } else { 1797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1798 AR5K_PHY_RESTART_DIV_GC, 0x8); 1799 1800 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1801 AR5K_PHY_FAST_ANT_DIV_EN); 1802 } 1803} 1804 1805/* 1806 * Set antenna operating mode 1807 */ 1808void 1809ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1810{ 1811 struct ieee80211_channel *channel = ah->ah_current_channel; 1812 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1813 bool use_def_for_sg; 1814 u8 def_ant, tx_ant, ee_mode; 1815 u32 sta_id1 = 0; 1816 1817 def_ant = ah->ah_def_ant; 1818 1819 ATH5K_TRACE(ah->ah_sc); 1820 1821 switch (channel->hw_value & CHANNEL_MODES) { 1822 case CHANNEL_A: 1823 case CHANNEL_T: 1824 case CHANNEL_XR: 1825 ee_mode = AR5K_EEPROM_MODE_11A; 1826 break; 1827 case CHANNEL_G: 1828 case CHANNEL_TG: 1829 ee_mode = AR5K_EEPROM_MODE_11G; 1830 break; 1831 case CHANNEL_B: 1832 ee_mode = AR5K_EEPROM_MODE_11B; 1833 break; 1834 default: 1835 ATH5K_ERR(ah->ah_sc, 1836 "invalid channel: %d\n", channel->center_freq); 1837 return; 1838 } 1839 1840 switch (ant_mode) { 1841 case AR5K_ANTMODE_DEFAULT: 1842 tx_ant = 0; 1843 use_def_for_tx = false; 1844 update_def_on_tx = false; 1845 use_def_for_rts = false; 1846 use_def_for_sg = false; 1847 fast_div = true; 1848 break; 1849 case AR5K_ANTMODE_FIXED_A: 1850 def_ant = 1; 1851 tx_ant = 1; 1852 use_def_for_tx = true; 1853 update_def_on_tx = false; 1854 use_def_for_rts = true; 1855 use_def_for_sg = true; 1856 fast_div = false; 1857 break; 1858 case AR5K_ANTMODE_FIXED_B: 1859 def_ant = 2; 1860 tx_ant = 2; 1861 use_def_for_tx = true; 1862 update_def_on_tx = false; 1863 use_def_for_rts = true; 1864 use_def_for_sg = true; 1865 fast_div = false; 1866 break; 1867 case AR5K_ANTMODE_SINGLE_AP: 1868 def_ant = 1; /* updated on tx */ 1869 tx_ant = 0; 1870 use_def_for_tx = true; 1871 update_def_on_tx = true; 1872 use_def_for_rts = true; 1873 use_def_for_sg = true; 1874 fast_div = true; 1875 break; 1876 case AR5K_ANTMODE_SECTOR_AP: 1877 tx_ant = 1; /* variable */ 1878 use_def_for_tx = false; 1879 update_def_on_tx = false; 1880 use_def_for_rts = true; 1881 use_def_for_sg = false; 1882 fast_div = false; 1883 break; 1884 case AR5K_ANTMODE_SECTOR_STA: 1885 tx_ant = 1; /* variable */ 1886 use_def_for_tx = true; 1887 update_def_on_tx = false; 1888 use_def_for_rts = true; 1889 use_def_for_sg = false; 1890 fast_div = true; 1891 break; 1892 case AR5K_ANTMODE_DEBUG: 1893 def_ant = 1; 1894 tx_ant = 2; 1895 use_def_for_tx = false; 1896 update_def_on_tx = false; 1897 use_def_for_rts = false; 1898 use_def_for_sg = false; 1899 fast_div = false; 1900 break; 1901 default: 1902 return; 1903 } 1904 1905 ah->ah_tx_ant = tx_ant; 1906 ah->ah_ant_mode = ant_mode; 1907 ah->ah_def_ant = def_ant; 1908 1909 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 1910 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 1911 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 1912 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 1913 1914 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 1915 1916 if (sta_id1) 1917 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 1918 1919 /* Note: set diversity before default antenna 1920 * because it won't work correctly */ 1921 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 1922 ath5k_hw_set_def_antenna(ah, def_ant); 1923} 1924 1925 1926/****************\ 1927* TX power setup * 1928\****************/ 1929 1930/* 1931 * Helper functions 1932 */ 1933 1934/* 1935 * Do linear interpolation between two given (x, y) points 1936 */ 1937static s16 1938ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 1939 s16 y_left, s16 y_right) 1940{ 1941 s16 ratio, result; 1942 1943 /* Avoid divide by zero and skip interpolation 1944 * if we have the same point */ 1945 if ((x_left == x_right) || (y_left == y_right)) 1946 return y_left; 1947 1948 /* 1949 * Since we use ints and not fps, we need to scale up in 1950 * order to get a sane ratio value (or else we 'll eg. get 1951 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 1952 * to have some accuracy both for 0.5 and 0.25 steps. 1953 */ 1954 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 1955 1956 /* Now scale down to be in range */ 1957 result = y_left + (ratio * (target - x_left) / 100); 1958 1959 return result; 1960} 1961 1962/* 1963 * Find vertical boundary (min pwr) for the linear PCDAC curve. 1964 * 1965 * Since we have the top of the curve and we draw the line below 1966 * until we reach 1 (1 pcdac step) we need to know which point 1967 * (x value) that is so that we don't go below y axis and have negative 1968 * pcdac values when creating the curve, or fill the table with zeroes. 1969 */ 1970static s16 1971ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 1972 const s16 *pwrL, const s16 *pwrR) 1973{ 1974 s8 tmp; 1975 s16 min_pwrL, min_pwrR; 1976 s16 pwr_i; 1977 1978 /* Some vendors write the same pcdac value twice !!! */ 1979 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 1980 return max(pwrL[0], pwrR[0]); 1981 1982 if (pwrL[0] == pwrL[1]) 1983 min_pwrL = pwrL[0]; 1984 else { 1985 pwr_i = pwrL[0]; 1986 do { 1987 pwr_i--; 1988 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1989 pwrL[0], pwrL[1], 1990 stepL[0], stepL[1]); 1991 } while (tmp > 1); 1992 1993 min_pwrL = pwr_i; 1994 } 1995 1996 if (pwrR[0] == pwrR[1]) 1997 min_pwrR = pwrR[0]; 1998 else { 1999 pwr_i = pwrR[0]; 2000 do { 2001 pwr_i--; 2002 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2003 pwrR[0], pwrR[1], 2004 stepR[0], stepR[1]); 2005 } while (tmp > 1); 2006 2007 min_pwrR = pwr_i; 2008 } 2009 2010 /* Keep the right boundary so that it works for both curves */ 2011 return max(min_pwrL, min_pwrR); 2012} 2013 2014/* 2015 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2016 * Power to PCDAC curve. 2017 * 2018 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2019 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2020 * PCDAC/PDADC step for each curve is 64 but we can write more than 2021 * one curves on hw so we can go up to 128 (which is the max step we 2022 * can write on the final table). 2023 * 2024 * We write y values (PCDAC/PDADC steps) on hw. 2025 */ 2026static void 2027ath5k_create_power_curve(s16 pmin, s16 pmax, 2028 const s16 *pwr, const u8 *vpd, 2029 u8 num_points, 2030 u8 *vpd_table, u8 type) 2031{ 2032 u8 idx[2] = { 0, 1 }; 2033 s16 pwr_i = 2*pmin; 2034 int i; 2035 2036 if (num_points < 2) 2037 return; 2038 2039 /* We want the whole line, so adjust boundaries 2040 * to cover the entire power range. Note that 2041 * power values are already 0.25dB so no need 2042 * to multiply pwr_i by 2 */ 2043 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2044 pwr_i = pmin; 2045 pmin = 0; 2046 pmax = 63; 2047 } 2048 2049 /* Find surrounding turning points (TPs) 2050 * and interpolate between them */ 2051 for (i = 0; (i <= (u16) (pmax - pmin)) && 2052 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2053 2054 /* We passed the right TP, move to the next set of TPs 2055 * if we pass the last TP, extrapolate above using the last 2056 * two TPs for ratio */ 2057 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2058 idx[0]++; 2059 idx[1]++; 2060 } 2061 2062 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2063 pwr[idx[0]], pwr[idx[1]], 2064 vpd[idx[0]], vpd[idx[1]]); 2065 2066 /* Increase by 0.5dB 2067 * (0.25 dB units) */ 2068 pwr_i += 2; 2069 } 2070} 2071 2072/* 2073 * Get the surrounding per-channel power calibration piers 2074 * for a given frequency so that we can interpolate between 2075 * them and come up with an apropriate dataset for our current 2076 * channel. 2077 */ 2078static void 2079ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2080 struct ieee80211_channel *channel, 2081 struct ath5k_chan_pcal_info **pcinfo_l, 2082 struct ath5k_chan_pcal_info **pcinfo_r) 2083{ 2084 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2085 struct ath5k_chan_pcal_info *pcinfo; 2086 u8 idx_l, idx_r; 2087 u8 mode, max, i; 2088 u32 target = channel->center_freq; 2089 2090 idx_l = 0; 2091 idx_r = 0; 2092 2093 if (!(channel->hw_value & CHANNEL_OFDM)) { 2094 pcinfo = ee->ee_pwr_cal_b; 2095 mode = AR5K_EEPROM_MODE_11B; 2096 } else if (channel->hw_value & CHANNEL_2GHZ) { 2097 pcinfo = ee->ee_pwr_cal_g; 2098 mode = AR5K_EEPROM_MODE_11G; 2099 } else { 2100 pcinfo = ee->ee_pwr_cal_a; 2101 mode = AR5K_EEPROM_MODE_11A; 2102 } 2103 max = ee->ee_n_piers[mode] - 1; 2104 2105 /* Frequency is below our calibrated 2106 * range. Use the lowest power curve 2107 * we have */ 2108 if (target < pcinfo[0].freq) { 2109 idx_l = idx_r = 0; 2110 goto done; 2111 } 2112 2113 /* Frequency is above our calibrated 2114 * range. Use the highest power curve 2115 * we have */ 2116 if (target > pcinfo[max].freq) { 2117 idx_l = idx_r = max; 2118 goto done; 2119 } 2120 2121 /* Frequency is inside our calibrated 2122 * channel range. Pick the surrounding 2123 * calibration piers so that we can 2124 * interpolate */ 2125 for (i = 0; i <= max; i++) { 2126 2127 /* Frequency matches one of our calibration 2128 * piers, no need to interpolate, just use 2129 * that calibration pier */ 2130 if (pcinfo[i].freq == target) { 2131 idx_l = idx_r = i; 2132 goto done; 2133 } 2134 2135 /* We found a calibration pier that's above 2136 * frequency, use this pier and the previous 2137 * one to interpolate */ 2138 if (target < pcinfo[i].freq) { 2139 idx_r = i; 2140 idx_l = idx_r - 1; 2141 goto done; 2142 } 2143 } 2144 2145done: 2146 *pcinfo_l = &pcinfo[idx_l]; 2147 *pcinfo_r = &pcinfo[idx_r]; 2148} 2149 2150/* 2151 * Get the surrounding per-rate power calibration data 2152 * for a given frequency and interpolate between power 2153 * values to set max target power supported by hw for 2154 * each rate. 2155 */ 2156static void 2157ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2158 struct ieee80211_channel *channel, 2159 struct ath5k_rate_pcal_info *rates) 2160{ 2161 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2162 struct ath5k_rate_pcal_info *rpinfo; 2163 u8 idx_l, idx_r; 2164 u8 mode, max, i; 2165 u32 target = channel->center_freq; 2166 2167 idx_l = 0; 2168 idx_r = 0; 2169 2170 if (!(channel->hw_value & CHANNEL_OFDM)) { 2171 rpinfo = ee->ee_rate_tpwr_b; 2172 mode = AR5K_EEPROM_MODE_11B; 2173 } else if (channel->hw_value & CHANNEL_2GHZ) { 2174 rpinfo = ee->ee_rate_tpwr_g; 2175 mode = AR5K_EEPROM_MODE_11G; 2176 } else { 2177 rpinfo = ee->ee_rate_tpwr_a; 2178 mode = AR5K_EEPROM_MODE_11A; 2179 } 2180 max = ee->ee_rate_target_pwr_num[mode] - 1; 2181 2182 /* Get the surrounding calibration 2183 * piers - same as above */ 2184 if (target < rpinfo[0].freq) { 2185 idx_l = idx_r = 0; 2186 goto done; 2187 } 2188 2189 if (target > rpinfo[max].freq) { 2190 idx_l = idx_r = max; 2191 goto done; 2192 } 2193 2194 for (i = 0; i <= max; i++) { 2195 2196 if (rpinfo[i].freq == target) { 2197 idx_l = idx_r = i; 2198 goto done; 2199 } 2200 2201 if (target < rpinfo[i].freq) { 2202 idx_r = i; 2203 idx_l = idx_r - 1; 2204 goto done; 2205 } 2206 } 2207 2208done: 2209 /* Now interpolate power value, based on the frequency */ 2210 rates->freq = target; 2211 2212 rates->target_power_6to24 = 2213 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2214 rpinfo[idx_r].freq, 2215 rpinfo[idx_l].target_power_6to24, 2216 rpinfo[idx_r].target_power_6to24); 2217 2218 rates->target_power_36 = 2219 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2220 rpinfo[idx_r].freq, 2221 rpinfo[idx_l].target_power_36, 2222 rpinfo[idx_r].target_power_36); 2223 2224 rates->target_power_48 = 2225 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2226 rpinfo[idx_r].freq, 2227 rpinfo[idx_l].target_power_48, 2228 rpinfo[idx_r].target_power_48); 2229 2230 rates->target_power_54 = 2231 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2232 rpinfo[idx_r].freq, 2233 rpinfo[idx_l].target_power_54, 2234 rpinfo[idx_r].target_power_54); 2235} 2236 2237/* 2238 * Get the max edge power for this channel if 2239 * we have such data from EEPROM's Conformance Test 2240 * Limits (CTL), and limit max power if needed. 2241 */ 2242static void 2243ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2244 struct ieee80211_channel *channel) 2245{ 2246 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2247 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2248 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2249 u8 *ctl_val = ee->ee_ctl; 2250 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2251 s16 edge_pwr = 0; 2252 u8 rep_idx; 2253 u8 i, ctl_mode; 2254 u8 ctl_idx = 0xFF; 2255 u32 target = channel->center_freq; 2256 2257 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2258 2259 switch (channel->hw_value & CHANNEL_MODES) { 2260 case CHANNEL_A: 2261 ctl_mode |= AR5K_CTL_11A; 2262 break; 2263 case CHANNEL_G: 2264 ctl_mode |= AR5K_CTL_11G; 2265 break; 2266 case CHANNEL_B: 2267 ctl_mode |= AR5K_CTL_11B; 2268 break; 2269 case CHANNEL_T: 2270 ctl_mode |= AR5K_CTL_TURBO; 2271 break; 2272 case CHANNEL_TG: 2273 ctl_mode |= AR5K_CTL_TURBOG; 2274 break; 2275 case CHANNEL_XR: 2276 /* Fall through */ 2277 default: 2278 return; 2279 } 2280 2281 for (i = 0; i < ee->ee_ctls; i++) { 2282 if (ctl_val[i] == ctl_mode) { 2283 ctl_idx = i; 2284 break; 2285 } 2286 } 2287 2288 /* If we have a CTL dataset available grab it and find the 2289 * edge power for our frequency */ 2290 if (ctl_idx == 0xFF) 2291 return; 2292 2293 /* Edge powers are sorted by frequency from lower 2294 * to higher. Each CTL corresponds to 8 edge power 2295 * measurements. */ 2296 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2297 2298 /* Don't do boundaries check because we 2299 * might have more that one bands defined 2300 * for this mode */ 2301 2302 /* Get the edge power that's closer to our 2303 * frequency */ 2304 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2305 rep_idx += i; 2306 if (target <= rep[rep_idx].freq) 2307 edge_pwr = (s16) rep[rep_idx].edge; 2308 } 2309 2310 if (edge_pwr) 2311 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2312} 2313 2314 2315/* 2316 * Power to PCDAC table functions 2317 */ 2318 2319/* 2320 * Fill Power to PCDAC table on RF5111 2321 * 2322 * No further processing is needed for RF5111, the only thing we have to 2323 * do is fill the values below and above calibration range since eeprom data 2324 * may not cover the entire PCDAC table. 2325 */ 2326static void 2327ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2328 s16 *table_max) 2329{ 2330 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2331 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2332 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2333 s16 min_pwr, max_pwr; 2334 2335 /* Get table boundaries */ 2336 min_pwr = table_min[0]; 2337 pcdac_0 = pcdac_tmp[0]; 2338 2339 max_pwr = table_max[0]; 2340 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2341 2342 /* Extrapolate below minimum using pcdac_0 */ 2343 pcdac_i = 0; 2344 for (i = 0; i < min_pwr; i++) 2345 pcdac_out[pcdac_i++] = pcdac_0; 2346 2347 /* Copy values from pcdac_tmp */ 2348 pwr_idx = min_pwr; 2349 for (i = 0 ; pwr_idx <= max_pwr && 2350 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2351 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2352 pwr_idx++; 2353 } 2354 2355 /* Extrapolate above maximum */ 2356 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2357 pcdac_out[pcdac_i++] = pcdac_n; 2358 2359} 2360 2361/* 2362 * Combine available XPD Curves and fill Linear Power to PCDAC table 2363 * on RF5112 2364 * 2365 * RFX112 can have up to 2 curves (one for low txpower range and one for 2366 * higher txpower range). We need to put them both on pcdac_out and place 2367 * them in the correct location. In case we only have one curve available 2368 * just fit it on pcdac_out (it's supposed to cover the entire range of 2369 * available pwr levels since it's always the higher power curve). Extrapolate 2370 * below and above final table if needed. 2371 */ 2372static void 2373ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2374 s16 *table_max, u8 pdcurves) 2375{ 2376 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2377 u8 *pcdac_low_pwr; 2378 u8 *pcdac_high_pwr; 2379 u8 *pcdac_tmp; 2380 u8 pwr; 2381 s16 max_pwr_idx; 2382 s16 min_pwr_idx; 2383 s16 mid_pwr_idx = 0; 2384 /* Edge flag turs on the 7nth bit on the PCDAC 2385 * to delcare the higher power curve (force values 2386 * to be greater than 64). If we only have one curve 2387 * we don't need to set this, if we have 2 curves and 2388 * fill the table backwards this can also be used to 2389 * switch from higher power curve to lower power curve */ 2390 u8 edge_flag; 2391 int i; 2392 2393 /* When we have only one curve available 2394 * that's the higher power curve. If we have 2395 * two curves the first is the high power curve 2396 * and the next is the low power curve. */ 2397 if (pdcurves > 1) { 2398 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2399 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2400 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2401 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2402 2403 /* If table size goes beyond 31.5dB, keep the 2404 * upper 31.5dB range when setting tx power. 2405 * Note: 126 = 31.5 dB in quarter dB steps */ 2406 if (table_max[0] - table_min[1] > 126) 2407 min_pwr_idx = table_max[0] - 126; 2408 else 2409 min_pwr_idx = table_min[1]; 2410 2411 /* Since we fill table backwards 2412 * start from high power curve */ 2413 pcdac_tmp = pcdac_high_pwr; 2414 2415 edge_flag = 0x40; 2416 } else { 2417 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2418 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2419 min_pwr_idx = table_min[0]; 2420 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2421 pcdac_tmp = pcdac_high_pwr; 2422 edge_flag = 0; 2423 } 2424 2425 /* This is used when setting tx power*/ 2426 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2427 2428 /* Fill Power to PCDAC table backwards */ 2429 pwr = max_pwr_idx; 2430 for (i = 63; i >= 0; i--) { 2431 /* Entering lower power range, reset 2432 * edge flag and set pcdac_tmp to lower 2433 * power curve.*/ 2434 if (edge_flag == 0x40 && 2435 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2436 edge_flag = 0x00; 2437 pcdac_tmp = pcdac_low_pwr; 2438 pwr = mid_pwr_idx/2; 2439 } 2440 2441 /* Don't go below 1, extrapolate below if we have 2442 * already swithced to the lower power curve -or 2443 * we only have one curve and edge_flag is zero 2444 * anyway */ 2445 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2446 while (i >= 0) { 2447 pcdac_out[i] = pcdac_out[i + 1]; 2448 i--; 2449 } 2450 break; 2451 } 2452 2453 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2454 2455 /* Extrapolate above if pcdac is greater than 2456 * 126 -this can happen because we OR pcdac_out 2457 * value with edge_flag on high power curve */ 2458 if (pcdac_out[i] > 126) 2459 pcdac_out[i] = 126; 2460 2461 /* Decrease by a 0.5dB step */ 2462 pwr--; 2463 } 2464} 2465 2466/* Write PCDAC values on hw */ 2467static void 2468ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2469{ 2470 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2471 int i; 2472 2473 /* 2474 * Write TX power values 2475 */ 2476 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2477 ath5k_hw_reg_write(ah, 2478 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2479 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2480 AR5K_PHY_PCDAC_TXPOWER(i)); 2481 } 2482} 2483 2484 2485/* 2486 * Power to PDADC table functions 2487 */ 2488 2489/* 2490 * Set the gain boundaries and create final Power to PDADC table 2491 * 2492 * We can have up to 4 pd curves, we need to do a simmilar process 2493 * as we do for RF5112. This time we don't have an edge_flag but we 2494 * set the gain boundaries on a separate register. 2495 */ 2496static void 2497ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2498 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2499{ 2500 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2501 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2502 u8 *pdadc_tmp; 2503 s16 pdadc_0; 2504 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2505 u8 pd_gain_overlap; 2506 2507 /* Note: Register value is initialized on initvals 2508 * there is no feedback from hw. 2509 * XXX: What about pd_gain_overlap from EEPROM ? */ 2510 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2511 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2512 2513 /* Create final PDADC table */ 2514 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2515 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2516 2517 if (pdg == pdcurves - 1) 2518 /* 2 dB boundary stretch for last 2519 * (higher power) curve */ 2520 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2521 else 2522 /* Set gain boundary in the middle 2523 * between this curve and the next one */ 2524 gain_boundaries[pdg] = 2525 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2526 2527 /* Sanity check in case our 2 db stretch got out of 2528 * range. */ 2529 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2530 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2531 2532 /* For the first curve (lower power) 2533 * start from 0 dB */ 2534 if (pdg == 0) 2535 pdadc_0 = 0; 2536 else 2537 /* For the other curves use the gain overlap */ 2538 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2539 pd_gain_overlap; 2540 2541 /* Force each power step to be at least 0.5 dB */ 2542 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2543 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2544 else 2545 pwr_step = 1; 2546 2547 /* If pdadc_0 is negative, we need to extrapolate 2548 * below this pdgain by a number of pwr_steps */ 2549 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2550 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2551 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2552 pdadc_0++; 2553 } 2554 2555 /* Set last pwr level, using gain boundaries */ 2556 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2557 /* Limit it to be inside pwr range */ 2558 table_size = pwr_max[pdg] - pwr_min[pdg]; 2559 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2560 2561 /* Fill pdadc_out table */ 2562 while (pdadc_0 < max_idx && pdadc_i < 128) 2563 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2564 2565 /* Need to extrapolate above this pdgain? */ 2566 if (pdadc_n <= max_idx) 2567 continue; 2568 2569 /* Force each power step to be at least 0.5 dB */ 2570 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2571 pwr_step = pdadc_tmp[table_size - 1] - 2572 pdadc_tmp[table_size - 2]; 2573 else 2574 pwr_step = 1; 2575 2576 /* Extrapolate above */ 2577 while ((pdadc_0 < (s16) pdadc_n) && 2578 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2579 s16 tmp = pdadc_tmp[table_size - 1] + 2580 (pdadc_0 - max_idx) * pwr_step; 2581 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2582 pdadc_0++; 2583 } 2584 } 2585 2586 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2587 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2588 pdg++; 2589 } 2590 2591 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2592 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2593 pdadc_i++; 2594 } 2595 2596 /* Set gain boundaries */ 2597 ath5k_hw_reg_write(ah, 2598 AR5K_REG_SM(pd_gain_overlap, 2599 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2600 AR5K_REG_SM(gain_boundaries[0], 2601 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2602 AR5K_REG_SM(gain_boundaries[1], 2603 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2604 AR5K_REG_SM(gain_boundaries[2], 2605 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2606 AR5K_REG_SM(gain_boundaries[3], 2607 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2608 AR5K_PHY_TPC_RG5); 2609 2610 /* Used for setting rate power table */ 2611 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2612 2613} 2614 2615/* Write PDADC values on hw */ 2616static void 2617ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2618 u8 pdcurves, u8 *pdg_to_idx) 2619{ 2620 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2621 u32 reg; 2622 u8 i; 2623 2624 /* Select the right pdgain curves */ 2625 2626 /* Clear current settings */ 2627 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2628 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2629 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2630 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2631 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2632 2633 /* 2634 * Use pd_gains curve from eeprom 2635 * 2636 * This overrides the default setting from initvals 2637 * in case some vendors (e.g. Zcomax) don't use the default 2638 * curves. If we don't honor their settings we 'll get a 2639 * 5dB (1 * gain overlap ?) drop. 2640 */ 2641 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2642 2643 switch (pdcurves) { 2644 case 3: 2645 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2646 /* Fall through */ 2647 case 2: 2648 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2649 /* Fall through */ 2650 case 1: 2651 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2652 break; 2653 } 2654 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2655 2656 /* 2657 * Write TX power values 2658 */ 2659 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2660 ath5k_hw_reg_write(ah, 2661 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2662 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2663 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2664 ((pdadc_out[4*i + 3] & 0xff) << 24), 2665 AR5K_PHY_PDADC_TXPOWER(i)); 2666 } 2667} 2668 2669 2670/* 2671 * Common code for PCDAC/PDADC tables 2672 */ 2673 2674/* 2675 * This is the main function that uses all of the above 2676 * to set PCDAC/PDADC table on hw for the current channel. 2677 * This table is used for tx power calibration on the basband, 2678 * without it we get weird tx power levels and in some cases 2679 * distorted spectral mask 2680 */ 2681static int 2682ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2683 struct ieee80211_channel *channel, 2684 u8 ee_mode, u8 type) 2685{ 2686 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2687 struct ath5k_chan_pcal_info *pcinfo_L; 2688 struct ath5k_chan_pcal_info *pcinfo_R; 2689 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2690 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2691 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2692 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2693 u8 *tmpL; 2694 u8 *tmpR; 2695 u32 target = channel->center_freq; 2696 int pdg, i; 2697 2698 /* Get surounding freq piers for this channel */ 2699 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2700 &pcinfo_L, 2701 &pcinfo_R); 2702 2703 /* Loop over pd gain curves on 2704 * surounding freq piers by index */ 2705 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2706 2707 /* Fill curves in reverse order 2708 * from lower power (max gain) 2709 * to higher power. Use curve -> idx 2710 * backmapping we did on eeprom init */ 2711 u8 idx = pdg_curve_to_idx[pdg]; 2712 2713 /* Grab the needed curves by index */ 2714 pdg_L = &pcinfo_L->pd_curves[idx]; 2715 pdg_R = &pcinfo_R->pd_curves[idx]; 2716 2717 /* Initialize the temp tables */ 2718 tmpL = ah->ah_txpower.tmpL[pdg]; 2719 tmpR = ah->ah_txpower.tmpR[pdg]; 2720 2721 /* Set curve's x boundaries and create 2722 * curves so that they cover the same 2723 * range (if we don't do that one table 2724 * will have values on some range and the 2725 * other one won't have any so interpolation 2726 * will fail) */ 2727 table_min[pdg] = min(pdg_L->pd_pwr[0], 2728 pdg_R->pd_pwr[0]) / 2; 2729 2730 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2731 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2732 2733 /* Now create the curves on surrounding channels 2734 * and interpolate if needed to get the final 2735 * curve for this gain on this channel */ 2736 switch (type) { 2737 case AR5K_PWRTABLE_LINEAR_PCDAC: 2738 /* Override min/max so that we don't loose 2739 * accuracy (don't divide by 2) */ 2740 table_min[pdg] = min(pdg_L->pd_pwr[0], 2741 pdg_R->pd_pwr[0]); 2742 2743 table_max[pdg] = 2744 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2745 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2746 2747 /* Override minimum so that we don't get 2748 * out of bounds while extrapolating 2749 * below. Don't do this when we have 2 2750 * curves and we are on the high power curve 2751 * because table_min is ok in this case */ 2752 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2753 2754 table_min[pdg] = 2755 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2756 pdg_R->pd_step, 2757 pdg_L->pd_pwr, 2758 pdg_R->pd_pwr); 2759 2760 /* Don't go too low because we will 2761 * miss the upper part of the curve. 2762 * Note: 126 = 31.5dB (max power supported) 2763 * in 0.25dB units */ 2764 if (table_max[pdg] - table_min[pdg] > 126) 2765 table_min[pdg] = table_max[pdg] - 126; 2766 } 2767 2768 /* Fall through */ 2769 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2770 case AR5K_PWRTABLE_PWR_TO_PDADC: 2771 2772 ath5k_create_power_curve(table_min[pdg], 2773 table_max[pdg], 2774 pdg_L->pd_pwr, 2775 pdg_L->pd_step, 2776 pdg_L->pd_points, tmpL, type); 2777 2778 /* We are in a calibration 2779 * pier, no need to interpolate 2780 * between freq piers */ 2781 if (pcinfo_L == pcinfo_R) 2782 continue; 2783 2784 ath5k_create_power_curve(table_min[pdg], 2785 table_max[pdg], 2786 pdg_R->pd_pwr, 2787 pdg_R->pd_step, 2788 pdg_R->pd_points, tmpR, type); 2789 break; 2790 default: 2791 return -EINVAL; 2792 } 2793 2794 /* Interpolate between curves 2795 * of surounding freq piers to 2796 * get the final curve for this 2797 * pd gain. Re-use tmpL for interpolation 2798 * output */ 2799 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2800 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2801 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2802 (s16) pcinfo_L->freq, 2803 (s16) pcinfo_R->freq, 2804 (s16) tmpL[i], 2805 (s16) tmpR[i]); 2806 } 2807 } 2808 2809 /* Now we have a set of curves for this 2810 * channel on tmpL (x range is table_max - table_min 2811 * and y values are tmpL[pdg][]) sorted in the same 2812 * order as EEPROM (because we've used the backmapping). 2813 * So for RF5112 it's from higher power to lower power 2814 * and for RF2413 it's from lower power to higher power. 2815 * For RF5111 we only have one curve. */ 2816 2817 /* Fill min and max power levels for this 2818 * channel by interpolating the values on 2819 * surounding channels to complete the dataset */ 2820 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2821 (s16) pcinfo_L->freq, 2822 (s16) pcinfo_R->freq, 2823 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2824 2825 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2826 (s16) pcinfo_L->freq, 2827 (s16) pcinfo_R->freq, 2828 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2829 2830 /* We are ready to go, fill PCDAC/PDADC 2831 * table and write settings on hardware */ 2832 switch (type) { 2833 case AR5K_PWRTABLE_LINEAR_PCDAC: 2834 /* For RF5112 we can have one or two curves 2835 * and each curve covers a certain power lvl 2836 * range so we need to do some more processing */ 2837 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2838 ee->ee_pd_gains[ee_mode]); 2839 2840 /* Set txp.offset so that we can 2841 * match max power value with max 2842 * table index */ 2843 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2844 2845 /* Write settings on hw */ 2846 ath5k_setup_pcdac_table(ah); 2847 break; 2848 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2849 /* We are done for RF5111 since it has only 2850 * one curve, just fit the curve on the table */ 2851 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2852 2853 /* No rate powertable adjustment for RF5111 */ 2854 ah->ah_txpower.txp_min_idx = 0; 2855 ah->ah_txpower.txp_offset = 0; 2856 2857 /* Write settings on hw */ 2858 ath5k_setup_pcdac_table(ah); 2859 break; 2860 case AR5K_PWRTABLE_PWR_TO_PDADC: 2861 /* Set PDADC boundaries and fill 2862 * final PDADC table */ 2863 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2864 ee->ee_pd_gains[ee_mode]); 2865 2866 /* Write settings on hw */ 2867 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2868 2869 /* Set txp.offset, note that table_min 2870 * can be negative */ 2871 ah->ah_txpower.txp_offset = table_min[0]; 2872 break; 2873 default: 2874 return -EINVAL; 2875 } 2876 2877 return 0; 2878} 2879 2880 2881/* 2882 * Per-rate tx power setting 2883 * 2884 * This is the code that sets the desired tx power (below 2885 * maximum) on hw for each rate (we also have TPC that sets 2886 * power per packet). We do that by providing an index on the 2887 * PCDAC/PDADC table we set up. 2888 */ 2889 2890/* 2891 * Set rate power table 2892 * 2893 * For now we only limit txpower based on maximum tx power 2894 * supported by hw (what's inside rate_info). We need to limit 2895 * this even more, based on regulatory domain etc. 2896 * 2897 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2898 * and is indexed as follows: 2899 * rates[0] - rates[7] -> OFDM rates 2900 * rates[8] - rates[14] -> CCK rates 2901 * rates[15] -> XR rates (they all have the same power) 2902 */ 2903static void 2904ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2905 struct ath5k_rate_pcal_info *rate_info, 2906 u8 ee_mode) 2907{ 2908 unsigned int i; 2909 u16 *rates; 2910 2911 /* max_pwr is power level we got from driver/user in 0.5dB 2912 * units, switch to 0.25dB units so we can compare */ 2913 max_pwr *= 2; 2914 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2915 2916 /* apply rate limits */ 2917 rates = ah->ah_txpower.txp_rates_power_table; 2918 2919 /* OFDM rates 6 to 24Mb/s */ 2920 for (i = 0; i < 5; i++) 2921 rates[i] = min(max_pwr, rate_info->target_power_6to24); 2922 2923 /* Rest OFDM rates */ 2924 rates[5] = min(rates[0], rate_info->target_power_36); 2925 rates[6] = min(rates[0], rate_info->target_power_48); 2926 rates[7] = min(rates[0], rate_info->target_power_54); 2927 2928 /* CCK rates */ 2929 /* 1L */ 2930 rates[8] = min(rates[0], rate_info->target_power_6to24); 2931 /* 2L */ 2932 rates[9] = min(rates[0], rate_info->target_power_36); 2933 /* 2S */ 2934 rates[10] = min(rates[0], rate_info->target_power_36); 2935 /* 5L */ 2936 rates[11] = min(rates[0], rate_info->target_power_48); 2937 /* 5S */ 2938 rates[12] = min(rates[0], rate_info->target_power_48); 2939 /* 11L */ 2940 rates[13] = min(rates[0], rate_info->target_power_54); 2941 /* 11S */ 2942 rates[14] = min(rates[0], rate_info->target_power_54); 2943 2944 /* XR rates */ 2945 rates[15] = min(rates[0], rate_info->target_power_6to24); 2946 2947 /* CCK rates have different peak to average ratio 2948 * so we have to tweak their power so that gainf 2949 * correction works ok. For this we use OFDM to 2950 * CCK delta from eeprom */ 2951 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 2952 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 2953 for (i = 8; i <= 15; i++) 2954 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 2955 2956 /* Now that we have all rates setup use table offset to 2957 * match the power range set by user with the power indices 2958 * on PCDAC/PDADC table */ 2959 for (i = 0; i < 16; i++) { 2960 rates[i] += ah->ah_txpower.txp_offset; 2961 /* Don't get out of bounds */ 2962 if (rates[i] > 63) 2963 rates[i] = 63; 2964 } 2965 2966 /* Min/max in 0.25dB units */ 2967 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 2968 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 2969 ah->ah_txpower.txp_ofdm = rates[7]; 2970} 2971 2972 2973/* 2974 * Set transmition power 2975 */ 2976int 2977ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 2978 u8 ee_mode, u8 txpower) 2979{ 2980 struct ath5k_rate_pcal_info rate_info; 2981 u8 type; 2982 int ret; 2983 2984 ATH5K_TRACE(ah->ah_sc); 2985 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2986 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 2987 return -EINVAL; 2988 } 2989 2990 /* Reset TX power values */ 2991 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 2992 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 2993 ah->ah_txpower.txp_min_pwr = 0; 2994 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 2995 2996 /* Initialize TX power table */ 2997 switch (ah->ah_radio) { 2998 case AR5K_RF5111: 2999 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3000 break; 3001 case AR5K_RF5112: 3002 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3003 break; 3004 case AR5K_RF2413: 3005 case AR5K_RF5413: 3006 case AR5K_RF2316: 3007 case AR5K_RF2317: 3008 case AR5K_RF2425: 3009 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3010 break; 3011 default: 3012 return -EINVAL; 3013 } 3014 3015 /* FIXME: Only on channel/mode change */ 3016 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 3017 if (ret) 3018 return ret; 3019 3020 /* Limit max power if we have a CTL available */ 3021 ath5k_get_max_ctl_power(ah, channel); 3022 3023 /* FIXME: Tx power limit for this regdomain 3024 * XXX: Mac80211/CRDA will do that anyway ? */ 3025 3026 /* FIXME: Antenna reduction stuff */ 3027 3028 /* FIXME: Limit power on turbo modes */ 3029 3030 /* FIXME: TPC scale reduction */ 3031 3032 /* Get surounding channels for per-rate power table 3033 * calibration */ 3034 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3035 3036 /* Setup rate power table */ 3037 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3038 3039 /* Write rate power table on hw */ 3040 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3041 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3042 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3043 3044 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3045 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3046 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3047 3048 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3049 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3050 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3051 3052 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3053 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3054 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3055 3056 /* FIXME: TPC support */ 3057 if (ah->ah_txpower.txp_tpc) { 3058 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3059 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3060 3061 ath5k_hw_reg_write(ah, 3062 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3063 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3064 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3065 AR5K_TPC); 3066 } else { 3067 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3068 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3069 } 3070 3071 return 0; 3072} 3073 3074int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3075{ 3076 /*Just a try M.F.*/ 3077 struct ieee80211_channel *channel = ah->ah_current_channel; 3078 u8 ee_mode; 3079 3080 ATH5K_TRACE(ah->ah_sc); 3081 3082 switch (channel->hw_value & CHANNEL_MODES) { 3083 case CHANNEL_A: 3084 case CHANNEL_T: 3085 case CHANNEL_XR: 3086 ee_mode = AR5K_EEPROM_MODE_11A; 3087 break; 3088 case CHANNEL_G: 3089 case CHANNEL_TG: 3090 ee_mode = AR5K_EEPROM_MODE_11G; 3091 break; 3092 case CHANNEL_B: 3093 ee_mode = AR5K_EEPROM_MODE_11B; 3094 break; 3095 default: 3096 ATH5K_ERR(ah->ah_sc, 3097 "invalid channel: %d\n", channel->center_freq); 3098 return -EINVAL; 3099 } 3100 3101 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3102 "changing txpower to %d\n", txpower); 3103 3104 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3105} 3106