phy.c revision ace5d5de6bbaff00d3b5dd7ea8f160b570fdb726
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24 25#include "ath5k.h" 26#include "reg.h" 27#include "base.h" 28#include "rfbuffer.h" 29#include "rfgain.h" 30 31/* 32 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 33 */ 34static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 35 const struct ath5k_rf_reg *rf_regs, 36 u32 val, u8 reg_id, bool set) 37{ 38 const struct ath5k_rf_reg *rfreg = NULL; 39 u8 offset, bank, num_bits, col, position; 40 u16 entry; 41 u32 mask, data, last_bit, bits_shifted, first_bit; 42 u32 *rfb; 43 s32 bits_left; 44 int i; 45 46 data = 0; 47 rfb = ah->ah_rf_banks; 48 49 for (i = 0; i < ah->ah_rf_regs_count; i++) { 50 if (rf_regs[i].index == reg_id) { 51 rfreg = &rf_regs[i]; 52 break; 53 } 54 } 55 56 if (rfb == NULL || rfreg == NULL) { 57 ATH5K_PRINTF("Rf register not found!\n"); 58 /* should not happen */ 59 return 0; 60 } 61 62 bank = rfreg->bank; 63 num_bits = rfreg->field.len; 64 first_bit = rfreg->field.pos; 65 col = rfreg->field.col; 66 67 /* first_bit is an offset from bank's 68 * start. Since we have all banks on 69 * the same array, we use this offset 70 * to mark each bank's start */ 71 offset = ah->ah_offset[bank]; 72 73 /* Boundary check */ 74 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 75 ATH5K_PRINTF("invalid values at offset %u\n", offset); 76 return 0; 77 } 78 79 entry = ((first_bit - 1) / 8) + offset; 80 position = (first_bit - 1) % 8; 81 82 if (set) 83 data = ath5k_hw_bitswap(val, num_bits); 84 85 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 86 position = 0, entry++) { 87 88 last_bit = (position + bits_left > 8) ? 8 : 89 position + bits_left; 90 91 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 92 (col * 8); 93 94 if (set) { 95 rfb[entry] &= ~mask; 96 rfb[entry] |= ((data << position) << (col * 8)) & mask; 97 data >>= (8 - position); 98 } else { 99 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 100 << bits_shifted; 101 bits_shifted += last_bit - position; 102 } 103 104 bits_left -= 8 - position; 105 } 106 107 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 108 109 return data; 110} 111 112/**********************\ 113* RF Gain optimization * 114\**********************/ 115 116/* 117 * This code is used to optimize rf gain on different environments 118 * (temperature mostly) based on feedback from a power detector. 119 * 120 * It's only used on RF5111 and RF5112, later RF chips seem to have 121 * auto adjustment on hw -notice they have a much smaller BANK 7 and 122 * no gain optimization ladder-. 123 * 124 * For more infos check out this patent doc 125 * http://www.freepatentsonline.com/7400691.html 126 * 127 * This paper describes power drops as seen on the receiver due to 128 * probe packets 129 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 130 * %20of%20Power%20Control.pdf 131 * 132 * And this is the MadWiFi bug entry related to the above 133 * http://madwifi-project.org/ticket/1659 134 * with various measurements and diagrams 135 * 136 * TODO: Deal with power drops due to probes by setting an apropriate 137 * tx power on the probe packets ! Make this part of the calibration process. 138 */ 139 140/* Initialize ah_gain durring attach */ 141int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 142{ 143 /* Initialize the gain optimization values */ 144 switch (ah->ah_radio) { 145 case AR5K_RF5111: 146 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 147 ah->ah_gain.g_low = 20; 148 ah->ah_gain.g_high = 35; 149 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 150 break; 151 case AR5K_RF5112: 152 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 153 ah->ah_gain.g_low = 20; 154 ah->ah_gain.g_high = 85; 155 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 156 break; 157 default: 158 return -EINVAL; 159 } 160 161 return 0; 162} 163 164/* Schedule a gain probe check on the next transmited packet. 165 * That means our next packet is going to be sent with lower 166 * tx power and a Peak to Average Power Detector (PAPD) will try 167 * to measure the gain. 168 * 169 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 170 * just after we enable the probe so that we don't mess with 171 * standard traffic ? Maybe it's time to use sw interrupts and 172 * a probe tasklet !!! 173 */ 174static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 175{ 176 177 /* Skip if gain calibration is inactive or 178 * we already handle a probe request */ 179 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 180 return; 181 182 /* Send the packet with 2dB below max power as 183 * patent doc suggest */ 184 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 185 AR5K_PHY_PAPD_PROBE_TXPOWER) | 186 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 187 188 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 189 190} 191 192/* Calculate gain_F measurement correction 193 * based on the current step for RF5112 rev. 2 */ 194static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 195{ 196 u32 mix, step; 197 u32 *rf; 198 const struct ath5k_gain_opt *go; 199 const struct ath5k_gain_opt_step *g_step; 200 const struct ath5k_rf_reg *rf_regs; 201 202 /* Only RF5112 Rev. 2 supports it */ 203 if ((ah->ah_radio != AR5K_RF5112) || 204 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 205 return 0; 206 207 go = &rfgain_opt_5112; 208 rf_regs = rf_regs_5112a; 209 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 210 211 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 212 213 if (ah->ah_rf_banks == NULL) 214 return 0; 215 216 rf = ah->ah_rf_banks; 217 ah->ah_gain.g_f_corr = 0; 218 219 /* No VGA (Variable Gain Amplifier) override, skip */ 220 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 221 return 0; 222 223 /* Mix gain stepping */ 224 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 225 226 /* Mix gain override */ 227 mix = g_step->gos_param[0]; 228 229 switch (mix) { 230 case 3: 231 ah->ah_gain.g_f_corr = step * 2; 232 break; 233 case 2: 234 ah->ah_gain.g_f_corr = (step - 5) * 2; 235 break; 236 case 1: 237 ah->ah_gain.g_f_corr = step; 238 break; 239 default: 240 ah->ah_gain.g_f_corr = 0; 241 break; 242 } 243 244 return ah->ah_gain.g_f_corr; 245} 246 247/* Check if current gain_F measurement is in the range of our 248 * power detector windows. If we get a measurement outside range 249 * we know it's not accurate (detectors can't measure anything outside 250 * their detection window) so we must ignore it */ 251static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 252{ 253 const struct ath5k_rf_reg *rf_regs; 254 u32 step, mix_ovr, level[4]; 255 u32 *rf; 256 257 if (ah->ah_rf_banks == NULL) 258 return false; 259 260 rf = ah->ah_rf_banks; 261 262 if (ah->ah_radio == AR5K_RF5111) { 263 264 rf_regs = rf_regs_5111; 265 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 266 267 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 268 false); 269 270 level[0] = 0; 271 level[1] = (step == 63) ? 50 : step + 4; 272 level[2] = (step != 63) ? 64 : level[0]; 273 level[3] = level[2] + 50 ; 274 275 ah->ah_gain.g_high = level[3] - 276 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 277 ah->ah_gain.g_low = level[0] + 278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 279 } else { 280 281 rf_regs = rf_regs_5112; 282 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 283 284 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 285 false); 286 287 level[0] = level[2] = 0; 288 289 if (mix_ovr == 1) { 290 level[1] = level[3] = 83; 291 } else { 292 level[1] = level[3] = 107; 293 ah->ah_gain.g_high = 55; 294 } 295 } 296 297 return (ah->ah_gain.g_current >= level[0] && 298 ah->ah_gain.g_current <= level[1]) || 299 (ah->ah_gain.g_current >= level[2] && 300 ah->ah_gain.g_current <= level[3]); 301} 302 303/* Perform gain_F adjustment by choosing the right set 304 * of parameters from rf gain optimization ladder */ 305static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 306{ 307 const struct ath5k_gain_opt *go; 308 const struct ath5k_gain_opt_step *g_step; 309 int ret = 0; 310 311 switch (ah->ah_radio) { 312 case AR5K_RF5111: 313 go = &rfgain_opt_5111; 314 break; 315 case AR5K_RF5112: 316 go = &rfgain_opt_5112; 317 break; 318 default: 319 return 0; 320 } 321 322 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 323 324 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 325 326 /* Reached maximum */ 327 if (ah->ah_gain.g_step_idx == 0) 328 return -1; 329 330 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 331 ah->ah_gain.g_target >= ah->ah_gain.g_high && 332 ah->ah_gain.g_step_idx > 0; 333 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 334 ah->ah_gain.g_target -= 2 * 335 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 336 g_step->gos_gain); 337 338 ret = 1; 339 goto done; 340 } 341 342 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 343 344 /* Reached minimum */ 345 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 346 return -2; 347 348 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 349 ah->ah_gain.g_target <= ah->ah_gain.g_low && 350 ah->ah_gain.g_step_idx < go->go_steps_count-1; 351 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 352 ah->ah_gain.g_target -= 2 * 353 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 354 g_step->gos_gain); 355 356 ret = 2; 357 goto done; 358 } 359 360done: 361 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 362 "ret %d, gain step %u, current gain %u, target gain %u\n", 363 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 364 ah->ah_gain.g_target); 365 366 return ret; 367} 368 369/* Main callback for thermal rf gain calibration engine 370 * Check for a new gain reading and schedule an adjustment 371 * if needed. 372 * 373 * TODO: Use sw interrupt to schedule reset if gain_F needs 374 * adjustment */ 375enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 376{ 377 u32 data, type; 378 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 379 380 ATH5K_TRACE(ah->ah_sc); 381 382 if (ah->ah_rf_banks == NULL || 383 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 384 return AR5K_RFGAIN_INACTIVE; 385 386 /* No check requested, either engine is inactive 387 * or an adjustment is already requested */ 388 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 389 goto done; 390 391 /* Read the PAPD (Peak to Average Power Detector) 392 * register */ 393 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 394 395 /* No probe is scheduled, read gain_F measurement */ 396 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 397 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 398 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 399 400 /* If tx packet is CCK correct the gain_F measurement 401 * by cck ofdm gain delta */ 402 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 403 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 404 ah->ah_gain.g_current += 405 ee->ee_cck_ofdm_gain_delta; 406 else 407 ah->ah_gain.g_current += 408 AR5K_GAIN_CCK_PROBE_CORR; 409 } 410 411 /* Further correct gain_F measurement for 412 * RF5112A radios */ 413 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 414 ath5k_hw_rf_gainf_corr(ah); 415 ah->ah_gain.g_current = 416 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 417 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 418 0; 419 } 420 421 /* Check if measurement is ok and if we need 422 * to adjust gain, schedule a gain adjustment, 423 * else switch back to the acive state */ 424 if (ath5k_hw_rf_check_gainf_readback(ah) && 425 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 426 ath5k_hw_rf_gainf_adjust(ah)) { 427 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 428 } else { 429 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 430 } 431 } 432 433done: 434 return ah->ah_gain.g_state; 435} 436 437/* Write initial rf gain table to set the RF sensitivity 438 * this one works on all RF chips and has nothing to do 439 * with gain_F calibration */ 440int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 441{ 442 const struct ath5k_ini_rfgain *ath5k_rfg; 443 unsigned int i, size; 444 445 switch (ah->ah_radio) { 446 case AR5K_RF5111: 447 ath5k_rfg = rfgain_5111; 448 size = ARRAY_SIZE(rfgain_5111); 449 break; 450 case AR5K_RF5112: 451 ath5k_rfg = rfgain_5112; 452 size = ARRAY_SIZE(rfgain_5112); 453 break; 454 case AR5K_RF2413: 455 ath5k_rfg = rfgain_2413; 456 size = ARRAY_SIZE(rfgain_2413); 457 break; 458 case AR5K_RF2316: 459 ath5k_rfg = rfgain_2316; 460 size = ARRAY_SIZE(rfgain_2316); 461 break; 462 case AR5K_RF5413: 463 ath5k_rfg = rfgain_5413; 464 size = ARRAY_SIZE(rfgain_5413); 465 break; 466 case AR5K_RF2317: 467 case AR5K_RF2425: 468 ath5k_rfg = rfgain_2425; 469 size = ARRAY_SIZE(rfgain_2425); 470 break; 471 default: 472 return -EINVAL; 473 } 474 475 switch (freq) { 476 case AR5K_INI_RFGAIN_2GHZ: 477 case AR5K_INI_RFGAIN_5GHZ: 478 break; 479 default: 480 return -EINVAL; 481 } 482 483 for (i = 0; i < size; i++) { 484 AR5K_REG_WAIT(i); 485 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 486 (u32)ath5k_rfg[i].rfg_register); 487 } 488 489 return 0; 490} 491 492 493 494/********************\ 495* RF Registers setup * 496\********************/ 497 498 499/* 500 * Setup RF registers by writing rf buffer on hw 501 */ 502int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 503 unsigned int mode) 504{ 505 const struct ath5k_rf_reg *rf_regs; 506 const struct ath5k_ini_rfbuffer *ini_rfb; 507 const struct ath5k_gain_opt *go = NULL; 508 const struct ath5k_gain_opt_step *g_step; 509 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 510 u8 ee_mode = 0; 511 u32 *rfb; 512 int i, obdb = -1, bank = -1; 513 514 switch (ah->ah_radio) { 515 case AR5K_RF5111: 516 rf_regs = rf_regs_5111; 517 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 518 ini_rfb = rfb_5111; 519 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 520 go = &rfgain_opt_5111; 521 break; 522 case AR5K_RF5112: 523 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 524 rf_regs = rf_regs_5112a; 525 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 526 ini_rfb = rfb_5112a; 527 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 528 } else { 529 rf_regs = rf_regs_5112; 530 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 531 ini_rfb = rfb_5112; 532 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 533 } 534 go = &rfgain_opt_5112; 535 break; 536 case AR5K_RF2413: 537 rf_regs = rf_regs_2413; 538 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 539 ini_rfb = rfb_2413; 540 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 541 break; 542 case AR5K_RF2316: 543 rf_regs = rf_regs_2316; 544 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 545 ini_rfb = rfb_2316; 546 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 547 break; 548 case AR5K_RF5413: 549 rf_regs = rf_regs_5413; 550 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 551 ini_rfb = rfb_5413; 552 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 553 break; 554 case AR5K_RF2317: 555 rf_regs = rf_regs_2425; 556 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 557 ini_rfb = rfb_2317; 558 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 559 break; 560 case AR5K_RF2425: 561 rf_regs = rf_regs_2425; 562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 563 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 564 ini_rfb = rfb_2425; 565 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 566 } else { 567 ini_rfb = rfb_2417; 568 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 569 } 570 break; 571 default: 572 return -EINVAL; 573 } 574 575 /* If it's the first time we set rf buffer, allocate 576 * ah->ah_rf_banks based on ah->ah_rf_banks_size 577 * we set above */ 578 if (ah->ah_rf_banks == NULL) { 579 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 580 GFP_KERNEL); 581 if (ah->ah_rf_banks == NULL) { 582 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 583 return -ENOMEM; 584 } 585 } 586 587 /* Copy values to modify them */ 588 rfb = ah->ah_rf_banks; 589 590 for (i = 0; i < ah->ah_rf_banks_size; i++) { 591 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 592 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 593 return -EINVAL; 594 } 595 596 /* Bank changed, write down the offset */ 597 if (bank != ini_rfb[i].rfb_bank) { 598 bank = ini_rfb[i].rfb_bank; 599 ah->ah_offset[bank] = i; 600 } 601 602 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 603 } 604 605 /* Set Output and Driver bias current (OB/DB) */ 606 if (channel->hw_value & CHANNEL_2GHZ) { 607 608 if (channel->hw_value & CHANNEL_CCK) 609 ee_mode = AR5K_EEPROM_MODE_11B; 610 else 611 ee_mode = AR5K_EEPROM_MODE_11G; 612 613 /* For RF511X/RF211X combination we 614 * use b_OB and b_DB parameters stored 615 * in eeprom on ee->ee_ob[ee_mode][0] 616 * 617 * For all other chips we use OB/DB for 2Ghz 618 * stored in the b/g modal section just like 619 * 802.11a on ee->ee_ob[ee_mode][1] */ 620 if ((ah->ah_radio == AR5K_RF5111) || 621 (ah->ah_radio == AR5K_RF5112)) 622 obdb = 0; 623 else 624 obdb = 1; 625 626 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 627 AR5K_RF_OB_2GHZ, true); 628 629 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 630 AR5K_RF_DB_2GHZ, true); 631 632 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 633 } else if ((channel->hw_value & CHANNEL_5GHZ) || 634 (ah->ah_radio == AR5K_RF5111)) { 635 636 /* For 11a, Turbo and XR we need to choose 637 * OB/DB based on frequency range */ 638 ee_mode = AR5K_EEPROM_MODE_11A; 639 obdb = channel->center_freq >= 5725 ? 3 : 640 (channel->center_freq >= 5500 ? 2 : 641 (channel->center_freq >= 5260 ? 1 : 642 (channel->center_freq > 4000 ? 0 : -1))); 643 644 if (obdb < 0) 645 return -EINVAL; 646 647 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 648 AR5K_RF_OB_5GHZ, true); 649 650 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 651 AR5K_RF_DB_5GHZ, true); 652 } 653 654 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 655 656 /* Bank Modifications (chip-specific) */ 657 if (ah->ah_radio == AR5K_RF5111) { 658 659 /* Set gain_F settings according to current step */ 660 if (channel->hw_value & CHANNEL_OFDM) { 661 662 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 663 AR5K_PHY_FRAME_CTL_TX_CLIP, 664 g_step->gos_param[0]); 665 666 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 667 AR5K_RF_PWD_90, true); 668 669 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 670 AR5K_RF_PWD_84, true); 671 672 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 673 AR5K_RF_RFGAIN_SEL, true); 674 675 /* We programmed gain_F parameters, switch back 676 * to active state */ 677 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 678 679 } 680 681 /* Bank 6/7 setup */ 682 683 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 684 AR5K_RF_PWD_XPD, true); 685 686 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 687 AR5K_RF_XPD_GAIN, true); 688 689 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 690 AR5K_RF_GAIN_I, true); 691 692 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 693 AR5K_RF_PLO_SEL, true); 694 695 /* TODO: Half/quarter channel support */ 696 } 697 698 if (ah->ah_radio == AR5K_RF5112) { 699 700 /* Set gain_F settings according to current step */ 701 if (channel->hw_value & CHANNEL_OFDM) { 702 703 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 704 AR5K_RF_MIXGAIN_OVR, true); 705 706 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 707 AR5K_RF_PWD_138, true); 708 709 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 710 AR5K_RF_PWD_137, true); 711 712 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 713 AR5K_RF_PWD_136, true); 714 715 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 716 AR5K_RF_PWD_132, true); 717 718 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 719 AR5K_RF_PWD_131, true); 720 721 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 722 AR5K_RF_PWD_130, true); 723 724 /* We programmed gain_F parameters, switch back 725 * to active state */ 726 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 727 } 728 729 /* Bank 6/7 setup */ 730 731 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 732 AR5K_RF_XPD_SEL, true); 733 734 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 735 /* Rev. 1 supports only one xpd */ 736 ath5k_hw_rfb_op(ah, rf_regs, 737 ee->ee_x_gain[ee_mode], 738 AR5K_RF_XPD_GAIN, true); 739 740 } else { 741 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 742 if (ee->ee_pd_gains[ee_mode] > 1) { 743 ath5k_hw_rfb_op(ah, rf_regs, 744 pdg_curve_to_idx[0], 745 AR5K_RF_PD_GAIN_LO, true); 746 ath5k_hw_rfb_op(ah, rf_regs, 747 pdg_curve_to_idx[1], 748 AR5K_RF_PD_GAIN_HI, true); 749 } else { 750 ath5k_hw_rfb_op(ah, rf_regs, 751 pdg_curve_to_idx[0], 752 AR5K_RF_PD_GAIN_LO, true); 753 ath5k_hw_rfb_op(ah, rf_regs, 754 pdg_curve_to_idx[0], 755 AR5K_RF_PD_GAIN_HI, true); 756 } 757 758 /* Lower synth voltage on Rev 2 */ 759 ath5k_hw_rfb_op(ah, rf_regs, 2, 760 AR5K_RF_HIGH_VC_CP, true); 761 762 ath5k_hw_rfb_op(ah, rf_regs, 2, 763 AR5K_RF_MID_VC_CP, true); 764 765 ath5k_hw_rfb_op(ah, rf_regs, 2, 766 AR5K_RF_LOW_VC_CP, true); 767 768 ath5k_hw_rfb_op(ah, rf_regs, 2, 769 AR5K_RF_PUSH_UP, true); 770 771 /* Decrease power consumption on 5213+ BaseBand */ 772 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 773 ath5k_hw_rfb_op(ah, rf_regs, 1, 774 AR5K_RF_PAD2GND, true); 775 776 ath5k_hw_rfb_op(ah, rf_regs, 1, 777 AR5K_RF_XB2_LVL, true); 778 779 ath5k_hw_rfb_op(ah, rf_regs, 1, 780 AR5K_RF_XB5_LVL, true); 781 782 ath5k_hw_rfb_op(ah, rf_regs, 1, 783 AR5K_RF_PWD_167, true); 784 785 ath5k_hw_rfb_op(ah, rf_regs, 1, 786 AR5K_RF_PWD_166, true); 787 } 788 } 789 790 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 791 AR5K_RF_GAIN_I, true); 792 793 /* TODO: Half/quarter channel support */ 794 795 } 796 797 if (ah->ah_radio == AR5K_RF5413 && 798 channel->hw_value & CHANNEL_2GHZ) { 799 800 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 801 true); 802 803 /* Set optimum value for early revisions (on pci-e chips) */ 804 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 805 ah->ah_mac_srev < AR5K_SREV_AR5413) 806 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 807 AR5K_RF_PWD_ICLOBUF_2G, true); 808 809 } 810 811 /* Write RF banks on hw */ 812 for (i = 0; i < ah->ah_rf_banks_size; i++) { 813 AR5K_REG_WAIT(i); 814 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 815 } 816 817 return 0; 818} 819 820 821/**************************\ 822 PHY/RF channel functions 823\**************************/ 824 825/* 826 * Check if a channel is supported 827 */ 828bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 829{ 830 /* Check if the channel is in our supported range */ 831 if (flags & CHANNEL_2GHZ) { 832 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 833 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 834 return true; 835 } else if (flags & CHANNEL_5GHZ) 836 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 837 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 838 return true; 839 840 return false; 841} 842 843/* 844 * Convertion needed for RF5110 845 */ 846static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 847{ 848 u32 athchan; 849 850 /* 851 * Convert IEEE channel/MHz to an internal channel value used 852 * by the AR5210 chipset. This has not been verified with 853 * newer chipsets like the AR5212A who have a completely 854 * different RF/PHY part. 855 */ 856 athchan = (ath5k_hw_bitswap( 857 (ieee80211_frequency_to_channel( 858 channel->center_freq) - 24) / 2, 5) 859 << 1) | (1 << 6) | 0x1; 860 return athchan; 861} 862 863/* 864 * Set channel on RF5110 865 */ 866static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 867 struct ieee80211_channel *channel) 868{ 869 u32 data; 870 871 /* 872 * Set the channel and wait 873 */ 874 data = ath5k_hw_rf5110_chan2athchan(channel); 875 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 876 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 877 mdelay(1); 878 879 return 0; 880} 881 882/* 883 * Convertion needed for 5111 884 */ 885static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 886 struct ath5k_athchan_2ghz *athchan) 887{ 888 int channel; 889 890 /* Cast this value to catch negative channel numbers (>= -19) */ 891 channel = (int)ieee; 892 893 /* 894 * Map 2GHz IEEE channel to 5GHz Atheros channel 895 */ 896 if (channel <= 13) { 897 athchan->a2_athchan = 115 + channel; 898 athchan->a2_flags = 0x46; 899 } else if (channel == 14) { 900 athchan->a2_athchan = 124; 901 athchan->a2_flags = 0x44; 902 } else if (channel >= 15 && channel <= 26) { 903 athchan->a2_athchan = ((channel - 14) * 4) + 132; 904 athchan->a2_flags = 0x46; 905 } else 906 return -EINVAL; 907 908 return 0; 909} 910 911/* 912 * Set channel on 5111 913 */ 914static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 915 struct ieee80211_channel *channel) 916{ 917 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 918 unsigned int ath5k_channel = 919 ieee80211_frequency_to_channel(channel->center_freq); 920 u32 data0, data1, clock; 921 int ret; 922 923 /* 924 * Set the channel on the RF5111 radio 925 */ 926 data0 = data1 = 0; 927 928 if (channel->hw_value & CHANNEL_2GHZ) { 929 /* Map 2GHz channel to 5GHz Atheros channel ID */ 930 ret = ath5k_hw_rf5111_chan2athchan( 931 ieee80211_frequency_to_channel(channel->center_freq), 932 &ath5k_channel_2ghz); 933 if (ret) 934 return ret; 935 936 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 937 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 938 << 5) | (1 << 4); 939 } 940 941 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 942 clock = 1; 943 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 944 (clock << 1) | (1 << 10) | 1; 945 } else { 946 clock = 0; 947 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 948 << 2) | (clock << 1) | (1 << 10) | 1; 949 } 950 951 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 952 AR5K_RF_BUFFER); 953 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 954 AR5K_RF_BUFFER_CONTROL_3); 955 956 return 0; 957} 958 959/* 960 * Set channel on 5112 and newer 961 */ 962static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 963 struct ieee80211_channel *channel) 964{ 965 u32 data, data0, data1, data2; 966 u16 c; 967 968 data = data0 = data1 = data2 = 0; 969 c = channel->center_freq; 970 971 if (c < 4800) { 972 if (!((c - 2224) % 5)) { 973 data0 = ((2 * (c - 704)) - 3040) / 10; 974 data1 = 1; 975 } else if (!((c - 2192) % 5)) { 976 data0 = ((2 * (c - 672)) - 3040) / 10; 977 data1 = 0; 978 } else 979 return -EINVAL; 980 981 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 982 } else if ((c % 5) != 2 || c > 5435) { 983 if (!(c % 20) && c >= 5120) { 984 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 985 data2 = ath5k_hw_bitswap(3, 2); 986 } else if (!(c % 10)) { 987 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 988 data2 = ath5k_hw_bitswap(2, 2); 989 } else if (!(c % 5)) { 990 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 991 data2 = ath5k_hw_bitswap(1, 2); 992 } else 993 return -EINVAL; 994 } else { 995 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 996 data2 = ath5k_hw_bitswap(0, 2); 997 } 998 999 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1000 1001 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1002 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1003 1004 return 0; 1005} 1006 1007/* 1008 * Set the channel on the RF2425 1009 */ 1010static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1011 struct ieee80211_channel *channel) 1012{ 1013 u32 data, data0, data2; 1014 u16 c; 1015 1016 data = data0 = data2 = 0; 1017 c = channel->center_freq; 1018 1019 if (c < 4800) { 1020 data0 = ath5k_hw_bitswap((c - 2272), 8); 1021 data2 = 0; 1022 /* ? 5GHz ? */ 1023 } else if ((c % 5) != 2 || c > 5435) { 1024 if (!(c % 20) && c < 5120) 1025 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1026 else if (!(c % 10)) 1027 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1028 else if (!(c % 5)) 1029 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1030 else 1031 return -EINVAL; 1032 data2 = ath5k_hw_bitswap(1, 2); 1033 } else { 1034 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1035 data2 = ath5k_hw_bitswap(0, 2); 1036 } 1037 1038 data = (data0 << 4) | data2 << 2 | 0x1001; 1039 1040 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1041 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1042 1043 return 0; 1044} 1045 1046/* 1047 * Set a channel on the radio chip 1048 */ 1049int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) 1050{ 1051 int ret; 1052 /* 1053 * Check bounds supported by the PHY (we don't care about regultory 1054 * restrictions at this point). Note: hw_value already has the band 1055 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1056 * of the band by that */ 1057 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1058 ATH5K_ERR(ah->ah_sc, 1059 "channel frequency (%u MHz) out of supported " 1060 "band range\n", 1061 channel->center_freq); 1062 return -EINVAL; 1063 } 1064 1065 /* 1066 * Set the channel and wait 1067 */ 1068 switch (ah->ah_radio) { 1069 case AR5K_RF5110: 1070 ret = ath5k_hw_rf5110_channel(ah, channel); 1071 break; 1072 case AR5K_RF5111: 1073 ret = ath5k_hw_rf5111_channel(ah, channel); 1074 break; 1075 case AR5K_RF2425: 1076 ret = ath5k_hw_rf2425_channel(ah, channel); 1077 break; 1078 default: 1079 ret = ath5k_hw_rf5112_channel(ah, channel); 1080 break; 1081 } 1082 1083 if (ret) 1084 return ret; 1085 1086 /* Set JAPAN setting for channel 14 */ 1087 if (channel->center_freq == 2484) { 1088 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1089 AR5K_PHY_CCKTXCTL_JAPAN); 1090 } else { 1091 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1092 AR5K_PHY_CCKTXCTL_WORLD); 1093 } 1094 1095 ah->ah_current_channel = channel; 1096 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; 1097 1098 return 0; 1099} 1100 1101/*****************\ 1102 PHY calibration 1103\*****************/ 1104 1105static int sign_extend(int val, const int nbits) 1106{ 1107 int order = BIT(nbits-1); 1108 return (val ^ order) - order; 1109} 1110 1111static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1112{ 1113 s32 val; 1114 1115 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1116 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9); 1117} 1118 1119void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1120{ 1121 int i; 1122 1123 ah->ah_nfcal_hist.index = 0; 1124 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1125 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1126} 1127 1128static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1129{ 1130 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1131 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1132 hist->nfval[hist->index] = noise_floor; 1133} 1134 1135static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1136{ 1137 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1138 s16 tmp; 1139 int i, j; 1140 1141 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1142 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1143 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1144 if (sort[j] > sort[j-1]) { 1145 tmp = sort[j]; 1146 sort[j] = sort[j-1]; 1147 sort[j-1] = tmp; 1148 } 1149 } 1150 } 1151 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1152 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1153 "cal %d:%d\n", i, sort[i]); 1154 } 1155 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1156} 1157 1158/* 1159 * When we tell the hardware to perform a noise floor calibration 1160 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1161 * sample-and-hold the minimum noise level seen at the antennas. 1162 * This value is then stored in a ring buffer of recently measured 1163 * noise floor values so we have a moving window of the last few 1164 * samples. 1165 * 1166 * The median of the values in the history is then loaded into the 1167 * hardware for its own use for RSSI and CCA measurements. 1168 */ 1169static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1170{ 1171 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1172 u32 val; 1173 s16 nf, threshold; 1174 u8 ee_mode; 1175 1176 /* keep last value if calibration hasn't completed */ 1177 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1178 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1179 "NF did not complete in calibration window\n"); 1180 1181 return; 1182 } 1183 1184 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { 1185 case CHANNEL_A: 1186 case CHANNEL_T: 1187 case CHANNEL_XR: 1188 ee_mode = AR5K_EEPROM_MODE_11A; 1189 break; 1190 case CHANNEL_G: 1191 case CHANNEL_TG: 1192 ee_mode = AR5K_EEPROM_MODE_11G; 1193 break; 1194 default: 1195 case CHANNEL_B: 1196 ee_mode = AR5K_EEPROM_MODE_11B; 1197 break; 1198 } 1199 1200 1201 /* completed NF calibration, test threshold */ 1202 nf = ath5k_hw_read_measured_noise_floor(ah); 1203 threshold = ee->ee_noise_floor_thr[ee_mode]; 1204 1205 if (nf > threshold) { 1206 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1207 "noise floor failure detected; " 1208 "read %d, threshold %d\n", 1209 nf, threshold); 1210 1211 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1212 } 1213 1214 ath5k_hw_update_nfcal_hist(ah, nf); 1215 nf = ath5k_hw_get_median_noise_floor(ah); 1216 1217 /* load noise floor (in .5 dBm) so the hardware will use it */ 1218 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1219 val |= (nf * 2) & AR5K_PHY_NF_M; 1220 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1221 1222 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1223 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1224 1225 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1226 0, false); 1227 1228 /* 1229 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1230 * so that we're not capped by the median we just loaded. 1231 * This will be used as the initial value for the next noise 1232 * floor calibration. 1233 */ 1234 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1235 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1236 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1237 AR5K_PHY_AGCCTL_NF_EN | 1238 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1239 AR5K_PHY_AGCCTL_NF); 1240 1241 ah->ah_noise_floor = nf; 1242 1243 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1244 "noise floor calibrated: %d\n", nf); 1245} 1246 1247/* 1248 * Perform a PHY calibration on RF5110 1249 * -Fix BPSK/QAM Constellation (I/Q correction) 1250 * -Calculate Noise Floor 1251 */ 1252static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1253 struct ieee80211_channel *channel) 1254{ 1255 u32 phy_sig, phy_agc, phy_sat, beacon; 1256 int ret; 1257 1258 /* 1259 * Disable beacons and RX/TX queues, wait 1260 */ 1261 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1262 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1263 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1264 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1265 1266 mdelay(2); 1267 1268 /* 1269 * Set the channel (with AGC turned off) 1270 */ 1271 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1272 udelay(10); 1273 ret = ath5k_hw_channel(ah, channel); 1274 1275 /* 1276 * Activate PHY and wait 1277 */ 1278 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1279 mdelay(1); 1280 1281 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1282 1283 if (ret) 1284 return ret; 1285 1286 /* 1287 * Calibrate the radio chip 1288 */ 1289 1290 /* Remember normal state */ 1291 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1292 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1293 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1294 1295 /* Update radio registers */ 1296 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1297 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1298 1299 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1300 AR5K_PHY_AGCCOARSE_LO)) | 1301 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1302 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1303 1304 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1305 AR5K_PHY_ADCSAT_THR)) | 1306 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1307 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1308 1309 udelay(20); 1310 1311 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1312 udelay(10); 1313 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1314 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1315 1316 mdelay(1); 1317 1318 /* 1319 * Enable calibration and wait until completion 1320 */ 1321 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1322 1323 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1324 AR5K_PHY_AGCCTL_CAL, 0, false); 1325 1326 /* Reset to normal state */ 1327 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1328 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1329 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1330 1331 if (ret) { 1332 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1333 channel->center_freq); 1334 return ret; 1335 } 1336 1337 ath5k_hw_update_noise_floor(ah); 1338 1339 /* 1340 * Re-enable RX/TX and beacons 1341 */ 1342 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1343 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1344 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1345 1346 return 0; 1347} 1348 1349/* 1350 * Perform a PHY calibration on RF5111/5112 and newer chips 1351 */ 1352static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, 1353 struct ieee80211_channel *channel) 1354{ 1355 u32 i_pwr, q_pwr; 1356 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1357 int i; 1358 ATH5K_TRACE(ah->ah_sc); 1359 1360 if (!ah->ah_calibration || 1361 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1362 goto done; 1363 1364 /* Calibration has finished, get the results and re-run */ 1365 1366 /* work around empty results which can apparently happen on 5212 */ 1367 for (i = 0; i <= 10; i++) { 1368 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1369 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1370 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1371 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1372 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1373 if (i_pwr && q_pwr) 1374 break; 1375 } 1376 1377 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1378 1379 if (ah->ah_version == AR5K_AR5211) 1380 q_coffd = q_pwr >> 6; 1381 else 1382 q_coffd = q_pwr >> 7; 1383 1384 /* protect against divide by 0 and loss of sign bits */ 1385 if (i_coffd == 0 || q_coffd < 2) 1386 goto done; 1387 1388 i_coff = (-iq_corr) / i_coffd; 1389 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1390 1391 if (ah->ah_version == AR5K_AR5211) 1392 q_coff = (i_pwr / q_coffd) - 64; 1393 else 1394 q_coff = (i_pwr / q_coffd) - 128; 1395 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1396 1397 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1398 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1399 i_coff, q_coff, i_coffd, q_coffd); 1400 1401 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1402 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1403 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1404 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1405 1406 /* Re-enable calibration -if we don't we'll commit 1407 * the same values again and again */ 1408 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1409 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1410 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1411 1412done: 1413 1414 /* TODO: Separate noise floor calibration from I/Q calibration 1415 * since noise floor calibration interrupts rx path while I/Q 1416 * calibration doesn't. We don't need to run noise floor calibration 1417 * as often as I/Q calibration.*/ 1418 ath5k_hw_update_noise_floor(ah); 1419 1420 /* Initiate a gain_F calibration */ 1421 ath5k_hw_request_rfgain_probe(ah); 1422 1423 return 0; 1424} 1425 1426/* 1427 * Perform a PHY calibration 1428 */ 1429int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1430 struct ieee80211_channel *channel) 1431{ 1432 int ret; 1433 1434 if (ah->ah_radio == AR5K_RF5110) 1435 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1436 else 1437 ret = ath5k_hw_rf511x_calibrate(ah, channel); 1438 1439 return ret; 1440} 1441 1442/***************************\ 1443* Spur mitigation functions * 1444\***************************/ 1445 1446bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1447 struct ieee80211_channel *channel) 1448{ 1449 u8 refclk_freq; 1450 1451 if ((ah->ah_radio == AR5K_RF5112) || 1452 (ah->ah_radio == AR5K_RF5413) || 1453 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 1454 refclk_freq = 40; 1455 else 1456 refclk_freq = 32; 1457 1458 if ((channel->center_freq % refclk_freq != 0) && 1459 ((channel->center_freq % refclk_freq < 10) || 1460 (channel->center_freq % refclk_freq > 22))) 1461 return true; 1462 else 1463 return false; 1464} 1465 1466void 1467ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1468 struct ieee80211_channel *channel) 1469{ 1470 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1471 u32 mag_mask[4] = {0, 0, 0, 0}; 1472 u32 pilot_mask[2] = {0, 0}; 1473 /* Note: fbin values are scaled up by 2 */ 1474 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1475 s32 spur_delta_phase, spur_freq_sigma_delta; 1476 s32 spur_offset, num_symbols_x16; 1477 u8 num_symbol_offsets, i, freq_band; 1478 1479 /* Convert current frequency to fbin value (the same way channels 1480 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1481 * up by 2 so we can compare it later */ 1482 if (channel->hw_value & CHANNEL_2GHZ) { 1483 chan_fbin = (channel->center_freq - 2300) * 10; 1484 freq_band = AR5K_EEPROM_BAND_2GHZ; 1485 } else { 1486 chan_fbin = (channel->center_freq - 4900) * 10; 1487 freq_band = AR5K_EEPROM_BAND_5GHZ; 1488 } 1489 1490 /* Check if any spur_chan_fbin from EEPROM is 1491 * within our current channel's spur detection range */ 1492 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1493 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1494 /* XXX: Half/Quarter channels ?*/ 1495 if (channel->hw_value & CHANNEL_TURBO) 1496 spur_detection_window *= 2; 1497 1498 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1499 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1500 1501 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1502 * so it's zero if we got nothing from EEPROM */ 1503 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1504 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1505 break; 1506 } 1507 1508 if ((chan_fbin - spur_detection_window <= 1509 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1510 (chan_fbin + spur_detection_window >= 1511 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1512 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1513 break; 1514 } 1515 } 1516 1517 /* We need to enable spur filter for this channel */ 1518 if (spur_chan_fbin) { 1519 spur_offset = spur_chan_fbin - chan_fbin; 1520 /* 1521 * Calculate deltas: 1522 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1523 * spur_delta_phase -> spur_offset / chip_freq << 11 1524 * Note: Both values have 100KHz resolution 1525 */ 1526 /* XXX: Half/Quarter rate channels ? */ 1527 switch (channel->hw_value) { 1528 case CHANNEL_A: 1529 /* Both sample_freq and chip_freq are 40MHz */ 1530 spur_delta_phase = (spur_offset << 17) / 25; 1531 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1532 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1533 break; 1534 case CHANNEL_G: 1535 /* sample_freq -> 40MHz chip_freq -> 44MHz 1536 * (for b compatibility) */ 1537 spur_freq_sigma_delta = (spur_offset << 8) / 55; 1538 spur_delta_phase = (spur_offset << 17) / 25; 1539 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1540 break; 1541 case CHANNEL_T: 1542 case CHANNEL_TG: 1543 /* Both sample_freq and chip_freq are 80MHz */ 1544 spur_delta_phase = (spur_offset << 16) / 25; 1545 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1546 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; 1547 break; 1548 default: 1549 return; 1550 } 1551 1552 /* Calculate pilot and magnitude masks */ 1553 1554 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1555 * and divide by symbol_width to find how many symbols we have 1556 * Note: number of symbols is scaled up by 16 */ 1557 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1558 1559 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1560 if (!(num_symbols_x16 & 0xF)) 1561 /* _X_ */ 1562 num_symbol_offsets = 3; 1563 else 1564 /* _xx_ */ 1565 num_symbol_offsets = 4; 1566 1567 for (i = 0; i < num_symbol_offsets; i++) { 1568 1569 /* Calculate pilot mask */ 1570 s32 curr_sym_off = 1571 (num_symbols_x16 / 16) + i + 25; 1572 1573 /* Pilot magnitude mask seems to be a way to 1574 * declare the boundaries for our detection 1575 * window or something, it's 2 for the middle 1576 * value(s) where the symbol is expected to be 1577 * and 1 on the boundary values */ 1578 u8 plt_mag_map = 1579 (i == 0 || i == (num_symbol_offsets - 1)) 1580 ? 1 : 2; 1581 1582 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1583 if (curr_sym_off <= 25) 1584 pilot_mask[0] |= 1 << curr_sym_off; 1585 else if (curr_sym_off >= 27) 1586 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1587 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1588 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1589 1590 /* Calculate magnitude mask (for viterbi decoder) */ 1591 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1592 mag_mask[0] |= 1593 plt_mag_map << (curr_sym_off + 1) * 2; 1594 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1595 mag_mask[1] |= 1596 plt_mag_map << (curr_sym_off - 15) * 2; 1597 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1598 mag_mask[2] |= 1599 plt_mag_map << (curr_sym_off - 31) * 2; 1600 else if (curr_sym_off >= 46 && curr_sym_off <= 53) 1601 mag_mask[3] |= 1602 plt_mag_map << (curr_sym_off - 47) * 2; 1603 1604 } 1605 1606 /* Write settings on hw to enable spur filter */ 1607 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1608 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1609 /* XXX: Self correlator also ? */ 1610 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1611 AR5K_PHY_IQ_PILOT_MASK_EN | 1612 AR5K_PHY_IQ_CHAN_MASK_EN | 1613 AR5K_PHY_IQ_SPUR_FILT_EN); 1614 1615 /* Set delta phase and freq sigma delta */ 1616 ath5k_hw_reg_write(ah, 1617 AR5K_REG_SM(spur_delta_phase, 1618 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1619 AR5K_REG_SM(spur_freq_sigma_delta, 1620 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1621 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1622 AR5K_PHY_TIMING_11); 1623 1624 /* Write pilot masks */ 1625 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1626 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1627 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1628 pilot_mask[1]); 1629 1630 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1631 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1632 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1633 pilot_mask[1]); 1634 1635 /* Write magnitude masks */ 1636 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1637 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1638 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1639 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1640 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1641 mag_mask[3]); 1642 1643 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1644 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1645 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1646 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1647 AR5K_PHY_BIN_MASK2_4_MASK_4, 1648 mag_mask[3]); 1649 1650 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1651 AR5K_PHY_IQ_SPUR_FILT_EN) { 1652 /* Clean up spur mitigation settings and disable fliter */ 1653 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1654 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1655 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1656 AR5K_PHY_IQ_PILOT_MASK_EN | 1657 AR5K_PHY_IQ_CHAN_MASK_EN | 1658 AR5K_PHY_IQ_SPUR_FILT_EN); 1659 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1660 1661 /* Clear pilot masks */ 1662 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1663 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1664 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1665 0); 1666 1667 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1668 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1669 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1670 0); 1671 1672 /* Clear magnitude masks */ 1673 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1674 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1675 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1676 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1677 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1678 0); 1679 1680 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1681 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1682 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1683 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1684 AR5K_PHY_BIN_MASK2_4_MASK_4, 1685 0); 1686 } 1687} 1688 1689/********************\ 1690 Misc PHY functions 1691\********************/ 1692 1693int ath5k_hw_phy_disable(struct ath5k_hw *ah) 1694{ 1695 ATH5K_TRACE(ah->ah_sc); 1696 /*Just a try M.F.*/ 1697 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1698 1699 return 0; 1700} 1701 1702/* 1703 * Get the PHY Chip revision 1704 */ 1705u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 1706{ 1707 unsigned int i; 1708 u32 srev; 1709 u16 ret; 1710 1711 ATH5K_TRACE(ah->ah_sc); 1712 1713 /* 1714 * Set the radio chip access register 1715 */ 1716 switch (chan) { 1717 case CHANNEL_2GHZ: 1718 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 1719 break; 1720 case CHANNEL_5GHZ: 1721 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1722 break; 1723 default: 1724 return 0; 1725 } 1726 1727 mdelay(2); 1728 1729 /* ...wait until PHY is ready and read the selected radio revision */ 1730 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 1731 1732 for (i = 0; i < 8; i++) 1733 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 1734 1735 if (ah->ah_version == AR5K_AR5210) { 1736 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 1737 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 1738 } else { 1739 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 1740 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 1741 ((srev & 0x0f) << 4), 8); 1742 } 1743 1744 /* Reset to the 5GHz mode */ 1745 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1746 1747 return ret; 1748} 1749 1750/*****************\ 1751* Antenna control * 1752\*****************/ 1753 1754static void /*TODO:Boundary check*/ 1755ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1756{ 1757 ATH5K_TRACE(ah->ah_sc); 1758 1759 if (ah->ah_version != AR5K_AR5210) 1760 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1761} 1762 1763/* 1764 * Enable/disable fast rx antenna diversity 1765 */ 1766static void 1767ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1768{ 1769 switch (ee_mode) { 1770 case AR5K_EEPROM_MODE_11G: 1771 /* XXX: This is set to 1772 * disabled on initvals !!! */ 1773 case AR5K_EEPROM_MODE_11A: 1774 if (enable) 1775 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1776 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1777 else 1778 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1779 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1780 break; 1781 case AR5K_EEPROM_MODE_11B: 1782 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1783 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1784 break; 1785 default: 1786 return; 1787 } 1788 1789 if (enable) { 1790 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1791 AR5K_PHY_RESTART_DIV_GC, 0xc); 1792 1793 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1794 AR5K_PHY_FAST_ANT_DIV_EN); 1795 } else { 1796 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1797 AR5K_PHY_RESTART_DIV_GC, 0x8); 1798 1799 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1800 AR5K_PHY_FAST_ANT_DIV_EN); 1801 } 1802} 1803 1804/* 1805 * Set antenna operating mode 1806 */ 1807void 1808ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1809{ 1810 struct ieee80211_channel *channel = ah->ah_current_channel; 1811 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1812 bool use_def_for_sg; 1813 u8 def_ant, tx_ant, ee_mode; 1814 u32 sta_id1 = 0; 1815 1816 def_ant = ah->ah_def_ant; 1817 1818 ATH5K_TRACE(ah->ah_sc); 1819 1820 switch (channel->hw_value & CHANNEL_MODES) { 1821 case CHANNEL_A: 1822 case CHANNEL_T: 1823 case CHANNEL_XR: 1824 ee_mode = AR5K_EEPROM_MODE_11A; 1825 break; 1826 case CHANNEL_G: 1827 case CHANNEL_TG: 1828 ee_mode = AR5K_EEPROM_MODE_11G; 1829 break; 1830 case CHANNEL_B: 1831 ee_mode = AR5K_EEPROM_MODE_11B; 1832 break; 1833 default: 1834 ATH5K_ERR(ah->ah_sc, 1835 "invalid channel: %d\n", channel->center_freq); 1836 return; 1837 } 1838 1839 switch (ant_mode) { 1840 case AR5K_ANTMODE_DEFAULT: 1841 tx_ant = 0; 1842 use_def_for_tx = false; 1843 update_def_on_tx = false; 1844 use_def_for_rts = false; 1845 use_def_for_sg = false; 1846 fast_div = true; 1847 break; 1848 case AR5K_ANTMODE_FIXED_A: 1849 def_ant = 1; 1850 tx_ant = 1; 1851 use_def_for_tx = true; 1852 update_def_on_tx = false; 1853 use_def_for_rts = true; 1854 use_def_for_sg = true; 1855 fast_div = false; 1856 break; 1857 case AR5K_ANTMODE_FIXED_B: 1858 def_ant = 2; 1859 tx_ant = 2; 1860 use_def_for_tx = true; 1861 update_def_on_tx = false; 1862 use_def_for_rts = true; 1863 use_def_for_sg = true; 1864 fast_div = false; 1865 break; 1866 case AR5K_ANTMODE_SINGLE_AP: 1867 def_ant = 1; /* updated on tx */ 1868 tx_ant = 0; 1869 use_def_for_tx = true; 1870 update_def_on_tx = true; 1871 use_def_for_rts = true; 1872 use_def_for_sg = true; 1873 fast_div = true; 1874 break; 1875 case AR5K_ANTMODE_SECTOR_AP: 1876 tx_ant = 1; /* variable */ 1877 use_def_for_tx = false; 1878 update_def_on_tx = false; 1879 use_def_for_rts = true; 1880 use_def_for_sg = false; 1881 fast_div = false; 1882 break; 1883 case AR5K_ANTMODE_SECTOR_STA: 1884 tx_ant = 1; /* variable */ 1885 use_def_for_tx = true; 1886 update_def_on_tx = false; 1887 use_def_for_rts = true; 1888 use_def_for_sg = false; 1889 fast_div = true; 1890 break; 1891 case AR5K_ANTMODE_DEBUG: 1892 def_ant = 1; 1893 tx_ant = 2; 1894 use_def_for_tx = false; 1895 update_def_on_tx = false; 1896 use_def_for_rts = false; 1897 use_def_for_sg = false; 1898 fast_div = false; 1899 break; 1900 default: 1901 return; 1902 } 1903 1904 ah->ah_tx_ant = tx_ant; 1905 ah->ah_ant_mode = ant_mode; 1906 ah->ah_def_ant = def_ant; 1907 1908 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 1909 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 1910 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 1911 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 1912 1913 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 1914 1915 if (sta_id1) 1916 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 1917 1918 /* Note: set diversity before default antenna 1919 * because it won't work correctly */ 1920 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 1921 ath5k_hw_set_def_antenna(ah, def_ant); 1922} 1923 1924 1925/****************\ 1926* TX power setup * 1927\****************/ 1928 1929/* 1930 * Helper functions 1931 */ 1932 1933/* 1934 * Do linear interpolation between two given (x, y) points 1935 */ 1936static s16 1937ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 1938 s16 y_left, s16 y_right) 1939{ 1940 s16 ratio, result; 1941 1942 /* Avoid divide by zero and skip interpolation 1943 * if we have the same point */ 1944 if ((x_left == x_right) || (y_left == y_right)) 1945 return y_left; 1946 1947 /* 1948 * Since we use ints and not fps, we need to scale up in 1949 * order to get a sane ratio value (or else we 'll eg. get 1950 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 1951 * to have some accuracy both for 0.5 and 0.25 steps. 1952 */ 1953 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 1954 1955 /* Now scale down to be in range */ 1956 result = y_left + (ratio * (target - x_left) / 100); 1957 1958 return result; 1959} 1960 1961/* 1962 * Find vertical boundary (min pwr) for the linear PCDAC curve. 1963 * 1964 * Since we have the top of the curve and we draw the line below 1965 * until we reach 1 (1 pcdac step) we need to know which point 1966 * (x value) that is so that we don't go below y axis and have negative 1967 * pcdac values when creating the curve, or fill the table with zeroes. 1968 */ 1969static s16 1970ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 1971 const s16 *pwrL, const s16 *pwrR) 1972{ 1973 s8 tmp; 1974 s16 min_pwrL, min_pwrR; 1975 s16 pwr_i; 1976 1977 /* Some vendors write the same pcdac value twice !!! */ 1978 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 1979 return max(pwrL[0], pwrR[0]); 1980 1981 if (pwrL[0] == pwrL[1]) 1982 min_pwrL = pwrL[0]; 1983 else { 1984 pwr_i = pwrL[0]; 1985 do { 1986 pwr_i--; 1987 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1988 pwrL[0], pwrL[1], 1989 stepL[0], stepL[1]); 1990 } while (tmp > 1); 1991 1992 min_pwrL = pwr_i; 1993 } 1994 1995 if (pwrR[0] == pwrR[1]) 1996 min_pwrR = pwrR[0]; 1997 else { 1998 pwr_i = pwrR[0]; 1999 do { 2000 pwr_i--; 2001 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2002 pwrR[0], pwrR[1], 2003 stepR[0], stepR[1]); 2004 } while (tmp > 1); 2005 2006 min_pwrR = pwr_i; 2007 } 2008 2009 /* Keep the right boundary so that it works for both curves */ 2010 return max(min_pwrL, min_pwrR); 2011} 2012 2013/* 2014 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2015 * Power to PCDAC curve. 2016 * 2017 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2018 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2019 * PCDAC/PDADC step for each curve is 64 but we can write more than 2020 * one curves on hw so we can go up to 128 (which is the max step we 2021 * can write on the final table). 2022 * 2023 * We write y values (PCDAC/PDADC steps) on hw. 2024 */ 2025static void 2026ath5k_create_power_curve(s16 pmin, s16 pmax, 2027 const s16 *pwr, const u8 *vpd, 2028 u8 num_points, 2029 u8 *vpd_table, u8 type) 2030{ 2031 u8 idx[2] = { 0, 1 }; 2032 s16 pwr_i = 2*pmin; 2033 int i; 2034 2035 if (num_points < 2) 2036 return; 2037 2038 /* We want the whole line, so adjust boundaries 2039 * to cover the entire power range. Note that 2040 * power values are already 0.25dB so no need 2041 * to multiply pwr_i by 2 */ 2042 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2043 pwr_i = pmin; 2044 pmin = 0; 2045 pmax = 63; 2046 } 2047 2048 /* Find surrounding turning points (TPs) 2049 * and interpolate between them */ 2050 for (i = 0; (i <= (u16) (pmax - pmin)) && 2051 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2052 2053 /* We passed the right TP, move to the next set of TPs 2054 * if we pass the last TP, extrapolate above using the last 2055 * two TPs for ratio */ 2056 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2057 idx[0]++; 2058 idx[1]++; 2059 } 2060 2061 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2062 pwr[idx[0]], pwr[idx[1]], 2063 vpd[idx[0]], vpd[idx[1]]); 2064 2065 /* Increase by 0.5dB 2066 * (0.25 dB units) */ 2067 pwr_i += 2; 2068 } 2069} 2070 2071/* 2072 * Get the surrounding per-channel power calibration piers 2073 * for a given frequency so that we can interpolate between 2074 * them and come up with an apropriate dataset for our current 2075 * channel. 2076 */ 2077static void 2078ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2079 struct ieee80211_channel *channel, 2080 struct ath5k_chan_pcal_info **pcinfo_l, 2081 struct ath5k_chan_pcal_info **pcinfo_r) 2082{ 2083 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2084 struct ath5k_chan_pcal_info *pcinfo; 2085 u8 idx_l, idx_r; 2086 u8 mode, max, i; 2087 u32 target = channel->center_freq; 2088 2089 idx_l = 0; 2090 idx_r = 0; 2091 2092 if (!(channel->hw_value & CHANNEL_OFDM)) { 2093 pcinfo = ee->ee_pwr_cal_b; 2094 mode = AR5K_EEPROM_MODE_11B; 2095 } else if (channel->hw_value & CHANNEL_2GHZ) { 2096 pcinfo = ee->ee_pwr_cal_g; 2097 mode = AR5K_EEPROM_MODE_11G; 2098 } else { 2099 pcinfo = ee->ee_pwr_cal_a; 2100 mode = AR5K_EEPROM_MODE_11A; 2101 } 2102 max = ee->ee_n_piers[mode] - 1; 2103 2104 /* Frequency is below our calibrated 2105 * range. Use the lowest power curve 2106 * we have */ 2107 if (target < pcinfo[0].freq) { 2108 idx_l = idx_r = 0; 2109 goto done; 2110 } 2111 2112 /* Frequency is above our calibrated 2113 * range. Use the highest power curve 2114 * we have */ 2115 if (target > pcinfo[max].freq) { 2116 idx_l = idx_r = max; 2117 goto done; 2118 } 2119 2120 /* Frequency is inside our calibrated 2121 * channel range. Pick the surrounding 2122 * calibration piers so that we can 2123 * interpolate */ 2124 for (i = 0; i <= max; i++) { 2125 2126 /* Frequency matches one of our calibration 2127 * piers, no need to interpolate, just use 2128 * that calibration pier */ 2129 if (pcinfo[i].freq == target) { 2130 idx_l = idx_r = i; 2131 goto done; 2132 } 2133 2134 /* We found a calibration pier that's above 2135 * frequency, use this pier and the previous 2136 * one to interpolate */ 2137 if (target < pcinfo[i].freq) { 2138 idx_r = i; 2139 idx_l = idx_r - 1; 2140 goto done; 2141 } 2142 } 2143 2144done: 2145 *pcinfo_l = &pcinfo[idx_l]; 2146 *pcinfo_r = &pcinfo[idx_r]; 2147 2148 return; 2149} 2150 2151/* 2152 * Get the surrounding per-rate power calibration data 2153 * for a given frequency and interpolate between power 2154 * values to set max target power supported by hw for 2155 * each rate. 2156 */ 2157static void 2158ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2159 struct ieee80211_channel *channel, 2160 struct ath5k_rate_pcal_info *rates) 2161{ 2162 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2163 struct ath5k_rate_pcal_info *rpinfo; 2164 u8 idx_l, idx_r; 2165 u8 mode, max, i; 2166 u32 target = channel->center_freq; 2167 2168 idx_l = 0; 2169 idx_r = 0; 2170 2171 if (!(channel->hw_value & CHANNEL_OFDM)) { 2172 rpinfo = ee->ee_rate_tpwr_b; 2173 mode = AR5K_EEPROM_MODE_11B; 2174 } else if (channel->hw_value & CHANNEL_2GHZ) { 2175 rpinfo = ee->ee_rate_tpwr_g; 2176 mode = AR5K_EEPROM_MODE_11G; 2177 } else { 2178 rpinfo = ee->ee_rate_tpwr_a; 2179 mode = AR5K_EEPROM_MODE_11A; 2180 } 2181 max = ee->ee_rate_target_pwr_num[mode] - 1; 2182 2183 /* Get the surrounding calibration 2184 * piers - same as above */ 2185 if (target < rpinfo[0].freq) { 2186 idx_l = idx_r = 0; 2187 goto done; 2188 } 2189 2190 if (target > rpinfo[max].freq) { 2191 idx_l = idx_r = max; 2192 goto done; 2193 } 2194 2195 for (i = 0; i <= max; i++) { 2196 2197 if (rpinfo[i].freq == target) { 2198 idx_l = idx_r = i; 2199 goto done; 2200 } 2201 2202 if (target < rpinfo[i].freq) { 2203 idx_r = i; 2204 idx_l = idx_r - 1; 2205 goto done; 2206 } 2207 } 2208 2209done: 2210 /* Now interpolate power value, based on the frequency */ 2211 rates->freq = target; 2212 2213 rates->target_power_6to24 = 2214 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2215 rpinfo[idx_r].freq, 2216 rpinfo[idx_l].target_power_6to24, 2217 rpinfo[idx_r].target_power_6to24); 2218 2219 rates->target_power_36 = 2220 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2221 rpinfo[idx_r].freq, 2222 rpinfo[idx_l].target_power_36, 2223 rpinfo[idx_r].target_power_36); 2224 2225 rates->target_power_48 = 2226 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2227 rpinfo[idx_r].freq, 2228 rpinfo[idx_l].target_power_48, 2229 rpinfo[idx_r].target_power_48); 2230 2231 rates->target_power_54 = 2232 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2233 rpinfo[idx_r].freq, 2234 rpinfo[idx_l].target_power_54, 2235 rpinfo[idx_r].target_power_54); 2236} 2237 2238/* 2239 * Get the max edge power for this channel if 2240 * we have such data from EEPROM's Conformance Test 2241 * Limits (CTL), and limit max power if needed. 2242 */ 2243static void 2244ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2245 struct ieee80211_channel *channel) 2246{ 2247 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2248 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2249 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2250 u8 *ctl_val = ee->ee_ctl; 2251 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2252 s16 edge_pwr = 0; 2253 u8 rep_idx; 2254 u8 i, ctl_mode; 2255 u8 ctl_idx = 0xFF; 2256 u32 target = channel->center_freq; 2257 2258 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2259 2260 switch (channel->hw_value & CHANNEL_MODES) { 2261 case CHANNEL_A: 2262 ctl_mode |= AR5K_CTL_11A; 2263 break; 2264 case CHANNEL_G: 2265 ctl_mode |= AR5K_CTL_11G; 2266 break; 2267 case CHANNEL_B: 2268 ctl_mode |= AR5K_CTL_11B; 2269 break; 2270 case CHANNEL_T: 2271 ctl_mode |= AR5K_CTL_TURBO; 2272 break; 2273 case CHANNEL_TG: 2274 ctl_mode |= AR5K_CTL_TURBOG; 2275 break; 2276 case CHANNEL_XR: 2277 /* Fall through */ 2278 default: 2279 return; 2280 } 2281 2282 for (i = 0; i < ee->ee_ctls; i++) { 2283 if (ctl_val[i] == ctl_mode) { 2284 ctl_idx = i; 2285 break; 2286 } 2287 } 2288 2289 /* If we have a CTL dataset available grab it and find the 2290 * edge power for our frequency */ 2291 if (ctl_idx == 0xFF) 2292 return; 2293 2294 /* Edge powers are sorted by frequency from lower 2295 * to higher. Each CTL corresponds to 8 edge power 2296 * measurements. */ 2297 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2298 2299 /* Don't do boundaries check because we 2300 * might have more that one bands defined 2301 * for this mode */ 2302 2303 /* Get the edge power that's closer to our 2304 * frequency */ 2305 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2306 rep_idx += i; 2307 if (target <= rep[rep_idx].freq) 2308 edge_pwr = (s16) rep[rep_idx].edge; 2309 } 2310 2311 if (edge_pwr) 2312 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2313} 2314 2315 2316/* 2317 * Power to PCDAC table functions 2318 */ 2319 2320/* 2321 * Fill Power to PCDAC table on RF5111 2322 * 2323 * No further processing is needed for RF5111, the only thing we have to 2324 * do is fill the values below and above calibration range since eeprom data 2325 * may not cover the entire PCDAC table. 2326 */ 2327static void 2328ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2329 s16 *table_max) 2330{ 2331 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2332 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2333 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2334 s16 min_pwr, max_pwr; 2335 2336 /* Get table boundaries */ 2337 min_pwr = table_min[0]; 2338 pcdac_0 = pcdac_tmp[0]; 2339 2340 max_pwr = table_max[0]; 2341 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2342 2343 /* Extrapolate below minimum using pcdac_0 */ 2344 pcdac_i = 0; 2345 for (i = 0; i < min_pwr; i++) 2346 pcdac_out[pcdac_i++] = pcdac_0; 2347 2348 /* Copy values from pcdac_tmp */ 2349 pwr_idx = min_pwr; 2350 for (i = 0 ; pwr_idx <= max_pwr && 2351 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2352 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2353 pwr_idx++; 2354 } 2355 2356 /* Extrapolate above maximum */ 2357 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2358 pcdac_out[pcdac_i++] = pcdac_n; 2359 2360} 2361 2362/* 2363 * Combine available XPD Curves and fill Linear Power to PCDAC table 2364 * on RF5112 2365 * 2366 * RFX112 can have up to 2 curves (one for low txpower range and one for 2367 * higher txpower range). We need to put them both on pcdac_out and place 2368 * them in the correct location. In case we only have one curve available 2369 * just fit it on pcdac_out (it's supposed to cover the entire range of 2370 * available pwr levels since it's always the higher power curve). Extrapolate 2371 * below and above final table if needed. 2372 */ 2373static void 2374ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2375 s16 *table_max, u8 pdcurves) 2376{ 2377 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2378 u8 *pcdac_low_pwr; 2379 u8 *pcdac_high_pwr; 2380 u8 *pcdac_tmp; 2381 u8 pwr; 2382 s16 max_pwr_idx; 2383 s16 min_pwr_idx; 2384 s16 mid_pwr_idx = 0; 2385 /* Edge flag turs on the 7nth bit on the PCDAC 2386 * to delcare the higher power curve (force values 2387 * to be greater than 64). If we only have one curve 2388 * we don't need to set this, if we have 2 curves and 2389 * fill the table backwards this can also be used to 2390 * switch from higher power curve to lower power curve */ 2391 u8 edge_flag; 2392 int i; 2393 2394 /* When we have only one curve available 2395 * that's the higher power curve. If we have 2396 * two curves the first is the high power curve 2397 * and the next is the low power curve. */ 2398 if (pdcurves > 1) { 2399 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2400 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2401 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2402 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2403 2404 /* If table size goes beyond 31.5dB, keep the 2405 * upper 31.5dB range when setting tx power. 2406 * Note: 126 = 31.5 dB in quarter dB steps */ 2407 if (table_max[0] - table_min[1] > 126) 2408 min_pwr_idx = table_max[0] - 126; 2409 else 2410 min_pwr_idx = table_min[1]; 2411 2412 /* Since we fill table backwards 2413 * start from high power curve */ 2414 pcdac_tmp = pcdac_high_pwr; 2415 2416 edge_flag = 0x40; 2417 } else { 2418 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2419 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2420 min_pwr_idx = table_min[0]; 2421 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2422 pcdac_tmp = pcdac_high_pwr; 2423 edge_flag = 0; 2424 } 2425 2426 /* This is used when setting tx power*/ 2427 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2428 2429 /* Fill Power to PCDAC table backwards */ 2430 pwr = max_pwr_idx; 2431 for (i = 63; i >= 0; i--) { 2432 /* Entering lower power range, reset 2433 * edge flag and set pcdac_tmp to lower 2434 * power curve.*/ 2435 if (edge_flag == 0x40 && 2436 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2437 edge_flag = 0x00; 2438 pcdac_tmp = pcdac_low_pwr; 2439 pwr = mid_pwr_idx/2; 2440 } 2441 2442 /* Don't go below 1, extrapolate below if we have 2443 * already swithced to the lower power curve -or 2444 * we only have one curve and edge_flag is zero 2445 * anyway */ 2446 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2447 while (i >= 0) { 2448 pcdac_out[i] = pcdac_out[i + 1]; 2449 i--; 2450 } 2451 break; 2452 } 2453 2454 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2455 2456 /* Extrapolate above if pcdac is greater than 2457 * 126 -this can happen because we OR pcdac_out 2458 * value with edge_flag on high power curve */ 2459 if (pcdac_out[i] > 126) 2460 pcdac_out[i] = 126; 2461 2462 /* Decrease by a 0.5dB step */ 2463 pwr--; 2464 } 2465} 2466 2467/* Write PCDAC values on hw */ 2468static void 2469ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2470{ 2471 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2472 int i; 2473 2474 /* 2475 * Write TX power values 2476 */ 2477 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2478 ath5k_hw_reg_write(ah, 2479 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2480 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2481 AR5K_PHY_PCDAC_TXPOWER(i)); 2482 } 2483} 2484 2485 2486/* 2487 * Power to PDADC table functions 2488 */ 2489 2490/* 2491 * Set the gain boundaries and create final Power to PDADC table 2492 * 2493 * We can have up to 4 pd curves, we need to do a simmilar process 2494 * as we do for RF5112. This time we don't have an edge_flag but we 2495 * set the gain boundaries on a separate register. 2496 */ 2497static void 2498ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2499 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2500{ 2501 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2502 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2503 u8 *pdadc_tmp; 2504 s16 pdadc_0; 2505 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2506 u8 pd_gain_overlap; 2507 2508 /* Note: Register value is initialized on initvals 2509 * there is no feedback from hw. 2510 * XXX: What about pd_gain_overlap from EEPROM ? */ 2511 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2512 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2513 2514 /* Create final PDADC table */ 2515 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2516 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2517 2518 if (pdg == pdcurves - 1) 2519 /* 2 dB boundary stretch for last 2520 * (higher power) curve */ 2521 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2522 else 2523 /* Set gain boundary in the middle 2524 * between this curve and the next one */ 2525 gain_boundaries[pdg] = 2526 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2527 2528 /* Sanity check in case our 2 db stretch got out of 2529 * range. */ 2530 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2531 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2532 2533 /* For the first curve (lower power) 2534 * start from 0 dB */ 2535 if (pdg == 0) 2536 pdadc_0 = 0; 2537 else 2538 /* For the other curves use the gain overlap */ 2539 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2540 pd_gain_overlap; 2541 2542 /* Force each power step to be at least 0.5 dB */ 2543 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2544 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2545 else 2546 pwr_step = 1; 2547 2548 /* If pdadc_0 is negative, we need to extrapolate 2549 * below this pdgain by a number of pwr_steps */ 2550 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2551 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2552 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2553 pdadc_0++; 2554 } 2555 2556 /* Set last pwr level, using gain boundaries */ 2557 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2558 /* Limit it to be inside pwr range */ 2559 table_size = pwr_max[pdg] - pwr_min[pdg]; 2560 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2561 2562 /* Fill pdadc_out table */ 2563 while (pdadc_0 < max_idx && pdadc_i < 128) 2564 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2565 2566 /* Need to extrapolate above this pdgain? */ 2567 if (pdadc_n <= max_idx) 2568 continue; 2569 2570 /* Force each power step to be at least 0.5 dB */ 2571 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2572 pwr_step = pdadc_tmp[table_size - 1] - 2573 pdadc_tmp[table_size - 2]; 2574 else 2575 pwr_step = 1; 2576 2577 /* Extrapolate above */ 2578 while ((pdadc_0 < (s16) pdadc_n) && 2579 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2580 s16 tmp = pdadc_tmp[table_size - 1] + 2581 (pdadc_0 - max_idx) * pwr_step; 2582 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2583 pdadc_0++; 2584 } 2585 } 2586 2587 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2588 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2589 pdg++; 2590 } 2591 2592 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2593 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2594 pdadc_i++; 2595 } 2596 2597 /* Set gain boundaries */ 2598 ath5k_hw_reg_write(ah, 2599 AR5K_REG_SM(pd_gain_overlap, 2600 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2601 AR5K_REG_SM(gain_boundaries[0], 2602 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2603 AR5K_REG_SM(gain_boundaries[1], 2604 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2605 AR5K_REG_SM(gain_boundaries[2], 2606 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2607 AR5K_REG_SM(gain_boundaries[3], 2608 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2609 AR5K_PHY_TPC_RG5); 2610 2611 /* Used for setting rate power table */ 2612 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2613 2614} 2615 2616/* Write PDADC values on hw */ 2617static void 2618ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2619 u8 pdcurves, u8 *pdg_to_idx) 2620{ 2621 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2622 u32 reg; 2623 u8 i; 2624 2625 /* Select the right pdgain curves */ 2626 2627 /* Clear current settings */ 2628 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2629 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2630 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2631 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2632 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2633 2634 /* 2635 * Use pd_gains curve from eeprom 2636 * 2637 * This overrides the default setting from initvals 2638 * in case some vendors (e.g. Zcomax) don't use the default 2639 * curves. If we don't honor their settings we 'll get a 2640 * 5dB (1 * gain overlap ?) drop. 2641 */ 2642 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2643 2644 switch (pdcurves) { 2645 case 3: 2646 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2647 /* Fall through */ 2648 case 2: 2649 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2650 /* Fall through */ 2651 case 1: 2652 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2653 break; 2654 } 2655 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2656 2657 /* 2658 * Write TX power values 2659 */ 2660 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2661 ath5k_hw_reg_write(ah, 2662 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2663 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2664 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2665 ((pdadc_out[4*i + 3] & 0xff) << 24), 2666 AR5K_PHY_PDADC_TXPOWER(i)); 2667 } 2668} 2669 2670 2671/* 2672 * Common code for PCDAC/PDADC tables 2673 */ 2674 2675/* 2676 * This is the main function that uses all of the above 2677 * to set PCDAC/PDADC table on hw for the current channel. 2678 * This table is used for tx power calibration on the basband, 2679 * without it we get weird tx power levels and in some cases 2680 * distorted spectral mask 2681 */ 2682static int 2683ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2684 struct ieee80211_channel *channel, 2685 u8 ee_mode, u8 type) 2686{ 2687 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2688 struct ath5k_chan_pcal_info *pcinfo_L; 2689 struct ath5k_chan_pcal_info *pcinfo_R; 2690 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2691 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2692 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2693 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2694 u8 *tmpL; 2695 u8 *tmpR; 2696 u32 target = channel->center_freq; 2697 int pdg, i; 2698 2699 /* Get surounding freq piers for this channel */ 2700 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2701 &pcinfo_L, 2702 &pcinfo_R); 2703 2704 /* Loop over pd gain curves on 2705 * surounding freq piers by index */ 2706 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2707 2708 /* Fill curves in reverse order 2709 * from lower power (max gain) 2710 * to higher power. Use curve -> idx 2711 * backmapping we did on eeprom init */ 2712 u8 idx = pdg_curve_to_idx[pdg]; 2713 2714 /* Grab the needed curves by index */ 2715 pdg_L = &pcinfo_L->pd_curves[idx]; 2716 pdg_R = &pcinfo_R->pd_curves[idx]; 2717 2718 /* Initialize the temp tables */ 2719 tmpL = ah->ah_txpower.tmpL[pdg]; 2720 tmpR = ah->ah_txpower.tmpR[pdg]; 2721 2722 /* Set curve's x boundaries and create 2723 * curves so that they cover the same 2724 * range (if we don't do that one table 2725 * will have values on some range and the 2726 * other one won't have any so interpolation 2727 * will fail) */ 2728 table_min[pdg] = min(pdg_L->pd_pwr[0], 2729 pdg_R->pd_pwr[0]) / 2; 2730 2731 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2732 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2733 2734 /* Now create the curves on surrounding channels 2735 * and interpolate if needed to get the final 2736 * curve for this gain on this channel */ 2737 switch (type) { 2738 case AR5K_PWRTABLE_LINEAR_PCDAC: 2739 /* Override min/max so that we don't loose 2740 * accuracy (don't divide by 2) */ 2741 table_min[pdg] = min(pdg_L->pd_pwr[0], 2742 pdg_R->pd_pwr[0]); 2743 2744 table_max[pdg] = 2745 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2746 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2747 2748 /* Override minimum so that we don't get 2749 * out of bounds while extrapolating 2750 * below. Don't do this when we have 2 2751 * curves and we are on the high power curve 2752 * because table_min is ok in this case */ 2753 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2754 2755 table_min[pdg] = 2756 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2757 pdg_R->pd_step, 2758 pdg_L->pd_pwr, 2759 pdg_R->pd_pwr); 2760 2761 /* Don't go too low because we will 2762 * miss the upper part of the curve. 2763 * Note: 126 = 31.5dB (max power supported) 2764 * in 0.25dB units */ 2765 if (table_max[pdg] - table_min[pdg] > 126) 2766 table_min[pdg] = table_max[pdg] - 126; 2767 } 2768 2769 /* Fall through */ 2770 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2771 case AR5K_PWRTABLE_PWR_TO_PDADC: 2772 2773 ath5k_create_power_curve(table_min[pdg], 2774 table_max[pdg], 2775 pdg_L->pd_pwr, 2776 pdg_L->pd_step, 2777 pdg_L->pd_points, tmpL, type); 2778 2779 /* We are in a calibration 2780 * pier, no need to interpolate 2781 * between freq piers */ 2782 if (pcinfo_L == pcinfo_R) 2783 continue; 2784 2785 ath5k_create_power_curve(table_min[pdg], 2786 table_max[pdg], 2787 pdg_R->pd_pwr, 2788 pdg_R->pd_step, 2789 pdg_R->pd_points, tmpR, type); 2790 break; 2791 default: 2792 return -EINVAL; 2793 } 2794 2795 /* Interpolate between curves 2796 * of surounding freq piers to 2797 * get the final curve for this 2798 * pd gain. Re-use tmpL for interpolation 2799 * output */ 2800 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2801 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2802 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2803 (s16) pcinfo_L->freq, 2804 (s16) pcinfo_R->freq, 2805 (s16) tmpL[i], 2806 (s16) tmpR[i]); 2807 } 2808 } 2809 2810 /* Now we have a set of curves for this 2811 * channel on tmpL (x range is table_max - table_min 2812 * and y values are tmpL[pdg][]) sorted in the same 2813 * order as EEPROM (because we've used the backmapping). 2814 * So for RF5112 it's from higher power to lower power 2815 * and for RF2413 it's from lower power to higher power. 2816 * For RF5111 we only have one curve. */ 2817 2818 /* Fill min and max power levels for this 2819 * channel by interpolating the values on 2820 * surounding channels to complete the dataset */ 2821 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2822 (s16) pcinfo_L->freq, 2823 (s16) pcinfo_R->freq, 2824 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2825 2826 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2827 (s16) pcinfo_L->freq, 2828 (s16) pcinfo_R->freq, 2829 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2830 2831 /* We are ready to go, fill PCDAC/PDADC 2832 * table and write settings on hardware */ 2833 switch (type) { 2834 case AR5K_PWRTABLE_LINEAR_PCDAC: 2835 /* For RF5112 we can have one or two curves 2836 * and each curve covers a certain power lvl 2837 * range so we need to do some more processing */ 2838 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2839 ee->ee_pd_gains[ee_mode]); 2840 2841 /* Set txp.offset so that we can 2842 * match max power value with max 2843 * table index */ 2844 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2845 2846 /* Write settings on hw */ 2847 ath5k_setup_pcdac_table(ah); 2848 break; 2849 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2850 /* We are done for RF5111 since it has only 2851 * one curve, just fit the curve on the table */ 2852 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2853 2854 /* No rate powertable adjustment for RF5111 */ 2855 ah->ah_txpower.txp_min_idx = 0; 2856 ah->ah_txpower.txp_offset = 0; 2857 2858 /* Write settings on hw */ 2859 ath5k_setup_pcdac_table(ah); 2860 break; 2861 case AR5K_PWRTABLE_PWR_TO_PDADC: 2862 /* Set PDADC boundaries and fill 2863 * final PDADC table */ 2864 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2865 ee->ee_pd_gains[ee_mode]); 2866 2867 /* Write settings on hw */ 2868 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2869 2870 /* Set txp.offset, note that table_min 2871 * can be negative */ 2872 ah->ah_txpower.txp_offset = table_min[0]; 2873 break; 2874 default: 2875 return -EINVAL; 2876 } 2877 2878 return 0; 2879} 2880 2881 2882/* 2883 * Per-rate tx power setting 2884 * 2885 * This is the code that sets the desired tx power (below 2886 * maximum) on hw for each rate (we also have TPC that sets 2887 * power per packet). We do that by providing an index on the 2888 * PCDAC/PDADC table we set up. 2889 */ 2890 2891/* 2892 * Set rate power table 2893 * 2894 * For now we only limit txpower based on maximum tx power 2895 * supported by hw (what's inside rate_info). We need to limit 2896 * this even more, based on regulatory domain etc. 2897 * 2898 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2899 * and is indexed as follows: 2900 * rates[0] - rates[7] -> OFDM rates 2901 * rates[8] - rates[14] -> CCK rates 2902 * rates[15] -> XR rates (they all have the same power) 2903 */ 2904static void 2905ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2906 struct ath5k_rate_pcal_info *rate_info, 2907 u8 ee_mode) 2908{ 2909 unsigned int i; 2910 u16 *rates; 2911 2912 /* max_pwr is power level we got from driver/user in 0.5dB 2913 * units, switch to 0.25dB units so we can compare */ 2914 max_pwr *= 2; 2915 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2916 2917 /* apply rate limits */ 2918 rates = ah->ah_txpower.txp_rates_power_table; 2919 2920 /* OFDM rates 6 to 24Mb/s */ 2921 for (i = 0; i < 5; i++) 2922 rates[i] = min(max_pwr, rate_info->target_power_6to24); 2923 2924 /* Rest OFDM rates */ 2925 rates[5] = min(rates[0], rate_info->target_power_36); 2926 rates[6] = min(rates[0], rate_info->target_power_48); 2927 rates[7] = min(rates[0], rate_info->target_power_54); 2928 2929 /* CCK rates */ 2930 /* 1L */ 2931 rates[8] = min(rates[0], rate_info->target_power_6to24); 2932 /* 2L */ 2933 rates[9] = min(rates[0], rate_info->target_power_36); 2934 /* 2S */ 2935 rates[10] = min(rates[0], rate_info->target_power_36); 2936 /* 5L */ 2937 rates[11] = min(rates[0], rate_info->target_power_48); 2938 /* 5S */ 2939 rates[12] = min(rates[0], rate_info->target_power_48); 2940 /* 11L */ 2941 rates[13] = min(rates[0], rate_info->target_power_54); 2942 /* 11S */ 2943 rates[14] = min(rates[0], rate_info->target_power_54); 2944 2945 /* XR rates */ 2946 rates[15] = min(rates[0], rate_info->target_power_6to24); 2947 2948 /* CCK rates have different peak to average ratio 2949 * so we have to tweak their power so that gainf 2950 * correction works ok. For this we use OFDM to 2951 * CCK delta from eeprom */ 2952 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 2953 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 2954 for (i = 8; i <= 15; i++) 2955 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 2956 2957 /* Now that we have all rates setup use table offset to 2958 * match the power range set by user with the power indices 2959 * on PCDAC/PDADC table */ 2960 for (i = 0; i < 16; i++) { 2961 rates[i] += ah->ah_txpower.txp_offset; 2962 /* Don't get out of bounds */ 2963 if (rates[i] > 63) 2964 rates[i] = 63; 2965 } 2966 2967 /* Min/max in 0.25dB units */ 2968 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 2969 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 2970 ah->ah_txpower.txp_ofdm = rates[7]; 2971} 2972 2973 2974/* 2975 * Set transmition power 2976 */ 2977int 2978ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 2979 u8 ee_mode, u8 txpower) 2980{ 2981 struct ath5k_rate_pcal_info rate_info; 2982 u8 type; 2983 int ret; 2984 2985 ATH5K_TRACE(ah->ah_sc); 2986 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2987 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 2988 return -EINVAL; 2989 } 2990 2991 /* Reset TX power values */ 2992 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 2993 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 2994 ah->ah_txpower.txp_min_pwr = 0; 2995 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 2996 2997 /* Initialize TX power table */ 2998 switch (ah->ah_radio) { 2999 case AR5K_RF5111: 3000 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3001 break; 3002 case AR5K_RF5112: 3003 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3004 break; 3005 case AR5K_RF2413: 3006 case AR5K_RF5413: 3007 case AR5K_RF2316: 3008 case AR5K_RF2317: 3009 case AR5K_RF2425: 3010 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3011 break; 3012 default: 3013 return -EINVAL; 3014 } 3015 3016 /* FIXME: Only on channel/mode change */ 3017 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 3018 if (ret) 3019 return ret; 3020 3021 /* Limit max power if we have a CTL available */ 3022 ath5k_get_max_ctl_power(ah, channel); 3023 3024 /* FIXME: Tx power limit for this regdomain 3025 * XXX: Mac80211/CRDA will do that anyway ? */ 3026 3027 /* FIXME: Antenna reduction stuff */ 3028 3029 /* FIXME: Limit power on turbo modes */ 3030 3031 /* FIXME: TPC scale reduction */ 3032 3033 /* Get surounding channels for per-rate power table 3034 * calibration */ 3035 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3036 3037 /* Setup rate power table */ 3038 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3039 3040 /* Write rate power table on hw */ 3041 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3042 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3043 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3044 3045 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3046 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3047 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3048 3049 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3050 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3051 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3052 3053 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3054 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3055 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3056 3057 /* FIXME: TPC support */ 3058 if (ah->ah_txpower.txp_tpc) { 3059 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3060 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3061 3062 ath5k_hw_reg_write(ah, 3063 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3064 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3065 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3066 AR5K_TPC); 3067 } else { 3068 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3069 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3070 } 3071 3072 return 0; 3073} 3074 3075int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3076{ 3077 /*Just a try M.F.*/ 3078 struct ieee80211_channel *channel = ah->ah_current_channel; 3079 u8 ee_mode; 3080 3081 ATH5K_TRACE(ah->ah_sc); 3082 3083 switch (channel->hw_value & CHANNEL_MODES) { 3084 case CHANNEL_A: 3085 case CHANNEL_T: 3086 case CHANNEL_XR: 3087 ee_mode = AR5K_EEPROM_MODE_11A; 3088 break; 3089 case CHANNEL_G: 3090 case CHANNEL_TG: 3091 ee_mode = AR5K_EEPROM_MODE_11G; 3092 break; 3093 case CHANNEL_B: 3094 ee_mode = AR5K_EEPROM_MODE_11B; 3095 break; 3096 default: 3097 ATH5K_ERR(ah->ah_sc, 3098 "invalid channel: %d\n", channel->center_freq); 3099 return -EINVAL; 3100 } 3101 3102 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3103 "changing txpower to %d\n", txpower); 3104 3105 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3106} 3107