phy.c revision b2b4c69f682a2868411899a77842061dd745884f
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32 33/******************\ 34* Helper functions * 35\******************/ 36 37/* 38 * Get the PHY Chip revision 39 */ 40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41{ 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81} 82 83/* 84 * Check if a channel is supported 85 */ 86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87{ 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99} 100 101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103{ 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119} 120 121/* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127{ 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200} 201 202/** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219{ 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 /* TODO: Half/quarter rate */ 232 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40; 233 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 234 235 /* Get exponent 236 * ALGO: coef_exp = 14 - highest set bit position */ 237 coef_exp = ilog2(coef_scaled); 238 239 /* Doesn't make sense if it's zero*/ 240 if (!coef_scaled || !coef_exp) 241 return -EINVAL; 242 243 /* Note: we've shifted coef_scaled by 24 */ 244 coef_exp = 14 - (coef_exp - 24); 245 246 247 /* Get mantissa (significant digits) 248 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 249 coef_man = coef_scaled + 250 (1 << (24 - coef_exp - 1)); 251 252 /* Calculate delta slope coefficient exponent 253 * and mantissa (remove scaling) and set them on hw */ 254 ds_coef_man = coef_man >> (24 - coef_exp); 255 ds_coef_exp = coef_exp - 16; 256 257 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 258 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 259 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 260 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 261 262 return 0; 263} 264 265int ath5k_hw_phy_disable(struct ath5k_hw *ah) 266{ 267 /*Just a try M.F.*/ 268 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 269 270 return 0; 271} 272 273 274/**********************\ 275* RF Gain optimization * 276\**********************/ 277 278/* 279 * This code is used to optimize RF gain on different environments 280 * (temperature mostly) based on feedback from a power detector. 281 * 282 * It's only used on RF5111 and RF5112, later RF chips seem to have 283 * auto adjustment on hw -notice they have a much smaller BANK 7 and 284 * no gain optimization ladder-. 285 * 286 * For more infos check out this patent doc 287 * http://www.freepatentsonline.com/7400691.html 288 * 289 * This paper describes power drops as seen on the receiver due to 290 * probe packets 291 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 292 * %20of%20Power%20Control.pdf 293 * 294 * And this is the MadWiFi bug entry related to the above 295 * http://madwifi-project.org/ticket/1659 296 * with various measurements and diagrams 297 * 298 * TODO: Deal with power drops due to probes by setting an apropriate 299 * tx power on the probe packets ! Make this part of the calibration process. 300 */ 301 302/* Initialize ah_gain durring attach */ 303int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 304{ 305 /* Initialize the gain optimization values */ 306 switch (ah->ah_radio) { 307 case AR5K_RF5111: 308 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 309 ah->ah_gain.g_low = 20; 310 ah->ah_gain.g_high = 35; 311 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 312 break; 313 case AR5K_RF5112: 314 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 315 ah->ah_gain.g_low = 20; 316 ah->ah_gain.g_high = 85; 317 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 318 break; 319 default: 320 return -EINVAL; 321 } 322 323 return 0; 324} 325 326/* Schedule a gain probe check on the next transmited packet. 327 * That means our next packet is going to be sent with lower 328 * tx power and a Peak to Average Power Detector (PAPD) will try 329 * to measure the gain. 330 * 331 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 332 * just after we enable the probe so that we don't mess with 333 * standard traffic ? Maybe it's time to use sw interrupts and 334 * a probe tasklet !!! 335 */ 336static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 337{ 338 339 /* Skip if gain calibration is inactive or 340 * we already handle a probe request */ 341 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 342 return; 343 344 /* Send the packet with 2dB below max power as 345 * patent doc suggest */ 346 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 347 AR5K_PHY_PAPD_PROBE_TXPOWER) | 348 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 349 350 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 351 352} 353 354/* Calculate gain_F measurement correction 355 * based on the current step for RF5112 rev. 2 */ 356static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 357{ 358 u32 mix, step; 359 u32 *rf; 360 const struct ath5k_gain_opt *go; 361 const struct ath5k_gain_opt_step *g_step; 362 const struct ath5k_rf_reg *rf_regs; 363 364 /* Only RF5112 Rev. 2 supports it */ 365 if ((ah->ah_radio != AR5K_RF5112) || 366 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 367 return 0; 368 369 go = &rfgain_opt_5112; 370 rf_regs = rf_regs_5112a; 371 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 372 373 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 374 375 if (ah->ah_rf_banks == NULL) 376 return 0; 377 378 rf = ah->ah_rf_banks; 379 ah->ah_gain.g_f_corr = 0; 380 381 /* No VGA (Variable Gain Amplifier) override, skip */ 382 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 383 return 0; 384 385 /* Mix gain stepping */ 386 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 387 388 /* Mix gain override */ 389 mix = g_step->gos_param[0]; 390 391 switch (mix) { 392 case 3: 393 ah->ah_gain.g_f_corr = step * 2; 394 break; 395 case 2: 396 ah->ah_gain.g_f_corr = (step - 5) * 2; 397 break; 398 case 1: 399 ah->ah_gain.g_f_corr = step; 400 break; 401 default: 402 ah->ah_gain.g_f_corr = 0; 403 break; 404 } 405 406 return ah->ah_gain.g_f_corr; 407} 408 409/* Check if current gain_F measurement is in the range of our 410 * power detector windows. If we get a measurement outside range 411 * we know it's not accurate (detectors can't measure anything outside 412 * their detection window) so we must ignore it */ 413static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 414{ 415 const struct ath5k_rf_reg *rf_regs; 416 u32 step, mix_ovr, level[4]; 417 u32 *rf; 418 419 if (ah->ah_rf_banks == NULL) 420 return false; 421 422 rf = ah->ah_rf_banks; 423 424 if (ah->ah_radio == AR5K_RF5111) { 425 426 rf_regs = rf_regs_5111; 427 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 428 429 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 430 false); 431 432 level[0] = 0; 433 level[1] = (step == 63) ? 50 : step + 4; 434 level[2] = (step != 63) ? 64 : level[0]; 435 level[3] = level[2] + 50 ; 436 437 ah->ah_gain.g_high = level[3] - 438 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 439 ah->ah_gain.g_low = level[0] + 440 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 441 } else { 442 443 rf_regs = rf_regs_5112; 444 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 445 446 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 447 false); 448 449 level[0] = level[2] = 0; 450 451 if (mix_ovr == 1) { 452 level[1] = level[3] = 83; 453 } else { 454 level[1] = level[3] = 107; 455 ah->ah_gain.g_high = 55; 456 } 457 } 458 459 return (ah->ah_gain.g_current >= level[0] && 460 ah->ah_gain.g_current <= level[1]) || 461 (ah->ah_gain.g_current >= level[2] && 462 ah->ah_gain.g_current <= level[3]); 463} 464 465/* Perform gain_F adjustment by choosing the right set 466 * of parameters from RF gain optimization ladder */ 467static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 468{ 469 const struct ath5k_gain_opt *go; 470 const struct ath5k_gain_opt_step *g_step; 471 int ret = 0; 472 473 switch (ah->ah_radio) { 474 case AR5K_RF5111: 475 go = &rfgain_opt_5111; 476 break; 477 case AR5K_RF5112: 478 go = &rfgain_opt_5112; 479 break; 480 default: 481 return 0; 482 } 483 484 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 485 486 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 487 488 /* Reached maximum */ 489 if (ah->ah_gain.g_step_idx == 0) 490 return -1; 491 492 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 493 ah->ah_gain.g_target >= ah->ah_gain.g_high && 494 ah->ah_gain.g_step_idx > 0; 495 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 496 ah->ah_gain.g_target -= 2 * 497 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 498 g_step->gos_gain); 499 500 ret = 1; 501 goto done; 502 } 503 504 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 505 506 /* Reached minimum */ 507 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 508 return -2; 509 510 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 511 ah->ah_gain.g_target <= ah->ah_gain.g_low && 512 ah->ah_gain.g_step_idx < go->go_steps_count-1; 513 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 514 ah->ah_gain.g_target -= 2 * 515 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 516 g_step->gos_gain); 517 518 ret = 2; 519 goto done; 520 } 521 522done: 523 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 524 "ret %d, gain step %u, current gain %u, target gain %u\n", 525 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 526 ah->ah_gain.g_target); 527 528 return ret; 529} 530 531/* Main callback for thermal RF gain calibration engine 532 * Check for a new gain reading and schedule an adjustment 533 * if needed. 534 * 535 * TODO: Use sw interrupt to schedule reset if gain_F needs 536 * adjustment */ 537enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 538{ 539 u32 data, type; 540 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 541 542 if (ah->ah_rf_banks == NULL || 543 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 544 return AR5K_RFGAIN_INACTIVE; 545 546 /* No check requested, either engine is inactive 547 * or an adjustment is already requested */ 548 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 549 goto done; 550 551 /* Read the PAPD (Peak to Average Power Detector) 552 * register */ 553 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 554 555 /* No probe is scheduled, read gain_F measurement */ 556 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 557 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 558 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 559 560 /* If tx packet is CCK correct the gain_F measurement 561 * by cck ofdm gain delta */ 562 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 563 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 564 ah->ah_gain.g_current += 565 ee->ee_cck_ofdm_gain_delta; 566 else 567 ah->ah_gain.g_current += 568 AR5K_GAIN_CCK_PROBE_CORR; 569 } 570 571 /* Further correct gain_F measurement for 572 * RF5112A radios */ 573 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 574 ath5k_hw_rf_gainf_corr(ah); 575 ah->ah_gain.g_current = 576 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 577 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 578 0; 579 } 580 581 /* Check if measurement is ok and if we need 582 * to adjust gain, schedule a gain adjustment, 583 * else switch back to the acive state */ 584 if (ath5k_hw_rf_check_gainf_readback(ah) && 585 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 586 ath5k_hw_rf_gainf_adjust(ah)) { 587 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 588 } else { 589 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 590 } 591 } 592 593done: 594 return ah->ah_gain.g_state; 595} 596 597/* Write initial RF gain table to set the RF sensitivity 598 * this one works on all RF chips and has nothing to do 599 * with gain_F calibration */ 600static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 601{ 602 const struct ath5k_ini_rfgain *ath5k_rfg; 603 unsigned int i, size; 604 605 switch (ah->ah_radio) { 606 case AR5K_RF5111: 607 ath5k_rfg = rfgain_5111; 608 size = ARRAY_SIZE(rfgain_5111); 609 break; 610 case AR5K_RF5112: 611 ath5k_rfg = rfgain_5112; 612 size = ARRAY_SIZE(rfgain_5112); 613 break; 614 case AR5K_RF2413: 615 ath5k_rfg = rfgain_2413; 616 size = ARRAY_SIZE(rfgain_2413); 617 break; 618 case AR5K_RF2316: 619 ath5k_rfg = rfgain_2316; 620 size = ARRAY_SIZE(rfgain_2316); 621 break; 622 case AR5K_RF5413: 623 ath5k_rfg = rfgain_5413; 624 size = ARRAY_SIZE(rfgain_5413); 625 break; 626 case AR5K_RF2317: 627 case AR5K_RF2425: 628 ath5k_rfg = rfgain_2425; 629 size = ARRAY_SIZE(rfgain_2425); 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 switch (freq) { 636 case AR5K_INI_RFGAIN_2GHZ: 637 case AR5K_INI_RFGAIN_5GHZ: 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 for (i = 0; i < size; i++) { 644 AR5K_REG_WAIT(i); 645 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 646 (u32)ath5k_rfg[i].rfg_register); 647 } 648 649 return 0; 650} 651 652 653 654/********************\ 655* RF Registers setup * 656\********************/ 657 658/* 659 * Setup RF registers by writing RF buffer on hw 660 */ 661static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 662 struct ieee80211_channel *channel, unsigned int mode) 663{ 664 const struct ath5k_rf_reg *rf_regs; 665 const struct ath5k_ini_rfbuffer *ini_rfb; 666 const struct ath5k_gain_opt *go = NULL; 667 const struct ath5k_gain_opt_step *g_step; 668 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 669 u8 ee_mode = 0; 670 u32 *rfb; 671 int i, obdb = -1, bank = -1; 672 673 switch (ah->ah_radio) { 674 case AR5K_RF5111: 675 rf_regs = rf_regs_5111; 676 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 677 ini_rfb = rfb_5111; 678 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 679 go = &rfgain_opt_5111; 680 break; 681 case AR5K_RF5112: 682 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 683 rf_regs = rf_regs_5112a; 684 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 685 ini_rfb = rfb_5112a; 686 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 687 } else { 688 rf_regs = rf_regs_5112; 689 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 690 ini_rfb = rfb_5112; 691 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 692 } 693 go = &rfgain_opt_5112; 694 break; 695 case AR5K_RF2413: 696 rf_regs = rf_regs_2413; 697 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 698 ini_rfb = rfb_2413; 699 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 700 break; 701 case AR5K_RF2316: 702 rf_regs = rf_regs_2316; 703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 704 ini_rfb = rfb_2316; 705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 706 break; 707 case AR5K_RF5413: 708 rf_regs = rf_regs_5413; 709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 710 ini_rfb = rfb_5413; 711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 712 break; 713 case AR5K_RF2317: 714 rf_regs = rf_regs_2425; 715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 716 ini_rfb = rfb_2317; 717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 718 break; 719 case AR5K_RF2425: 720 rf_regs = rf_regs_2425; 721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 722 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 723 ini_rfb = rfb_2425; 724 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 725 } else { 726 ini_rfb = rfb_2417; 727 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 728 } 729 break; 730 default: 731 return -EINVAL; 732 } 733 734 /* If it's the first time we set RF buffer, allocate 735 * ah->ah_rf_banks based on ah->ah_rf_banks_size 736 * we set above */ 737 if (ah->ah_rf_banks == NULL) { 738 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 739 GFP_KERNEL); 740 if (ah->ah_rf_banks == NULL) { 741 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 742 return -ENOMEM; 743 } 744 } 745 746 /* Copy values to modify them */ 747 rfb = ah->ah_rf_banks; 748 749 for (i = 0; i < ah->ah_rf_banks_size; i++) { 750 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 751 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 752 return -EINVAL; 753 } 754 755 /* Bank changed, write down the offset */ 756 if (bank != ini_rfb[i].rfb_bank) { 757 bank = ini_rfb[i].rfb_bank; 758 ah->ah_offset[bank] = i; 759 } 760 761 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 762 } 763 764 /* Set Output and Driver bias current (OB/DB) */ 765 if (channel->hw_value & CHANNEL_2GHZ) { 766 767 if (channel->hw_value & CHANNEL_CCK) 768 ee_mode = AR5K_EEPROM_MODE_11B; 769 else 770 ee_mode = AR5K_EEPROM_MODE_11G; 771 772 /* For RF511X/RF211X combination we 773 * use b_OB and b_DB parameters stored 774 * in eeprom on ee->ee_ob[ee_mode][0] 775 * 776 * For all other chips we use OB/DB for 2Ghz 777 * stored in the b/g modal section just like 778 * 802.11a on ee->ee_ob[ee_mode][1] */ 779 if ((ah->ah_radio == AR5K_RF5111) || 780 (ah->ah_radio == AR5K_RF5112)) 781 obdb = 0; 782 else 783 obdb = 1; 784 785 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 786 AR5K_RF_OB_2GHZ, true); 787 788 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 789 AR5K_RF_DB_2GHZ, true); 790 791 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 792 } else if ((channel->hw_value & CHANNEL_5GHZ) || 793 (ah->ah_radio == AR5K_RF5111)) { 794 795 /* For 11a, Turbo and XR we need to choose 796 * OB/DB based on frequency range */ 797 ee_mode = AR5K_EEPROM_MODE_11A; 798 obdb = channel->center_freq >= 5725 ? 3 : 799 (channel->center_freq >= 5500 ? 2 : 800 (channel->center_freq >= 5260 ? 1 : 801 (channel->center_freq > 4000 ? 0 : -1))); 802 803 if (obdb < 0) 804 return -EINVAL; 805 806 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 807 AR5K_RF_OB_5GHZ, true); 808 809 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 810 AR5K_RF_DB_5GHZ, true); 811 } 812 813 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 814 815 /* Bank Modifications (chip-specific) */ 816 if (ah->ah_radio == AR5K_RF5111) { 817 818 /* Set gain_F settings according to current step */ 819 if (channel->hw_value & CHANNEL_OFDM) { 820 821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 822 AR5K_PHY_FRAME_CTL_TX_CLIP, 823 g_step->gos_param[0]); 824 825 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 826 AR5K_RF_PWD_90, true); 827 828 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 829 AR5K_RF_PWD_84, true); 830 831 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 832 AR5K_RF_RFGAIN_SEL, true); 833 834 /* We programmed gain_F parameters, switch back 835 * to active state */ 836 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 837 838 } 839 840 /* Bank 6/7 setup */ 841 842 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 843 AR5K_RF_PWD_XPD, true); 844 845 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 846 AR5K_RF_XPD_GAIN, true); 847 848 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 849 AR5K_RF_GAIN_I, true); 850 851 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 852 AR5K_RF_PLO_SEL, true); 853 854 /* Tweak power detectors for half/quarter rate support */ 855 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 856 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 857 u8 wait_i; 858 859 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 860 AR5K_RF_WAIT_S, true); 861 862 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 863 0x1f : 0x10; 864 865 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 866 AR5K_RF_WAIT_I, true); 867 ath5k_hw_rfb_op(ah, rf_regs, 3, 868 AR5K_RF_MAX_TIME, true); 869 870 } 871 } 872 873 if (ah->ah_radio == AR5K_RF5112) { 874 875 /* Set gain_F settings according to current step */ 876 if (channel->hw_value & CHANNEL_OFDM) { 877 878 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 879 AR5K_RF_MIXGAIN_OVR, true); 880 881 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 882 AR5K_RF_PWD_138, true); 883 884 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 885 AR5K_RF_PWD_137, true); 886 887 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 888 AR5K_RF_PWD_136, true); 889 890 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 891 AR5K_RF_PWD_132, true); 892 893 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 894 AR5K_RF_PWD_131, true); 895 896 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 897 AR5K_RF_PWD_130, true); 898 899 /* We programmed gain_F parameters, switch back 900 * to active state */ 901 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 902 } 903 904 /* Bank 6/7 setup */ 905 906 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 907 AR5K_RF_XPD_SEL, true); 908 909 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 910 /* Rev. 1 supports only one xpd */ 911 ath5k_hw_rfb_op(ah, rf_regs, 912 ee->ee_x_gain[ee_mode], 913 AR5K_RF_XPD_GAIN, true); 914 915 } else { 916 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 917 if (ee->ee_pd_gains[ee_mode] > 1) { 918 ath5k_hw_rfb_op(ah, rf_regs, 919 pdg_curve_to_idx[0], 920 AR5K_RF_PD_GAIN_LO, true); 921 ath5k_hw_rfb_op(ah, rf_regs, 922 pdg_curve_to_idx[1], 923 AR5K_RF_PD_GAIN_HI, true); 924 } else { 925 ath5k_hw_rfb_op(ah, rf_regs, 926 pdg_curve_to_idx[0], 927 AR5K_RF_PD_GAIN_LO, true); 928 ath5k_hw_rfb_op(ah, rf_regs, 929 pdg_curve_to_idx[0], 930 AR5K_RF_PD_GAIN_HI, true); 931 } 932 933 /* Lower synth voltage on Rev 2 */ 934 ath5k_hw_rfb_op(ah, rf_regs, 2, 935 AR5K_RF_HIGH_VC_CP, true); 936 937 ath5k_hw_rfb_op(ah, rf_regs, 2, 938 AR5K_RF_MID_VC_CP, true); 939 940 ath5k_hw_rfb_op(ah, rf_regs, 2, 941 AR5K_RF_LOW_VC_CP, true); 942 943 ath5k_hw_rfb_op(ah, rf_regs, 2, 944 AR5K_RF_PUSH_UP, true); 945 946 /* Decrease power consumption on 5213+ BaseBand */ 947 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 948 ath5k_hw_rfb_op(ah, rf_regs, 1, 949 AR5K_RF_PAD2GND, true); 950 951 ath5k_hw_rfb_op(ah, rf_regs, 1, 952 AR5K_RF_XB2_LVL, true); 953 954 ath5k_hw_rfb_op(ah, rf_regs, 1, 955 AR5K_RF_XB5_LVL, true); 956 957 ath5k_hw_rfb_op(ah, rf_regs, 1, 958 AR5K_RF_PWD_167, true); 959 960 ath5k_hw_rfb_op(ah, rf_regs, 1, 961 AR5K_RF_PWD_166, true); 962 } 963 } 964 965 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 966 AR5K_RF_GAIN_I, true); 967 968 /* Tweak power detector for half/quarter rates */ 969 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 970 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 971 u8 pd_delay; 972 973 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 974 0xf : 0x8; 975 976 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 977 AR5K_RF_PD_PERIOD_A, true); 978 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 979 AR5K_RF_PD_DELAY_A, true); 980 981 } 982 } 983 984 if (ah->ah_radio == AR5K_RF5413 && 985 channel->hw_value & CHANNEL_2GHZ) { 986 987 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 988 true); 989 990 /* Set optimum value for early revisions (on pci-e chips) */ 991 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 992 ah->ah_mac_srev < AR5K_SREV_AR5413) 993 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 994 AR5K_RF_PWD_ICLOBUF_2G, true); 995 996 } 997 998 /* Write RF banks on hw */ 999 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1000 AR5K_REG_WAIT(i); 1001 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1002 } 1003 1004 return 0; 1005} 1006 1007 1008/**************************\ 1009 PHY/RF channel functions 1010\**************************/ 1011 1012/* 1013 * Convertion needed for RF5110 1014 */ 1015static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1016{ 1017 u32 athchan; 1018 1019 /* 1020 * Convert IEEE channel/MHz to an internal channel value used 1021 * by the AR5210 chipset. This has not been verified with 1022 * newer chipsets like the AR5212A who have a completely 1023 * different RF/PHY part. 1024 */ 1025 athchan = (ath5k_hw_bitswap( 1026 (ieee80211_frequency_to_channel( 1027 channel->center_freq) - 24) / 2, 5) 1028 << 1) | (1 << 6) | 0x1; 1029 return athchan; 1030} 1031 1032/* 1033 * Set channel on RF5110 1034 */ 1035static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1036 struct ieee80211_channel *channel) 1037{ 1038 u32 data; 1039 1040 /* 1041 * Set the channel and wait 1042 */ 1043 data = ath5k_hw_rf5110_chan2athchan(channel); 1044 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1045 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1046 mdelay(1); 1047 1048 return 0; 1049} 1050 1051/* 1052 * Convertion needed for 5111 1053 */ 1054static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1055 struct ath5k_athchan_2ghz *athchan) 1056{ 1057 int channel; 1058 1059 /* Cast this value to catch negative channel numbers (>= -19) */ 1060 channel = (int)ieee; 1061 1062 /* 1063 * Map 2GHz IEEE channel to 5GHz Atheros channel 1064 */ 1065 if (channel <= 13) { 1066 athchan->a2_athchan = 115 + channel; 1067 athchan->a2_flags = 0x46; 1068 } else if (channel == 14) { 1069 athchan->a2_athchan = 124; 1070 athchan->a2_flags = 0x44; 1071 } else if (channel >= 15 && channel <= 26) { 1072 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1073 athchan->a2_flags = 0x46; 1074 } else 1075 return -EINVAL; 1076 1077 return 0; 1078} 1079 1080/* 1081 * Set channel on 5111 1082 */ 1083static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1084 struct ieee80211_channel *channel) 1085{ 1086 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1087 unsigned int ath5k_channel = 1088 ieee80211_frequency_to_channel(channel->center_freq); 1089 u32 data0, data1, clock; 1090 int ret; 1091 1092 /* 1093 * Set the channel on the RF5111 radio 1094 */ 1095 data0 = data1 = 0; 1096 1097 if (channel->hw_value & CHANNEL_2GHZ) { 1098 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1099 ret = ath5k_hw_rf5111_chan2athchan( 1100 ieee80211_frequency_to_channel(channel->center_freq), 1101 &ath5k_channel_2ghz); 1102 if (ret) 1103 return ret; 1104 1105 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1106 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1107 << 5) | (1 << 4); 1108 } 1109 1110 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1111 clock = 1; 1112 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1113 (clock << 1) | (1 << 10) | 1; 1114 } else { 1115 clock = 0; 1116 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1117 << 2) | (clock << 1) | (1 << 10) | 1; 1118 } 1119 1120 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1121 AR5K_RF_BUFFER); 1122 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1123 AR5K_RF_BUFFER_CONTROL_3); 1124 1125 return 0; 1126} 1127 1128/* 1129 * Set channel on 5112 and newer 1130 */ 1131static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1132 struct ieee80211_channel *channel) 1133{ 1134 u32 data, data0, data1, data2; 1135 u16 c; 1136 1137 data = data0 = data1 = data2 = 0; 1138 c = channel->center_freq; 1139 1140 if (c < 4800) { 1141 if (!((c - 2224) % 5)) { 1142 data0 = ((2 * (c - 704)) - 3040) / 10; 1143 data1 = 1; 1144 } else if (!((c - 2192) % 5)) { 1145 data0 = ((2 * (c - 672)) - 3040) / 10; 1146 data1 = 0; 1147 } else 1148 return -EINVAL; 1149 1150 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1151 } else if ((c % 5) != 2 || c > 5435) { 1152 if (!(c % 20) && c >= 5120) { 1153 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1154 data2 = ath5k_hw_bitswap(3, 2); 1155 } else if (!(c % 10)) { 1156 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1157 data2 = ath5k_hw_bitswap(2, 2); 1158 } else if (!(c % 5)) { 1159 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1160 data2 = ath5k_hw_bitswap(1, 2); 1161 } else 1162 return -EINVAL; 1163 } else { 1164 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1165 data2 = ath5k_hw_bitswap(0, 2); 1166 } 1167 1168 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1169 1170 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1171 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1172 1173 return 0; 1174} 1175 1176/* 1177 * Set the channel on the RF2425 1178 */ 1179static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1180 struct ieee80211_channel *channel) 1181{ 1182 u32 data, data0, data2; 1183 u16 c; 1184 1185 data = data0 = data2 = 0; 1186 c = channel->center_freq; 1187 1188 if (c < 4800) { 1189 data0 = ath5k_hw_bitswap((c - 2272), 8); 1190 data2 = 0; 1191 /* ? 5GHz ? */ 1192 } else if ((c % 5) != 2 || c > 5435) { 1193 if (!(c % 20) && c < 5120) 1194 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1195 else if (!(c % 10)) 1196 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1197 else if (!(c % 5)) 1198 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1199 else 1200 return -EINVAL; 1201 data2 = ath5k_hw_bitswap(1, 2); 1202 } else { 1203 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1204 data2 = ath5k_hw_bitswap(0, 2); 1205 } 1206 1207 data = (data0 << 4) | data2 << 2 | 0x1001; 1208 1209 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1210 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1211 1212 return 0; 1213} 1214 1215/* 1216 * Set a channel on the radio chip 1217 */ 1218static int ath5k_hw_channel(struct ath5k_hw *ah, 1219 struct ieee80211_channel *channel) 1220{ 1221 int ret; 1222 /* 1223 * Check bounds supported by the PHY (we don't care about regultory 1224 * restrictions at this point). Note: hw_value already has the band 1225 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1226 * of the band by that */ 1227 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1228 ATH5K_ERR(ah->ah_sc, 1229 "channel frequency (%u MHz) out of supported " 1230 "band range\n", 1231 channel->center_freq); 1232 return -EINVAL; 1233 } 1234 1235 /* 1236 * Set the channel and wait 1237 */ 1238 switch (ah->ah_radio) { 1239 case AR5K_RF5110: 1240 ret = ath5k_hw_rf5110_channel(ah, channel); 1241 break; 1242 case AR5K_RF5111: 1243 ret = ath5k_hw_rf5111_channel(ah, channel); 1244 break; 1245 case AR5K_RF2425: 1246 ret = ath5k_hw_rf2425_channel(ah, channel); 1247 break; 1248 default: 1249 ret = ath5k_hw_rf5112_channel(ah, channel); 1250 break; 1251 } 1252 1253 if (ret) 1254 return ret; 1255 1256 /* Set JAPAN setting for channel 14 */ 1257 if (channel->center_freq == 2484) { 1258 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1259 AR5K_PHY_CCKTXCTL_JAPAN); 1260 } else { 1261 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1262 AR5K_PHY_CCKTXCTL_WORLD); 1263 } 1264 1265 ah->ah_current_channel = channel; 1266 1267 return 0; 1268} 1269 1270/*****************\ 1271 PHY calibration 1272\*****************/ 1273 1274static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1275{ 1276 s32 val; 1277 1278 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1279 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1280} 1281 1282void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1283{ 1284 int i; 1285 1286 ah->ah_nfcal_hist.index = 0; 1287 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1288 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1289} 1290 1291static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1292{ 1293 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1294 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1295 hist->nfval[hist->index] = noise_floor; 1296} 1297 1298static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1299{ 1300 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1301 s16 tmp; 1302 int i, j; 1303 1304 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1305 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1306 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1307 if (sort[j] > sort[j-1]) { 1308 tmp = sort[j]; 1309 sort[j] = sort[j-1]; 1310 sort[j-1] = tmp; 1311 } 1312 } 1313 } 1314 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1315 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1316 "cal %d:%d\n", i, sort[i]); 1317 } 1318 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1319} 1320 1321/* 1322 * When we tell the hardware to perform a noise floor calibration 1323 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1324 * sample-and-hold the minimum noise level seen at the antennas. 1325 * This value is then stored in a ring buffer of recently measured 1326 * noise floor values so we have a moving window of the last few 1327 * samples. 1328 * 1329 * The median of the values in the history is then loaded into the 1330 * hardware for its own use for RSSI and CCA measurements. 1331 */ 1332void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1333{ 1334 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1335 u32 val; 1336 s16 nf, threshold; 1337 u8 ee_mode; 1338 1339 /* keep last value if calibration hasn't completed */ 1340 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1341 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1342 "NF did not complete in calibration window\n"); 1343 1344 return; 1345 } 1346 1347 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) { 1348 case CHANNEL_A: 1349 case CHANNEL_T: 1350 case CHANNEL_XR: 1351 ee_mode = AR5K_EEPROM_MODE_11A; 1352 break; 1353 case CHANNEL_G: 1354 case CHANNEL_TG: 1355 ee_mode = AR5K_EEPROM_MODE_11G; 1356 break; 1357 default: 1358 case CHANNEL_B: 1359 ee_mode = AR5K_EEPROM_MODE_11B; 1360 break; 1361 } 1362 1363 1364 /* completed NF calibration, test threshold */ 1365 nf = ath5k_hw_read_measured_noise_floor(ah); 1366 threshold = ee->ee_noise_floor_thr[ee_mode]; 1367 1368 if (nf > threshold) { 1369 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1370 "noise floor failure detected; " 1371 "read %d, threshold %d\n", 1372 nf, threshold); 1373 1374 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1375 } 1376 1377 ath5k_hw_update_nfcal_hist(ah, nf); 1378 nf = ath5k_hw_get_median_noise_floor(ah); 1379 1380 /* load noise floor (in .5 dBm) so the hardware will use it */ 1381 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1382 val |= (nf * 2) & AR5K_PHY_NF_M; 1383 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1384 1385 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1386 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1387 1388 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1389 0, false); 1390 1391 /* 1392 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1393 * so that we're not capped by the median we just loaded. 1394 * This will be used as the initial value for the next noise 1395 * floor calibration. 1396 */ 1397 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1398 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1399 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1400 AR5K_PHY_AGCCTL_NF_EN | 1401 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1402 AR5K_PHY_AGCCTL_NF); 1403 1404 ah->ah_noise_floor = nf; 1405 1406 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1407 "noise floor calibrated: %d\n", nf); 1408} 1409 1410/* 1411 * Perform a PHY calibration on RF5110 1412 * -Fix BPSK/QAM Constellation (I/Q correction) 1413 */ 1414static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1415 struct ieee80211_channel *channel) 1416{ 1417 u32 phy_sig, phy_agc, phy_sat, beacon; 1418 int ret; 1419 1420 /* 1421 * Disable beacons and RX/TX queues, wait 1422 */ 1423 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1424 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1425 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1426 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1427 1428 mdelay(2); 1429 1430 /* 1431 * Set the channel (with AGC turned off) 1432 */ 1433 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1434 udelay(10); 1435 ret = ath5k_hw_channel(ah, channel); 1436 1437 /* 1438 * Activate PHY and wait 1439 */ 1440 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1441 mdelay(1); 1442 1443 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1444 1445 if (ret) 1446 return ret; 1447 1448 /* 1449 * Calibrate the radio chip 1450 */ 1451 1452 /* Remember normal state */ 1453 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1454 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1455 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1456 1457 /* Update radio registers */ 1458 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1459 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1460 1461 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1462 AR5K_PHY_AGCCOARSE_LO)) | 1463 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1464 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1465 1466 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1467 AR5K_PHY_ADCSAT_THR)) | 1468 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1469 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1470 1471 udelay(20); 1472 1473 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1474 udelay(10); 1475 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1476 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1477 1478 mdelay(1); 1479 1480 /* 1481 * Enable calibration and wait until completion 1482 */ 1483 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1484 1485 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1486 AR5K_PHY_AGCCTL_CAL, 0, false); 1487 1488 /* Reset to normal state */ 1489 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1490 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1491 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1492 1493 if (ret) { 1494 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1495 channel->center_freq); 1496 return ret; 1497 } 1498 1499 /* 1500 * Re-enable RX/TX and beacons 1501 */ 1502 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1503 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1504 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1505 1506 return 0; 1507} 1508 1509/* 1510 * Perform I/Q calibration on RF5111/5112 and newer chips 1511 */ 1512static int 1513ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1514{ 1515 u32 i_pwr, q_pwr; 1516 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1517 int i; 1518 1519 if (!ah->ah_calibration || 1520 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1521 return 0; 1522 1523 /* Calibration has finished, get the results and re-run */ 1524 /* work around empty results which can apparently happen on 5212 */ 1525 for (i = 0; i <= 10; i++) { 1526 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1527 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1528 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1529 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1530 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1531 if (i_pwr && q_pwr) 1532 break; 1533 } 1534 1535 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1536 1537 if (ah->ah_version == AR5K_AR5211) 1538 q_coffd = q_pwr >> 6; 1539 else 1540 q_coffd = q_pwr >> 7; 1541 1542 /* protect against divide by 0 and loss of sign bits */ 1543 if (i_coffd == 0 || q_coffd < 2) 1544 return 0; 1545 1546 i_coff = (-iq_corr) / i_coffd; 1547 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1548 1549 if (ah->ah_version == AR5K_AR5211) 1550 q_coff = (i_pwr / q_coffd) - 64; 1551 else 1552 q_coff = (i_pwr / q_coffd) - 128; 1553 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1554 1555 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1556 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1557 i_coff, q_coff, i_coffd, q_coffd); 1558 1559 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1560 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1561 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1562 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1563 1564 /* Re-enable calibration -if we don't we'll commit 1565 * the same values again and again */ 1566 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1567 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1568 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1569 1570 return 0; 1571} 1572 1573/* 1574 * Perform a PHY calibration 1575 */ 1576int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1577 struct ieee80211_channel *channel) 1578{ 1579 int ret; 1580 1581 if (ah->ah_radio == AR5K_RF5110) 1582 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1583 else { 1584 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1585 ath5k_hw_request_rfgain_probe(ah); 1586 } 1587 1588 return ret; 1589} 1590 1591 1592/***************************\ 1593* Spur mitigation functions * 1594\***************************/ 1595 1596static void 1597ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1598 struct ieee80211_channel *channel) 1599{ 1600 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1601 u32 mag_mask[4] = {0, 0, 0, 0}; 1602 u32 pilot_mask[2] = {0, 0}; 1603 /* Note: fbin values are scaled up by 2 */ 1604 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1605 s32 spur_delta_phase, spur_freq_sigma_delta; 1606 s32 spur_offset, num_symbols_x16; 1607 u8 num_symbol_offsets, i, freq_band; 1608 1609 /* Convert current frequency to fbin value (the same way channels 1610 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1611 * up by 2 so we can compare it later */ 1612 if (channel->hw_value & CHANNEL_2GHZ) { 1613 chan_fbin = (channel->center_freq - 2300) * 10; 1614 freq_band = AR5K_EEPROM_BAND_2GHZ; 1615 } else { 1616 chan_fbin = (channel->center_freq - 4900) * 10; 1617 freq_band = AR5K_EEPROM_BAND_5GHZ; 1618 } 1619 1620 /* Check if any spur_chan_fbin from EEPROM is 1621 * within our current channel's spur detection range */ 1622 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1623 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1624 /* XXX: Half/Quarter channels ?*/ 1625 if (channel->hw_value & CHANNEL_TURBO) 1626 spur_detection_window *= 2; 1627 1628 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1629 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1630 1631 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1632 * so it's zero if we got nothing from EEPROM */ 1633 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1634 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1635 break; 1636 } 1637 1638 if ((chan_fbin - spur_detection_window <= 1639 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1640 (chan_fbin + spur_detection_window >= 1641 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1642 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1643 break; 1644 } 1645 } 1646 1647 /* We need to enable spur filter for this channel */ 1648 if (spur_chan_fbin) { 1649 spur_offset = spur_chan_fbin - chan_fbin; 1650 /* 1651 * Calculate deltas: 1652 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1653 * spur_delta_phase -> spur_offset / chip_freq << 11 1654 * Note: Both values have 100KHz resolution 1655 */ 1656 /* XXX: Half/Quarter rate channels ? */ 1657 switch (channel->hw_value) { 1658 case CHANNEL_A: 1659 /* Both sample_freq and chip_freq are 40MHz */ 1660 spur_delta_phase = (spur_offset << 17) / 25; 1661 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1662 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1663 break; 1664 case CHANNEL_G: 1665 /* sample_freq -> 40MHz chip_freq -> 44MHz 1666 * (for b compatibility) */ 1667 spur_freq_sigma_delta = (spur_offset << 8) / 55; 1668 spur_delta_phase = (spur_offset << 17) / 25; 1669 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1670 break; 1671 case CHANNEL_T: 1672 case CHANNEL_TG: 1673 /* Both sample_freq and chip_freq are 80MHz */ 1674 spur_delta_phase = (spur_offset << 16) / 25; 1675 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1676 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz; 1677 break; 1678 default: 1679 return; 1680 } 1681 1682 /* Calculate pilot and magnitude masks */ 1683 1684 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1685 * and divide by symbol_width to find how many symbols we have 1686 * Note: number of symbols is scaled up by 16 */ 1687 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1688 1689 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1690 if (!(num_symbols_x16 & 0xF)) 1691 /* _X_ */ 1692 num_symbol_offsets = 3; 1693 else 1694 /* _xx_ */ 1695 num_symbol_offsets = 4; 1696 1697 for (i = 0; i < num_symbol_offsets; i++) { 1698 1699 /* Calculate pilot mask */ 1700 s32 curr_sym_off = 1701 (num_symbols_x16 / 16) + i + 25; 1702 1703 /* Pilot magnitude mask seems to be a way to 1704 * declare the boundaries for our detection 1705 * window or something, it's 2 for the middle 1706 * value(s) where the symbol is expected to be 1707 * and 1 on the boundary values */ 1708 u8 plt_mag_map = 1709 (i == 0 || i == (num_symbol_offsets - 1)) 1710 ? 1 : 2; 1711 1712 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1713 if (curr_sym_off <= 25) 1714 pilot_mask[0] |= 1 << curr_sym_off; 1715 else if (curr_sym_off >= 27) 1716 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1717 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1718 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1719 1720 /* Calculate magnitude mask (for viterbi decoder) */ 1721 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1722 mag_mask[0] |= 1723 plt_mag_map << (curr_sym_off + 1) * 2; 1724 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1725 mag_mask[1] |= 1726 plt_mag_map << (curr_sym_off - 15) * 2; 1727 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1728 mag_mask[2] |= 1729 plt_mag_map << (curr_sym_off - 31) * 2; 1730 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1731 mag_mask[3] |= 1732 plt_mag_map << (curr_sym_off - 47) * 2; 1733 1734 } 1735 1736 /* Write settings on hw to enable spur filter */ 1737 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1738 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1739 /* XXX: Self correlator also ? */ 1740 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1741 AR5K_PHY_IQ_PILOT_MASK_EN | 1742 AR5K_PHY_IQ_CHAN_MASK_EN | 1743 AR5K_PHY_IQ_SPUR_FILT_EN); 1744 1745 /* Set delta phase and freq sigma delta */ 1746 ath5k_hw_reg_write(ah, 1747 AR5K_REG_SM(spur_delta_phase, 1748 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1749 AR5K_REG_SM(spur_freq_sigma_delta, 1750 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1751 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1752 AR5K_PHY_TIMING_11); 1753 1754 /* Write pilot masks */ 1755 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1756 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1757 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1758 pilot_mask[1]); 1759 1760 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1761 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1762 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1763 pilot_mask[1]); 1764 1765 /* Write magnitude masks */ 1766 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1767 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1768 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1769 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1770 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1771 mag_mask[3]); 1772 1773 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1774 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1775 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1776 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1777 AR5K_PHY_BIN_MASK2_4_MASK_4, 1778 mag_mask[3]); 1779 1780 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1781 AR5K_PHY_IQ_SPUR_FILT_EN) { 1782 /* Clean up spur mitigation settings and disable fliter */ 1783 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1784 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1785 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1786 AR5K_PHY_IQ_PILOT_MASK_EN | 1787 AR5K_PHY_IQ_CHAN_MASK_EN | 1788 AR5K_PHY_IQ_SPUR_FILT_EN); 1789 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1790 1791 /* Clear pilot masks */ 1792 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1793 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1794 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1795 0); 1796 1797 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1798 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1799 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1800 0); 1801 1802 /* Clear magnitude masks */ 1803 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1804 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1805 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1806 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1807 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1808 0); 1809 1810 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1811 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1812 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1814 AR5K_PHY_BIN_MASK2_4_MASK_4, 1815 0); 1816 } 1817} 1818 1819 1820/*****************\ 1821* Antenna control * 1822\*****************/ 1823 1824static void /*TODO:Boundary check*/ 1825ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1826{ 1827 if (ah->ah_version != AR5K_AR5210) 1828 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1829} 1830 1831/* 1832 * Enable/disable fast rx antenna diversity 1833 */ 1834static void 1835ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1836{ 1837 switch (ee_mode) { 1838 case AR5K_EEPROM_MODE_11G: 1839 /* XXX: This is set to 1840 * disabled on initvals !!! */ 1841 case AR5K_EEPROM_MODE_11A: 1842 if (enable) 1843 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1844 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1845 else 1846 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1847 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1848 break; 1849 case AR5K_EEPROM_MODE_11B: 1850 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1851 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1852 break; 1853 default: 1854 return; 1855 } 1856 1857 if (enable) { 1858 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1859 AR5K_PHY_RESTART_DIV_GC, 4); 1860 1861 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1862 AR5K_PHY_FAST_ANT_DIV_EN); 1863 } else { 1864 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1865 AR5K_PHY_RESTART_DIV_GC, 0); 1866 1867 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1868 AR5K_PHY_FAST_ANT_DIV_EN); 1869 } 1870} 1871 1872void 1873ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1874{ 1875 u8 ant0, ant1; 1876 1877 /* 1878 * In case a fixed antenna was set as default 1879 * use the same switch table twice. 1880 */ 1881 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1882 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1883 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1884 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1885 else { 1886 ant0 = AR5K_ANT_SWTABLE_A; 1887 ant1 = AR5K_ANT_SWTABLE_B; 1888 } 1889 1890 /* Set antenna idle switch table */ 1891 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1892 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1893 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1894 AR5K_PHY_ANT_CTL_TXRX_EN)); 1895 1896 /* Set antenna switch tables */ 1897 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1898 AR5K_PHY_ANT_SWITCH_TABLE_0); 1899 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1900 AR5K_PHY_ANT_SWITCH_TABLE_1); 1901} 1902 1903/* 1904 * Set antenna operating mode 1905 */ 1906void 1907ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1908{ 1909 struct ieee80211_channel *channel = ah->ah_current_channel; 1910 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1911 bool use_def_for_sg; 1912 u8 def_ant, tx_ant, ee_mode; 1913 u32 sta_id1 = 0; 1914 1915 /* if channel is not initialized yet we can't set the antennas 1916 * so just store the mode. it will be set on the next reset */ 1917 if (channel == NULL) { 1918 ah->ah_ant_mode = ant_mode; 1919 return; 1920 } 1921 1922 def_ant = ah->ah_def_ant; 1923 1924 switch (channel->hw_value & CHANNEL_MODES) { 1925 case CHANNEL_A: 1926 case CHANNEL_T: 1927 case CHANNEL_XR: 1928 ee_mode = AR5K_EEPROM_MODE_11A; 1929 break; 1930 case CHANNEL_G: 1931 case CHANNEL_TG: 1932 ee_mode = AR5K_EEPROM_MODE_11G; 1933 break; 1934 case CHANNEL_B: 1935 ee_mode = AR5K_EEPROM_MODE_11B; 1936 break; 1937 default: 1938 ATH5K_ERR(ah->ah_sc, 1939 "invalid channel: %d\n", channel->center_freq); 1940 return; 1941 } 1942 1943 switch (ant_mode) { 1944 case AR5K_ANTMODE_DEFAULT: 1945 tx_ant = 0; 1946 use_def_for_tx = false; 1947 update_def_on_tx = false; 1948 use_def_for_rts = false; 1949 use_def_for_sg = false; 1950 fast_div = true; 1951 break; 1952 case AR5K_ANTMODE_FIXED_A: 1953 def_ant = 1; 1954 tx_ant = 1; 1955 use_def_for_tx = true; 1956 update_def_on_tx = false; 1957 use_def_for_rts = true; 1958 use_def_for_sg = true; 1959 fast_div = false; 1960 break; 1961 case AR5K_ANTMODE_FIXED_B: 1962 def_ant = 2; 1963 tx_ant = 2; 1964 use_def_for_tx = true; 1965 update_def_on_tx = false; 1966 use_def_for_rts = true; 1967 use_def_for_sg = true; 1968 fast_div = false; 1969 break; 1970 case AR5K_ANTMODE_SINGLE_AP: 1971 def_ant = 1; /* updated on tx */ 1972 tx_ant = 0; 1973 use_def_for_tx = true; 1974 update_def_on_tx = true; 1975 use_def_for_rts = true; 1976 use_def_for_sg = true; 1977 fast_div = true; 1978 break; 1979 case AR5K_ANTMODE_SECTOR_AP: 1980 tx_ant = 1; /* variable */ 1981 use_def_for_tx = false; 1982 update_def_on_tx = false; 1983 use_def_for_rts = true; 1984 use_def_for_sg = false; 1985 fast_div = false; 1986 break; 1987 case AR5K_ANTMODE_SECTOR_STA: 1988 tx_ant = 1; /* variable */ 1989 use_def_for_tx = true; 1990 update_def_on_tx = false; 1991 use_def_for_rts = true; 1992 use_def_for_sg = false; 1993 fast_div = true; 1994 break; 1995 case AR5K_ANTMODE_DEBUG: 1996 def_ant = 1; 1997 tx_ant = 2; 1998 use_def_for_tx = false; 1999 update_def_on_tx = false; 2000 use_def_for_rts = false; 2001 use_def_for_sg = false; 2002 fast_div = false; 2003 break; 2004 default: 2005 return; 2006 } 2007 2008 ah->ah_tx_ant = tx_ant; 2009 ah->ah_ant_mode = ant_mode; 2010 ah->ah_def_ant = def_ant; 2011 2012 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2013 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2014 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2015 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2016 2017 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2018 2019 if (sta_id1) 2020 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2021 2022 ath5k_hw_set_antenna_switch(ah, ee_mode); 2023 /* Note: set diversity before default antenna 2024 * because it won't work correctly */ 2025 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2026 ath5k_hw_set_def_antenna(ah, def_ant); 2027} 2028 2029 2030/****************\ 2031* TX power setup * 2032\****************/ 2033 2034/* 2035 * Helper functions 2036 */ 2037 2038/* 2039 * Do linear interpolation between two given (x, y) points 2040 */ 2041static s16 2042ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2043 s16 y_left, s16 y_right) 2044{ 2045 s16 ratio, result; 2046 2047 /* Avoid divide by zero and skip interpolation 2048 * if we have the same point */ 2049 if ((x_left == x_right) || (y_left == y_right)) 2050 return y_left; 2051 2052 /* 2053 * Since we use ints and not fps, we need to scale up in 2054 * order to get a sane ratio value (or else we 'll eg. get 2055 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2056 * to have some accuracy both for 0.5 and 0.25 steps. 2057 */ 2058 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2059 2060 /* Now scale down to be in range */ 2061 result = y_left + (ratio * (target - x_left) / 100); 2062 2063 return result; 2064} 2065 2066/* 2067 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2068 * 2069 * Since we have the top of the curve and we draw the line below 2070 * until we reach 1 (1 pcdac step) we need to know which point 2071 * (x value) that is so that we don't go below y axis and have negative 2072 * pcdac values when creating the curve, or fill the table with zeroes. 2073 */ 2074static s16 2075ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2076 const s16 *pwrL, const s16 *pwrR) 2077{ 2078 s8 tmp; 2079 s16 min_pwrL, min_pwrR; 2080 s16 pwr_i; 2081 2082 /* Some vendors write the same pcdac value twice !!! */ 2083 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2084 return max(pwrL[0], pwrR[0]); 2085 2086 if (pwrL[0] == pwrL[1]) 2087 min_pwrL = pwrL[0]; 2088 else { 2089 pwr_i = pwrL[0]; 2090 do { 2091 pwr_i--; 2092 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2093 pwrL[0], pwrL[1], 2094 stepL[0], stepL[1]); 2095 } while (tmp > 1); 2096 2097 min_pwrL = pwr_i; 2098 } 2099 2100 if (pwrR[0] == pwrR[1]) 2101 min_pwrR = pwrR[0]; 2102 else { 2103 pwr_i = pwrR[0]; 2104 do { 2105 pwr_i--; 2106 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2107 pwrR[0], pwrR[1], 2108 stepR[0], stepR[1]); 2109 } while (tmp > 1); 2110 2111 min_pwrR = pwr_i; 2112 } 2113 2114 /* Keep the right boundary so that it works for both curves */ 2115 return max(min_pwrL, min_pwrR); 2116} 2117 2118/* 2119 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2120 * Power to PCDAC curve. 2121 * 2122 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2123 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2124 * PCDAC/PDADC step for each curve is 64 but we can write more than 2125 * one curves on hw so we can go up to 128 (which is the max step we 2126 * can write on the final table). 2127 * 2128 * We write y values (PCDAC/PDADC steps) on hw. 2129 */ 2130static void 2131ath5k_create_power_curve(s16 pmin, s16 pmax, 2132 const s16 *pwr, const u8 *vpd, 2133 u8 num_points, 2134 u8 *vpd_table, u8 type) 2135{ 2136 u8 idx[2] = { 0, 1 }; 2137 s16 pwr_i = 2*pmin; 2138 int i; 2139 2140 if (num_points < 2) 2141 return; 2142 2143 /* We want the whole line, so adjust boundaries 2144 * to cover the entire power range. Note that 2145 * power values are already 0.25dB so no need 2146 * to multiply pwr_i by 2 */ 2147 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2148 pwr_i = pmin; 2149 pmin = 0; 2150 pmax = 63; 2151 } 2152 2153 /* Find surrounding turning points (TPs) 2154 * and interpolate between them */ 2155 for (i = 0; (i <= (u16) (pmax - pmin)) && 2156 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2157 2158 /* We passed the right TP, move to the next set of TPs 2159 * if we pass the last TP, extrapolate above using the last 2160 * two TPs for ratio */ 2161 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2162 idx[0]++; 2163 idx[1]++; 2164 } 2165 2166 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2167 pwr[idx[0]], pwr[idx[1]], 2168 vpd[idx[0]], vpd[idx[1]]); 2169 2170 /* Increase by 0.5dB 2171 * (0.25 dB units) */ 2172 pwr_i += 2; 2173 } 2174} 2175 2176/* 2177 * Get the surrounding per-channel power calibration piers 2178 * for a given frequency so that we can interpolate between 2179 * them and come up with an apropriate dataset for our current 2180 * channel. 2181 */ 2182static void 2183ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2184 struct ieee80211_channel *channel, 2185 struct ath5k_chan_pcal_info **pcinfo_l, 2186 struct ath5k_chan_pcal_info **pcinfo_r) 2187{ 2188 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2189 struct ath5k_chan_pcal_info *pcinfo; 2190 u8 idx_l, idx_r; 2191 u8 mode, max, i; 2192 u32 target = channel->center_freq; 2193 2194 idx_l = 0; 2195 idx_r = 0; 2196 2197 if (!(channel->hw_value & CHANNEL_OFDM)) { 2198 pcinfo = ee->ee_pwr_cal_b; 2199 mode = AR5K_EEPROM_MODE_11B; 2200 } else if (channel->hw_value & CHANNEL_2GHZ) { 2201 pcinfo = ee->ee_pwr_cal_g; 2202 mode = AR5K_EEPROM_MODE_11G; 2203 } else { 2204 pcinfo = ee->ee_pwr_cal_a; 2205 mode = AR5K_EEPROM_MODE_11A; 2206 } 2207 max = ee->ee_n_piers[mode] - 1; 2208 2209 /* Frequency is below our calibrated 2210 * range. Use the lowest power curve 2211 * we have */ 2212 if (target < pcinfo[0].freq) { 2213 idx_l = idx_r = 0; 2214 goto done; 2215 } 2216 2217 /* Frequency is above our calibrated 2218 * range. Use the highest power curve 2219 * we have */ 2220 if (target > pcinfo[max].freq) { 2221 idx_l = idx_r = max; 2222 goto done; 2223 } 2224 2225 /* Frequency is inside our calibrated 2226 * channel range. Pick the surrounding 2227 * calibration piers so that we can 2228 * interpolate */ 2229 for (i = 0; i <= max; i++) { 2230 2231 /* Frequency matches one of our calibration 2232 * piers, no need to interpolate, just use 2233 * that calibration pier */ 2234 if (pcinfo[i].freq == target) { 2235 idx_l = idx_r = i; 2236 goto done; 2237 } 2238 2239 /* We found a calibration pier that's above 2240 * frequency, use this pier and the previous 2241 * one to interpolate */ 2242 if (target < pcinfo[i].freq) { 2243 idx_r = i; 2244 idx_l = idx_r - 1; 2245 goto done; 2246 } 2247 } 2248 2249done: 2250 *pcinfo_l = &pcinfo[idx_l]; 2251 *pcinfo_r = &pcinfo[idx_r]; 2252} 2253 2254/* 2255 * Get the surrounding per-rate power calibration data 2256 * for a given frequency and interpolate between power 2257 * values to set max target power supported by hw for 2258 * each rate. 2259 */ 2260static void 2261ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2262 struct ieee80211_channel *channel, 2263 struct ath5k_rate_pcal_info *rates) 2264{ 2265 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2266 struct ath5k_rate_pcal_info *rpinfo; 2267 u8 idx_l, idx_r; 2268 u8 mode, max, i; 2269 u32 target = channel->center_freq; 2270 2271 idx_l = 0; 2272 idx_r = 0; 2273 2274 if (!(channel->hw_value & CHANNEL_OFDM)) { 2275 rpinfo = ee->ee_rate_tpwr_b; 2276 mode = AR5K_EEPROM_MODE_11B; 2277 } else if (channel->hw_value & CHANNEL_2GHZ) { 2278 rpinfo = ee->ee_rate_tpwr_g; 2279 mode = AR5K_EEPROM_MODE_11G; 2280 } else { 2281 rpinfo = ee->ee_rate_tpwr_a; 2282 mode = AR5K_EEPROM_MODE_11A; 2283 } 2284 max = ee->ee_rate_target_pwr_num[mode] - 1; 2285 2286 /* Get the surrounding calibration 2287 * piers - same as above */ 2288 if (target < rpinfo[0].freq) { 2289 idx_l = idx_r = 0; 2290 goto done; 2291 } 2292 2293 if (target > rpinfo[max].freq) { 2294 idx_l = idx_r = max; 2295 goto done; 2296 } 2297 2298 for (i = 0; i <= max; i++) { 2299 2300 if (rpinfo[i].freq == target) { 2301 idx_l = idx_r = i; 2302 goto done; 2303 } 2304 2305 if (target < rpinfo[i].freq) { 2306 idx_r = i; 2307 idx_l = idx_r - 1; 2308 goto done; 2309 } 2310 } 2311 2312done: 2313 /* Now interpolate power value, based on the frequency */ 2314 rates->freq = target; 2315 2316 rates->target_power_6to24 = 2317 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2318 rpinfo[idx_r].freq, 2319 rpinfo[idx_l].target_power_6to24, 2320 rpinfo[idx_r].target_power_6to24); 2321 2322 rates->target_power_36 = 2323 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2324 rpinfo[idx_r].freq, 2325 rpinfo[idx_l].target_power_36, 2326 rpinfo[idx_r].target_power_36); 2327 2328 rates->target_power_48 = 2329 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2330 rpinfo[idx_r].freq, 2331 rpinfo[idx_l].target_power_48, 2332 rpinfo[idx_r].target_power_48); 2333 2334 rates->target_power_54 = 2335 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2336 rpinfo[idx_r].freq, 2337 rpinfo[idx_l].target_power_54, 2338 rpinfo[idx_r].target_power_54); 2339} 2340 2341/* 2342 * Get the max edge power for this channel if 2343 * we have such data from EEPROM's Conformance Test 2344 * Limits (CTL), and limit max power if needed. 2345 */ 2346static void 2347ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2348 struct ieee80211_channel *channel) 2349{ 2350 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2351 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2352 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2353 u8 *ctl_val = ee->ee_ctl; 2354 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2355 s16 edge_pwr = 0; 2356 u8 rep_idx; 2357 u8 i, ctl_mode; 2358 u8 ctl_idx = 0xFF; 2359 u32 target = channel->center_freq; 2360 2361 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2362 2363 switch (channel->hw_value & CHANNEL_MODES) { 2364 case CHANNEL_A: 2365 ctl_mode |= AR5K_CTL_11A; 2366 break; 2367 case CHANNEL_G: 2368 ctl_mode |= AR5K_CTL_11G; 2369 break; 2370 case CHANNEL_B: 2371 ctl_mode |= AR5K_CTL_11B; 2372 break; 2373 case CHANNEL_T: 2374 ctl_mode |= AR5K_CTL_TURBO; 2375 break; 2376 case CHANNEL_TG: 2377 ctl_mode |= AR5K_CTL_TURBOG; 2378 break; 2379 case CHANNEL_XR: 2380 /* Fall through */ 2381 default: 2382 return; 2383 } 2384 2385 for (i = 0; i < ee->ee_ctls; i++) { 2386 if (ctl_val[i] == ctl_mode) { 2387 ctl_idx = i; 2388 break; 2389 } 2390 } 2391 2392 /* If we have a CTL dataset available grab it and find the 2393 * edge power for our frequency */ 2394 if (ctl_idx == 0xFF) 2395 return; 2396 2397 /* Edge powers are sorted by frequency from lower 2398 * to higher. Each CTL corresponds to 8 edge power 2399 * measurements. */ 2400 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2401 2402 /* Don't do boundaries check because we 2403 * might have more that one bands defined 2404 * for this mode */ 2405 2406 /* Get the edge power that's closer to our 2407 * frequency */ 2408 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2409 rep_idx += i; 2410 if (target <= rep[rep_idx].freq) 2411 edge_pwr = (s16) rep[rep_idx].edge; 2412 } 2413 2414 if (edge_pwr) 2415 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2416} 2417 2418 2419/* 2420 * Power to PCDAC table functions 2421 */ 2422 2423/* 2424 * Fill Power to PCDAC table on RF5111 2425 * 2426 * No further processing is needed for RF5111, the only thing we have to 2427 * do is fill the values below and above calibration range since eeprom data 2428 * may not cover the entire PCDAC table. 2429 */ 2430static void 2431ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2432 s16 *table_max) 2433{ 2434 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2435 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2436 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2437 s16 min_pwr, max_pwr; 2438 2439 /* Get table boundaries */ 2440 min_pwr = table_min[0]; 2441 pcdac_0 = pcdac_tmp[0]; 2442 2443 max_pwr = table_max[0]; 2444 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2445 2446 /* Extrapolate below minimum using pcdac_0 */ 2447 pcdac_i = 0; 2448 for (i = 0; i < min_pwr; i++) 2449 pcdac_out[pcdac_i++] = pcdac_0; 2450 2451 /* Copy values from pcdac_tmp */ 2452 pwr_idx = min_pwr; 2453 for (i = 0 ; pwr_idx <= max_pwr && 2454 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2455 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2456 pwr_idx++; 2457 } 2458 2459 /* Extrapolate above maximum */ 2460 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2461 pcdac_out[pcdac_i++] = pcdac_n; 2462 2463} 2464 2465/* 2466 * Combine available XPD Curves and fill Linear Power to PCDAC table 2467 * on RF5112 2468 * 2469 * RFX112 can have up to 2 curves (one for low txpower range and one for 2470 * higher txpower range). We need to put them both on pcdac_out and place 2471 * them in the correct location. In case we only have one curve available 2472 * just fit it on pcdac_out (it's supposed to cover the entire range of 2473 * available pwr levels since it's always the higher power curve). Extrapolate 2474 * below and above final table if needed. 2475 */ 2476static void 2477ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2478 s16 *table_max, u8 pdcurves) 2479{ 2480 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2481 u8 *pcdac_low_pwr; 2482 u8 *pcdac_high_pwr; 2483 u8 *pcdac_tmp; 2484 u8 pwr; 2485 s16 max_pwr_idx; 2486 s16 min_pwr_idx; 2487 s16 mid_pwr_idx = 0; 2488 /* Edge flag turs on the 7nth bit on the PCDAC 2489 * to delcare the higher power curve (force values 2490 * to be greater than 64). If we only have one curve 2491 * we don't need to set this, if we have 2 curves and 2492 * fill the table backwards this can also be used to 2493 * switch from higher power curve to lower power curve */ 2494 u8 edge_flag; 2495 int i; 2496 2497 /* When we have only one curve available 2498 * that's the higher power curve. If we have 2499 * two curves the first is the high power curve 2500 * and the next is the low power curve. */ 2501 if (pdcurves > 1) { 2502 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2503 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2504 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2505 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2506 2507 /* If table size goes beyond 31.5dB, keep the 2508 * upper 31.5dB range when setting tx power. 2509 * Note: 126 = 31.5 dB in quarter dB steps */ 2510 if (table_max[0] - table_min[1] > 126) 2511 min_pwr_idx = table_max[0] - 126; 2512 else 2513 min_pwr_idx = table_min[1]; 2514 2515 /* Since we fill table backwards 2516 * start from high power curve */ 2517 pcdac_tmp = pcdac_high_pwr; 2518 2519 edge_flag = 0x40; 2520 } else { 2521 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2522 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2523 min_pwr_idx = table_min[0]; 2524 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2525 pcdac_tmp = pcdac_high_pwr; 2526 edge_flag = 0; 2527 } 2528 2529 /* This is used when setting tx power*/ 2530 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2531 2532 /* Fill Power to PCDAC table backwards */ 2533 pwr = max_pwr_idx; 2534 for (i = 63; i >= 0; i--) { 2535 /* Entering lower power range, reset 2536 * edge flag and set pcdac_tmp to lower 2537 * power curve.*/ 2538 if (edge_flag == 0x40 && 2539 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2540 edge_flag = 0x00; 2541 pcdac_tmp = pcdac_low_pwr; 2542 pwr = mid_pwr_idx/2; 2543 } 2544 2545 /* Don't go below 1, extrapolate below if we have 2546 * already swithced to the lower power curve -or 2547 * we only have one curve and edge_flag is zero 2548 * anyway */ 2549 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2550 while (i >= 0) { 2551 pcdac_out[i] = pcdac_out[i + 1]; 2552 i--; 2553 } 2554 break; 2555 } 2556 2557 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2558 2559 /* Extrapolate above if pcdac is greater than 2560 * 126 -this can happen because we OR pcdac_out 2561 * value with edge_flag on high power curve */ 2562 if (pcdac_out[i] > 126) 2563 pcdac_out[i] = 126; 2564 2565 /* Decrease by a 0.5dB step */ 2566 pwr--; 2567 } 2568} 2569 2570/* Write PCDAC values on hw */ 2571static void 2572ath5k_setup_pcdac_table(struct ath5k_hw *ah) 2573{ 2574 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2575 int i; 2576 2577 /* 2578 * Write TX power values 2579 */ 2580 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2581 ath5k_hw_reg_write(ah, 2582 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2583 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2584 AR5K_PHY_PCDAC_TXPOWER(i)); 2585 } 2586} 2587 2588 2589/* 2590 * Power to PDADC table functions 2591 */ 2592 2593/* 2594 * Set the gain boundaries and create final Power to PDADC table 2595 * 2596 * We can have up to 4 pd curves, we need to do a simmilar process 2597 * as we do for RF5112. This time we don't have an edge_flag but we 2598 * set the gain boundaries on a separate register. 2599 */ 2600static void 2601ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2602 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2603{ 2604 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2605 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2606 u8 *pdadc_tmp; 2607 s16 pdadc_0; 2608 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2609 u8 pd_gain_overlap; 2610 2611 /* Note: Register value is initialized on initvals 2612 * there is no feedback from hw. 2613 * XXX: What about pd_gain_overlap from EEPROM ? */ 2614 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2615 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2616 2617 /* Create final PDADC table */ 2618 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2619 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2620 2621 if (pdg == pdcurves - 1) 2622 /* 2 dB boundary stretch for last 2623 * (higher power) curve */ 2624 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2625 else 2626 /* Set gain boundary in the middle 2627 * between this curve and the next one */ 2628 gain_boundaries[pdg] = 2629 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2630 2631 /* Sanity check in case our 2 db stretch got out of 2632 * range. */ 2633 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2634 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2635 2636 /* For the first curve (lower power) 2637 * start from 0 dB */ 2638 if (pdg == 0) 2639 pdadc_0 = 0; 2640 else 2641 /* For the other curves use the gain overlap */ 2642 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2643 pd_gain_overlap; 2644 2645 /* Force each power step to be at least 0.5 dB */ 2646 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2647 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2648 else 2649 pwr_step = 1; 2650 2651 /* If pdadc_0 is negative, we need to extrapolate 2652 * below this pdgain by a number of pwr_steps */ 2653 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2654 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2655 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2656 pdadc_0++; 2657 } 2658 2659 /* Set last pwr level, using gain boundaries */ 2660 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2661 /* Limit it to be inside pwr range */ 2662 table_size = pwr_max[pdg] - pwr_min[pdg]; 2663 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2664 2665 /* Fill pdadc_out table */ 2666 while (pdadc_0 < max_idx && pdadc_i < 128) 2667 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2668 2669 /* Need to extrapolate above this pdgain? */ 2670 if (pdadc_n <= max_idx) 2671 continue; 2672 2673 /* Force each power step to be at least 0.5 dB */ 2674 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2675 pwr_step = pdadc_tmp[table_size - 1] - 2676 pdadc_tmp[table_size - 2]; 2677 else 2678 pwr_step = 1; 2679 2680 /* Extrapolate above */ 2681 while ((pdadc_0 < (s16) pdadc_n) && 2682 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2683 s16 tmp = pdadc_tmp[table_size - 1] + 2684 (pdadc_0 - max_idx) * pwr_step; 2685 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2686 pdadc_0++; 2687 } 2688 } 2689 2690 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2691 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2692 pdg++; 2693 } 2694 2695 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2696 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2697 pdadc_i++; 2698 } 2699 2700 /* Set gain boundaries */ 2701 ath5k_hw_reg_write(ah, 2702 AR5K_REG_SM(pd_gain_overlap, 2703 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2704 AR5K_REG_SM(gain_boundaries[0], 2705 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2706 AR5K_REG_SM(gain_boundaries[1], 2707 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2708 AR5K_REG_SM(gain_boundaries[2], 2709 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2710 AR5K_REG_SM(gain_boundaries[3], 2711 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2712 AR5K_PHY_TPC_RG5); 2713 2714 /* Used for setting rate power table */ 2715 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2716 2717} 2718 2719/* Write PDADC values on hw */ 2720static void 2721ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2722 u8 pdcurves, u8 *pdg_to_idx) 2723{ 2724 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2725 u32 reg; 2726 u8 i; 2727 2728 /* Select the right pdgain curves */ 2729 2730 /* Clear current settings */ 2731 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2732 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2733 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2734 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2735 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2736 2737 /* 2738 * Use pd_gains curve from eeprom 2739 * 2740 * This overrides the default setting from initvals 2741 * in case some vendors (e.g. Zcomax) don't use the default 2742 * curves. If we don't honor their settings we 'll get a 2743 * 5dB (1 * gain overlap ?) drop. 2744 */ 2745 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2746 2747 switch (pdcurves) { 2748 case 3: 2749 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2750 /* Fall through */ 2751 case 2: 2752 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2753 /* Fall through */ 2754 case 1: 2755 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2756 break; 2757 } 2758 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2759 2760 /* 2761 * Write TX power values 2762 */ 2763 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2764 ath5k_hw_reg_write(ah, 2765 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2766 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2767 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2768 ((pdadc_out[4*i + 3] & 0xff) << 24), 2769 AR5K_PHY_PDADC_TXPOWER(i)); 2770 } 2771} 2772 2773 2774/* 2775 * Common code for PCDAC/PDADC tables 2776 */ 2777 2778/* 2779 * This is the main function that uses all of the above 2780 * to set PCDAC/PDADC table on hw for the current channel. 2781 * This table is used for tx power calibration on the basband, 2782 * without it we get weird tx power levels and in some cases 2783 * distorted spectral mask 2784 */ 2785static int 2786ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2787 struct ieee80211_channel *channel, 2788 u8 ee_mode, u8 type) 2789{ 2790 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2791 struct ath5k_chan_pcal_info *pcinfo_L; 2792 struct ath5k_chan_pcal_info *pcinfo_R; 2793 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2794 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2795 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2796 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2797 u8 *tmpL; 2798 u8 *tmpR; 2799 u32 target = channel->center_freq; 2800 int pdg, i; 2801 2802 /* Get surounding freq piers for this channel */ 2803 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2804 &pcinfo_L, 2805 &pcinfo_R); 2806 2807 /* Loop over pd gain curves on 2808 * surounding freq piers by index */ 2809 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2810 2811 /* Fill curves in reverse order 2812 * from lower power (max gain) 2813 * to higher power. Use curve -> idx 2814 * backmapping we did on eeprom init */ 2815 u8 idx = pdg_curve_to_idx[pdg]; 2816 2817 /* Grab the needed curves by index */ 2818 pdg_L = &pcinfo_L->pd_curves[idx]; 2819 pdg_R = &pcinfo_R->pd_curves[idx]; 2820 2821 /* Initialize the temp tables */ 2822 tmpL = ah->ah_txpower.tmpL[pdg]; 2823 tmpR = ah->ah_txpower.tmpR[pdg]; 2824 2825 /* Set curve's x boundaries and create 2826 * curves so that they cover the same 2827 * range (if we don't do that one table 2828 * will have values on some range and the 2829 * other one won't have any so interpolation 2830 * will fail) */ 2831 table_min[pdg] = min(pdg_L->pd_pwr[0], 2832 pdg_R->pd_pwr[0]) / 2; 2833 2834 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2835 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2836 2837 /* Now create the curves on surrounding channels 2838 * and interpolate if needed to get the final 2839 * curve for this gain on this channel */ 2840 switch (type) { 2841 case AR5K_PWRTABLE_LINEAR_PCDAC: 2842 /* Override min/max so that we don't loose 2843 * accuracy (don't divide by 2) */ 2844 table_min[pdg] = min(pdg_L->pd_pwr[0], 2845 pdg_R->pd_pwr[0]); 2846 2847 table_max[pdg] = 2848 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2849 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2850 2851 /* Override minimum so that we don't get 2852 * out of bounds while extrapolating 2853 * below. Don't do this when we have 2 2854 * curves and we are on the high power curve 2855 * because table_min is ok in this case */ 2856 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2857 2858 table_min[pdg] = 2859 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2860 pdg_R->pd_step, 2861 pdg_L->pd_pwr, 2862 pdg_R->pd_pwr); 2863 2864 /* Don't go too low because we will 2865 * miss the upper part of the curve. 2866 * Note: 126 = 31.5dB (max power supported) 2867 * in 0.25dB units */ 2868 if (table_max[pdg] - table_min[pdg] > 126) 2869 table_min[pdg] = table_max[pdg] - 126; 2870 } 2871 2872 /* Fall through */ 2873 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2874 case AR5K_PWRTABLE_PWR_TO_PDADC: 2875 2876 ath5k_create_power_curve(table_min[pdg], 2877 table_max[pdg], 2878 pdg_L->pd_pwr, 2879 pdg_L->pd_step, 2880 pdg_L->pd_points, tmpL, type); 2881 2882 /* We are in a calibration 2883 * pier, no need to interpolate 2884 * between freq piers */ 2885 if (pcinfo_L == pcinfo_R) 2886 continue; 2887 2888 ath5k_create_power_curve(table_min[pdg], 2889 table_max[pdg], 2890 pdg_R->pd_pwr, 2891 pdg_R->pd_step, 2892 pdg_R->pd_points, tmpR, type); 2893 break; 2894 default: 2895 return -EINVAL; 2896 } 2897 2898 /* Interpolate between curves 2899 * of surounding freq piers to 2900 * get the final curve for this 2901 * pd gain. Re-use tmpL for interpolation 2902 * output */ 2903 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2904 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2905 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2906 (s16) pcinfo_L->freq, 2907 (s16) pcinfo_R->freq, 2908 (s16) tmpL[i], 2909 (s16) tmpR[i]); 2910 } 2911 } 2912 2913 /* Now we have a set of curves for this 2914 * channel on tmpL (x range is table_max - table_min 2915 * and y values are tmpL[pdg][]) sorted in the same 2916 * order as EEPROM (because we've used the backmapping). 2917 * So for RF5112 it's from higher power to lower power 2918 * and for RF2413 it's from lower power to higher power. 2919 * For RF5111 we only have one curve. */ 2920 2921 /* Fill min and max power levels for this 2922 * channel by interpolating the values on 2923 * surounding channels to complete the dataset */ 2924 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2925 (s16) pcinfo_L->freq, 2926 (s16) pcinfo_R->freq, 2927 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2928 2929 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2930 (s16) pcinfo_L->freq, 2931 (s16) pcinfo_R->freq, 2932 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2933 2934 /* We are ready to go, fill PCDAC/PDADC 2935 * table and write settings on hardware */ 2936 switch (type) { 2937 case AR5K_PWRTABLE_LINEAR_PCDAC: 2938 /* For RF5112 we can have one or two curves 2939 * and each curve covers a certain power lvl 2940 * range so we need to do some more processing */ 2941 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2942 ee->ee_pd_gains[ee_mode]); 2943 2944 /* Set txp.offset so that we can 2945 * match max power value with max 2946 * table index */ 2947 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2948 2949 /* Write settings on hw */ 2950 ath5k_setup_pcdac_table(ah); 2951 break; 2952 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2953 /* We are done for RF5111 since it has only 2954 * one curve, just fit the curve on the table */ 2955 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2956 2957 /* No rate powertable adjustment for RF5111 */ 2958 ah->ah_txpower.txp_min_idx = 0; 2959 ah->ah_txpower.txp_offset = 0; 2960 2961 /* Write settings on hw */ 2962 ath5k_setup_pcdac_table(ah); 2963 break; 2964 case AR5K_PWRTABLE_PWR_TO_PDADC: 2965 /* Set PDADC boundaries and fill 2966 * final PDADC table */ 2967 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2968 ee->ee_pd_gains[ee_mode]); 2969 2970 /* Write settings on hw */ 2971 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2972 2973 /* Set txp.offset, note that table_min 2974 * can be negative */ 2975 ah->ah_txpower.txp_offset = table_min[0]; 2976 break; 2977 default: 2978 return -EINVAL; 2979 } 2980 2981 return 0; 2982} 2983 2984 2985/* 2986 * Per-rate tx power setting 2987 * 2988 * This is the code that sets the desired tx power (below 2989 * maximum) on hw for each rate (we also have TPC that sets 2990 * power per packet). We do that by providing an index on the 2991 * PCDAC/PDADC table we set up. 2992 */ 2993 2994/* 2995 * Set rate power table 2996 * 2997 * For now we only limit txpower based on maximum tx power 2998 * supported by hw (what's inside rate_info). We need to limit 2999 * this even more, based on regulatory domain etc. 3000 * 3001 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3002 * and is indexed as follows: 3003 * rates[0] - rates[7] -> OFDM rates 3004 * rates[8] - rates[14] -> CCK rates 3005 * rates[15] -> XR rates (they all have the same power) 3006 */ 3007static void 3008ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3009 struct ath5k_rate_pcal_info *rate_info, 3010 u8 ee_mode) 3011{ 3012 unsigned int i; 3013 u16 *rates; 3014 3015 /* max_pwr is power level we got from driver/user in 0.5dB 3016 * units, switch to 0.25dB units so we can compare */ 3017 max_pwr *= 2; 3018 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3019 3020 /* apply rate limits */ 3021 rates = ah->ah_txpower.txp_rates_power_table; 3022 3023 /* OFDM rates 6 to 24Mb/s */ 3024 for (i = 0; i < 5; i++) 3025 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3026 3027 /* Rest OFDM rates */ 3028 rates[5] = min(rates[0], rate_info->target_power_36); 3029 rates[6] = min(rates[0], rate_info->target_power_48); 3030 rates[7] = min(rates[0], rate_info->target_power_54); 3031 3032 /* CCK rates */ 3033 /* 1L */ 3034 rates[8] = min(rates[0], rate_info->target_power_6to24); 3035 /* 2L */ 3036 rates[9] = min(rates[0], rate_info->target_power_36); 3037 /* 2S */ 3038 rates[10] = min(rates[0], rate_info->target_power_36); 3039 /* 5L */ 3040 rates[11] = min(rates[0], rate_info->target_power_48); 3041 /* 5S */ 3042 rates[12] = min(rates[0], rate_info->target_power_48); 3043 /* 11L */ 3044 rates[13] = min(rates[0], rate_info->target_power_54); 3045 /* 11S */ 3046 rates[14] = min(rates[0], rate_info->target_power_54); 3047 3048 /* XR rates */ 3049 rates[15] = min(rates[0], rate_info->target_power_6to24); 3050 3051 /* CCK rates have different peak to average ratio 3052 * so we have to tweak their power so that gainf 3053 * correction works ok. For this we use OFDM to 3054 * CCK delta from eeprom */ 3055 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3056 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3057 for (i = 8; i <= 15; i++) 3058 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3059 3060 /* Now that we have all rates setup use table offset to 3061 * match the power range set by user with the power indices 3062 * on PCDAC/PDADC table */ 3063 for (i = 0; i < 16; i++) { 3064 rates[i] += ah->ah_txpower.txp_offset; 3065 /* Don't get out of bounds */ 3066 if (rates[i] > 63) 3067 rates[i] = 63; 3068 } 3069 3070 /* Min/max in 0.25dB units */ 3071 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3072 ah->ah_txpower.txp_max_pwr = 2 * rates[0]; 3073 ah->ah_txpower.txp_ofdm = rates[7]; 3074} 3075 3076 3077/* 3078 * Set transmission power 3079 */ 3080static int 3081ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3082 u8 ee_mode, u8 txpower) 3083{ 3084 struct ath5k_rate_pcal_info rate_info; 3085 u8 type; 3086 int ret; 3087 3088 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3089 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3090 return -EINVAL; 3091 } 3092 3093 /* Reset TX power values */ 3094 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3095 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3096 ah->ah_txpower.txp_min_pwr = 0; 3097 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 3098 3099 /* Initialize TX power table */ 3100 switch (ah->ah_radio) { 3101 case AR5K_RF5111: 3102 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3103 break; 3104 case AR5K_RF5112: 3105 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3106 break; 3107 case AR5K_RF2413: 3108 case AR5K_RF5413: 3109 case AR5K_RF2316: 3110 case AR5K_RF2317: 3111 case AR5K_RF2425: 3112 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3113 break; 3114 default: 3115 return -EINVAL; 3116 } 3117 3118 /* FIXME: Only on channel/mode change */ 3119 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 3120 if (ret) 3121 return ret; 3122 3123 /* Limit max power if we have a CTL available */ 3124 ath5k_get_max_ctl_power(ah, channel); 3125 3126 /* FIXME: Antenna reduction stuff */ 3127 3128 /* FIXME: Limit power on turbo modes */ 3129 3130 /* FIXME: TPC scale reduction */ 3131 3132 /* Get surounding channels for per-rate power table 3133 * calibration */ 3134 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3135 3136 /* Setup rate power table */ 3137 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3138 3139 /* Write rate power table on hw */ 3140 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3141 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3142 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3143 3144 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3145 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3146 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3147 3148 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3149 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3150 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3151 3152 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3153 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3154 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3155 3156 /* FIXME: TPC support */ 3157 if (ah->ah_txpower.txp_tpc) { 3158 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3159 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3160 3161 ath5k_hw_reg_write(ah, 3162 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3163 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3164 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3165 AR5K_TPC); 3166 } else { 3167 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3168 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3169 } 3170 3171 return 0; 3172} 3173 3174int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3175{ 3176 /*Just a try M.F.*/ 3177 struct ieee80211_channel *channel = ah->ah_current_channel; 3178 u8 ee_mode; 3179 3180 switch (channel->hw_value & CHANNEL_MODES) { 3181 case CHANNEL_A: 3182 case CHANNEL_T: 3183 case CHANNEL_XR: 3184 ee_mode = AR5K_EEPROM_MODE_11A; 3185 break; 3186 case CHANNEL_G: 3187 case CHANNEL_TG: 3188 ee_mode = AR5K_EEPROM_MODE_11G; 3189 break; 3190 case CHANNEL_B: 3191 ee_mode = AR5K_EEPROM_MODE_11B; 3192 break; 3193 default: 3194 ATH5K_ERR(ah->ah_sc, 3195 "invalid channel: %d\n", channel->center_freq); 3196 return -EINVAL; 3197 } 3198 3199 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3200 "changing txpower to %d\n", txpower); 3201 3202 return ath5k_hw_txpower(ah, channel, ee_mode, txpower); 3203} 3204 3205/*************\ 3206 Init function 3207\*************/ 3208 3209int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3210 u8 mode, u8 ee_mode, u8 freq) 3211{ 3212 int ret, i; 3213 u32 phy_tst1; 3214 3215 ret = 0; 3216 3217 /* 3218 * 5211/5212 Specific 3219 */ 3220 if (ah->ah_version != AR5K_AR5210) { 3221 3222 /* 3223 * Write initial RF gain settings 3224 * This should work for both 5111/5112 3225 */ 3226 ret = ath5k_hw_rfgain_init(ah, freq); 3227 if (ret) 3228 return ret; 3229 3230 mdelay(1); 3231 3232 /* 3233 * Set TX power 3234 */ 3235 ret = ath5k_hw_txpower(ah, channel, ee_mode, 3236 ah->ah_txpower.txp_max_pwr / 2); 3237 if (ret) 3238 return ret; 3239 3240 /* 3241 * Write RF buffer 3242 */ 3243 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3244 if (ret) 3245 return ret; 3246 3247 3248 /* Write OFDM timings on 5212*/ 3249 if (ah->ah_version == AR5K_AR5212 && 3250 channel->hw_value & CHANNEL_OFDM) { 3251 3252 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3253 if (ret) 3254 return ret; 3255 3256 /* Spur info is available only from EEPROM versions 3257 * greater than 5.3, but the EEPROM routines will use 3258 * static values for older versions */ 3259 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3260 ath5k_hw_set_spur_mitigation_filter(ah, 3261 channel); 3262 } 3263 3264 /*Enable/disable 802.11b mode on 5111 3265 (enable 2111 frequency converter + CCK)*/ 3266 if (ah->ah_radio == AR5K_RF5111) { 3267 if (mode == AR5K_MODE_11B) 3268 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3269 AR5K_TXCFG_B_MODE); 3270 else 3271 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3272 AR5K_TXCFG_B_MODE); 3273 } 3274 3275 } else { 3276 /* 3277 * For 5210 we do all initialization using 3278 * initvals, so we don't have to modify 3279 * any settings (5210 also only supports 3280 * a/aturbo modes) 3281 */ 3282 mdelay(1); 3283 /* Disable phy and wait */ 3284 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3285 mdelay(1); 3286 } 3287 3288 /* Set channel on PHY */ 3289 ret = ath5k_hw_channel(ah, channel); 3290 if (ret) 3291 return ret; 3292 3293 /* 3294 * Enable the PHY and wait until completion 3295 * This includes BaseBand and Synthesizer 3296 * activation. 3297 */ 3298 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3299 3300 /* 3301 * On 5211+ read activation -> rx delay 3302 * and use it. 3303 * 3304 * TODO: Half/quarter rate support 3305 */ 3306 if (ah->ah_version != AR5K_AR5210) { 3307 u32 delay; 3308 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 3309 AR5K_PHY_RX_DELAY_M; 3310 delay = (channel->hw_value & CHANNEL_CCK) ? 3311 ((delay << 2) / 22) : (delay / 10); 3312 3313 udelay(100 + (2 * delay)); 3314 } else { 3315 mdelay(1); 3316 } 3317 3318 /* 3319 * Perform ADC test to see if baseband is ready 3320 * Set TX hold and check ADC test register 3321 */ 3322 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3323 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3324 for (i = 0; i <= 20; i++) { 3325 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3326 break; 3327 udelay(200); 3328 } 3329 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3330 3331 /* 3332 * Start automatic gain control calibration 3333 * 3334 * During AGC calibration RX path is re-routed to 3335 * a power detector so we don't receive anything. 3336 * 3337 * This method is used to calibrate some static offsets 3338 * used together with on-the fly I/Q calibration (the 3339 * one performed via ath5k_hw_phy_calibrate), which doesn't 3340 * interrupt rx path. 3341 * 3342 * While rx path is re-routed to the power detector we also 3343 * start a noise floor calibration to measure the 3344 * card's noise floor (the noise we measure when we are not 3345 * transmitting or receiving anything). 3346 * 3347 * If we are in a noisy environment, AGC calibration may time 3348 * out and/or noise floor calibration might timeout. 3349 */ 3350 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3351 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3352 3353 /* At the same time start I/Q calibration for QAM constellation 3354 * -no need for CCK- */ 3355 ah->ah_calibration = false; 3356 if (!(mode == AR5K_MODE_11B)) { 3357 ah->ah_calibration = true; 3358 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3359 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3360 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3361 AR5K_PHY_IQ_RUN); 3362 } 3363 3364 /* Wait for gain calibration to finish (we check for I/Q calibration 3365 * during ath5k_phy_calibrate) */ 3366 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3367 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3368 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3369 channel->center_freq); 3370 } 3371 3372 /* Restore antenna mode */ 3373 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3374 3375 return ret; 3376} 3377