phy.c revision ca8bfd94bbe5bd89ff6a4bbf5a050251950cce25
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32 33/******************\ 34* Helper functions * 35\******************/ 36 37/* 38 * Get the PHY Chip revision 39 */ 40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41{ 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81} 82 83/* 84 * Check if a channel is supported 85 */ 86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87{ 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99} 100 101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103{ 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119} 120 121/* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127{ 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200} 201 202/** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219{ 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 switch (ah->ah_bwmode) { 232 case AR5K_BWMODE_40MHZ: 233 clock = 40 * 2; 234 break; 235 case AR5K_BWMODE_10MHZ: 236 clock = 40 / 2; 237 break; 238 case AR5K_BWMODE_5MHZ: 239 clock = 40 / 4; 240 break; 241 default: 242 clock = 40; 243 break; 244 } 245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 246 247 /* Get exponent 248 * ALGO: coef_exp = 14 - highest set bit position */ 249 coef_exp = ilog2(coef_scaled); 250 251 /* Doesn't make sense if it's zero*/ 252 if (!coef_scaled || !coef_exp) 253 return -EINVAL; 254 255 /* Note: we've shifted coef_scaled by 24 */ 256 coef_exp = 14 - (coef_exp - 24); 257 258 259 /* Get mantissa (significant digits) 260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 261 coef_man = coef_scaled + 262 (1 << (24 - coef_exp - 1)); 263 264 /* Calculate delta slope coefficient exponent 265 * and mantissa (remove scaling) and set them on hw */ 266 ds_coef_man = coef_man >> (24 - coef_exp); 267 ds_coef_exp = coef_exp - 16; 268 269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 273 274 return 0; 275} 276 277int ath5k_hw_phy_disable(struct ath5k_hw *ah) 278{ 279 /*Just a try M.F.*/ 280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 281 282 return 0; 283} 284 285/* 286 * Wait for synth to settle 287 */ 288static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 289 struct ieee80211_channel *channel) 290{ 291 /* 292 * On 5211+ read activation -> rx delay 293 * and use it (100ns steps). 294 */ 295 if (ah->ah_version != AR5K_AR5210) { 296 u32 delay; 297 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 298 AR5K_PHY_RX_DELAY_M; 299 delay = (channel->hw_value & CHANNEL_CCK) ? 300 ((delay << 2) / 22) : (delay / 10); 301 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 302 delay = delay << 1; 303 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 304 delay = delay << 2; 305 /* XXX: /2 on turbo ? Let's be safe 306 * for now */ 307 udelay(100 + delay); 308 } else { 309 mdelay(1); 310 } 311} 312 313 314/**********************\ 315* RF Gain optimization * 316\**********************/ 317 318/* 319 * This code is used to optimize RF gain on different environments 320 * (temperature mostly) based on feedback from a power detector. 321 * 322 * It's only used on RF5111 and RF5112, later RF chips seem to have 323 * auto adjustment on hw -notice they have a much smaller BANK 7 and 324 * no gain optimization ladder-. 325 * 326 * For more infos check out this patent doc 327 * http://www.freepatentsonline.com/7400691.html 328 * 329 * This paper describes power drops as seen on the receiver due to 330 * probe packets 331 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 332 * %20of%20Power%20Control.pdf 333 * 334 * And this is the MadWiFi bug entry related to the above 335 * http://madwifi-project.org/ticket/1659 336 * with various measurements and diagrams 337 * 338 * TODO: Deal with power drops due to probes by setting an appropriate 339 * tx power on the probe packets ! Make this part of the calibration process. 340 */ 341 342/* Initialize ah_gain during attach */ 343int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 344{ 345 /* Initialize the gain optimization values */ 346 switch (ah->ah_radio) { 347 case AR5K_RF5111: 348 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 349 ah->ah_gain.g_low = 20; 350 ah->ah_gain.g_high = 35; 351 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 352 break; 353 case AR5K_RF5112: 354 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 355 ah->ah_gain.g_low = 20; 356 ah->ah_gain.g_high = 85; 357 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 358 break; 359 default: 360 return -EINVAL; 361 } 362 363 return 0; 364} 365 366/* Schedule a gain probe check on the next transmitted packet. 367 * That means our next packet is going to be sent with lower 368 * tx power and a Peak to Average Power Detector (PAPD) will try 369 * to measure the gain. 370 * 371 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 372 * just after we enable the probe so that we don't mess with 373 * standard traffic ? Maybe it's time to use sw interrupts and 374 * a probe tasklet !!! 375 */ 376static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 377{ 378 379 /* Skip if gain calibration is inactive or 380 * we already handle a probe request */ 381 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 382 return; 383 384 /* Send the packet with 2dB below max power as 385 * patent doc suggest */ 386 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 387 AR5K_PHY_PAPD_PROBE_TXPOWER) | 388 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 389 390 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 391 392} 393 394/* Calculate gain_F measurement correction 395 * based on the current step for RF5112 rev. 2 */ 396static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 397{ 398 u32 mix, step; 399 u32 *rf; 400 const struct ath5k_gain_opt *go; 401 const struct ath5k_gain_opt_step *g_step; 402 const struct ath5k_rf_reg *rf_regs; 403 404 /* Only RF5112 Rev. 2 supports it */ 405 if ((ah->ah_radio != AR5K_RF5112) || 406 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 407 return 0; 408 409 go = &rfgain_opt_5112; 410 rf_regs = rf_regs_5112a; 411 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 412 413 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 414 415 if (ah->ah_rf_banks == NULL) 416 return 0; 417 418 rf = ah->ah_rf_banks; 419 ah->ah_gain.g_f_corr = 0; 420 421 /* No VGA (Variable Gain Amplifier) override, skip */ 422 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 423 return 0; 424 425 /* Mix gain stepping */ 426 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 427 428 /* Mix gain override */ 429 mix = g_step->gos_param[0]; 430 431 switch (mix) { 432 case 3: 433 ah->ah_gain.g_f_corr = step * 2; 434 break; 435 case 2: 436 ah->ah_gain.g_f_corr = (step - 5) * 2; 437 break; 438 case 1: 439 ah->ah_gain.g_f_corr = step; 440 break; 441 default: 442 ah->ah_gain.g_f_corr = 0; 443 break; 444 } 445 446 return ah->ah_gain.g_f_corr; 447} 448 449/* Check if current gain_F measurement is in the range of our 450 * power detector windows. If we get a measurement outside range 451 * we know it's not accurate (detectors can't measure anything outside 452 * their detection window) so we must ignore it */ 453static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 454{ 455 const struct ath5k_rf_reg *rf_regs; 456 u32 step, mix_ovr, level[4]; 457 u32 *rf; 458 459 if (ah->ah_rf_banks == NULL) 460 return false; 461 462 rf = ah->ah_rf_banks; 463 464 if (ah->ah_radio == AR5K_RF5111) { 465 466 rf_regs = rf_regs_5111; 467 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 468 469 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 470 false); 471 472 level[0] = 0; 473 level[1] = (step == 63) ? 50 : step + 4; 474 level[2] = (step != 63) ? 64 : level[0]; 475 level[3] = level[2] + 50; 476 477 ah->ah_gain.g_high = level[3] - 478 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 479 ah->ah_gain.g_low = level[0] + 480 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 481 } else { 482 483 rf_regs = rf_regs_5112; 484 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 485 486 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 487 false); 488 489 level[0] = level[2] = 0; 490 491 if (mix_ovr == 1) { 492 level[1] = level[3] = 83; 493 } else { 494 level[1] = level[3] = 107; 495 ah->ah_gain.g_high = 55; 496 } 497 } 498 499 return (ah->ah_gain.g_current >= level[0] && 500 ah->ah_gain.g_current <= level[1]) || 501 (ah->ah_gain.g_current >= level[2] && 502 ah->ah_gain.g_current <= level[3]); 503} 504 505/* Perform gain_F adjustment by choosing the right set 506 * of parameters from RF gain optimization ladder */ 507static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 508{ 509 const struct ath5k_gain_opt *go; 510 const struct ath5k_gain_opt_step *g_step; 511 int ret = 0; 512 513 switch (ah->ah_radio) { 514 case AR5K_RF5111: 515 go = &rfgain_opt_5111; 516 break; 517 case AR5K_RF5112: 518 go = &rfgain_opt_5112; 519 break; 520 default: 521 return 0; 522 } 523 524 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 525 526 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 527 528 /* Reached maximum */ 529 if (ah->ah_gain.g_step_idx == 0) 530 return -1; 531 532 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 533 ah->ah_gain.g_target >= ah->ah_gain.g_high && 534 ah->ah_gain.g_step_idx > 0; 535 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 536 ah->ah_gain.g_target -= 2 * 537 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 538 g_step->gos_gain); 539 540 ret = 1; 541 goto done; 542 } 543 544 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 545 546 /* Reached minimum */ 547 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 548 return -2; 549 550 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 551 ah->ah_gain.g_target <= ah->ah_gain.g_low && 552 ah->ah_gain.g_step_idx < go->go_steps_count - 1; 553 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 554 ah->ah_gain.g_target -= 2 * 555 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 556 g_step->gos_gain); 557 558 ret = 2; 559 goto done; 560 } 561 562done: 563 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 564 "ret %d, gain step %u, current gain %u, target gain %u\n", 565 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 566 ah->ah_gain.g_target); 567 568 return ret; 569} 570 571/* Main callback for thermal RF gain calibration engine 572 * Check for a new gain reading and schedule an adjustment 573 * if needed. 574 * 575 * TODO: Use sw interrupt to schedule reset if gain_F needs 576 * adjustment */ 577enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 578{ 579 u32 data, type; 580 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 581 582 if (ah->ah_rf_banks == NULL || 583 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 584 return AR5K_RFGAIN_INACTIVE; 585 586 /* No check requested, either engine is inactive 587 * or an adjustment is already requested */ 588 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 589 goto done; 590 591 /* Read the PAPD (Peak to Average Power Detector) 592 * register */ 593 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 594 595 /* No probe is scheduled, read gain_F measurement */ 596 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 597 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 598 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 599 600 /* If tx packet is CCK correct the gain_F measurement 601 * by cck ofdm gain delta */ 602 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 603 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 604 ah->ah_gain.g_current += 605 ee->ee_cck_ofdm_gain_delta; 606 else 607 ah->ah_gain.g_current += 608 AR5K_GAIN_CCK_PROBE_CORR; 609 } 610 611 /* Further correct gain_F measurement for 612 * RF5112A radios */ 613 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 614 ath5k_hw_rf_gainf_corr(ah); 615 ah->ah_gain.g_current = 616 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 617 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : 618 0; 619 } 620 621 /* Check if measurement is ok and if we need 622 * to adjust gain, schedule a gain adjustment, 623 * else switch back to the active state */ 624 if (ath5k_hw_rf_check_gainf_readback(ah) && 625 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 626 ath5k_hw_rf_gainf_adjust(ah)) { 627 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 628 } else { 629 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 630 } 631 } 632 633done: 634 return ah->ah_gain.g_state; 635} 636 637/* Write initial RF gain table to set the RF sensitivity 638 * this one works on all RF chips and has nothing to do 639 * with gain_F calibration */ 640static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 641{ 642 const struct ath5k_ini_rfgain *ath5k_rfg; 643 unsigned int i, size, index; 644 645 switch (ah->ah_radio) { 646 case AR5K_RF5111: 647 ath5k_rfg = rfgain_5111; 648 size = ARRAY_SIZE(rfgain_5111); 649 break; 650 case AR5K_RF5112: 651 ath5k_rfg = rfgain_5112; 652 size = ARRAY_SIZE(rfgain_5112); 653 break; 654 case AR5K_RF2413: 655 ath5k_rfg = rfgain_2413; 656 size = ARRAY_SIZE(rfgain_2413); 657 break; 658 case AR5K_RF2316: 659 ath5k_rfg = rfgain_2316; 660 size = ARRAY_SIZE(rfgain_2316); 661 break; 662 case AR5K_RF5413: 663 ath5k_rfg = rfgain_5413; 664 size = ARRAY_SIZE(rfgain_5413); 665 break; 666 case AR5K_RF2317: 667 case AR5K_RF2425: 668 ath5k_rfg = rfgain_2425; 669 size = ARRAY_SIZE(rfgain_2425); 670 break; 671 default: 672 return -EINVAL; 673 } 674 675 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 676 677 for (i = 0; i < size; i++) { 678 AR5K_REG_WAIT(i); 679 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 680 (u32)ath5k_rfg[i].rfg_register); 681 } 682 683 return 0; 684} 685 686 687 688/********************\ 689* RF Registers setup * 690\********************/ 691 692/* 693 * Setup RF registers by writing RF buffer on hw 694 */ 695static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 696 struct ieee80211_channel *channel, unsigned int mode) 697{ 698 const struct ath5k_rf_reg *rf_regs; 699 const struct ath5k_ini_rfbuffer *ini_rfb; 700 const struct ath5k_gain_opt *go = NULL; 701 const struct ath5k_gain_opt_step *g_step; 702 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 703 u8 ee_mode = 0; 704 u32 *rfb; 705 int i, obdb = -1, bank = -1; 706 707 switch (ah->ah_radio) { 708 case AR5K_RF5111: 709 rf_regs = rf_regs_5111; 710 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 711 ini_rfb = rfb_5111; 712 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 713 go = &rfgain_opt_5111; 714 break; 715 case AR5K_RF5112: 716 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 717 rf_regs = rf_regs_5112a; 718 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 719 ini_rfb = rfb_5112a; 720 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 721 } else { 722 rf_regs = rf_regs_5112; 723 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 724 ini_rfb = rfb_5112; 725 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 726 } 727 go = &rfgain_opt_5112; 728 break; 729 case AR5K_RF2413: 730 rf_regs = rf_regs_2413; 731 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 732 ini_rfb = rfb_2413; 733 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 734 break; 735 case AR5K_RF2316: 736 rf_regs = rf_regs_2316; 737 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 738 ini_rfb = rfb_2316; 739 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 740 break; 741 case AR5K_RF5413: 742 rf_regs = rf_regs_5413; 743 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 744 ini_rfb = rfb_5413; 745 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 746 break; 747 case AR5K_RF2317: 748 rf_regs = rf_regs_2425; 749 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 750 ini_rfb = rfb_2317; 751 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 752 break; 753 case AR5K_RF2425: 754 rf_regs = rf_regs_2425; 755 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 756 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 757 ini_rfb = rfb_2425; 758 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 759 } else { 760 ini_rfb = rfb_2417; 761 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 762 } 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 /* If it's the first time we set RF buffer, allocate 769 * ah->ah_rf_banks based on ah->ah_rf_banks_size 770 * we set above */ 771 if (ah->ah_rf_banks == NULL) { 772 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 773 GFP_KERNEL); 774 if (ah->ah_rf_banks == NULL) { 775 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 776 return -ENOMEM; 777 } 778 } 779 780 /* Copy values to modify them */ 781 rfb = ah->ah_rf_banks; 782 783 for (i = 0; i < ah->ah_rf_banks_size; i++) { 784 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 785 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 786 return -EINVAL; 787 } 788 789 /* Bank changed, write down the offset */ 790 if (bank != ini_rfb[i].rfb_bank) { 791 bank = ini_rfb[i].rfb_bank; 792 ah->ah_offset[bank] = i; 793 } 794 795 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 796 } 797 798 /* Set Output and Driver bias current (OB/DB) */ 799 if (channel->hw_value & CHANNEL_2GHZ) { 800 801 if (channel->hw_value & CHANNEL_CCK) 802 ee_mode = AR5K_EEPROM_MODE_11B; 803 else 804 ee_mode = AR5K_EEPROM_MODE_11G; 805 806 /* For RF511X/RF211X combination we 807 * use b_OB and b_DB parameters stored 808 * in eeprom on ee->ee_ob[ee_mode][0] 809 * 810 * For all other chips we use OB/DB for 2GHz 811 * stored in the b/g modal section just like 812 * 802.11a on ee->ee_ob[ee_mode][1] */ 813 if ((ah->ah_radio == AR5K_RF5111) || 814 (ah->ah_radio == AR5K_RF5112)) 815 obdb = 0; 816 else 817 obdb = 1; 818 819 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 820 AR5K_RF_OB_2GHZ, true); 821 822 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 823 AR5K_RF_DB_2GHZ, true); 824 825 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 826 } else if ((channel->hw_value & CHANNEL_5GHZ) || 827 (ah->ah_radio == AR5K_RF5111)) { 828 829 /* For 11a, Turbo and XR we need to choose 830 * OB/DB based on frequency range */ 831 ee_mode = AR5K_EEPROM_MODE_11A; 832 obdb = channel->center_freq >= 5725 ? 3 : 833 (channel->center_freq >= 5500 ? 2 : 834 (channel->center_freq >= 5260 ? 1 : 835 (channel->center_freq > 4000 ? 0 : -1))); 836 837 if (obdb < 0) 838 return -EINVAL; 839 840 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 841 AR5K_RF_OB_5GHZ, true); 842 843 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 844 AR5K_RF_DB_5GHZ, true); 845 } 846 847 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 848 849 /* Set turbo mode (N/A on RF5413) */ 850 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 851 (ah->ah_radio != AR5K_RF5413)) 852 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 853 854 /* Bank Modifications (chip-specific) */ 855 if (ah->ah_radio == AR5K_RF5111) { 856 857 /* Set gain_F settings according to current step */ 858 if (channel->hw_value & CHANNEL_OFDM) { 859 860 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 861 AR5K_PHY_FRAME_CTL_TX_CLIP, 862 g_step->gos_param[0]); 863 864 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 865 AR5K_RF_PWD_90, true); 866 867 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 868 AR5K_RF_PWD_84, true); 869 870 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 871 AR5K_RF_RFGAIN_SEL, true); 872 873 /* We programmed gain_F parameters, switch back 874 * to active state */ 875 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 876 877 } 878 879 /* Bank 6/7 setup */ 880 881 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 882 AR5K_RF_PWD_XPD, true); 883 884 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 885 AR5K_RF_XPD_GAIN, true); 886 887 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 888 AR5K_RF_GAIN_I, true); 889 890 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 891 AR5K_RF_PLO_SEL, true); 892 893 /* Tweak power detectors for half/quarter rate support */ 894 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 895 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 896 u8 wait_i; 897 898 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 899 AR5K_RF_WAIT_S, true); 900 901 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 902 0x1f : 0x10; 903 904 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 905 AR5K_RF_WAIT_I, true); 906 ath5k_hw_rfb_op(ah, rf_regs, 3, 907 AR5K_RF_MAX_TIME, true); 908 909 } 910 } 911 912 if (ah->ah_radio == AR5K_RF5112) { 913 914 /* Set gain_F settings according to current step */ 915 if (channel->hw_value & CHANNEL_OFDM) { 916 917 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 918 AR5K_RF_MIXGAIN_OVR, true); 919 920 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 921 AR5K_RF_PWD_138, true); 922 923 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 924 AR5K_RF_PWD_137, true); 925 926 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 927 AR5K_RF_PWD_136, true); 928 929 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 930 AR5K_RF_PWD_132, true); 931 932 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 933 AR5K_RF_PWD_131, true); 934 935 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 936 AR5K_RF_PWD_130, true); 937 938 /* We programmed gain_F parameters, switch back 939 * to active state */ 940 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 941 } 942 943 /* Bank 6/7 setup */ 944 945 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 946 AR5K_RF_XPD_SEL, true); 947 948 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 949 /* Rev. 1 supports only one xpd */ 950 ath5k_hw_rfb_op(ah, rf_regs, 951 ee->ee_x_gain[ee_mode], 952 AR5K_RF_XPD_GAIN, true); 953 954 } else { 955 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 956 if (ee->ee_pd_gains[ee_mode] > 1) { 957 ath5k_hw_rfb_op(ah, rf_regs, 958 pdg_curve_to_idx[0], 959 AR5K_RF_PD_GAIN_LO, true); 960 ath5k_hw_rfb_op(ah, rf_regs, 961 pdg_curve_to_idx[1], 962 AR5K_RF_PD_GAIN_HI, true); 963 } else { 964 ath5k_hw_rfb_op(ah, rf_regs, 965 pdg_curve_to_idx[0], 966 AR5K_RF_PD_GAIN_LO, true); 967 ath5k_hw_rfb_op(ah, rf_regs, 968 pdg_curve_to_idx[0], 969 AR5K_RF_PD_GAIN_HI, true); 970 } 971 972 /* Lower synth voltage on Rev 2 */ 973 if (ah->ah_radio == AR5K_RF5112 && 974 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { 975 ath5k_hw_rfb_op(ah, rf_regs, 2, 976 AR5K_RF_HIGH_VC_CP, true); 977 978 ath5k_hw_rfb_op(ah, rf_regs, 2, 979 AR5K_RF_MID_VC_CP, true); 980 981 ath5k_hw_rfb_op(ah, rf_regs, 2, 982 AR5K_RF_LOW_VC_CP, true); 983 984 ath5k_hw_rfb_op(ah, rf_regs, 2, 985 AR5K_RF_PUSH_UP, true); 986 } 987 988 /* Decrease power consumption on 5213+ BaseBand */ 989 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 990 ath5k_hw_rfb_op(ah, rf_regs, 1, 991 AR5K_RF_PAD2GND, true); 992 993 ath5k_hw_rfb_op(ah, rf_regs, 1, 994 AR5K_RF_XB2_LVL, true); 995 996 ath5k_hw_rfb_op(ah, rf_regs, 1, 997 AR5K_RF_XB5_LVL, true); 998 999 ath5k_hw_rfb_op(ah, rf_regs, 1, 1000 AR5K_RF_PWD_167, true); 1001 1002 ath5k_hw_rfb_op(ah, rf_regs, 1, 1003 AR5K_RF_PWD_166, true); 1004 } 1005 } 1006 1007 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1008 AR5K_RF_GAIN_I, true); 1009 1010 /* Tweak power detector for half/quarter rates */ 1011 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1012 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1013 u8 pd_delay; 1014 1015 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1016 0xf : 0x8; 1017 1018 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 1019 AR5K_RF_PD_PERIOD_A, true); 1020 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 1021 AR5K_RF_PD_DELAY_A, true); 1022 1023 } 1024 } 1025 1026 if (ah->ah_radio == AR5K_RF5413 && 1027 channel->hw_value & CHANNEL_2GHZ) { 1028 1029 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1030 true); 1031 1032 /* Set optimum value for early revisions (on pci-e chips) */ 1033 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1034 ah->ah_mac_srev < AR5K_SREV_AR5413) 1035 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1036 AR5K_RF_PWD_ICLOBUF_2G, true); 1037 1038 } 1039 1040 /* Write RF banks on hw */ 1041 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1042 AR5K_REG_WAIT(i); 1043 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1044 } 1045 1046 return 0; 1047} 1048 1049 1050/**************************\ 1051 PHY/RF channel functions 1052\**************************/ 1053 1054/* 1055 * Conversion needed for RF5110 1056 */ 1057static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1058{ 1059 u32 athchan; 1060 1061 /* 1062 * Convert IEEE channel/MHz to an internal channel value used 1063 * by the AR5210 chipset. This has not been verified with 1064 * newer chipsets like the AR5212A who have a completely 1065 * different RF/PHY part. 1066 */ 1067 athchan = (ath5k_hw_bitswap( 1068 (ieee80211_frequency_to_channel( 1069 channel->center_freq) - 24) / 2, 5) 1070 << 1) | (1 << 6) | 0x1; 1071 return athchan; 1072} 1073 1074/* 1075 * Set channel on RF5110 1076 */ 1077static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1078 struct ieee80211_channel *channel) 1079{ 1080 u32 data; 1081 1082 /* 1083 * Set the channel and wait 1084 */ 1085 data = ath5k_hw_rf5110_chan2athchan(channel); 1086 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1087 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1088 mdelay(1); 1089 1090 return 0; 1091} 1092 1093/* 1094 * Conversion needed for 5111 1095 */ 1096static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1097 struct ath5k_athchan_2ghz *athchan) 1098{ 1099 int channel; 1100 1101 /* Cast this value to catch negative channel numbers (>= -19) */ 1102 channel = (int)ieee; 1103 1104 /* 1105 * Map 2GHz IEEE channel to 5GHz Atheros channel 1106 */ 1107 if (channel <= 13) { 1108 athchan->a2_athchan = 115 + channel; 1109 athchan->a2_flags = 0x46; 1110 } else if (channel == 14) { 1111 athchan->a2_athchan = 124; 1112 athchan->a2_flags = 0x44; 1113 } else if (channel >= 15 && channel <= 26) { 1114 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1115 athchan->a2_flags = 0x46; 1116 } else 1117 return -EINVAL; 1118 1119 return 0; 1120} 1121 1122/* 1123 * Set channel on 5111 1124 */ 1125static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1126 struct ieee80211_channel *channel) 1127{ 1128 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1129 unsigned int ath5k_channel = 1130 ieee80211_frequency_to_channel(channel->center_freq); 1131 u32 data0, data1, clock; 1132 int ret; 1133 1134 /* 1135 * Set the channel on the RF5111 radio 1136 */ 1137 data0 = data1 = 0; 1138 1139 if (channel->hw_value & CHANNEL_2GHZ) { 1140 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1141 ret = ath5k_hw_rf5111_chan2athchan( 1142 ieee80211_frequency_to_channel(channel->center_freq), 1143 &ath5k_channel_2ghz); 1144 if (ret) 1145 return ret; 1146 1147 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1148 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1149 << 5) | (1 << 4); 1150 } 1151 1152 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1153 clock = 1; 1154 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1155 (clock << 1) | (1 << 10) | 1; 1156 } else { 1157 clock = 0; 1158 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1159 << 2) | (clock << 1) | (1 << 10) | 1; 1160 } 1161 1162 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1163 AR5K_RF_BUFFER); 1164 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1165 AR5K_RF_BUFFER_CONTROL_3); 1166 1167 return 0; 1168} 1169 1170/* 1171 * Set channel on 5112 and newer 1172 */ 1173static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1174 struct ieee80211_channel *channel) 1175{ 1176 u32 data, data0, data1, data2; 1177 u16 c; 1178 1179 data = data0 = data1 = data2 = 0; 1180 c = channel->center_freq; 1181 1182 if (c < 4800) { 1183 if (!((c - 2224) % 5)) { 1184 data0 = ((2 * (c - 704)) - 3040) / 10; 1185 data1 = 1; 1186 } else if (!((c - 2192) % 5)) { 1187 data0 = ((2 * (c - 672)) - 3040) / 10; 1188 data1 = 0; 1189 } else 1190 return -EINVAL; 1191 1192 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1193 } else if ((c % 5) != 2 || c > 5435) { 1194 if (!(c % 20) && c >= 5120) { 1195 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1196 data2 = ath5k_hw_bitswap(3, 2); 1197 } else if (!(c % 10)) { 1198 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1199 data2 = ath5k_hw_bitswap(2, 2); 1200 } else if (!(c % 5)) { 1201 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1202 data2 = ath5k_hw_bitswap(1, 2); 1203 } else 1204 return -EINVAL; 1205 } else { 1206 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1207 data2 = ath5k_hw_bitswap(0, 2); 1208 } 1209 1210 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1211 1212 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1213 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1214 1215 return 0; 1216} 1217 1218/* 1219 * Set the channel on the RF2425 1220 */ 1221static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1222 struct ieee80211_channel *channel) 1223{ 1224 u32 data, data0, data2; 1225 u16 c; 1226 1227 data = data0 = data2 = 0; 1228 c = channel->center_freq; 1229 1230 if (c < 4800) { 1231 data0 = ath5k_hw_bitswap((c - 2272), 8); 1232 data2 = 0; 1233 /* ? 5GHz ? */ 1234 } else if ((c % 5) != 2 || c > 5435) { 1235 if (!(c % 20) && c < 5120) 1236 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1237 else if (!(c % 10)) 1238 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1239 else if (!(c % 5)) 1240 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1241 else 1242 return -EINVAL; 1243 data2 = ath5k_hw_bitswap(1, 2); 1244 } else { 1245 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1246 data2 = ath5k_hw_bitswap(0, 2); 1247 } 1248 1249 data = (data0 << 4) | data2 << 2 | 0x1001; 1250 1251 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1252 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1253 1254 return 0; 1255} 1256 1257/* 1258 * Set a channel on the radio chip 1259 */ 1260static int ath5k_hw_channel(struct ath5k_hw *ah, 1261 struct ieee80211_channel *channel) 1262{ 1263 int ret; 1264 /* 1265 * Check bounds supported by the PHY (we don't care about regulatory 1266 * restrictions at this point). Note: hw_value already has the band 1267 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1268 * of the band by that */ 1269 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1270 ATH5K_ERR(ah->ah_sc, 1271 "channel frequency (%u MHz) out of supported " 1272 "band range\n", 1273 channel->center_freq); 1274 return -EINVAL; 1275 } 1276 1277 /* 1278 * Set the channel and wait 1279 */ 1280 switch (ah->ah_radio) { 1281 case AR5K_RF5110: 1282 ret = ath5k_hw_rf5110_channel(ah, channel); 1283 break; 1284 case AR5K_RF5111: 1285 ret = ath5k_hw_rf5111_channel(ah, channel); 1286 break; 1287 case AR5K_RF2317: 1288 case AR5K_RF2425: 1289 ret = ath5k_hw_rf2425_channel(ah, channel); 1290 break; 1291 default: 1292 ret = ath5k_hw_rf5112_channel(ah, channel); 1293 break; 1294 } 1295 1296 if (ret) 1297 return ret; 1298 1299 /* Set JAPAN setting for channel 14 */ 1300 if (channel->center_freq == 2484) { 1301 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1302 AR5K_PHY_CCKTXCTL_JAPAN); 1303 } else { 1304 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1305 AR5K_PHY_CCKTXCTL_WORLD); 1306 } 1307 1308 ah->ah_current_channel = channel; 1309 1310 return 0; 1311} 1312 1313/*****************\ 1314 PHY calibration 1315\*****************/ 1316 1317static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1318{ 1319 s32 val; 1320 1321 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1322 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1323} 1324 1325void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1326{ 1327 int i; 1328 1329 ah->ah_nfcal_hist.index = 0; 1330 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1331 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1332} 1333 1334static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1335{ 1336 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1337 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1); 1338 hist->nfval[hist->index] = noise_floor; 1339} 1340 1341static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1342{ 1343 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1344 s16 tmp; 1345 int i, j; 1346 1347 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1348 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1349 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1350 if (sort[j] > sort[j - 1]) { 1351 tmp = sort[j]; 1352 sort[j] = sort[j - 1]; 1353 sort[j - 1] = tmp; 1354 } 1355 } 1356 } 1357 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1358 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1359 "cal %d:%d\n", i, sort[i]); 1360 } 1361 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; 1362} 1363 1364/* 1365 * When we tell the hardware to perform a noise floor calibration 1366 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1367 * sample-and-hold the minimum noise level seen at the antennas. 1368 * This value is then stored in a ring buffer of recently measured 1369 * noise floor values so we have a moving window of the last few 1370 * samples. 1371 * 1372 * The median of the values in the history is then loaded into the 1373 * hardware for its own use for RSSI and CCA measurements. 1374 */ 1375void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1376{ 1377 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1378 u32 val; 1379 s16 nf, threshold; 1380 u8 ee_mode; 1381 1382 /* keep last value if calibration hasn't completed */ 1383 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1384 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1385 "NF did not complete in calibration window\n"); 1386 1387 return; 1388 } 1389 1390 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1391 1392 /* completed NF calibration, test threshold */ 1393 nf = ath5k_hw_read_measured_noise_floor(ah); 1394 threshold = ee->ee_noise_floor_thr[ee_mode]; 1395 1396 if (nf > threshold) { 1397 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1398 "noise floor failure detected; " 1399 "read %d, threshold %d\n", 1400 nf, threshold); 1401 1402 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1403 } 1404 1405 ath5k_hw_update_nfcal_hist(ah, nf); 1406 nf = ath5k_hw_get_median_noise_floor(ah); 1407 1408 /* load noise floor (in .5 dBm) so the hardware will use it */ 1409 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1410 val |= (nf * 2) & AR5K_PHY_NF_M; 1411 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1412 1413 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1414 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1415 1416 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1417 0, false); 1418 1419 /* 1420 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1421 * so that we're not capped by the median we just loaded. 1422 * This will be used as the initial value for the next noise 1423 * floor calibration. 1424 */ 1425 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1426 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1427 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1428 AR5K_PHY_AGCCTL_NF_EN | 1429 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1430 AR5K_PHY_AGCCTL_NF); 1431 1432 ah->ah_noise_floor = nf; 1433 1434 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1435 "noise floor calibrated: %d\n", nf); 1436} 1437 1438/* 1439 * Perform a PHY calibration on RF5110 1440 * -Fix BPSK/QAM Constellation (I/Q correction) 1441 */ 1442static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1443 struct ieee80211_channel *channel) 1444{ 1445 u32 phy_sig, phy_agc, phy_sat, beacon; 1446 int ret; 1447 1448 /* 1449 * Disable beacons and RX/TX queues, wait 1450 */ 1451 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1452 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1453 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1454 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1455 1456 mdelay(2); 1457 1458 /* 1459 * Set the channel (with AGC turned off) 1460 */ 1461 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1462 udelay(10); 1463 ret = ath5k_hw_channel(ah, channel); 1464 1465 /* 1466 * Activate PHY and wait 1467 */ 1468 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1469 mdelay(1); 1470 1471 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1472 1473 if (ret) 1474 return ret; 1475 1476 /* 1477 * Calibrate the radio chip 1478 */ 1479 1480 /* Remember normal state */ 1481 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1482 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1483 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1484 1485 /* Update radio registers */ 1486 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1487 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1488 1489 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1490 AR5K_PHY_AGCCOARSE_LO)) | 1491 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1492 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1493 1494 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1495 AR5K_PHY_ADCSAT_THR)) | 1496 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1497 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1498 1499 udelay(20); 1500 1501 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1502 udelay(10); 1503 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1504 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1505 1506 mdelay(1); 1507 1508 /* 1509 * Enable calibration and wait until completion 1510 */ 1511 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1512 1513 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1514 AR5K_PHY_AGCCTL_CAL, 0, false); 1515 1516 /* Reset to normal state */ 1517 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1518 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1519 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1520 1521 if (ret) { 1522 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1523 channel->center_freq); 1524 return ret; 1525 } 1526 1527 /* 1528 * Re-enable RX/TX and beacons 1529 */ 1530 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1531 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1532 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1533 1534 return 0; 1535} 1536 1537/* 1538 * Perform I/Q calibration on RF5111/5112 and newer chips 1539 */ 1540static int 1541ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1542{ 1543 u32 i_pwr, q_pwr; 1544 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1545 int i; 1546 1547 if (!ah->ah_calibration || 1548 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1549 return 0; 1550 1551 /* Calibration has finished, get the results and re-run */ 1552 /* work around empty results which can apparently happen on 5212 */ 1553 for (i = 0; i <= 10; i++) { 1554 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1555 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1556 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1557 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1558 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1559 if (i_pwr && q_pwr) 1560 break; 1561 } 1562 1563 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1564 1565 if (ah->ah_version == AR5K_AR5211) 1566 q_coffd = q_pwr >> 6; 1567 else 1568 q_coffd = q_pwr >> 7; 1569 1570 /* protect against divide by 0 and loss of sign bits */ 1571 if (i_coffd == 0 || q_coffd < 2) 1572 return 0; 1573 1574 i_coff = (-iq_corr) / i_coffd; 1575 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1576 1577 if (ah->ah_version == AR5K_AR5211) 1578 q_coff = (i_pwr / q_coffd) - 64; 1579 else 1580 q_coff = (i_pwr / q_coffd) - 128; 1581 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1582 1583 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1584 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1585 i_coff, q_coff, i_coffd, q_coffd); 1586 1587 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1588 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1589 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1590 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1591 1592 /* Re-enable calibration -if we don't we'll commit 1593 * the same values again and again */ 1594 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1595 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1596 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1597 1598 return 0; 1599} 1600 1601/* 1602 * Perform a PHY calibration 1603 */ 1604int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1605 struct ieee80211_channel *channel) 1606{ 1607 int ret; 1608 1609 if (ah->ah_radio == AR5K_RF5110) 1610 return ath5k_hw_rf5110_calibrate(ah, channel); 1611 1612 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1613 1614 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) && 1615 (channel->hw_value & CHANNEL_OFDM)) 1616 ath5k_hw_request_rfgain_probe(ah); 1617 1618 return ret; 1619} 1620 1621 1622/***************************\ 1623* Spur mitigation functions * 1624\***************************/ 1625 1626static void 1627ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1628 struct ieee80211_channel *channel) 1629{ 1630 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1631 u32 mag_mask[4] = {0, 0, 0, 0}; 1632 u32 pilot_mask[2] = {0, 0}; 1633 /* Note: fbin values are scaled up by 2 */ 1634 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1635 s32 spur_delta_phase, spur_freq_sigma_delta; 1636 s32 spur_offset, num_symbols_x16; 1637 u8 num_symbol_offsets, i, freq_band; 1638 1639 /* Convert current frequency to fbin value (the same way channels 1640 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1641 * up by 2 so we can compare it later */ 1642 if (channel->hw_value & CHANNEL_2GHZ) { 1643 chan_fbin = (channel->center_freq - 2300) * 10; 1644 freq_band = AR5K_EEPROM_BAND_2GHZ; 1645 } else { 1646 chan_fbin = (channel->center_freq - 4900) * 10; 1647 freq_band = AR5K_EEPROM_BAND_5GHZ; 1648 } 1649 1650 /* Check if any spur_chan_fbin from EEPROM is 1651 * within our current channel's spur detection range */ 1652 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1653 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1654 /* XXX: Half/Quarter channels ?*/ 1655 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1656 spur_detection_window *= 2; 1657 1658 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1659 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1660 1661 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1662 * so it's zero if we got nothing from EEPROM */ 1663 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1664 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1665 break; 1666 } 1667 1668 if ((chan_fbin - spur_detection_window <= 1669 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1670 (chan_fbin + spur_detection_window >= 1671 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1672 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1673 break; 1674 } 1675 } 1676 1677 /* We need to enable spur filter for this channel */ 1678 if (spur_chan_fbin) { 1679 spur_offset = spur_chan_fbin - chan_fbin; 1680 /* 1681 * Calculate deltas: 1682 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1683 * spur_delta_phase -> spur_offset / chip_freq << 11 1684 * Note: Both values have 100Hz resolution 1685 */ 1686 switch (ah->ah_bwmode) { 1687 case AR5K_BWMODE_40MHZ: 1688 /* Both sample_freq and chip_freq are 80MHz */ 1689 spur_delta_phase = (spur_offset << 16) / 25; 1690 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1691 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1692 break; 1693 case AR5K_BWMODE_10MHZ: 1694 /* Both sample_freq and chip_freq are 20MHz (?) */ 1695 spur_delta_phase = (spur_offset << 18) / 25; 1696 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1697 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1698 case AR5K_BWMODE_5MHZ: 1699 /* Both sample_freq and chip_freq are 10MHz (?) */ 1700 spur_delta_phase = (spur_offset << 19) / 25; 1701 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1702 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1703 default: 1704 if (channel->hw_value == CHANNEL_A) { 1705 /* Both sample_freq and chip_freq are 40MHz */ 1706 spur_delta_phase = (spur_offset << 17) / 25; 1707 spur_freq_sigma_delta = 1708 (spur_delta_phase >> 10); 1709 symbol_width = 1710 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1711 } else { 1712 /* sample_freq -> 40MHz chip_freq -> 44MHz 1713 * (for b compatibility) */ 1714 spur_delta_phase = (spur_offset << 17) / 25; 1715 spur_freq_sigma_delta = 1716 (spur_offset << 8) / 55; 1717 symbol_width = 1718 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1719 } 1720 break; 1721 } 1722 1723 /* Calculate pilot and magnitude masks */ 1724 1725 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1726 * and divide by symbol_width to find how many symbols we have 1727 * Note: number of symbols is scaled up by 16 */ 1728 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1729 1730 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1731 if (!(num_symbols_x16 & 0xF)) 1732 /* _X_ */ 1733 num_symbol_offsets = 3; 1734 else 1735 /* _xx_ */ 1736 num_symbol_offsets = 4; 1737 1738 for (i = 0; i < num_symbol_offsets; i++) { 1739 1740 /* Calculate pilot mask */ 1741 s32 curr_sym_off = 1742 (num_symbols_x16 / 16) + i + 25; 1743 1744 /* Pilot magnitude mask seems to be a way to 1745 * declare the boundaries for our detection 1746 * window or something, it's 2 for the middle 1747 * value(s) where the symbol is expected to be 1748 * and 1 on the boundary values */ 1749 u8 plt_mag_map = 1750 (i == 0 || i == (num_symbol_offsets - 1)) 1751 ? 1 : 2; 1752 1753 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1754 if (curr_sym_off <= 25) 1755 pilot_mask[0] |= 1 << curr_sym_off; 1756 else if (curr_sym_off >= 27) 1757 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1758 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1759 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1760 1761 /* Calculate magnitude mask (for viterbi decoder) */ 1762 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1763 mag_mask[0] |= 1764 plt_mag_map << (curr_sym_off + 1) * 2; 1765 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1766 mag_mask[1] |= 1767 plt_mag_map << (curr_sym_off - 15) * 2; 1768 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1769 mag_mask[2] |= 1770 plt_mag_map << (curr_sym_off - 31) * 2; 1771 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1772 mag_mask[3] |= 1773 plt_mag_map << (curr_sym_off - 47) * 2; 1774 1775 } 1776 1777 /* Write settings on hw to enable spur filter */ 1778 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1779 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1780 /* XXX: Self correlator also ? */ 1781 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1782 AR5K_PHY_IQ_PILOT_MASK_EN | 1783 AR5K_PHY_IQ_CHAN_MASK_EN | 1784 AR5K_PHY_IQ_SPUR_FILT_EN); 1785 1786 /* Set delta phase and freq sigma delta */ 1787 ath5k_hw_reg_write(ah, 1788 AR5K_REG_SM(spur_delta_phase, 1789 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1790 AR5K_REG_SM(spur_freq_sigma_delta, 1791 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1792 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1793 AR5K_PHY_TIMING_11); 1794 1795 /* Write pilot masks */ 1796 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1798 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1799 pilot_mask[1]); 1800 1801 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1802 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1803 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1804 pilot_mask[1]); 1805 1806 /* Write magnitude masks */ 1807 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1808 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1809 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1810 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1811 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1812 mag_mask[3]); 1813 1814 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1815 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1816 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1817 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1818 AR5K_PHY_BIN_MASK2_4_MASK_4, 1819 mag_mask[3]); 1820 1821 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1822 AR5K_PHY_IQ_SPUR_FILT_EN) { 1823 /* Clean up spur mitigation settings and disable filter */ 1824 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1825 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1826 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1827 AR5K_PHY_IQ_PILOT_MASK_EN | 1828 AR5K_PHY_IQ_CHAN_MASK_EN | 1829 AR5K_PHY_IQ_SPUR_FILT_EN); 1830 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1831 1832 /* Clear pilot masks */ 1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1835 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1836 0); 1837 1838 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1839 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1840 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1841 0); 1842 1843 /* Clear magnitude masks */ 1844 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1845 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1846 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1847 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1848 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1849 0); 1850 1851 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1852 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1853 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1854 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1855 AR5K_PHY_BIN_MASK2_4_MASK_4, 1856 0); 1857 } 1858} 1859 1860 1861/*****************\ 1862* Antenna control * 1863\*****************/ 1864 1865static void /*TODO:Boundary check*/ 1866ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1867{ 1868 if (ah->ah_version != AR5K_AR5210) 1869 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1870} 1871 1872/* 1873 * Enable/disable fast rx antenna diversity 1874 */ 1875static void 1876ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1877{ 1878 switch (ee_mode) { 1879 case AR5K_EEPROM_MODE_11G: 1880 /* XXX: This is set to 1881 * disabled on initvals !!! */ 1882 case AR5K_EEPROM_MODE_11A: 1883 if (enable) 1884 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1885 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1886 else 1887 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1888 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1889 break; 1890 case AR5K_EEPROM_MODE_11B: 1891 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1892 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1893 break; 1894 default: 1895 return; 1896 } 1897 1898 if (enable) { 1899 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1900 AR5K_PHY_RESTART_DIV_GC, 4); 1901 1902 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1903 AR5K_PHY_FAST_ANT_DIV_EN); 1904 } else { 1905 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1906 AR5K_PHY_RESTART_DIV_GC, 0); 1907 1908 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1909 AR5K_PHY_FAST_ANT_DIV_EN); 1910 } 1911} 1912 1913void 1914ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1915{ 1916 u8 ant0, ant1; 1917 1918 /* 1919 * In case a fixed antenna was set as default 1920 * use the same switch table twice. 1921 */ 1922 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1923 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1924 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1925 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1926 else { 1927 ant0 = AR5K_ANT_SWTABLE_A; 1928 ant1 = AR5K_ANT_SWTABLE_B; 1929 } 1930 1931 /* Set antenna idle switch table */ 1932 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1933 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1934 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1935 AR5K_PHY_ANT_CTL_TXRX_EN)); 1936 1937 /* Set antenna switch tables */ 1938 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1939 AR5K_PHY_ANT_SWITCH_TABLE_0); 1940 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1941 AR5K_PHY_ANT_SWITCH_TABLE_1); 1942} 1943 1944/* 1945 * Set antenna operating mode 1946 */ 1947void 1948ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1949{ 1950 struct ieee80211_channel *channel = ah->ah_current_channel; 1951 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1952 bool use_def_for_sg; 1953 int ee_mode; 1954 u8 def_ant, tx_ant; 1955 u32 sta_id1 = 0; 1956 1957 /* if channel is not initialized yet we can't set the antennas 1958 * so just store the mode. it will be set on the next reset */ 1959 if (channel == NULL) { 1960 ah->ah_ant_mode = ant_mode; 1961 return; 1962 } 1963 1964 def_ant = ah->ah_def_ant; 1965 1966 ee_mode = ath5k_eeprom_mode_from_channel(channel); 1967 if (ee_mode < 0) { 1968 ATH5K_ERR(ah->ah_sc, 1969 "invalid channel: %d\n", channel->center_freq); 1970 return; 1971 } 1972 1973 switch (ant_mode) { 1974 case AR5K_ANTMODE_DEFAULT: 1975 tx_ant = 0; 1976 use_def_for_tx = false; 1977 update_def_on_tx = false; 1978 use_def_for_rts = false; 1979 use_def_for_sg = false; 1980 fast_div = true; 1981 break; 1982 case AR5K_ANTMODE_FIXED_A: 1983 def_ant = 1; 1984 tx_ant = 1; 1985 use_def_for_tx = true; 1986 update_def_on_tx = false; 1987 use_def_for_rts = true; 1988 use_def_for_sg = true; 1989 fast_div = false; 1990 break; 1991 case AR5K_ANTMODE_FIXED_B: 1992 def_ant = 2; 1993 tx_ant = 2; 1994 use_def_for_tx = true; 1995 update_def_on_tx = false; 1996 use_def_for_rts = true; 1997 use_def_for_sg = true; 1998 fast_div = false; 1999 break; 2000 case AR5K_ANTMODE_SINGLE_AP: 2001 def_ant = 1; /* updated on tx */ 2002 tx_ant = 0; 2003 use_def_for_tx = true; 2004 update_def_on_tx = true; 2005 use_def_for_rts = true; 2006 use_def_for_sg = true; 2007 fast_div = true; 2008 break; 2009 case AR5K_ANTMODE_SECTOR_AP: 2010 tx_ant = 1; /* variable */ 2011 use_def_for_tx = false; 2012 update_def_on_tx = false; 2013 use_def_for_rts = true; 2014 use_def_for_sg = false; 2015 fast_div = false; 2016 break; 2017 case AR5K_ANTMODE_SECTOR_STA: 2018 tx_ant = 1; /* variable */ 2019 use_def_for_tx = true; 2020 update_def_on_tx = false; 2021 use_def_for_rts = true; 2022 use_def_for_sg = false; 2023 fast_div = true; 2024 break; 2025 case AR5K_ANTMODE_DEBUG: 2026 def_ant = 1; 2027 tx_ant = 2; 2028 use_def_for_tx = false; 2029 update_def_on_tx = false; 2030 use_def_for_rts = false; 2031 use_def_for_sg = false; 2032 fast_div = false; 2033 break; 2034 default: 2035 return; 2036 } 2037 2038 ah->ah_tx_ant = tx_ant; 2039 ah->ah_ant_mode = ant_mode; 2040 ah->ah_def_ant = def_ant; 2041 2042 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2043 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2044 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2045 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2046 2047 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2048 2049 if (sta_id1) 2050 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2051 2052 ath5k_hw_set_antenna_switch(ah, ee_mode); 2053 /* Note: set diversity before default antenna 2054 * because it won't work correctly */ 2055 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2056 ath5k_hw_set_def_antenna(ah, def_ant); 2057} 2058 2059 2060/****************\ 2061* TX power setup * 2062\****************/ 2063 2064/* 2065 * Helper functions 2066 */ 2067 2068/* 2069 * Do linear interpolation between two given (x, y) points 2070 */ 2071static s16 2072ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2073 s16 y_left, s16 y_right) 2074{ 2075 s16 ratio, result; 2076 2077 /* Avoid divide by zero and skip interpolation 2078 * if we have the same point */ 2079 if ((x_left == x_right) || (y_left == y_right)) 2080 return y_left; 2081 2082 /* 2083 * Since we use ints and not fps, we need to scale up in 2084 * order to get a sane ratio value (or else we 'll eg. get 2085 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2086 * to have some accuracy both for 0.5 and 0.25 steps. 2087 */ 2088 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left)); 2089 2090 /* Now scale down to be in range */ 2091 result = y_left + (ratio * (target - x_left) / 100); 2092 2093 return result; 2094} 2095 2096/* 2097 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2098 * 2099 * Since we have the top of the curve and we draw the line below 2100 * until we reach 1 (1 pcdac step) we need to know which point 2101 * (x value) that is so that we don't go below y axis and have negative 2102 * pcdac values when creating the curve, or fill the table with zeroes. 2103 */ 2104static s16 2105ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2106 const s16 *pwrL, const s16 *pwrR) 2107{ 2108 s8 tmp; 2109 s16 min_pwrL, min_pwrR; 2110 s16 pwr_i; 2111 2112 /* Some vendors write the same pcdac value twice !!! */ 2113 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2114 return max(pwrL[0], pwrR[0]); 2115 2116 if (pwrL[0] == pwrL[1]) 2117 min_pwrL = pwrL[0]; 2118 else { 2119 pwr_i = pwrL[0]; 2120 do { 2121 pwr_i--; 2122 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2123 pwrL[0], pwrL[1], 2124 stepL[0], stepL[1]); 2125 } while (tmp > 1); 2126 2127 min_pwrL = pwr_i; 2128 } 2129 2130 if (pwrR[0] == pwrR[1]) 2131 min_pwrR = pwrR[0]; 2132 else { 2133 pwr_i = pwrR[0]; 2134 do { 2135 pwr_i--; 2136 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2137 pwrR[0], pwrR[1], 2138 stepR[0], stepR[1]); 2139 } while (tmp > 1); 2140 2141 min_pwrR = pwr_i; 2142 } 2143 2144 /* Keep the right boundary so that it works for both curves */ 2145 return max(min_pwrL, min_pwrR); 2146} 2147 2148/* 2149 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2150 * Power to PCDAC curve. 2151 * 2152 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2153 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2154 * PCDAC/PDADC step for each curve is 64 but we can write more than 2155 * one curves on hw so we can go up to 128 (which is the max step we 2156 * can write on the final table). 2157 * 2158 * We write y values (PCDAC/PDADC steps) on hw. 2159 */ 2160static void 2161ath5k_create_power_curve(s16 pmin, s16 pmax, 2162 const s16 *pwr, const u8 *vpd, 2163 u8 num_points, 2164 u8 *vpd_table, u8 type) 2165{ 2166 u8 idx[2] = { 0, 1 }; 2167 s16 pwr_i = 2 * pmin; 2168 int i; 2169 2170 if (num_points < 2) 2171 return; 2172 2173 /* We want the whole line, so adjust boundaries 2174 * to cover the entire power range. Note that 2175 * power values are already 0.25dB so no need 2176 * to multiply pwr_i by 2 */ 2177 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2178 pwr_i = pmin; 2179 pmin = 0; 2180 pmax = 63; 2181 } 2182 2183 /* Find surrounding turning points (TPs) 2184 * and interpolate between them */ 2185 for (i = 0; (i <= (u16) (pmax - pmin)) && 2186 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2187 2188 /* We passed the right TP, move to the next set of TPs 2189 * if we pass the last TP, extrapolate above using the last 2190 * two TPs for ratio */ 2191 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2192 idx[0]++; 2193 idx[1]++; 2194 } 2195 2196 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2197 pwr[idx[0]], pwr[idx[1]], 2198 vpd[idx[0]], vpd[idx[1]]); 2199 2200 /* Increase by 0.5dB 2201 * (0.25 dB units) */ 2202 pwr_i += 2; 2203 } 2204} 2205 2206/* 2207 * Get the surrounding per-channel power calibration piers 2208 * for a given frequency so that we can interpolate between 2209 * them and come up with an appropriate dataset for our current 2210 * channel. 2211 */ 2212static void 2213ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2214 struct ieee80211_channel *channel, 2215 struct ath5k_chan_pcal_info **pcinfo_l, 2216 struct ath5k_chan_pcal_info **pcinfo_r) 2217{ 2218 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2219 struct ath5k_chan_pcal_info *pcinfo; 2220 u8 idx_l, idx_r; 2221 u8 mode, max, i; 2222 u32 target = channel->center_freq; 2223 2224 idx_l = 0; 2225 idx_r = 0; 2226 2227 if (!(channel->hw_value & CHANNEL_OFDM)) { 2228 pcinfo = ee->ee_pwr_cal_b; 2229 mode = AR5K_EEPROM_MODE_11B; 2230 } else if (channel->hw_value & CHANNEL_2GHZ) { 2231 pcinfo = ee->ee_pwr_cal_g; 2232 mode = AR5K_EEPROM_MODE_11G; 2233 } else { 2234 pcinfo = ee->ee_pwr_cal_a; 2235 mode = AR5K_EEPROM_MODE_11A; 2236 } 2237 max = ee->ee_n_piers[mode] - 1; 2238 2239 /* Frequency is below our calibrated 2240 * range. Use the lowest power curve 2241 * we have */ 2242 if (target < pcinfo[0].freq) { 2243 idx_l = idx_r = 0; 2244 goto done; 2245 } 2246 2247 /* Frequency is above our calibrated 2248 * range. Use the highest power curve 2249 * we have */ 2250 if (target > pcinfo[max].freq) { 2251 idx_l = idx_r = max; 2252 goto done; 2253 } 2254 2255 /* Frequency is inside our calibrated 2256 * channel range. Pick the surrounding 2257 * calibration piers so that we can 2258 * interpolate */ 2259 for (i = 0; i <= max; i++) { 2260 2261 /* Frequency matches one of our calibration 2262 * piers, no need to interpolate, just use 2263 * that calibration pier */ 2264 if (pcinfo[i].freq == target) { 2265 idx_l = idx_r = i; 2266 goto done; 2267 } 2268 2269 /* We found a calibration pier that's above 2270 * frequency, use this pier and the previous 2271 * one to interpolate */ 2272 if (target < pcinfo[i].freq) { 2273 idx_r = i; 2274 idx_l = idx_r - 1; 2275 goto done; 2276 } 2277 } 2278 2279done: 2280 *pcinfo_l = &pcinfo[idx_l]; 2281 *pcinfo_r = &pcinfo[idx_r]; 2282} 2283 2284/* 2285 * Get the surrounding per-rate power calibration data 2286 * for a given frequency and interpolate between power 2287 * values to set max target power supported by hw for 2288 * each rate. 2289 */ 2290static void 2291ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2292 struct ieee80211_channel *channel, 2293 struct ath5k_rate_pcal_info *rates) 2294{ 2295 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2296 struct ath5k_rate_pcal_info *rpinfo; 2297 u8 idx_l, idx_r; 2298 u8 mode, max, i; 2299 u32 target = channel->center_freq; 2300 2301 idx_l = 0; 2302 idx_r = 0; 2303 2304 if (!(channel->hw_value & CHANNEL_OFDM)) { 2305 rpinfo = ee->ee_rate_tpwr_b; 2306 mode = AR5K_EEPROM_MODE_11B; 2307 } else if (channel->hw_value & CHANNEL_2GHZ) { 2308 rpinfo = ee->ee_rate_tpwr_g; 2309 mode = AR5K_EEPROM_MODE_11G; 2310 } else { 2311 rpinfo = ee->ee_rate_tpwr_a; 2312 mode = AR5K_EEPROM_MODE_11A; 2313 } 2314 max = ee->ee_rate_target_pwr_num[mode] - 1; 2315 2316 /* Get the surrounding calibration 2317 * piers - same as above */ 2318 if (target < rpinfo[0].freq) { 2319 idx_l = idx_r = 0; 2320 goto done; 2321 } 2322 2323 if (target > rpinfo[max].freq) { 2324 idx_l = idx_r = max; 2325 goto done; 2326 } 2327 2328 for (i = 0; i <= max; i++) { 2329 2330 if (rpinfo[i].freq == target) { 2331 idx_l = idx_r = i; 2332 goto done; 2333 } 2334 2335 if (target < rpinfo[i].freq) { 2336 idx_r = i; 2337 idx_l = idx_r - 1; 2338 goto done; 2339 } 2340 } 2341 2342done: 2343 /* Now interpolate power value, based on the frequency */ 2344 rates->freq = target; 2345 2346 rates->target_power_6to24 = 2347 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2348 rpinfo[idx_r].freq, 2349 rpinfo[idx_l].target_power_6to24, 2350 rpinfo[idx_r].target_power_6to24); 2351 2352 rates->target_power_36 = 2353 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2354 rpinfo[idx_r].freq, 2355 rpinfo[idx_l].target_power_36, 2356 rpinfo[idx_r].target_power_36); 2357 2358 rates->target_power_48 = 2359 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2360 rpinfo[idx_r].freq, 2361 rpinfo[idx_l].target_power_48, 2362 rpinfo[idx_r].target_power_48); 2363 2364 rates->target_power_54 = 2365 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2366 rpinfo[idx_r].freq, 2367 rpinfo[idx_l].target_power_54, 2368 rpinfo[idx_r].target_power_54); 2369} 2370 2371/* 2372 * Get the max edge power for this channel if 2373 * we have such data from EEPROM's Conformance Test 2374 * Limits (CTL), and limit max power if needed. 2375 */ 2376static void 2377ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2378 struct ieee80211_channel *channel) 2379{ 2380 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2381 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2382 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2383 u8 *ctl_val = ee->ee_ctl; 2384 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2385 s16 edge_pwr = 0; 2386 u8 rep_idx; 2387 u8 i, ctl_mode; 2388 u8 ctl_idx = 0xFF; 2389 u32 target = channel->center_freq; 2390 2391 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2392 2393 switch (channel->hw_value & CHANNEL_MODES) { 2394 case CHANNEL_A: 2395 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2396 ctl_mode |= AR5K_CTL_TURBO; 2397 else 2398 ctl_mode |= AR5K_CTL_11A; 2399 break; 2400 case CHANNEL_G: 2401 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2402 ctl_mode |= AR5K_CTL_TURBOG; 2403 else 2404 ctl_mode |= AR5K_CTL_11G; 2405 break; 2406 case CHANNEL_B: 2407 ctl_mode |= AR5K_CTL_11B; 2408 break; 2409 case CHANNEL_XR: 2410 /* Fall through */ 2411 default: 2412 return; 2413 } 2414 2415 for (i = 0; i < ee->ee_ctls; i++) { 2416 if (ctl_val[i] == ctl_mode) { 2417 ctl_idx = i; 2418 break; 2419 } 2420 } 2421 2422 /* If we have a CTL dataset available grab it and find the 2423 * edge power for our frequency */ 2424 if (ctl_idx == 0xFF) 2425 return; 2426 2427 /* Edge powers are sorted by frequency from lower 2428 * to higher. Each CTL corresponds to 8 edge power 2429 * measurements. */ 2430 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2431 2432 /* Don't do boundaries check because we 2433 * might have more that one bands defined 2434 * for this mode */ 2435 2436 /* Get the edge power that's closer to our 2437 * frequency */ 2438 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2439 rep_idx += i; 2440 if (target <= rep[rep_idx].freq) 2441 edge_pwr = (s16) rep[rep_idx].edge; 2442 } 2443 2444 if (edge_pwr) 2445 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); 2446} 2447 2448 2449/* 2450 * Power to PCDAC table functions 2451 */ 2452 2453/* 2454 * Fill Power to PCDAC table on RF5111 2455 * 2456 * No further processing is needed for RF5111, the only thing we have to 2457 * do is fill the values below and above calibration range since eeprom data 2458 * may not cover the entire PCDAC table. 2459 */ 2460static void 2461ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2462 s16 *table_max) 2463{ 2464 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2465 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2466 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2467 s16 min_pwr, max_pwr; 2468 2469 /* Get table boundaries */ 2470 min_pwr = table_min[0]; 2471 pcdac_0 = pcdac_tmp[0]; 2472 2473 max_pwr = table_max[0]; 2474 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2475 2476 /* Extrapolate below minimum using pcdac_0 */ 2477 pcdac_i = 0; 2478 for (i = 0; i < min_pwr; i++) 2479 pcdac_out[pcdac_i++] = pcdac_0; 2480 2481 /* Copy values from pcdac_tmp */ 2482 pwr_idx = min_pwr; 2483 for (i = 0; pwr_idx <= max_pwr && 2484 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2485 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2486 pwr_idx++; 2487 } 2488 2489 /* Extrapolate above maximum */ 2490 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2491 pcdac_out[pcdac_i++] = pcdac_n; 2492 2493} 2494 2495/* 2496 * Combine available XPD Curves and fill Linear Power to PCDAC table 2497 * on RF5112 2498 * 2499 * RFX112 can have up to 2 curves (one for low txpower range and one for 2500 * higher txpower range). We need to put them both on pcdac_out and place 2501 * them in the correct location. In case we only have one curve available 2502 * just fit it on pcdac_out (it's supposed to cover the entire range of 2503 * available pwr levels since it's always the higher power curve). Extrapolate 2504 * below and above final table if needed. 2505 */ 2506static void 2507ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2508 s16 *table_max, u8 pdcurves) 2509{ 2510 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2511 u8 *pcdac_low_pwr; 2512 u8 *pcdac_high_pwr; 2513 u8 *pcdac_tmp; 2514 u8 pwr; 2515 s16 max_pwr_idx; 2516 s16 min_pwr_idx; 2517 s16 mid_pwr_idx = 0; 2518 /* Edge flag turns on the 7nth bit on the PCDAC 2519 * to declare the higher power curve (force values 2520 * to be greater than 64). If we only have one curve 2521 * we don't need to set this, if we have 2 curves and 2522 * fill the table backwards this can also be used to 2523 * switch from higher power curve to lower power curve */ 2524 u8 edge_flag; 2525 int i; 2526 2527 /* When we have only one curve available 2528 * that's the higher power curve. If we have 2529 * two curves the first is the high power curve 2530 * and the next is the low power curve. */ 2531 if (pdcurves > 1) { 2532 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2533 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2534 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2535 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2536 2537 /* If table size goes beyond 31.5dB, keep the 2538 * upper 31.5dB range when setting tx power. 2539 * Note: 126 = 31.5 dB in quarter dB steps */ 2540 if (table_max[0] - table_min[1] > 126) 2541 min_pwr_idx = table_max[0] - 126; 2542 else 2543 min_pwr_idx = table_min[1]; 2544 2545 /* Since we fill table backwards 2546 * start from high power curve */ 2547 pcdac_tmp = pcdac_high_pwr; 2548 2549 edge_flag = 0x40; 2550 } else { 2551 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2552 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2553 min_pwr_idx = table_min[0]; 2554 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2555 pcdac_tmp = pcdac_high_pwr; 2556 edge_flag = 0; 2557 } 2558 2559 /* This is used when setting tx power*/ 2560 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; 2561 2562 /* Fill Power to PCDAC table backwards */ 2563 pwr = max_pwr_idx; 2564 for (i = 63; i >= 0; i--) { 2565 /* Entering lower power range, reset 2566 * edge flag and set pcdac_tmp to lower 2567 * power curve.*/ 2568 if (edge_flag == 0x40 && 2569 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2570 edge_flag = 0x00; 2571 pcdac_tmp = pcdac_low_pwr; 2572 pwr = mid_pwr_idx / 2; 2573 } 2574 2575 /* Don't go below 1, extrapolate below if we have 2576 * already switched to the lower power curve -or 2577 * we only have one curve and edge_flag is zero 2578 * anyway */ 2579 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2580 while (i >= 0) { 2581 pcdac_out[i] = pcdac_out[i + 1]; 2582 i--; 2583 } 2584 break; 2585 } 2586 2587 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2588 2589 /* Extrapolate above if pcdac is greater than 2590 * 126 -this can happen because we OR pcdac_out 2591 * value with edge_flag on high power curve */ 2592 if (pcdac_out[i] > 126) 2593 pcdac_out[i] = 126; 2594 2595 /* Decrease by a 0.5dB step */ 2596 pwr--; 2597 } 2598} 2599 2600/* Write PCDAC values on hw */ 2601static void 2602ath5k_write_pcdac_table(struct ath5k_hw *ah) 2603{ 2604 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2605 int i; 2606 2607 /* 2608 * Write TX power values 2609 */ 2610 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2611 ath5k_hw_reg_write(ah, 2612 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) | 2613 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16), 2614 AR5K_PHY_PCDAC_TXPOWER(i)); 2615 } 2616} 2617 2618 2619/* 2620 * Power to PDADC table functions 2621 */ 2622 2623/* 2624 * Set the gain boundaries and create final Power to PDADC table 2625 * 2626 * We can have up to 4 pd curves, we need to do a similar process 2627 * as we do for RF5112. This time we don't have an edge_flag but we 2628 * set the gain boundaries on a separate register. 2629 */ 2630static void 2631ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2632 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2633{ 2634 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2635 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2636 u8 *pdadc_tmp; 2637 s16 pdadc_0; 2638 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2639 u8 pd_gain_overlap; 2640 2641 /* Note: Register value is initialized on initvals 2642 * there is no feedback from hw. 2643 * XXX: What about pd_gain_overlap from EEPROM ? */ 2644 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2645 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2646 2647 /* Create final PDADC table */ 2648 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2649 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2650 2651 if (pdg == pdcurves - 1) 2652 /* 2 dB boundary stretch for last 2653 * (higher power) curve */ 2654 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2655 else 2656 /* Set gain boundary in the middle 2657 * between this curve and the next one */ 2658 gain_boundaries[pdg] = 2659 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2660 2661 /* Sanity check in case our 2 db stretch got out of 2662 * range. */ 2663 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2664 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2665 2666 /* For the first curve (lower power) 2667 * start from 0 dB */ 2668 if (pdg == 0) 2669 pdadc_0 = 0; 2670 else 2671 /* For the other curves use the gain overlap */ 2672 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2673 pd_gain_overlap; 2674 2675 /* Force each power step to be at least 0.5 dB */ 2676 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2677 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2678 else 2679 pwr_step = 1; 2680 2681 /* If pdadc_0 is negative, we need to extrapolate 2682 * below this pdgain by a number of pwr_steps */ 2683 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2684 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2685 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2686 pdadc_0++; 2687 } 2688 2689 /* Set last pwr level, using gain boundaries */ 2690 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2691 /* Limit it to be inside pwr range */ 2692 table_size = pwr_max[pdg] - pwr_min[pdg]; 2693 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2694 2695 /* Fill pdadc_out table */ 2696 while (pdadc_0 < max_idx && pdadc_i < 128) 2697 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2698 2699 /* Need to extrapolate above this pdgain? */ 2700 if (pdadc_n <= max_idx) 2701 continue; 2702 2703 /* Force each power step to be at least 0.5 dB */ 2704 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2705 pwr_step = pdadc_tmp[table_size - 1] - 2706 pdadc_tmp[table_size - 2]; 2707 else 2708 pwr_step = 1; 2709 2710 /* Extrapolate above */ 2711 while ((pdadc_0 < (s16) pdadc_n) && 2712 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2713 s16 tmp = pdadc_tmp[table_size - 1] + 2714 (pdadc_0 - max_idx) * pwr_step; 2715 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2716 pdadc_0++; 2717 } 2718 } 2719 2720 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2721 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2722 pdg++; 2723 } 2724 2725 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2726 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2727 pdadc_i++; 2728 } 2729 2730 /* Set gain boundaries */ 2731 ath5k_hw_reg_write(ah, 2732 AR5K_REG_SM(pd_gain_overlap, 2733 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2734 AR5K_REG_SM(gain_boundaries[0], 2735 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2736 AR5K_REG_SM(gain_boundaries[1], 2737 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2738 AR5K_REG_SM(gain_boundaries[2], 2739 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2740 AR5K_REG_SM(gain_boundaries[3], 2741 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2742 AR5K_PHY_TPC_RG5); 2743 2744 /* Used for setting rate power table */ 2745 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2746 2747} 2748 2749/* Write PDADC values on hw */ 2750static void 2751ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 2752{ 2753 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2754 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2755 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2756 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 2757 u32 reg; 2758 u8 i; 2759 2760 /* Select the right pdgain curves */ 2761 2762 /* Clear current settings */ 2763 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2764 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2765 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2766 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2767 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2768 2769 /* 2770 * Use pd_gains curve from eeprom 2771 * 2772 * This overrides the default setting from initvals 2773 * in case some vendors (e.g. Zcomax) don't use the default 2774 * curves. If we don't honor their settings we 'll get a 2775 * 5dB (1 * gain overlap ?) drop. 2776 */ 2777 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2778 2779 switch (pdcurves) { 2780 case 3: 2781 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2782 /* Fall through */ 2783 case 2: 2784 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2785 /* Fall through */ 2786 case 1: 2787 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2788 break; 2789 } 2790 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2791 2792 /* 2793 * Write TX power values 2794 */ 2795 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2796 ath5k_hw_reg_write(ah, 2797 ((pdadc_out[4 * i + 0] & 0xff) << 0) | 2798 ((pdadc_out[4 * i + 1] & 0xff) << 8) | 2799 ((pdadc_out[4 * i + 2] & 0xff) << 16) | 2800 ((pdadc_out[4 * i + 3] & 0xff) << 24), 2801 AR5K_PHY_PDADC_TXPOWER(i)); 2802 } 2803} 2804 2805 2806/* 2807 * Common code for PCDAC/PDADC tables 2808 */ 2809 2810/* 2811 * This is the main function that uses all of the above 2812 * to set PCDAC/PDADC table on hw for the current channel. 2813 * This table is used for tx power calibration on the baseband, 2814 * without it we get weird tx power levels and in some cases 2815 * distorted spectral mask 2816 */ 2817static int 2818ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2819 struct ieee80211_channel *channel, 2820 u8 ee_mode, u8 type) 2821{ 2822 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2823 struct ath5k_chan_pcal_info *pcinfo_L; 2824 struct ath5k_chan_pcal_info *pcinfo_R; 2825 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2826 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2827 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2828 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2829 u8 *tmpL; 2830 u8 *tmpR; 2831 u32 target = channel->center_freq; 2832 int pdg, i; 2833 2834 /* Get surrounding freq piers for this channel */ 2835 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2836 &pcinfo_L, 2837 &pcinfo_R); 2838 2839 /* Loop over pd gain curves on 2840 * surrounding freq piers by index */ 2841 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2842 2843 /* Fill curves in reverse order 2844 * from lower power (max gain) 2845 * to higher power. Use curve -> idx 2846 * backmapping we did on eeprom init */ 2847 u8 idx = pdg_curve_to_idx[pdg]; 2848 2849 /* Grab the needed curves by index */ 2850 pdg_L = &pcinfo_L->pd_curves[idx]; 2851 pdg_R = &pcinfo_R->pd_curves[idx]; 2852 2853 /* Initialize the temp tables */ 2854 tmpL = ah->ah_txpower.tmpL[pdg]; 2855 tmpR = ah->ah_txpower.tmpR[pdg]; 2856 2857 /* Set curve's x boundaries and create 2858 * curves so that they cover the same 2859 * range (if we don't do that one table 2860 * will have values on some range and the 2861 * other one won't have any so interpolation 2862 * will fail) */ 2863 table_min[pdg] = min(pdg_L->pd_pwr[0], 2864 pdg_R->pd_pwr[0]) / 2; 2865 2866 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2867 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2868 2869 /* Now create the curves on surrounding channels 2870 * and interpolate if needed to get the final 2871 * curve for this gain on this channel */ 2872 switch (type) { 2873 case AR5K_PWRTABLE_LINEAR_PCDAC: 2874 /* Override min/max so that we don't loose 2875 * accuracy (don't divide by 2) */ 2876 table_min[pdg] = min(pdg_L->pd_pwr[0], 2877 pdg_R->pd_pwr[0]); 2878 2879 table_max[pdg] = 2880 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2881 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2882 2883 /* Override minimum so that we don't get 2884 * out of bounds while extrapolating 2885 * below. Don't do this when we have 2 2886 * curves and we are on the high power curve 2887 * because table_min is ok in this case */ 2888 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2889 2890 table_min[pdg] = 2891 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2892 pdg_R->pd_step, 2893 pdg_L->pd_pwr, 2894 pdg_R->pd_pwr); 2895 2896 /* Don't go too low because we will 2897 * miss the upper part of the curve. 2898 * Note: 126 = 31.5dB (max power supported) 2899 * in 0.25dB units */ 2900 if (table_max[pdg] - table_min[pdg] > 126) 2901 table_min[pdg] = table_max[pdg] - 126; 2902 } 2903 2904 /* Fall through */ 2905 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2906 case AR5K_PWRTABLE_PWR_TO_PDADC: 2907 2908 ath5k_create_power_curve(table_min[pdg], 2909 table_max[pdg], 2910 pdg_L->pd_pwr, 2911 pdg_L->pd_step, 2912 pdg_L->pd_points, tmpL, type); 2913 2914 /* We are in a calibration 2915 * pier, no need to interpolate 2916 * between freq piers */ 2917 if (pcinfo_L == pcinfo_R) 2918 continue; 2919 2920 ath5k_create_power_curve(table_min[pdg], 2921 table_max[pdg], 2922 pdg_R->pd_pwr, 2923 pdg_R->pd_step, 2924 pdg_R->pd_points, tmpR, type); 2925 break; 2926 default: 2927 return -EINVAL; 2928 } 2929 2930 /* Interpolate between curves 2931 * of surrounding freq piers to 2932 * get the final curve for this 2933 * pd gain. Re-use tmpL for interpolation 2934 * output */ 2935 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2936 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2937 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2938 (s16) pcinfo_L->freq, 2939 (s16) pcinfo_R->freq, 2940 (s16) tmpL[i], 2941 (s16) tmpR[i]); 2942 } 2943 } 2944 2945 /* Now we have a set of curves for this 2946 * channel on tmpL (x range is table_max - table_min 2947 * and y values are tmpL[pdg][]) sorted in the same 2948 * order as EEPROM (because we've used the backmapping). 2949 * So for RF5112 it's from higher power to lower power 2950 * and for RF2413 it's from lower power to higher power. 2951 * For RF5111 we only have one curve. */ 2952 2953 /* Fill min and max power levels for this 2954 * channel by interpolating the values on 2955 * surrounding channels to complete the dataset */ 2956 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2957 (s16) pcinfo_L->freq, 2958 (s16) pcinfo_R->freq, 2959 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2960 2961 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2962 (s16) pcinfo_L->freq, 2963 (s16) pcinfo_R->freq, 2964 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2965 2966 /* Fill PCDAC/PDADC table */ 2967 switch (type) { 2968 case AR5K_PWRTABLE_LINEAR_PCDAC: 2969 /* For RF5112 we can have one or two curves 2970 * and each curve covers a certain power lvl 2971 * range so we need to do some more processing */ 2972 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2973 ee->ee_pd_gains[ee_mode]); 2974 2975 /* Set txp.offset so that we can 2976 * match max power value with max 2977 * table index */ 2978 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2979 break; 2980 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2981 /* We are done for RF5111 since it has only 2982 * one curve, just fit the curve on the table */ 2983 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2984 2985 /* No rate powertable adjustment for RF5111 */ 2986 ah->ah_txpower.txp_min_idx = 0; 2987 ah->ah_txpower.txp_offset = 0; 2988 break; 2989 case AR5K_PWRTABLE_PWR_TO_PDADC: 2990 /* Set PDADC boundaries and fill 2991 * final PDADC table */ 2992 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2993 ee->ee_pd_gains[ee_mode]); 2994 2995 /* Set txp.offset, note that table_min 2996 * can be negative */ 2997 ah->ah_txpower.txp_offset = table_min[0]; 2998 break; 2999 default: 3000 return -EINVAL; 3001 } 3002 3003 ah->ah_txpower.txp_setup = true; 3004 3005 return 0; 3006} 3007 3008/* Write power table for current channel to hw */ 3009static void 3010ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3011{ 3012 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 3013 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 3014 else 3015 ath5k_write_pcdac_table(ah); 3016} 3017 3018/* 3019 * Per-rate tx power setting 3020 * 3021 * This is the code that sets the desired tx power (below 3022 * maximum) on hw for each rate (we also have TPC that sets 3023 * power per packet). We do that by providing an index on the 3024 * PCDAC/PDADC table we set up. 3025 */ 3026 3027/* 3028 * Set rate power table 3029 * 3030 * For now we only limit txpower based on maximum tx power 3031 * supported by hw (what's inside rate_info). We need to limit 3032 * this even more, based on regulatory domain etc. 3033 * 3034 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3035 * and is indexed as follows: 3036 * rates[0] - rates[7] -> OFDM rates 3037 * rates[8] - rates[14] -> CCK rates 3038 * rates[15] -> XR rates (they all have the same power) 3039 */ 3040static void 3041ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3042 struct ath5k_rate_pcal_info *rate_info, 3043 u8 ee_mode) 3044{ 3045 unsigned int i; 3046 u16 *rates; 3047 3048 /* max_pwr is power level we got from driver/user in 0.5dB 3049 * units, switch to 0.25dB units so we can compare */ 3050 max_pwr *= 2; 3051 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3052 3053 /* apply rate limits */ 3054 rates = ah->ah_txpower.txp_rates_power_table; 3055 3056 /* OFDM rates 6 to 24Mb/s */ 3057 for (i = 0; i < 5; i++) 3058 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3059 3060 /* Rest OFDM rates */ 3061 rates[5] = min(rates[0], rate_info->target_power_36); 3062 rates[6] = min(rates[0], rate_info->target_power_48); 3063 rates[7] = min(rates[0], rate_info->target_power_54); 3064 3065 /* CCK rates */ 3066 /* 1L */ 3067 rates[8] = min(rates[0], rate_info->target_power_6to24); 3068 /* 2L */ 3069 rates[9] = min(rates[0], rate_info->target_power_36); 3070 /* 2S */ 3071 rates[10] = min(rates[0], rate_info->target_power_36); 3072 /* 5L */ 3073 rates[11] = min(rates[0], rate_info->target_power_48); 3074 /* 5S */ 3075 rates[12] = min(rates[0], rate_info->target_power_48); 3076 /* 11L */ 3077 rates[13] = min(rates[0], rate_info->target_power_54); 3078 /* 11S */ 3079 rates[14] = min(rates[0], rate_info->target_power_54); 3080 3081 /* XR rates */ 3082 rates[15] = min(rates[0], rate_info->target_power_6to24); 3083 3084 /* CCK rates have different peak to average ratio 3085 * so we have to tweak their power so that gainf 3086 * correction works ok. For this we use OFDM to 3087 * CCK delta from eeprom */ 3088 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3089 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3090 for (i = 8; i <= 15; i++) 3091 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3092 3093 /* Now that we have all rates setup use table offset to 3094 * match the power range set by user with the power indices 3095 * on PCDAC/PDADC table */ 3096 for (i = 0; i < 16; i++) { 3097 rates[i] += ah->ah_txpower.txp_offset; 3098 /* Don't get out of bounds */ 3099 if (rates[i] > 63) 3100 rates[i] = 63; 3101 } 3102 3103 /* Min/max in 0.25dB units */ 3104 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3105 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3106 ah->ah_txpower.txp_ofdm = rates[7]; 3107} 3108 3109 3110/* 3111 * Set transmission power 3112 */ 3113static int 3114ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3115 u8 txpower) 3116{ 3117 struct ath5k_rate_pcal_info rate_info; 3118 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3119 int ee_mode; 3120 u8 type; 3121 int ret; 3122 3123 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3124 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3125 return -EINVAL; 3126 } 3127 3128 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3129 if (ee_mode < 0) { 3130 ATH5K_ERR(ah->ah_sc, 3131 "invalid channel: %d\n", channel->center_freq); 3132 return -EINVAL; 3133 } 3134 3135 /* Initialize TX power table */ 3136 switch (ah->ah_radio) { 3137 case AR5K_RF5110: 3138 /* TODO */ 3139 return 0; 3140 case AR5K_RF5111: 3141 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3142 break; 3143 case AR5K_RF5112: 3144 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3145 break; 3146 case AR5K_RF2413: 3147 case AR5K_RF5413: 3148 case AR5K_RF2316: 3149 case AR5K_RF2317: 3150 case AR5K_RF2425: 3151 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3152 break; 3153 default: 3154 return -EINVAL; 3155 } 3156 3157 /* 3158 * If we don't change channel/mode skip tx powertable calculation 3159 * and use the cached one. 3160 */ 3161 if (!ah->ah_txpower.txp_setup || 3162 (channel->hw_value != curr_channel->hw_value) || 3163 (channel->center_freq != curr_channel->center_freq)) { 3164 /* Reset TX power values */ 3165 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3166 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3167 3168 /* Calculate the powertable */ 3169 ret = ath5k_setup_channel_powertable(ah, channel, 3170 ee_mode, type); 3171 if (ret) 3172 return ret; 3173 } 3174 3175 /* Write table on hw */ 3176 ath5k_write_channel_powertable(ah, ee_mode, type); 3177 3178 /* Limit max power if we have a CTL available */ 3179 ath5k_get_max_ctl_power(ah, channel); 3180 3181 /* FIXME: Antenna reduction stuff */ 3182 3183 /* FIXME: Limit power on turbo modes */ 3184 3185 /* FIXME: TPC scale reduction */ 3186 3187 /* Get surrounding channels for per-rate power table 3188 * calibration */ 3189 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3190 3191 /* Setup rate power table */ 3192 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3193 3194 /* Write rate power table on hw */ 3195 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3196 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3197 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3198 3199 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3200 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3201 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3202 3203 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3204 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3205 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3206 3207 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3208 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3209 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3210 3211 /* FIXME: TPC support */ 3212 if (ah->ah_txpower.txp_tpc) { 3213 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3214 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3215 3216 ath5k_hw_reg_write(ah, 3217 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3218 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3219 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3220 AR5K_TPC); 3221 } else { 3222 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3223 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3224 } 3225 3226 return 0; 3227} 3228 3229int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3230{ 3231 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3232 "changing txpower to %d\n", txpower); 3233 3234 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3235} 3236 3237/*************\ 3238 Init function 3239\*************/ 3240 3241int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3242 u8 mode, bool fast) 3243{ 3244 struct ieee80211_channel *curr_channel; 3245 int ret, i; 3246 u32 phy_tst1; 3247 ret = 0; 3248 3249 /* 3250 * Sanity check for fast flag 3251 * Don't try fast channel change when changing modulation 3252 * mode/band. We check for chip compatibility on 3253 * ath5k_hw_reset. 3254 */ 3255 curr_channel = ah->ah_current_channel; 3256 if (fast && (channel->hw_value != curr_channel->hw_value)) 3257 return -EINVAL; 3258 3259 /* 3260 * On fast channel change we only set the synth parameters 3261 * while PHY is running, enable calibration and skip the rest. 3262 */ 3263 if (fast) { 3264 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3265 AR5K_PHY_RFBUS_REQ_REQUEST); 3266 for (i = 0; i < 100; i++) { 3267 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3268 break; 3269 udelay(5); 3270 } 3271 /* Failed */ 3272 if (i >= 100) 3273 return -EIO; 3274 3275 /* Set channel and wait for synth */ 3276 ret = ath5k_hw_channel(ah, channel); 3277 if (ret) 3278 return ret; 3279 3280 ath5k_hw_wait_for_synth(ah, channel); 3281 } 3282 3283 /* 3284 * Set TX power 3285 * 3286 * Note: We need to do that before we set 3287 * RF buffer settings on 5211/5212+ so that we 3288 * properly set curve indices. 3289 */ 3290 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3291 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3292 if (ret) 3293 return ret; 3294 3295 /* Write OFDM timings on 5212*/ 3296 if (ah->ah_version == AR5K_AR5212 && 3297 channel->hw_value & CHANNEL_OFDM) { 3298 3299 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3300 if (ret) 3301 return ret; 3302 3303 /* Spur info is available only from EEPROM versions 3304 * greater than 5.3, but the EEPROM routines will use 3305 * static values for older versions */ 3306 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3307 ath5k_hw_set_spur_mitigation_filter(ah, 3308 channel); 3309 } 3310 3311 /* If we used fast channel switching 3312 * we are done, release RF bus and 3313 * fire up NF calibration. 3314 * 3315 * Note: Only NF calibration due to 3316 * channel change, not AGC calibration 3317 * since AGC is still running ! 3318 */ 3319 if (fast) { 3320 /* 3321 * Release RF Bus grant 3322 */ 3323 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3324 AR5K_PHY_RFBUS_REQ_REQUEST); 3325 3326 /* 3327 * Start NF calibration 3328 */ 3329 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3330 AR5K_PHY_AGCCTL_NF); 3331 3332 return ret; 3333 } 3334 3335 /* 3336 * For 5210 we do all initialization using 3337 * initvals, so we don't have to modify 3338 * any settings (5210 also only supports 3339 * a/aturbo modes) 3340 */ 3341 if (ah->ah_version != AR5K_AR5210) { 3342 3343 /* 3344 * Write initial RF gain settings 3345 * This should work for both 5111/5112 3346 */ 3347 ret = ath5k_hw_rfgain_init(ah, channel->band); 3348 if (ret) 3349 return ret; 3350 3351 mdelay(1); 3352 3353 /* 3354 * Write RF buffer 3355 */ 3356 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3357 if (ret) 3358 return ret; 3359 3360 /*Enable/disable 802.11b mode on 5111 3361 (enable 2111 frequency converter + CCK)*/ 3362 if (ah->ah_radio == AR5K_RF5111) { 3363 if (mode == AR5K_MODE_11B) 3364 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3365 AR5K_TXCFG_B_MODE); 3366 else 3367 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3368 AR5K_TXCFG_B_MODE); 3369 } 3370 3371 } else if (ah->ah_version == AR5K_AR5210) { 3372 mdelay(1); 3373 /* Disable phy and wait */ 3374 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3375 mdelay(1); 3376 } 3377 3378 /* Set channel on PHY */ 3379 ret = ath5k_hw_channel(ah, channel); 3380 if (ret) 3381 return ret; 3382 3383 /* 3384 * Enable the PHY and wait until completion 3385 * This includes BaseBand and Synthesizer 3386 * activation. 3387 */ 3388 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3389 3390 ath5k_hw_wait_for_synth(ah, channel); 3391 3392 /* 3393 * Perform ADC test to see if baseband is ready 3394 * Set tx hold and check adc test register 3395 */ 3396 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3397 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3398 for (i = 0; i <= 20; i++) { 3399 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3400 break; 3401 udelay(200); 3402 } 3403 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3404 3405 /* 3406 * Start automatic gain control calibration 3407 * 3408 * During AGC calibration RX path is re-routed to 3409 * a power detector so we don't receive anything. 3410 * 3411 * This method is used to calibrate some static offsets 3412 * used together with on-the fly I/Q calibration (the 3413 * one performed via ath5k_hw_phy_calibrate), which doesn't 3414 * interrupt rx path. 3415 * 3416 * While rx path is re-routed to the power detector we also 3417 * start a noise floor calibration to measure the 3418 * card's noise floor (the noise we measure when we are not 3419 * transmitting or receiving anything). 3420 * 3421 * If we are in a noisy environment, AGC calibration may time 3422 * out and/or noise floor calibration might timeout. 3423 */ 3424 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3425 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3426 3427 /* At the same time start I/Q calibration for QAM constellation 3428 * -no need for CCK- */ 3429 ah->ah_calibration = false; 3430 if (!(mode == AR5K_MODE_11B)) { 3431 ah->ah_calibration = true; 3432 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3433 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3434 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3435 AR5K_PHY_IQ_RUN); 3436 } 3437 3438 /* Wait for gain calibration to finish (we check for I/Q calibration 3439 * during ath5k_phy_calibrate) */ 3440 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3441 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3442 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3443 channel->center_freq); 3444 } 3445 3446 /* Restore antenna mode */ 3447 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3448 3449 return ret; 3450} 3451