1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Linux Wireless <ilw@linux.intel.com> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 *****************************************************************************/ 26 27#include <linux/kernel.h> 28#include <linux/module.h> 29#include <linux/slab.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/delay.h> 33#include <linux/sched.h> 34#include <linux/skbuff.h> 35#include <linux/netdevice.h> 36#include <linux/firmware.h> 37#include <linux/etherdevice.h> 38#include <asm/unaligned.h> 39#include <net/mac80211.h> 40 41#include "common.h" 42#include "3945.h" 43 44/* Send led command */ 45static int 46il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) 47{ 48 struct il_host_cmd cmd = { 49 .id = C_LEDS, 50 .len = sizeof(struct il_led_cmd), 51 .data = led_cmd, 52 .flags = CMD_ASYNC, 53 .callback = NULL, 54 }; 55 56 return il_send_cmd(il, &cmd); 57} 58 59#define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ 60 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \ 61 RATE_##r##M_IEEE, \ 62 RATE_##ip##M_IDX, \ 63 RATE_##in##M_IDX, \ 64 RATE_##rp##M_IDX, \ 65 RATE_##rn##M_IDX, \ 66 RATE_##pp##M_IDX, \ 67 RATE_##np##M_IDX, \ 68 RATE_##r##M_IDX_TBL, \ 69 RATE_##ip##M_IDX_TBL } 70 71/* 72 * Parameter order: 73 * rate, prev rate, next rate, prev tgg rate, next tgg rate 74 * 75 * If there isn't a valid next or previous rate then INV is used which 76 * maps to RATE_INVALID 77 * 78 */ 79const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = { 80 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ 81 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ 82 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ 83 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */ 84 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */ 85 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */ 86 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */ 87 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */ 88 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */ 89 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */ 90 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */ 91 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */ 92}; 93 94static inline u8 95il3945_get_prev_ieee_rate(u8 rate_idx) 96{ 97 u8 rate = il3945_rates[rate_idx].prev_ieee; 98 99 if (rate == RATE_INVALID) 100 rate = rate_idx; 101 return rate; 102} 103 104/* 1 = enable the il3945_disable_events() function */ 105#define IL_EVT_DISABLE (0) 106#define IL_EVT_DISABLE_SIZE (1532/32) 107 108/** 109 * il3945_disable_events - Disable selected events in uCode event log 110 * 111 * Disable an event by writing "1"s into "disable" 112 * bitmap in SRAM. Bit position corresponds to Event # (id/type). 113 * Default values of 0 enable uCode events to be logged. 114 * Use for only special debugging. This function is just a placeholder as-is, 115 * you'll need to provide the special bits! ... 116 * ... and set IL_EVT_DISABLE to 1. */ 117void 118il3945_disable_events(struct il_priv *il) 119{ 120 int i; 121 u32 base; /* SRAM address of event log header */ 122 u32 disable_ptr; /* SRAM address of event-disable bitmap array */ 123 u32 array_size; /* # of u32 entries in array */ 124 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = { 125 0x00000000, /* 31 - 0 Event id numbers */ 126 0x00000000, /* 63 - 32 */ 127 0x00000000, /* 95 - 64 */ 128 0x00000000, /* 127 - 96 */ 129 0x00000000, /* 159 - 128 */ 130 0x00000000, /* 191 - 160 */ 131 0x00000000, /* 223 - 192 */ 132 0x00000000, /* 255 - 224 */ 133 0x00000000, /* 287 - 256 */ 134 0x00000000, /* 319 - 288 */ 135 0x00000000, /* 351 - 320 */ 136 0x00000000, /* 383 - 352 */ 137 0x00000000, /* 415 - 384 */ 138 0x00000000, /* 447 - 416 */ 139 0x00000000, /* 479 - 448 */ 140 0x00000000, /* 511 - 480 */ 141 0x00000000, /* 543 - 512 */ 142 0x00000000, /* 575 - 544 */ 143 0x00000000, /* 607 - 576 */ 144 0x00000000, /* 639 - 608 */ 145 0x00000000, /* 671 - 640 */ 146 0x00000000, /* 703 - 672 */ 147 0x00000000, /* 735 - 704 */ 148 0x00000000, /* 767 - 736 */ 149 0x00000000, /* 799 - 768 */ 150 0x00000000, /* 831 - 800 */ 151 0x00000000, /* 863 - 832 */ 152 0x00000000, /* 895 - 864 */ 153 0x00000000, /* 927 - 896 */ 154 0x00000000, /* 959 - 928 */ 155 0x00000000, /* 991 - 960 */ 156 0x00000000, /* 1023 - 992 */ 157 0x00000000, /* 1055 - 1024 */ 158 0x00000000, /* 1087 - 1056 */ 159 0x00000000, /* 1119 - 1088 */ 160 0x00000000, /* 1151 - 1120 */ 161 0x00000000, /* 1183 - 1152 */ 162 0x00000000, /* 1215 - 1184 */ 163 0x00000000, /* 1247 - 1216 */ 164 0x00000000, /* 1279 - 1248 */ 165 0x00000000, /* 1311 - 1280 */ 166 0x00000000, /* 1343 - 1312 */ 167 0x00000000, /* 1375 - 1344 */ 168 0x00000000, /* 1407 - 1376 */ 169 0x00000000, /* 1439 - 1408 */ 170 0x00000000, /* 1471 - 1440 */ 171 0x00000000, /* 1503 - 1472 */ 172 }; 173 174 base = le32_to_cpu(il->card_alive.log_event_table_ptr); 175 if (!il3945_hw_valid_rtc_data_addr(base)) { 176 IL_ERR("Invalid event log pointer 0x%08X\n", base); 177 return; 178 } 179 180 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32))); 181 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32))); 182 183 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) { 184 D_INFO("Disabling selected uCode log events at 0x%x\n", 185 disable_ptr); 186 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++) 187 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)), 188 evt_disable[i]); 189 190 } else { 191 D_INFO("Selected uCode log events may be disabled\n"); 192 D_INFO(" by writing \"1\"s into disable bitmap\n"); 193 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr, 194 array_size); 195 } 196 197} 198 199static int 200il3945_hwrate_to_plcp_idx(u8 plcp) 201{ 202 int idx; 203 204 for (idx = 0; idx < RATE_COUNT_3945; idx++) 205 if (il3945_rates[idx].plcp == plcp) 206 return idx; 207 return -1; 208} 209 210#ifdef CONFIG_IWLEGACY_DEBUG 211#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x 212 213static const char * 214il3945_get_tx_fail_reason(u32 status) 215{ 216 switch (status & TX_STATUS_MSK) { 217 case TX_3945_STATUS_SUCCESS: 218 return "SUCCESS"; 219 TX_STATUS_ENTRY(SHORT_LIMIT); 220 TX_STATUS_ENTRY(LONG_LIMIT); 221 TX_STATUS_ENTRY(FIFO_UNDERRUN); 222 TX_STATUS_ENTRY(MGMNT_ABORT); 223 TX_STATUS_ENTRY(NEXT_FRAG); 224 TX_STATUS_ENTRY(LIFE_EXPIRE); 225 TX_STATUS_ENTRY(DEST_PS); 226 TX_STATUS_ENTRY(ABORTED); 227 TX_STATUS_ENTRY(BT_RETRY); 228 TX_STATUS_ENTRY(STA_INVALID); 229 TX_STATUS_ENTRY(FRAG_DROPPED); 230 TX_STATUS_ENTRY(TID_DISABLE); 231 TX_STATUS_ENTRY(FRAME_FLUSHED); 232 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); 233 TX_STATUS_ENTRY(TX_LOCKED); 234 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); 235 } 236 237 return "UNKNOWN"; 238} 239#else 240static inline const char * 241il3945_get_tx_fail_reason(u32 status) 242{ 243 return ""; 244} 245#endif 246 247/* 248 * get ieee prev rate from rate scale table. 249 * for A and B mode we need to overright prev 250 * value 251 */ 252int 253il3945_rs_next_rate(struct il_priv *il, int rate) 254{ 255 int next_rate = il3945_get_prev_ieee_rate(rate); 256 257 switch (il->band) { 258 case IEEE80211_BAND_5GHZ: 259 if (rate == RATE_12M_IDX) 260 next_rate = RATE_9M_IDX; 261 else if (rate == RATE_6M_IDX) 262 next_rate = RATE_6M_IDX; 263 break; 264 case IEEE80211_BAND_2GHZ: 265 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) && 266 il_is_associated(il)) { 267 if (rate == RATE_11M_IDX) 268 next_rate = RATE_5M_IDX; 269 } 270 break; 271 272 default: 273 break; 274 } 275 276 return next_rate; 277} 278 279/** 280 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd 281 * 282 * When FW advances 'R' idx, all entries between old and new 'R' idx 283 * need to be reclaimed. As result, some free space forms. If there is 284 * enough free space (> low mark), wake the stack that feeds us. 285 */ 286static void 287il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) 288{ 289 struct il_tx_queue *txq = &il->txq[txq_id]; 290 struct il_queue *q = &txq->q; 291 struct sk_buff *skb; 292 293 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM); 294 295 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 296 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { 297 298 skb = txq->skbs[txq->q.read_ptr]; 299 ieee80211_tx_status_irqsafe(il->hw, skb); 300 txq->skbs[txq->q.read_ptr] = NULL; 301 il->ops->txq_free_tfd(il, txq); 302 } 303 304 if (il_queue_space(q) > q->low_mark && txq_id >= 0 && 305 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered) 306 il_wake_queue(il, txq); 307} 308 309/** 310 * il3945_hdl_tx - Handle Tx response 311 */ 312static void 313il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) 314{ 315 struct il_rx_pkt *pkt = rxb_addr(rxb); 316 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 317 int txq_id = SEQ_TO_QUEUE(sequence); 318 int idx = SEQ_TO_IDX(sequence); 319 struct il_tx_queue *txq = &il->txq[txq_id]; 320 struct ieee80211_tx_info *info; 321 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 322 u32 status = le32_to_cpu(tx_resp->status); 323 int rate_idx; 324 int fail; 325 326 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { 327 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " 328 "is out of range [0-%d] %d %d\n", txq_id, idx, 329 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr); 330 return; 331 } 332 333 /* 334 * Firmware will not transmit frame on passive channel, if it not yet 335 * received some valid frame on that channel. When this error happen 336 * we have to wait until firmware will unblock itself i.e. when we 337 * note received beacon or other frame. We unblock queues in 338 * il3945_pass_packet_to_mac80211 or in il_mac_bss_info_changed. 339 */ 340 if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) && 341 il->iw_mode == NL80211_IFTYPE_STATION) { 342 il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 343 D_INFO("Stopped queues - RX waiting on passive channel\n"); 344 } 345 346 txq->time_stamp = jiffies; 347 info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]); 348 ieee80211_tx_info_clear_status(info); 349 350 /* Fill the MRR chain with some info about on-chip retransmissions */ 351 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate); 352 if (info->band == IEEE80211_BAND_5GHZ) 353 rate_idx -= IL_FIRST_OFDM_RATE; 354 355 fail = tx_resp->failure_frame; 356 357 info->status.rates[0].idx = rate_idx; 358 info->status.rates[0].count = fail + 1; /* add final attempt */ 359 360 /* tx_status->rts_retry_count = tx_resp->failure_rts; */ 361 info->flags |= 362 ((status & TX_STATUS_MSK) == 363 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0; 364 365 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id, 366 il3945_get_tx_fail_reason(status), status, tx_resp->rate, 367 tx_resp->failure_frame); 368 369 D_TX_REPLY("Tx queue reclaim %d\n", idx); 370 il3945_tx_queue_reclaim(il, txq_id, idx); 371 372 if (status & TX_ABORT_REQUIRED_MSK) 373 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 374} 375 376/***************************************************************************** 377 * 378 * Intel PRO/Wireless 3945ABG/BG Network Connection 379 * 380 * RX handler implementations 381 * 382 *****************************************************************************/ 383#ifdef CONFIG_IWLEGACY_DEBUGFS 384static void 385il3945_accumulative_stats(struct il_priv *il, __le32 * stats) 386{ 387 int i; 388 __le32 *prev_stats; 389 u32 *accum_stats; 390 u32 *delta, *max_delta; 391 392 prev_stats = (__le32 *) &il->_3945.stats; 393 accum_stats = (u32 *) &il->_3945.accum_stats; 394 delta = (u32 *) &il->_3945.delta_stats; 395 max_delta = (u32 *) &il->_3945.max_delta; 396 397 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats); 398 i += 399 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, 400 accum_stats++) { 401 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 402 *delta = 403 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); 404 *accum_stats += *delta; 405 if (*delta > *max_delta) 406 *max_delta = *delta; 407 } 408 } 409 410 /* reset accumulative stats for "no-counter" type stats */ 411 il->_3945.accum_stats.general.temperature = 412 il->_3945.stats.general.temperature; 413 il->_3945.accum_stats.general.ttl_timestamp = 414 il->_3945.stats.general.ttl_timestamp; 415} 416#endif 417 418void 419il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) 420{ 421 struct il_rx_pkt *pkt = rxb_addr(rxb); 422 423 D_RX("Statistics notification received (%d vs %d).\n", 424 (int)sizeof(struct il3945_notif_stats), 425 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); 426#ifdef CONFIG_IWLEGACY_DEBUGFS 427 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw); 428#endif 429 430 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats)); 431} 432 433void 434il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) 435{ 436 struct il_rx_pkt *pkt = rxb_addr(rxb); 437 __le32 *flag = (__le32 *) &pkt->u.raw; 438 439 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) { 440#ifdef CONFIG_IWLEGACY_DEBUGFS 441 memset(&il->_3945.accum_stats, 0, 442 sizeof(struct il3945_notif_stats)); 443 memset(&il->_3945.delta_stats, 0, 444 sizeof(struct il3945_notif_stats)); 445 memset(&il->_3945.max_delta, 0, 446 sizeof(struct il3945_notif_stats)); 447#endif 448 D_RX("Statistics have been cleared\n"); 449 } 450 il3945_hdl_stats(il, rxb); 451} 452 453/****************************************************************************** 454 * 455 * Misc. internal state and helper functions 456 * 457 ******************************************************************************/ 458 459/* This is necessary only for a number of stats, see the caller. */ 460static int 461il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header) 462{ 463 /* Filter incoming packets to determine if they are targeted toward 464 * this network, discarding packets coming from ourselves */ 465 switch (il->iw_mode) { 466 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ 467 /* packets to our IBSS update information */ 468 return ether_addr_equal_64bits(header->addr3, il->bssid); 469 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ 470 /* packets to our IBSS update information */ 471 return ether_addr_equal_64bits(header->addr2, il->bssid); 472 default: 473 return 1; 474 } 475} 476 477#define SMALL_PACKET_SIZE 256 478 479static void 480il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb, 481 struct ieee80211_rx_status *stats) 482{ 483 struct il_rx_pkt *pkt = rxb_addr(rxb); 484 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt); 485 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt); 486 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt); 487 u32 len = le16_to_cpu(rx_hdr->len); 488 struct sk_buff *skb; 489 __le16 fc = hdr->frame_control; 490 u32 fraglen = PAGE_SIZE << il->hw_params.rx_page_order; 491 492 /* We received data from the HW, so stop the watchdog */ 493 if (unlikely(len + IL39_RX_FRAME_SIZE > fraglen)) { 494 D_DROP("Corruption detected!\n"); 495 return; 496 } 497 498 /* We only process data packets if the interface is open */ 499 if (unlikely(!il->is_open)) { 500 D_DROP("Dropping packet while interface is not open.\n"); 501 return; 502 } 503 504 if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) { 505 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 506 D_INFO("Woke queues - frame received on passive channel\n"); 507 } 508 509 skb = dev_alloc_skb(SMALL_PACKET_SIZE); 510 if (!skb) { 511 IL_ERR("dev_alloc_skb failed\n"); 512 return; 513 } 514 515 if (!il3945_mod_params.sw_crypto) 516 il_set_decrypted_flag(il, (struct ieee80211_hdr *)pkt, 517 le32_to_cpu(rx_end->status), stats); 518 519 /* If frame is small enough to fit into skb->head, copy it 520 * and do not consume a full page 521 */ 522 if (len <= SMALL_PACKET_SIZE) { 523 memcpy(skb_put(skb, len), rx_hdr->payload, len); 524 } else { 525 skb_add_rx_frag(skb, 0, rxb->page, 526 (void *)rx_hdr->payload - (void *)pkt, len, 527 fraglen); 528 il->alloc_rxb_page--; 529 rxb->page = NULL; 530 } 531 il_update_stats(il, false, fc, len); 532 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 533 534 ieee80211_rx(il->hw, skb); 535} 536 537#define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) 538 539static void 540il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) 541{ 542 struct ieee80211_hdr *header; 543 struct ieee80211_rx_status rx_status = {}; 544 struct il_rx_pkt *pkt = rxb_addr(rxb); 545 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt); 546 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt); 547 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt); 548 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg); 549 u16 rx_stats_noise_diff __maybe_unused = 550 le16_to_cpu(rx_stats->noise_diff); 551 u8 network_packet; 552 553 rx_status.flag = 0; 554 rx_status.mactime = le64_to_cpu(rx_end->timestamp); 555 rx_status.band = 556 (rx_hdr-> 557 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ : 558 IEEE80211_BAND_5GHZ; 559 rx_status.freq = 560 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel), 561 rx_status.band); 562 563 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate); 564 if (rx_status.band == IEEE80211_BAND_5GHZ) 565 rx_status.rate_idx -= IL_FIRST_OFDM_RATE; 566 567 rx_status.antenna = 568 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 569 4; 570 571 /* set the preamble flag if appropriate */ 572 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 573 rx_status.flag |= RX_FLAG_SHORTPRE; 574 575 if ((unlikely(rx_stats->phy_count > 20))) { 576 D_DROP("dsp size out of range [0,20]: %d\n", 577 rx_stats->phy_count); 578 return; 579 } 580 581 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) || 582 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 583 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status); 584 return; 585 } 586 587 /* Convert 3945's rssi indicator to dBm */ 588 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET; 589 590 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal, 591 rx_stats_sig_avg, rx_stats_noise_diff); 592 593 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt); 594 595 network_packet = il3945_is_network_packet(il, header); 596 597 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n", 598 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel), 599 rx_status.signal, rx_status.signal, rx_status.rate_idx); 600 601 if (network_packet) { 602 il->_3945.last_beacon_time = 603 le32_to_cpu(rx_end->beacon_timestamp); 604 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp); 605 il->_3945.last_rx_rssi = rx_status.signal; 606 } 607 608 il3945_pass_packet_to_mac80211(il, rxb, &rx_status); 609} 610 611int 612il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 613 dma_addr_t addr, u16 len, u8 reset, u8 pad) 614{ 615 int count; 616 struct il_queue *q; 617 struct il3945_tfd *tfd, *tfd_tmp; 618 619 q = &txq->q; 620 tfd_tmp = (struct il3945_tfd *)txq->tfds; 621 tfd = &tfd_tmp[q->write_ptr]; 622 623 if (reset) 624 memset(tfd, 0, sizeof(*tfd)); 625 626 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 627 628 if (count >= NUM_TFD_CHUNKS || count < 0) { 629 IL_ERR("Error can not send more than %d chunks\n", 630 NUM_TFD_CHUNKS); 631 return -EINVAL; 632 } 633 634 tfd->tbs[count].addr = cpu_to_le32(addr); 635 tfd->tbs[count].len = cpu_to_le32(len); 636 637 count++; 638 639 tfd->control_flags = 640 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad)); 641 642 return 0; 643} 644 645/** 646 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr] 647 * 648 * Does NOT advance any idxes 649 */ 650void 651il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) 652{ 653 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds; 654 int idx = txq->q.read_ptr; 655 struct il3945_tfd *tfd = &tfd_tmp[idx]; 656 struct pci_dev *dev = il->pci_dev; 657 int i; 658 int counter; 659 660 /* sanity check */ 661 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 662 if (counter > NUM_TFD_CHUNKS) { 663 IL_ERR("Too many chunks: %i\n", counter); 664 /* @todo issue fatal error, it is quite serious situation */ 665 return; 666 } 667 668 /* Unmap tx_cmd */ 669 if (counter) 670 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping), 671 dma_unmap_len(&txq->meta[idx], len), 672 PCI_DMA_TODEVICE); 673 674 /* unmap chunks if any */ 675 676 for (i = 1; i < counter; i++) 677 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr), 678 le32_to_cpu(tfd->tbs[i].len), 679 PCI_DMA_TODEVICE); 680 681 /* free SKB */ 682 if (txq->skbs) { 683 struct sk_buff *skb = txq->skbs[txq->q.read_ptr]; 684 685 /* can be called from irqs-disabled context */ 686 if (skb) { 687 dev_kfree_skb_any(skb); 688 txq->skbs[txq->q.read_ptr] = NULL; 689 } 690 } 691} 692 693/** 694 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: 695 * 696*/ 697void 698il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd, 699 struct ieee80211_tx_info *info, 700 struct ieee80211_hdr *hdr, int sta_id) 701{ 702 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value; 703 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1); 704 u16 rate_mask; 705 int rate; 706 const u8 rts_retry_limit = 7; 707 u8 data_retry_limit; 708 __le32 tx_flags; 709 __le16 fc = hdr->frame_control; 710 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload; 711 712 rate = il3945_rates[rate_idx].plcp; 713 tx_flags = tx_cmd->tx_flags; 714 715 /* We need to figure out how to get the sta->supp_rates while 716 * in this running context */ 717 rate_mask = RATES_MASK_3945; 718 719 /* Set retry limit on DATA packets and Probe Responses */ 720 if (ieee80211_is_probe_resp(fc)) 721 data_retry_limit = 3; 722 else 723 data_retry_limit = IL_DEFAULT_TX_RETRY; 724 tx_cmd->data_retry_limit = data_retry_limit; 725 /* Set retry limit on RTS packets */ 726 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); 727 728 tx_cmd->rate = rate; 729 tx_cmd->tx_flags = tx_flags; 730 731 /* OFDM */ 732 tx_cmd->supp_rates[0] = 733 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF; 734 735 /* CCK */ 736 tx_cmd->supp_rates[1] = (rate_mask & 0xF); 737 738 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X " 739 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate, 740 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1], 741 tx_cmd->supp_rates[0]); 742} 743 744static u8 745il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate) 746{ 747 unsigned long flags_spin; 748 struct il_station_entry *station; 749 750 if (sta_id == IL_INVALID_STATION) 751 return IL_INVALID_STATION; 752 753 spin_lock_irqsave(&il->sta_lock, flags_spin); 754 station = &il->stations[sta_id]; 755 756 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK; 757 station->sta.rate_n_flags = cpu_to_le16(tx_rate); 758 station->sta.mode = STA_CONTROL_MODIFY_MSK; 759 il_send_add_sta(il, &station->sta, CMD_ASYNC); 760 spin_unlock_irqrestore(&il->sta_lock, flags_spin); 761 762 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate); 763 return sta_id; 764} 765 766static void 767il3945_set_pwr_vmain(struct il_priv *il) 768{ 769/* 770 * (for documentation purposes) 771 * to set power to V_AUX, do 772 773 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) { 774 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 775 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 776 ~APMG_PS_CTRL_MSK_PWR_SRC); 777 778 _il_poll_bit(il, CSR_GPIO_IN, 779 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 780 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 781 } 782 */ 783 784 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 785 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 786 ~APMG_PS_CTRL_MSK_PWR_SRC); 787 788 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 789 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 790} 791 792static int 793il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 794{ 795 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma); 796 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma); 797 il_wr(il, FH39_RCSR_WPTR(0), 0); 798 il_wr(il, FH39_RCSR_CONFIG(0), 799 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 800 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 801 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 802 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG 803 << 804 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) 805 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 << 806 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) 807 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 808 809 /* fake read to flush all prev I/O */ 810 il_rd(il, FH39_RSSR_CTRL); 811 812 return 0; 813} 814 815static int 816il3945_tx_reset(struct il_priv *il) 817{ 818 /* bypass mode */ 819 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2); 820 821 /* RA 0 is active */ 822 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01); 823 824 /* all 6 fifo are active */ 825 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f); 826 827 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000); 828 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002); 829 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004); 830 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005); 831 832 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys); 833 834 il_wr(il, FH39_TSSR_MSG_CONFIG, 835 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 836 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 837 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 838 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | 839 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | 840 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 841 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 842 843 return 0; 844} 845 846/** 847 * il3945_txq_ctx_reset - Reset TX queue context 848 * 849 * Destroys all DMA structures and initialize them again 850 */ 851static int 852il3945_txq_ctx_reset(struct il_priv *il) 853{ 854 int rc, txq_id; 855 856 il3945_hw_txq_ctx_free(il); 857 858 /* allocate tx queue structure */ 859 rc = il_alloc_txq_mem(il); 860 if (rc) 861 return rc; 862 863 /* Tx CMD queue */ 864 rc = il3945_tx_reset(il); 865 if (rc) 866 goto error; 867 868 /* Tx queue(s) */ 869 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 870 rc = il_tx_queue_init(il, txq_id); 871 if (rc) { 872 IL_ERR("Tx %d queue init failed\n", txq_id); 873 goto error; 874 } 875 } 876 877 return rc; 878 879error: 880 il3945_hw_txq_ctx_free(il); 881 return rc; 882} 883 884/* 885 * Start up 3945's basic functionality after it has been reset 886 * (e.g. after platform boot, or shutdown via il_apm_stop()) 887 * NOTE: This does not load uCode nor start the embedded processor 888 */ 889static int 890il3945_apm_init(struct il_priv *il) 891{ 892 int ret = il_apm_init(il); 893 894 /* Clear APMG (NIC's internal power management) interrupts */ 895 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0); 896 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF); 897 898 /* Reset radio chip */ 899 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 900 udelay(5); 901 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 902 903 return ret; 904} 905 906static void 907il3945_nic_config(struct il_priv *il) 908{ 909 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 910 unsigned long flags; 911 u8 rev_id = il->pci_dev->revision; 912 913 spin_lock_irqsave(&il->lock, flags); 914 915 /* Determine HW type */ 916 D_INFO("HW Revision ID = 0x%X\n", rev_id); 917 918 if (rev_id & PCI_CFG_REV_ID_BIT_RTP) 919 D_INFO("RTP type\n"); 920 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 921 D_INFO("3945 RADIO-MB type\n"); 922 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 923 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); 924 } else { 925 D_INFO("3945 RADIO-MM type\n"); 926 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 927 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); 928 } 929 930 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) { 931 D_INFO("SKU OP mode is mrc\n"); 932 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 933 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); 934 } else 935 D_INFO("SKU OP mode is basic\n"); 936 937 if ((eeprom->board_revision & 0xF0) == 0xD0) { 938 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision); 939 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 940 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 941 } else { 942 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision); 943 il_clear_bit(il, CSR_HW_IF_CONFIG_REG, 944 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 945 } 946 947 if (eeprom->almgor_m_version <= 1) { 948 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 949 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 950 D_INFO("Card M type A version is 0x%X\n", 951 eeprom->almgor_m_version); 952 } else { 953 D_INFO("Card M type B version is 0x%X\n", 954 eeprom->almgor_m_version); 955 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 956 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 957 } 958 spin_unlock_irqrestore(&il->lock, flags); 959 960 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) 961 D_RF_KILL("SW RF KILL supported in EEPROM.\n"); 962 963 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) 964 D_RF_KILL("HW RF KILL supported in EEPROM.\n"); 965} 966 967int 968il3945_hw_nic_init(struct il_priv *il) 969{ 970 int rc; 971 unsigned long flags; 972 struct il_rx_queue *rxq = &il->rxq; 973 974 spin_lock_irqsave(&il->lock, flags); 975 il3945_apm_init(il); 976 spin_unlock_irqrestore(&il->lock, flags); 977 978 il3945_set_pwr_vmain(il); 979 il3945_nic_config(il); 980 981 /* Allocate the RX queue, or reset if it is already allocated */ 982 if (!rxq->bd) { 983 rc = il_rx_queue_alloc(il); 984 if (rc) { 985 IL_ERR("Unable to initialize Rx queue\n"); 986 return -ENOMEM; 987 } 988 } else 989 il3945_rx_queue_reset(il, rxq); 990 991 il3945_rx_replenish(il); 992 993 il3945_rx_init(il, rxq); 994 995 /* Look at using this instead: 996 rxq->need_update = 1; 997 il_rx_queue_update_write_ptr(il, rxq); 998 */ 999 1000 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7); 1001 1002 rc = il3945_txq_ctx_reset(il); 1003 if (rc) 1004 return rc; 1005 1006 set_bit(S_INIT, &il->status); 1007 1008 return 0; 1009} 1010 1011/** 1012 * il3945_hw_txq_ctx_free - Free TXQ Context 1013 * 1014 * Destroy all TX DMA queues and structures 1015 */ 1016void 1017il3945_hw_txq_ctx_free(struct il_priv *il) 1018{ 1019 int txq_id; 1020 1021 /* Tx queues */ 1022 if (il->txq) 1023 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 1024 if (txq_id == IL39_CMD_QUEUE_NUM) 1025 il_cmd_queue_free(il); 1026 else 1027 il_tx_queue_free(il, txq_id); 1028 1029 /* free tx queue structure */ 1030 il_free_txq_mem(il); 1031} 1032 1033void 1034il3945_hw_txq_ctx_stop(struct il_priv *il) 1035{ 1036 int txq_id; 1037 1038 /* stop SCD */ 1039 _il_wr_prph(il, ALM_SCD_MODE_REG, 0); 1040 _il_wr_prph(il, ALM_SCD_TXFACT_REG, 0); 1041 1042 /* reset TFD queues */ 1043 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 1044 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0); 1045 _il_poll_bit(il, FH39_TSSR_TX_STATUS, 1046 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1047 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1048 1000); 1049 } 1050} 1051 1052/** 1053 * il3945_hw_reg_adjust_power_by_temp 1054 * return idx delta into power gain settings table 1055*/ 1056static int 1057il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) 1058{ 1059 return (new_reading - old_reading) * (-11) / 100; 1060} 1061 1062/** 1063 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range 1064 */ 1065static inline int 1066il3945_hw_reg_temp_out_of_range(int temperature) 1067{ 1068 return (temperature < -260 || temperature > 25) ? 1 : 0; 1069} 1070 1071int 1072il3945_hw_get_temperature(struct il_priv *il) 1073{ 1074 return _il_rd(il, CSR_UCODE_DRV_GP2); 1075} 1076 1077/** 1078 * il3945_hw_reg_txpower_get_temperature 1079 * get the current temperature by reading from NIC 1080*/ 1081static int 1082il3945_hw_reg_txpower_get_temperature(struct il_priv *il) 1083{ 1084 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1085 int temperature; 1086 1087 temperature = il3945_hw_get_temperature(il); 1088 1089 /* driver's okay range is -260 to +25. 1090 * human readable okay range is 0 to +285 */ 1091 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT); 1092 1093 /* handle insane temp reading */ 1094 if (il3945_hw_reg_temp_out_of_range(temperature)) { 1095 IL_ERR("Error bad temperature value %d\n", temperature); 1096 1097 /* if really really hot(?), 1098 * substitute the 3rd band/group's temp measured at factory */ 1099 if (il->last_temperature > 100) 1100 temperature = eeprom->groups[2].temperature; 1101 else /* else use most recent "sane" value from driver */ 1102 temperature = il->last_temperature; 1103 } 1104 1105 return temperature; /* raw, not "human readable" */ 1106} 1107 1108/* Adjust Txpower only if temperature variance is greater than threshold. 1109 * 1110 * Both are lower than older versions' 9 degrees */ 1111#define IL_TEMPERATURE_LIMIT_TIMER 6 1112 1113/** 1114 * il3945_is_temp_calib_needed - determines if new calibration is needed 1115 * 1116 * records new temperature in tx_mgr->temperature. 1117 * replaces tx_mgr->last_temperature *only* if calib needed 1118 * (assumes caller will actually do the calibration!). */ 1119static int 1120il3945_is_temp_calib_needed(struct il_priv *il) 1121{ 1122 int temp_diff; 1123 1124 il->temperature = il3945_hw_reg_txpower_get_temperature(il); 1125 temp_diff = il->temperature - il->last_temperature; 1126 1127 /* get absolute value */ 1128 if (temp_diff < 0) { 1129 D_POWER("Getting cooler, delta %d,\n", temp_diff); 1130 temp_diff = -temp_diff; 1131 } else if (temp_diff == 0) 1132 D_POWER("Same temp,\n"); 1133 else 1134 D_POWER("Getting warmer, delta %d,\n", temp_diff); 1135 1136 /* if we don't need calibration, *don't* update last_temperature */ 1137 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) { 1138 D_POWER("Timed thermal calib not needed\n"); 1139 return 0; 1140 } 1141 1142 D_POWER("Timed thermal calib needed\n"); 1143 1144 /* assume that caller will actually do calib ... 1145 * update the "last temperature" value */ 1146 il->last_temperature = il->temperature; 1147 return 1; 1148} 1149 1150#define IL_MAX_GAIN_ENTRIES 78 1151#define IL_CCK_FROM_OFDM_POWER_DIFF -5 1152#define IL_CCK_FROM_OFDM_IDX_DIFF (10) 1153 1154/* radio and DSP power table, each step is 1/2 dB. 1155 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ 1156static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = { 1157 { 1158 {251, 127}, /* 2.4 GHz, highest power */ 1159 {251, 127}, 1160 {251, 127}, 1161 {251, 127}, 1162 {251, 125}, 1163 {251, 110}, 1164 {251, 105}, 1165 {251, 98}, 1166 {187, 125}, 1167 {187, 115}, 1168 {187, 108}, 1169 {187, 99}, 1170 {243, 119}, 1171 {243, 111}, 1172 {243, 105}, 1173 {243, 97}, 1174 {243, 92}, 1175 {211, 106}, 1176 {211, 100}, 1177 {179, 120}, 1178 {179, 113}, 1179 {179, 107}, 1180 {147, 125}, 1181 {147, 119}, 1182 {147, 112}, 1183 {147, 106}, 1184 {147, 101}, 1185 {147, 97}, 1186 {147, 91}, 1187 {115, 107}, 1188 {235, 121}, 1189 {235, 115}, 1190 {235, 109}, 1191 {203, 127}, 1192 {203, 121}, 1193 {203, 115}, 1194 {203, 108}, 1195 {203, 102}, 1196 {203, 96}, 1197 {203, 92}, 1198 {171, 110}, 1199 {171, 104}, 1200 {171, 98}, 1201 {139, 116}, 1202 {227, 125}, 1203 {227, 119}, 1204 {227, 113}, 1205 {227, 107}, 1206 {227, 101}, 1207 {227, 96}, 1208 {195, 113}, 1209 {195, 106}, 1210 {195, 102}, 1211 {195, 95}, 1212 {163, 113}, 1213 {163, 106}, 1214 {163, 102}, 1215 {163, 95}, 1216 {131, 113}, 1217 {131, 106}, 1218 {131, 102}, 1219 {131, 95}, 1220 {99, 113}, 1221 {99, 106}, 1222 {99, 102}, 1223 {99, 95}, 1224 {67, 113}, 1225 {67, 106}, 1226 {67, 102}, 1227 {67, 95}, 1228 {35, 113}, 1229 {35, 106}, 1230 {35, 102}, 1231 {35, 95}, 1232 {3, 113}, 1233 {3, 106}, 1234 {3, 102}, 1235 {3, 95} /* 2.4 GHz, lowest power */ 1236 }, 1237 { 1238 {251, 127}, /* 5.x GHz, highest power */ 1239 {251, 120}, 1240 {251, 114}, 1241 {219, 119}, 1242 {219, 101}, 1243 {187, 113}, 1244 {187, 102}, 1245 {155, 114}, 1246 {155, 103}, 1247 {123, 117}, 1248 {123, 107}, 1249 {123, 99}, 1250 {123, 92}, 1251 {91, 108}, 1252 {59, 125}, 1253 {59, 118}, 1254 {59, 109}, 1255 {59, 102}, 1256 {59, 96}, 1257 {59, 90}, 1258 {27, 104}, 1259 {27, 98}, 1260 {27, 92}, 1261 {115, 118}, 1262 {115, 111}, 1263 {115, 104}, 1264 {83, 126}, 1265 {83, 121}, 1266 {83, 113}, 1267 {83, 105}, 1268 {83, 99}, 1269 {51, 118}, 1270 {51, 111}, 1271 {51, 104}, 1272 {51, 98}, 1273 {19, 116}, 1274 {19, 109}, 1275 {19, 102}, 1276 {19, 98}, 1277 {19, 93}, 1278 {171, 113}, 1279 {171, 107}, 1280 {171, 99}, 1281 {139, 120}, 1282 {139, 113}, 1283 {139, 107}, 1284 {139, 99}, 1285 {107, 120}, 1286 {107, 113}, 1287 {107, 107}, 1288 {107, 99}, 1289 {75, 120}, 1290 {75, 113}, 1291 {75, 107}, 1292 {75, 99}, 1293 {43, 120}, 1294 {43, 113}, 1295 {43, 107}, 1296 {43, 99}, 1297 {11, 120}, 1298 {11, 113}, 1299 {11, 107}, 1300 {11, 99}, 1301 {131, 107}, 1302 {131, 99}, 1303 {99, 120}, 1304 {99, 113}, 1305 {99, 107}, 1306 {99, 99}, 1307 {67, 120}, 1308 {67, 113}, 1309 {67, 107}, 1310 {67, 99}, 1311 {35, 120}, 1312 {35, 113}, 1313 {35, 107}, 1314 {35, 99}, 1315 {3, 120} /* 5.x GHz, lowest power */ 1316 } 1317}; 1318 1319static inline u8 1320il3945_hw_reg_fix_power_idx(int idx) 1321{ 1322 if (idx < 0) 1323 return 0; 1324 if (idx >= IL_MAX_GAIN_ENTRIES) 1325 return IL_MAX_GAIN_ENTRIES - 1; 1326 return (u8) idx; 1327} 1328 1329/* Kick off thermal recalibration check every 60 seconds */ 1330#define REG_RECALIB_PERIOD (60) 1331 1332/** 1333 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests 1334 * 1335 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) 1336 * or 6 Mbit (OFDM) rates. 1337 */ 1338static void 1339il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx, 1340 const s8 *clip_pwrs, 1341 struct il_channel_info *ch_info, int band_idx) 1342{ 1343 struct il3945_scan_power_info *scan_power_info; 1344 s8 power; 1345 u8 power_idx; 1346 1347 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx]; 1348 1349 /* use this channel group's 6Mbit clipping/saturation pwr, 1350 * but cap at regulatory scan power restriction (set during init 1351 * based on eeprom channel data) for this channel. */ 1352 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]); 1353 1354 power = min(power, il->tx_power_user_lmt); 1355 scan_power_info->requested_power = power; 1356 1357 /* find difference between new scan *power* and current "normal" 1358 * Tx *power* for 6Mb. Use this difference (x2) to adjust the 1359 * current "normal" temperature-compensated Tx power *idx* for 1360 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power 1361 * *idx*. */ 1362 power_idx = 1363 ch_info->power_info[rate_idx].power_table_idx - (power - 1364 ch_info-> 1365 power_info 1366 [RATE_6M_IDX_TBL]. 1367 requested_power) * 1368 2; 1369 1370 /* store reference idx that we use when adjusting *all* scan 1371 * powers. So we can accommodate user (all channel) or spectrum 1372 * management (single channel) power changes "between" temperature 1373 * feedback compensation procedures. 1374 * don't force fit this reference idx into gain table; it may be a 1375 * negative number. This will help avoid errors when we're at 1376 * the lower bounds (highest gains, for warmest temperatures) 1377 * of the table. */ 1378 1379 /* don't exceed table bounds for "real" setting */ 1380 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 1381 1382 scan_power_info->power_table_idx = power_idx; 1383 scan_power_info->tpc.tx_gain = 1384 power_gain_table[band_idx][power_idx].tx_gain; 1385 scan_power_info->tpc.dsp_atten = 1386 power_gain_table[band_idx][power_idx].dsp_atten; 1387} 1388 1389/** 1390 * il3945_send_tx_power - fill in Tx Power command with gain settings 1391 * 1392 * Configures power settings for all rates for the current channel, 1393 * using values from channel info struct, and send to NIC 1394 */ 1395static int 1396il3945_send_tx_power(struct il_priv *il) 1397{ 1398 int rate_idx, i; 1399 const struct il_channel_info *ch_info = NULL; 1400 struct il3945_txpowertable_cmd txpower = { 1401 .channel = il->active.channel, 1402 }; 1403 u16 chan; 1404 1405 if (WARN_ONCE 1406 (test_bit(S_SCAN_HW, &il->status), 1407 "TX Power requested while scanning!\n")) 1408 return -EAGAIN; 1409 1410 chan = le16_to_cpu(il->active.channel); 1411 1412 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1; 1413 ch_info = il_get_channel_info(il, il->band, chan); 1414 if (!ch_info) { 1415 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan, 1416 il->band); 1417 return -EINVAL; 1418 } 1419 1420 if (!il_is_channel_valid(ch_info)) { 1421 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n"); 1422 return 0; 1423 } 1424 1425 /* fill cmd with power settings for all rates for current channel */ 1426 /* Fill OFDM rate */ 1427 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0; 1428 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) { 1429 1430 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1431 txpower.power[i].rate = il3945_rates[rate_idx].plcp; 1432 1433 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1434 le16_to_cpu(txpower.channel), txpower.band, 1435 txpower.power[i].tpc.tx_gain, 1436 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate); 1437 } 1438 /* Fill CCK rates */ 1439 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE; 1440 rate_idx++, i++) { 1441 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1442 txpower.power[i].rate = il3945_rates[rate_idx].plcp; 1443 1444 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1445 le16_to_cpu(txpower.channel), txpower.band, 1446 txpower.power[i].tpc.tx_gain, 1447 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate); 1448 } 1449 1450 return il_send_cmd_pdu(il, C_TX_PWR_TBL, 1451 sizeof(struct il3945_txpowertable_cmd), 1452 &txpower); 1453 1454} 1455 1456/** 1457 * il3945_hw_reg_set_new_power - Configures power tables at new levels 1458 * @ch_info: Channel to update. Uses power_info.requested_power. 1459 * 1460 * Replace requested_power and base_power_idx ch_info fields for 1461 * one channel. 1462 * 1463 * Called if user or spectrum management changes power preferences. 1464 * Takes into account h/w and modulation limitations (clip power). 1465 * 1466 * This does *not* send anything to NIC, just sets up ch_info for one channel. 1467 * 1468 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to 1469 * properly fill out the scan powers, and actual h/w gain settings, 1470 * and send changes to NIC 1471 */ 1472static int 1473il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info) 1474{ 1475 struct il3945_channel_power_info *power_info; 1476 int power_changed = 0; 1477 int i; 1478 const s8 *clip_pwrs; 1479 int power; 1480 1481 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1482 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers; 1483 1484 /* Get this channel's rate-to-current-power settings table */ 1485 power_info = ch_info->power_info; 1486 1487 /* update OFDM Txpower settings */ 1488 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) { 1489 int delta_idx; 1490 1491 /* limit new power to be no more than h/w capability */ 1492 power = min(ch_info->curr_txpow, clip_pwrs[i]); 1493 if (power == power_info->requested_power) 1494 continue; 1495 1496 /* find difference between old and new requested powers, 1497 * update base (non-temp-compensated) power idx */ 1498 delta_idx = (power - power_info->requested_power) * 2; 1499 power_info->base_power_idx -= delta_idx; 1500 1501 /* save new requested power value */ 1502 power_info->requested_power = power; 1503 1504 power_changed = 1; 1505 } 1506 1507 /* update CCK Txpower settings, based on OFDM 12M setting ... 1508 * ... all CCK power settings for a given channel are the *same*. */ 1509 if (power_changed) { 1510 power = 1511 ch_info->power_info[RATE_12M_IDX_TBL].requested_power + 1512 IL_CCK_FROM_OFDM_POWER_DIFF; 1513 1514 /* do all CCK rates' il3945_channel_power_info structures */ 1515 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) { 1516 power_info->requested_power = power; 1517 power_info->base_power_idx = 1518 ch_info->power_info[RATE_12M_IDX_TBL]. 1519 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 1520 ++power_info; 1521 } 1522 } 1523 1524 return 0; 1525} 1526 1527/** 1528 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel 1529 * 1530 * NOTE: Returned power limit may be less (but not more) than requested, 1531 * based strictly on regulatory (eeprom and spectrum mgt) limitations 1532 * (no consideration for h/w clipping limitations). 1533 */ 1534static int 1535il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info) 1536{ 1537 s8 max_power; 1538 1539#if 0 1540 /* if we're using TGd limits, use lower of TGd or EEPROM */ 1541 if (ch_info->tgd_data.max_power != 0) 1542 max_power = 1543 min(ch_info->tgd_data.max_power, 1544 ch_info->eeprom.max_power_avg); 1545 1546 /* else just use EEPROM limits */ 1547 else 1548#endif 1549 max_power = ch_info->eeprom.max_power_avg; 1550 1551 return min(max_power, ch_info->max_power_avg); 1552} 1553 1554/** 1555 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature 1556 * 1557 * Compensate txpower settings of *all* channels for temperature. 1558 * This only accounts for the difference between current temperature 1559 * and the factory calibration temperatures, and bases the new settings 1560 * on the channel's base_power_idx. 1561 * 1562 * If RxOn is "associated", this sends the new Txpower to NIC! 1563 */ 1564static int 1565il3945_hw_reg_comp_txpower_temp(struct il_priv *il) 1566{ 1567 struct il_channel_info *ch_info = NULL; 1568 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1569 int delta_idx; 1570 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ 1571 u8 a_band; 1572 u8 rate_idx; 1573 u8 scan_tbl_idx; 1574 u8 i; 1575 int ref_temp; 1576 int temperature = il->temperature; 1577 1578 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) { 1579 /* do not perform tx power calibration */ 1580 return 0; 1581 } 1582 /* set up new Tx power info for each and every channel, 2.4 and 5.x */ 1583 for (i = 0; i < il->channel_count; i++) { 1584 ch_info = &il->channel_info[i]; 1585 a_band = il_is_channel_a_band(ch_info); 1586 1587 /* Get this chnlgrp's factory calibration temperature */ 1588 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature; 1589 1590 /* get power idx adjustment based on current and factory 1591 * temps */ 1592 delta_idx = 1593 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp); 1594 1595 /* set tx power value for all rates, OFDM and CCK */ 1596 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) { 1597 int power_idx = 1598 ch_info->power_info[rate_idx].base_power_idx; 1599 1600 /* temperature compensate */ 1601 power_idx += delta_idx; 1602 1603 /* stay within table range */ 1604 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 1605 ch_info->power_info[rate_idx].power_table_idx = 1606 (u8) power_idx; 1607 ch_info->power_info[rate_idx].tpc = 1608 power_gain_table[a_band][power_idx]; 1609 } 1610 1611 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1612 clip_pwrs = 1613 il->_3945.clip_groups[ch_info->group_idx].clip_powers; 1614 1615 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 1616 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES; 1617 scan_tbl_idx++) { 1618 s32 actual_idx = 1619 (scan_tbl_idx == 1620 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL; 1621 il3945_hw_reg_set_scan_power(il, scan_tbl_idx, 1622 actual_idx, clip_pwrs, 1623 ch_info, a_band); 1624 } 1625 } 1626 1627 /* send Txpower command for current channel to ucode */ 1628 return il->ops->send_tx_power(il); 1629} 1630 1631int 1632il3945_hw_reg_set_txpower(struct il_priv *il, s8 power) 1633{ 1634 struct il_channel_info *ch_info; 1635 s8 max_power; 1636 u8 a_band; 1637 u8 i; 1638 1639 if (il->tx_power_user_lmt == power) { 1640 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n", 1641 power); 1642 return 0; 1643 } 1644 1645 D_POWER("Setting upper limit clamp to %ddBm.\n", power); 1646 il->tx_power_user_lmt = power; 1647 1648 /* set up new Tx powers for each and every channel, 2.4 and 5.x */ 1649 1650 for (i = 0; i < il->channel_count; i++) { 1651 ch_info = &il->channel_info[i]; 1652 a_band = il_is_channel_a_band(ch_info); 1653 1654 /* find minimum power of all user and regulatory constraints 1655 * (does not consider h/w clipping limitations) */ 1656 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info); 1657 max_power = min(power, max_power); 1658 if (max_power != ch_info->curr_txpow) { 1659 ch_info->curr_txpow = max_power; 1660 1661 /* this considers the h/w clipping limitations */ 1662 il3945_hw_reg_set_new_power(il, ch_info); 1663 } 1664 } 1665 1666 /* update txpower settings for all channels, 1667 * send to NIC if associated. */ 1668 il3945_is_temp_calib_needed(il); 1669 il3945_hw_reg_comp_txpower_temp(il); 1670 1671 return 0; 1672} 1673 1674static int 1675il3945_send_rxon_assoc(struct il_priv *il) 1676{ 1677 int rc = 0; 1678 struct il_rx_pkt *pkt; 1679 struct il3945_rxon_assoc_cmd rxon_assoc; 1680 struct il_host_cmd cmd = { 1681 .id = C_RXON_ASSOC, 1682 .len = sizeof(rxon_assoc), 1683 .flags = CMD_WANT_SKB, 1684 .data = &rxon_assoc, 1685 }; 1686 const struct il_rxon_cmd *rxon1 = &il->staging; 1687 const struct il_rxon_cmd *rxon2 = &il->active; 1688 1689 if (rxon1->flags == rxon2->flags && 1690 rxon1->filter_flags == rxon2->filter_flags && 1691 rxon1->cck_basic_rates == rxon2->cck_basic_rates && 1692 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) { 1693 D_INFO("Using current RXON_ASSOC. Not resending.\n"); 1694 return 0; 1695 } 1696 1697 rxon_assoc.flags = il->staging.flags; 1698 rxon_assoc.filter_flags = il->staging.filter_flags; 1699 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates; 1700 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates; 1701 rxon_assoc.reserved = 0; 1702 1703 rc = il_send_cmd_sync(il, &cmd); 1704 if (rc) 1705 return rc; 1706 1707 pkt = (struct il_rx_pkt *)cmd.reply_page; 1708 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { 1709 IL_ERR("Bad return from C_RXON_ASSOC command\n"); 1710 rc = -EIO; 1711 } 1712 1713 il_free_pages(il, cmd.reply_page); 1714 1715 return rc; 1716} 1717 1718/** 1719 * il3945_commit_rxon - commit staging_rxon to hardware 1720 * 1721 * The RXON command in staging_rxon is committed to the hardware and 1722 * the active_rxon structure is updated with the new data. This 1723 * function correctly transitions out of the RXON_ASSOC_MSK state if 1724 * a HW tune is required based on the RXON structure changes. 1725 */ 1726int 1727il3945_commit_rxon(struct il_priv *il) 1728{ 1729 /* cast away the const for active_rxon in this function */ 1730 struct il3945_rxon_cmd *active_rxon = (void *)&il->active; 1731 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging; 1732 int rc = 0; 1733 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK); 1734 1735 if (test_bit(S_EXIT_PENDING, &il->status)) 1736 return -EINVAL; 1737 1738 if (!il_is_alive(il)) 1739 return -1; 1740 1741 /* always get timestamp with Rx frame */ 1742 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK; 1743 1744 /* select antenna */ 1745 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); 1746 staging_rxon->flags |= il3945_get_antenna_flags(il); 1747 1748 rc = il_check_rxon_cmd(il); 1749 if (rc) { 1750 IL_ERR("Invalid RXON configuration. Not committing.\n"); 1751 return -EINVAL; 1752 } 1753 1754 /* If we don't need to send a full RXON, we can use 1755 * il3945_rxon_assoc_cmd which is used to reconfigure filter 1756 * and other flags for the current radio configuration. */ 1757 if (!il_full_rxon_required(il)) { 1758 rc = il_send_rxon_assoc(il); 1759 if (rc) { 1760 IL_ERR("Error setting RXON_ASSOC " 1761 "configuration (%d).\n", rc); 1762 return rc; 1763 } 1764 1765 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1766 /* 1767 * We do not commit tx power settings while channel changing, 1768 * do it now if tx power changed. 1769 */ 1770 il_set_tx_power(il, il->tx_power_next, false); 1771 return 0; 1772 } 1773 1774 /* If we are currently associated and the new config requires 1775 * an RXON_ASSOC and the new config wants the associated mask enabled, 1776 * we must clear the associated from the active configuration 1777 * before we apply the new config */ 1778 if (il_is_associated(il) && new_assoc) { 1779 D_INFO("Toggling associated bit on current RXON\n"); 1780 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 1781 1782 /* 1783 * reserved4 and 5 could have been filled by the iwlcore code. 1784 * Let's clear them before pushing to the 3945. 1785 */ 1786 active_rxon->reserved4 = 0; 1787 active_rxon->reserved5 = 0; 1788 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd), 1789 &il->active); 1790 1791 /* If the mask clearing failed then we set 1792 * active_rxon back to what it was previously */ 1793 if (rc) { 1794 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; 1795 IL_ERR("Error clearing ASSOC_MSK on current " 1796 "configuration (%d).\n", rc); 1797 return rc; 1798 } 1799 il_clear_ucode_stations(il); 1800 il_restore_stations(il); 1801 } 1802 1803 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n" 1804 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"), 1805 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr); 1806 1807 /* 1808 * reserved4 and 5 could have been filled by the iwlcore code. 1809 * Let's clear them before pushing to the 3945. 1810 */ 1811 staging_rxon->reserved4 = 0; 1812 staging_rxon->reserved5 = 0; 1813 1814 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto); 1815 1816 /* Apply the new configuration */ 1817 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd), 1818 staging_rxon); 1819 if (rc) { 1820 IL_ERR("Error setting new configuration (%d).\n", rc); 1821 return rc; 1822 } 1823 1824 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1825 1826 if (!new_assoc) { 1827 il_clear_ucode_stations(il); 1828 il_restore_stations(il); 1829 } 1830 1831 /* If we issue a new RXON command which required a tune then we must 1832 * send a new TXPOWER command or we won't be able to Tx any frames */ 1833 rc = il_set_tx_power(il, il->tx_power_next, true); 1834 if (rc) { 1835 IL_ERR("Error setting Tx power (%d).\n", rc); 1836 return rc; 1837 } 1838 1839 /* Init the hardware's rate fallback order based on the band */ 1840 rc = il3945_init_hw_rate_table(il); 1841 if (rc) { 1842 IL_ERR("Error setting HW rate table: %02X\n", rc); 1843 return -EIO; 1844 } 1845 1846 return 0; 1847} 1848 1849/** 1850 * il3945_reg_txpower_periodic - called when time to check our temperature. 1851 * 1852 * -- reset periodic timer 1853 * -- see if temp has changed enough to warrant re-calibration ... if so: 1854 * -- correct coeffs for temp (can reset temp timer) 1855 * -- save this temp as "last", 1856 * -- send new set of gain settings to NIC 1857 * NOTE: This should continue working, even when we're not associated, 1858 * so we can keep our internal table of scan powers current. */ 1859void 1860il3945_reg_txpower_periodic(struct il_priv *il) 1861{ 1862 /* This will kick in the "brute force" 1863 * il3945_hw_reg_comp_txpower_temp() below */ 1864 if (!il3945_is_temp_calib_needed(il)) 1865 goto reschedule; 1866 1867 /* Set up a new set of temp-adjusted TxPowers, send to NIC. 1868 * This is based *only* on current temperature, 1869 * ignoring any previous power measurements */ 1870 il3945_hw_reg_comp_txpower_temp(il); 1871 1872reschedule: 1873 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic, 1874 REG_RECALIB_PERIOD * HZ); 1875} 1876 1877static void 1878il3945_bg_reg_txpower_periodic(struct work_struct *work) 1879{ 1880 struct il_priv *il = container_of(work, struct il_priv, 1881 _3945.thermal_periodic.work); 1882 1883 mutex_lock(&il->mutex); 1884 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL) 1885 goto out; 1886 1887 il3945_reg_txpower_periodic(il); 1888out: 1889 mutex_unlock(&il->mutex); 1890} 1891 1892/** 1893 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel. 1894 * 1895 * This function is used when initializing channel-info structs. 1896 * 1897 * NOTE: These channel groups do *NOT* match the bands above! 1898 * These channel groups are based on factory-tested channels; 1899 * on A-band, EEPROM's "group frequency" entries represent the top 1900 * channel in each group 1-4. Group 5 All B/G channels are in group 0. 1901 */ 1902static u16 1903il3945_hw_reg_get_ch_grp_idx(struct il_priv *il, 1904 const struct il_channel_info *ch_info) 1905{ 1906 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1907 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0]; 1908 u8 group; 1909 u16 group_idx = 0; /* based on factory calib frequencies */ 1910 u8 grp_channel; 1911 1912 /* Find the group idx for the channel ... don't use idx 1(?) */ 1913 if (il_is_channel_a_band(ch_info)) { 1914 for (group = 1; group < 5; group++) { 1915 grp_channel = ch_grp[group].group_channel; 1916 if (ch_info->channel <= grp_channel) { 1917 group_idx = group; 1918 break; 1919 } 1920 } 1921 /* group 4 has a few channels *above* its factory cal freq */ 1922 if (group == 5) 1923 group_idx = 4; 1924 } else 1925 group_idx = 0; /* 2.4 GHz, group 0 */ 1926 1927 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx); 1928 return group_idx; 1929} 1930 1931/** 1932 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx 1933 * 1934 * Interpolate to get nominal (i.e. at factory calibration temperature) idx 1935 * into radio/DSP gain settings table for requested power. 1936 */ 1937static int 1938il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power, 1939 s32 setting_idx, s32 *new_idx) 1940{ 1941 const struct il3945_eeprom_txpower_group *chnl_grp = NULL; 1942 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1943 s32 idx0, idx1; 1944 s32 power = 2 * requested_power; 1945 s32 i; 1946 const struct il3945_eeprom_txpower_sample *samples; 1947 s32 gains0, gains1; 1948 s32 res; 1949 s32 denominator; 1950 1951 chnl_grp = &eeprom->groups[setting_idx]; 1952 samples = chnl_grp->samples; 1953 for (i = 0; i < 5; i++) { 1954 if (power == samples[i].power) { 1955 *new_idx = samples[i].gain_idx; 1956 return 0; 1957 } 1958 } 1959 1960 if (power > samples[1].power) { 1961 idx0 = 0; 1962 idx1 = 1; 1963 } else if (power > samples[2].power) { 1964 idx0 = 1; 1965 idx1 = 2; 1966 } else if (power > samples[3].power) { 1967 idx0 = 2; 1968 idx1 = 3; 1969 } else { 1970 idx0 = 3; 1971 idx1 = 4; 1972 } 1973 1974 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power; 1975 if (denominator == 0) 1976 return -EINVAL; 1977 gains0 = (s32) samples[idx0].gain_idx * (1 << 19); 1978 gains1 = (s32) samples[idx1].gain_idx * (1 << 19); 1979 res = 1980 gains0 + (gains1 - gains0) * ((s32) power - 1981 (s32) samples[idx0].power) / 1982 denominator + (1 << 18); 1983 *new_idx = res >> 19; 1984 return 0; 1985} 1986 1987static void 1988il3945_hw_reg_init_channel_groups(struct il_priv *il) 1989{ 1990 u32 i; 1991 s32 rate_idx; 1992 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1993 const struct il3945_eeprom_txpower_group *group; 1994 1995 D_POWER("Initializing factory calib info from EEPROM\n"); 1996 1997 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) { 1998 s8 *clip_pwrs; /* table of power levels for each rate */ 1999 s8 satur_pwr; /* saturation power for each chnl group */ 2000 group = &eeprom->groups[i]; 2001 2002 /* sanity check on factory saturation power value */ 2003 if (group->saturation_power < 40) { 2004 IL_WARN("Error: saturation power is %d, " 2005 "less than minimum expected 40\n", 2006 group->saturation_power); 2007 return; 2008 } 2009 2010 /* 2011 * Derive requested power levels for each rate, based on 2012 * hardware capabilities (saturation power for band). 2013 * Basic value is 3dB down from saturation, with further 2014 * power reductions for highest 3 data rates. These 2015 * backoffs provide headroom for high rate modulation 2016 * power peaks, without too much distortion (clipping). 2017 */ 2018 /* we'll fill in this array with h/w max power levels */ 2019 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers; 2020 2021 /* divide factory saturation power by 2 to find -3dB level */ 2022 satur_pwr = (s8) (group->saturation_power >> 1); 2023 2024 /* fill in channel group's nominal powers for each rate */ 2025 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; 2026 rate_idx++, clip_pwrs++) { 2027 switch (rate_idx) { 2028 case RATE_36M_IDX_TBL: 2029 if (i == 0) /* B/G */ 2030 *clip_pwrs = satur_pwr; 2031 else /* A */ 2032 *clip_pwrs = satur_pwr - 5; 2033 break; 2034 case RATE_48M_IDX_TBL: 2035 if (i == 0) 2036 *clip_pwrs = satur_pwr - 7; 2037 else 2038 *clip_pwrs = satur_pwr - 10; 2039 break; 2040 case RATE_54M_IDX_TBL: 2041 if (i == 0) 2042 *clip_pwrs = satur_pwr - 9; 2043 else 2044 *clip_pwrs = satur_pwr - 12; 2045 break; 2046 default: 2047 *clip_pwrs = satur_pwr; 2048 break; 2049 } 2050 } 2051 } 2052} 2053 2054/** 2055 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM 2056 * 2057 * Second pass (during init) to set up il->channel_info 2058 * 2059 * Set up Tx-power settings in our channel info database for each VALID 2060 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values 2061 * and current temperature. 2062 * 2063 * Since this is based on current temperature (at init time), these values may 2064 * not be valid for very long, but it gives us a starting/default point, 2065 * and allows us to active (i.e. using Tx) scan. 2066 * 2067 * This does *not* write values to NIC, just sets up our internal table. 2068 */ 2069int 2070il3945_txpower_set_from_eeprom(struct il_priv *il) 2071{ 2072 struct il_channel_info *ch_info = NULL; 2073 struct il3945_channel_power_info *pwr_info; 2074 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 2075 int delta_idx; 2076 u8 rate_idx; 2077 u8 scan_tbl_idx; 2078 const s8 *clip_pwrs; /* array of power levels for each rate */ 2079 u8 gain, dsp_atten; 2080 s8 power; 2081 u8 pwr_idx, base_pwr_idx, a_band; 2082 u8 i; 2083 int temperature; 2084 2085 /* save temperature reference, 2086 * so we can determine next time to calibrate */ 2087 temperature = il3945_hw_reg_txpower_get_temperature(il); 2088 il->last_temperature = temperature; 2089 2090 il3945_hw_reg_init_channel_groups(il); 2091 2092 /* initialize Tx power info for each and every channel, 2.4 and 5.x */ 2093 for (i = 0, ch_info = il->channel_info; i < il->channel_count; 2094 i++, ch_info++) { 2095 a_band = il_is_channel_a_band(ch_info); 2096 if (!il_is_channel_valid(ch_info)) 2097 continue; 2098 2099 /* find this channel's channel group (*not* "band") idx */ 2100 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info); 2101 2102 /* Get this chnlgrp's rate->max/clip-powers table */ 2103 clip_pwrs = 2104 il->_3945.clip_groups[ch_info->group_idx].clip_powers; 2105 2106 /* calculate power idx *adjustment* value according to 2107 * diff between current temperature and factory temperature */ 2108 delta_idx = 2109 il3945_hw_reg_adjust_power_by_temp(temperature, 2110 eeprom->groups[ch_info-> 2111 group_idx]. 2112 temperature); 2113 2114 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel, 2115 delta_idx, temperature + IL_TEMP_CONVERT); 2116 2117 /* set tx power value for all OFDM rates */ 2118 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) { 2119 s32 uninitialized_var(power_idx); 2120 int rc; 2121 2122 /* use channel group's clip-power table, 2123 * but don't exceed channel's max power */ 2124 s8 pwr = min(ch_info->max_power_avg, 2125 clip_pwrs[rate_idx]); 2126 2127 pwr_info = &ch_info->power_info[rate_idx]; 2128 2129 /* get base (i.e. at factory-measured temperature) 2130 * power table idx for this rate's power */ 2131 rc = il3945_hw_reg_get_matched_power_idx(il, pwr, 2132 ch_info-> 2133 group_idx, 2134 &power_idx); 2135 if (rc) { 2136 IL_ERR("Invalid power idx\n"); 2137 return rc; 2138 } 2139 pwr_info->base_power_idx = (u8) power_idx; 2140 2141 /* temperature compensate */ 2142 power_idx += delta_idx; 2143 2144 /* stay within range of gain table */ 2145 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 2146 2147 /* fill 1 OFDM rate's il3945_channel_power_info struct */ 2148 pwr_info->requested_power = pwr; 2149 pwr_info->power_table_idx = (u8) power_idx; 2150 pwr_info->tpc.tx_gain = 2151 power_gain_table[a_band][power_idx].tx_gain; 2152 pwr_info->tpc.dsp_atten = 2153 power_gain_table[a_band][power_idx].dsp_atten; 2154 } 2155 2156 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */ 2157 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL]; 2158 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF; 2159 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 2160 base_pwr_idx = 2161 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 2162 2163 /* stay within table range */ 2164 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx); 2165 gain = power_gain_table[a_band][pwr_idx].tx_gain; 2166 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten; 2167 2168 /* fill each CCK rate's il3945_channel_power_info structure 2169 * NOTE: All CCK-rate Txpwrs are the same for a given chnl! 2170 * NOTE: CCK rates start at end of OFDM rates! */ 2171 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) { 2172 pwr_info = 2173 &ch_info->power_info[rate_idx + IL_OFDM_RATES]; 2174 pwr_info->requested_power = power; 2175 pwr_info->power_table_idx = pwr_idx; 2176 pwr_info->base_power_idx = base_pwr_idx; 2177 pwr_info->tpc.tx_gain = gain; 2178 pwr_info->tpc.dsp_atten = dsp_atten; 2179 } 2180 2181 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 2182 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES; 2183 scan_tbl_idx++) { 2184 s32 actual_idx = 2185 (scan_tbl_idx == 2186 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL; 2187 il3945_hw_reg_set_scan_power(il, scan_tbl_idx, 2188 actual_idx, clip_pwrs, 2189 ch_info, a_band); 2190 } 2191 } 2192 2193 return 0; 2194} 2195 2196int 2197il3945_hw_rxq_stop(struct il_priv *il) 2198{ 2199 int ret; 2200 2201 _il_wr(il, FH39_RCSR_CONFIG(0), 0); 2202 ret = _il_poll_bit(il, FH39_RSSR_STATUS, 2203 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 2204 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 2205 1000); 2206 if (ret < 0) 2207 IL_ERR("Can't stop Rx DMA.\n"); 2208 2209 return 0; 2210} 2211 2212int 2213il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 2214{ 2215 int txq_id = txq->q.id; 2216 2217 struct il3945_shared *shared_data = il->_3945.shared_virt; 2218 2219 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr); 2220 2221 il_wr(il, FH39_CBCC_CTRL(txq_id), 0); 2222 il_wr(il, FH39_CBCC_BASE(txq_id), 0); 2223 2224 il_wr(il, FH39_TCSR_CONFIG(txq_id), 2225 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2226 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2227 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2228 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2229 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2230 2231 /* fake read to flush all prev. writes */ 2232 _il_rd(il, FH39_TSSR_CBB_BASE); 2233 2234 return 0; 2235} 2236 2237/* 2238 * HCMD utils 2239 */ 2240static u16 2241il3945_get_hcmd_size(u8 cmd_id, u16 len) 2242{ 2243 switch (cmd_id) { 2244 case C_RXON: 2245 return sizeof(struct il3945_rxon_cmd); 2246 case C_POWER_TBL: 2247 return sizeof(struct il3945_powertable_cmd); 2248 default: 2249 return len; 2250 } 2251} 2252 2253static u16 2254il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data) 2255{ 2256 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data; 2257 addsta->mode = cmd->mode; 2258 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); 2259 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo)); 2260 addsta->station_flags = cmd->station_flags; 2261 addsta->station_flags_msk = cmd->station_flags_msk; 2262 addsta->tid_disable_tx = cpu_to_le16(0); 2263 addsta->rate_n_flags = cmd->rate_n_flags; 2264 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; 2265 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; 2266 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; 2267 2268 return (u16) sizeof(struct il3945_addsta_cmd); 2269} 2270 2271static int 2272il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r) 2273{ 2274 int ret; 2275 u8 sta_id; 2276 unsigned long flags; 2277 2278 if (sta_id_r) 2279 *sta_id_r = IL_INVALID_STATION; 2280 2281 ret = il_add_station_common(il, addr, 0, NULL, &sta_id); 2282 if (ret) { 2283 IL_ERR("Unable to add station %pM\n", addr); 2284 return ret; 2285 } 2286 2287 if (sta_id_r) 2288 *sta_id_r = sta_id; 2289 2290 spin_lock_irqsave(&il->sta_lock, flags); 2291 il->stations[sta_id].used |= IL_STA_LOCAL; 2292 spin_unlock_irqrestore(&il->sta_lock, flags); 2293 2294 return 0; 2295} 2296 2297static int 2298il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 2299 bool add) 2300{ 2301 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 2302 int ret; 2303 2304 if (add) { 2305 ret = 2306 il3945_add_bssid_station(il, vif->bss_conf.bssid, 2307 &vif_priv->ibss_bssid_sta_id); 2308 if (ret) 2309 return ret; 2310 2311 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id, 2312 (il->band == 2313 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : 2314 RATE_1M_PLCP); 2315 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id); 2316 2317 return 0; 2318 } 2319 2320 return il_remove_station(il, vif_priv->ibss_bssid_sta_id, 2321 vif->bss_conf.bssid); 2322} 2323 2324/** 2325 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table 2326 */ 2327int 2328il3945_init_hw_rate_table(struct il_priv *il) 2329{ 2330 int rc, i, idx, prev_idx; 2331 struct il3945_rate_scaling_cmd rate_cmd = { 2332 .reserved = {0, 0, 0}, 2333 }; 2334 struct il3945_rate_scaling_info *table = rate_cmd.table; 2335 2336 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) { 2337 idx = il3945_rates[i].table_rs_idx; 2338 2339 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp); 2340 table[idx].try_cnt = il->retry_rate; 2341 prev_idx = il3945_get_prev_ieee_rate(i); 2342 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx; 2343 } 2344 2345 switch (il->band) { 2346 case IEEE80211_BAND_5GHZ: 2347 D_RATE("Select A mode rate scale\n"); 2348 /* If one of the following CCK rates is used, 2349 * have it fall back to the 6M OFDM rate */ 2350 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) 2351 table[i].next_rate_idx = 2352 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx; 2353 2354 /* Don't fall back to CCK rates */ 2355 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL; 2356 2357 /* Don't drop out of OFDM rates */ 2358 table[RATE_6M_IDX_TBL].next_rate_idx = 2359 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx; 2360 break; 2361 2362 case IEEE80211_BAND_2GHZ: 2363 D_RATE("Select B/G mode rate scale\n"); 2364 /* If an OFDM rate is used, have it fall back to the 2365 * 1M CCK rates */ 2366 2367 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) && 2368 il_is_associated(il)) { 2369 2370 idx = IL_FIRST_CCK_RATE; 2371 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++) 2372 table[i].next_rate_idx = 2373 il3945_rates[idx].table_rs_idx; 2374 2375 idx = RATE_11M_IDX_TBL; 2376 /* CCK shouldn't fall back to OFDM... */ 2377 table[idx].next_rate_idx = RATE_5M_IDX_TBL; 2378 } 2379 break; 2380 2381 default: 2382 WARN_ON(1); 2383 break; 2384 } 2385 2386 /* Update the rate scaling for control frame Tx */ 2387 rate_cmd.table_id = 0; 2388 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd); 2389 if (rc) 2390 return rc; 2391 2392 /* Update the rate scaling for data frame Tx */ 2393 rate_cmd.table_id = 1; 2394 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd); 2395} 2396 2397/* Called when initializing driver */ 2398int 2399il3945_hw_set_hw_params(struct il_priv *il) 2400{ 2401 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params)); 2402 2403 il->_3945.shared_virt = 2404 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared), 2405 &il->_3945.shared_phys, GFP_KERNEL); 2406 if (!il->_3945.shared_virt) 2407 return -ENOMEM; 2408 2409 il->hw_params.bcast_id = IL3945_BROADCAST_ID; 2410 2411 /* Assign number of Usable TX queues */ 2412 il->hw_params.max_txq_num = il->cfg->num_of_queues; 2413 2414 il->hw_params.tfd_size = sizeof(struct il3945_tfd); 2415 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K); 2416 il->hw_params.max_rxq_size = RX_QUEUE_SIZE; 2417 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 2418 il->hw_params.max_stations = IL3945_STATION_COUNT; 2419 2420 il->sta_key_max_num = STA_KEY_MAX_NUM; 2421 2422 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR; 2423 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL; 2424 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS; 2425 2426 return 0; 2427} 2428 2429unsigned int 2430il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame, 2431 u8 rate) 2432{ 2433 struct il3945_tx_beacon_cmd *tx_beacon_cmd; 2434 unsigned int frame_size; 2435 2436 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u; 2437 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 2438 2439 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id; 2440 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 2441 2442 frame_size = 2443 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame, 2444 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 2445 2446 BUG_ON(frame_size > MAX_MPDU_SIZE); 2447 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); 2448 2449 tx_beacon_cmd->tx.rate = rate; 2450 tx_beacon_cmd->tx.tx_flags = 2451 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK); 2452 2453 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */ 2454 tx_beacon_cmd->tx.supp_rates[0] = 2455 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; 2456 2457 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF); 2458 2459 return sizeof(struct il3945_tx_beacon_cmd) + frame_size; 2460} 2461 2462void 2463il3945_hw_handler_setup(struct il_priv *il) 2464{ 2465 il->handlers[C_TX] = il3945_hdl_tx; 2466 il->handlers[N_3945_RX] = il3945_hdl_rx; 2467} 2468 2469void 2470il3945_hw_setup_deferred_work(struct il_priv *il) 2471{ 2472 INIT_DELAYED_WORK(&il->_3945.thermal_periodic, 2473 il3945_bg_reg_txpower_periodic); 2474} 2475 2476void 2477il3945_hw_cancel_deferred_work(struct il_priv *il) 2478{ 2479 cancel_delayed_work(&il->_3945.thermal_periodic); 2480} 2481 2482/* check contents of special bootstrap uCode SRAM */ 2483static int 2484il3945_verify_bsm(struct il_priv *il) 2485{ 2486 __le32 *image = il->ucode_boot.v_addr; 2487 u32 len = il->ucode_boot.len; 2488 u32 reg; 2489 u32 val; 2490 2491 D_INFO("Begin verify bsm\n"); 2492 2493 /* verify BSM SRAM contents */ 2494 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); 2495 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len; 2496 reg += sizeof(u32), image++) { 2497 val = il_rd_prph(il, reg); 2498 if (val != le32_to_cpu(*image)) { 2499 IL_ERR("BSM uCode verification failed at " 2500 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 2501 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND, 2502 len, val, le32_to_cpu(*image)); 2503 return -EIO; 2504 } 2505 } 2506 2507 D_INFO("BSM bootstrap uCode image OK\n"); 2508 2509 return 0; 2510} 2511 2512/****************************************************************************** 2513 * 2514 * EEPROM related functions 2515 * 2516 ******************************************************************************/ 2517 2518/* 2519 * Clear the OWNER_MSK, to establish driver (instead of uCode running on 2520 * embedded controller) as EEPROM reader; each read is a series of pulses 2521 * to/from the EEPROM chip, not a single event, so even reads could conflict 2522 * if they weren't arbitrated by some ownership mechanism. Here, the driver 2523 * simply claims ownership, which should be safe when this function is called 2524 * (i.e. before loading uCode!). 2525 */ 2526static int 2527il3945_eeprom_acquire_semaphore(struct il_priv *il) 2528{ 2529 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); 2530 return 0; 2531} 2532 2533static void 2534il3945_eeprom_release_semaphore(struct il_priv *il) 2535{ 2536 return; 2537} 2538 2539 /** 2540 * il3945_load_bsm - Load bootstrap instructions 2541 * 2542 * BSM operation: 2543 * 2544 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program 2545 * in special SRAM that does not power down during RFKILL. When powering back 2546 * up after power-saving sleeps (or during initial uCode load), the BSM loads 2547 * the bootstrap program into the on-board processor, and starts it. 2548 * 2549 * The bootstrap program loads (via DMA) instructions and data for a new 2550 * program from host DRAM locations indicated by the host driver in the 2551 * BSM_DRAM_* registers. Once the new program is loaded, it starts 2552 * automatically. 2553 * 2554 * When initializing the NIC, the host driver points the BSM to the 2555 * "initialize" uCode image. This uCode sets up some internal data, then 2556 * notifies host via "initialize alive" that it is complete. 2557 * 2558 * The host then replaces the BSM_DRAM_* pointer values to point to the 2559 * normal runtime uCode instructions and a backup uCode data cache buffer 2560 * (filled initially with starting data values for the on-board processor), 2561 * then triggers the "initialize" uCode to load and launch the runtime uCode, 2562 * which begins normal operation. 2563 * 2564 * When doing a power-save shutdown, runtime uCode saves data SRAM into 2565 * the backup data cache in DRAM before SRAM is powered down. 2566 * 2567 * When powering back up, the BSM loads the bootstrap program. This reloads 2568 * the runtime uCode instructions and the backup data cache into SRAM, 2569 * and re-launches the runtime uCode from where it left off. 2570 */ 2571static int 2572il3945_load_bsm(struct il_priv *il) 2573{ 2574 __le32 *image = il->ucode_boot.v_addr; 2575 u32 len = il->ucode_boot.len; 2576 dma_addr_t pinst; 2577 dma_addr_t pdata; 2578 u32 inst_len; 2579 u32 data_len; 2580 int rc; 2581 int i; 2582 u32 done; 2583 u32 reg_offset; 2584 2585 D_INFO("Begin load bsm\n"); 2586 2587 /* make sure bootstrap program is no larger than BSM's SRAM size */ 2588 if (len > IL39_MAX_BSM_SIZE) 2589 return -EINVAL; 2590 2591 /* Tell bootstrap uCode where to find the "Initialize" uCode 2592 * in host DRAM ... host DRAM physical address bits 31:0 for 3945. 2593 * NOTE: il3945_initialize_alive_start() will replace these values, 2594 * after the "initialize" uCode has run, to point to 2595 * runtime/protocol instructions and backup data cache. */ 2596 pinst = il->ucode_init.p_addr; 2597 pdata = il->ucode_init_data.p_addr; 2598 inst_len = il->ucode_init.len; 2599 data_len = il->ucode_init_data.len; 2600 2601 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); 2602 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); 2603 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 2604 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 2605 2606 /* Fill BSM memory with bootstrap instructions */ 2607 for (reg_offset = BSM_SRAM_LOWER_BOUND; 2608 reg_offset < BSM_SRAM_LOWER_BOUND + len; 2609 reg_offset += sizeof(u32), image++) 2610 _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); 2611 2612 rc = il3945_verify_bsm(il); 2613 if (rc) 2614 return rc; 2615 2616 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 2617 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0); 2618 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND); 2619 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 2620 2621 /* Load bootstrap code into instruction SRAM now, 2622 * to prepare to load "initialize" uCode */ 2623 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START); 2624 2625 /* Wait for load of bootstrap uCode to finish */ 2626 for (i = 0; i < 100; i++) { 2627 done = il_rd_prph(il, BSM_WR_CTRL_REG); 2628 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 2629 break; 2630 udelay(10); 2631 } 2632 if (i < 100) 2633 D_INFO("BSM write complete, poll %d iterations\n", i); 2634 else { 2635 IL_ERR("BSM write did not complete!\n"); 2636 return -EIO; 2637 } 2638 2639 /* Enable future boot loads whenever power management unit triggers it 2640 * (e.g. when powering back up after power-save shutdown) */ 2641 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); 2642 2643 return 0; 2644} 2645 2646const struct il_ops il3945_ops = { 2647 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd, 2648 .txq_free_tfd = il3945_hw_txq_free_tfd, 2649 .txq_init = il3945_hw_tx_queue_init, 2650 .load_ucode = il3945_load_bsm, 2651 .dump_nic_error_log = il3945_dump_nic_error_log, 2652 .apm_init = il3945_apm_init, 2653 .send_tx_power = il3945_send_tx_power, 2654 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr, 2655 .eeprom_acquire_semaphore = il3945_eeprom_acquire_semaphore, 2656 .eeprom_release_semaphore = il3945_eeprom_release_semaphore, 2657 2658 .rxon_assoc = il3945_send_rxon_assoc, 2659 .commit_rxon = il3945_commit_rxon, 2660 2661 .get_hcmd_size = il3945_get_hcmd_size, 2662 .build_addsta_hcmd = il3945_build_addsta_hcmd, 2663 .request_scan = il3945_request_scan, 2664 .post_scan = il3945_post_scan, 2665 2666 .post_associate = il3945_post_associate, 2667 .config_ap = il3945_config_ap, 2668 .manage_ibss_station = il3945_manage_ibss_station, 2669 2670 .send_led_cmd = il3945_send_led_cmd, 2671}; 2672 2673static struct il_cfg il3945_bg_cfg = { 2674 .name = "3945BG", 2675 .fw_name_pre = IL3945_FW_PRE, 2676 .ucode_api_max = IL3945_UCODE_API_MAX, 2677 .ucode_api_min = IL3945_UCODE_API_MIN, 2678 .sku = IL_SKU_G, 2679 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2680 .mod_params = &il3945_mod_params, 2681 .led_mode = IL_LED_BLINK, 2682 2683 .eeprom_size = IL3945_EEPROM_IMG_SIZE, 2684 .num_of_queues = IL39_NUM_QUEUES, 2685 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, 2686 .set_l0s = false, 2687 .use_bsm = true, 2688 .led_compensation = 64, 2689 .wd_timeout = IL_DEF_WD_TIMEOUT, 2690 2691 .regulatory_bands = { 2692 EEPROM_REGULATORY_BAND_1_CHANNELS, 2693 EEPROM_REGULATORY_BAND_2_CHANNELS, 2694 EEPROM_REGULATORY_BAND_3_CHANNELS, 2695 EEPROM_REGULATORY_BAND_4_CHANNELS, 2696 EEPROM_REGULATORY_BAND_5_CHANNELS, 2697 EEPROM_REGULATORY_BAND_NO_HT40, 2698 EEPROM_REGULATORY_BAND_NO_HT40, 2699 }, 2700}; 2701 2702static struct il_cfg il3945_abg_cfg = { 2703 .name = "3945ABG", 2704 .fw_name_pre = IL3945_FW_PRE, 2705 .ucode_api_max = IL3945_UCODE_API_MAX, 2706 .ucode_api_min = IL3945_UCODE_API_MIN, 2707 .sku = IL_SKU_A | IL_SKU_G, 2708 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2709 .mod_params = &il3945_mod_params, 2710 .led_mode = IL_LED_BLINK, 2711 2712 .eeprom_size = IL3945_EEPROM_IMG_SIZE, 2713 .num_of_queues = IL39_NUM_QUEUES, 2714 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, 2715 .set_l0s = false, 2716 .use_bsm = true, 2717 .led_compensation = 64, 2718 .wd_timeout = IL_DEF_WD_TIMEOUT, 2719 2720 .regulatory_bands = { 2721 EEPROM_REGULATORY_BAND_1_CHANNELS, 2722 EEPROM_REGULATORY_BAND_2_CHANNELS, 2723 EEPROM_REGULATORY_BAND_3_CHANNELS, 2724 EEPROM_REGULATORY_BAND_4_CHANNELS, 2725 EEPROM_REGULATORY_BAND_5_CHANNELS, 2726 EEPROM_REGULATORY_BAND_NO_HT40, 2727 EEPROM_REGULATORY_BAND_NO_HT40, 2728 }, 2729}; 2730 2731const struct pci_device_id il3945_hw_card_ids[] = { 2732 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)}, 2733 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)}, 2734 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)}, 2735 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)}, 2736 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)}, 2737 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)}, 2738 {0} 2739}; 2740 2741MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids); 2742