1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 5 * 6 * Portions of this file are derived from the ipw3945 project, as well 7 * as portions of the ieee80211 subsystem header files. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 21 * 22 * The full GNU General Public License is included in this distribution in the 23 * file called LICENSE. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <ilw@linux.intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 *****************************************************************************/ 30#include <linux/etherdevice.h> 31#include <linux/slab.h> 32#include <linux/sched.h> 33 34#include "iwl-debug.h" 35#include "iwl-csr.h" 36#include "iwl-prph.h" 37#include "iwl-io.h" 38#include "iwl-scd.h" 39#include "iwl-op-mode.h" 40#include "internal.h" 41/* FIXME: need to abstract out TX command (once we know what it looks like) */ 42#include "dvm/commands.h" 43 44#define IWL_TX_CRC_SIZE 4 45#define IWL_TX_DELIMITER_SIZE 4 46 47/*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 48 * DMA services 49 * 50 * Theory of operation 51 * 52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 53 * of buffer descriptors, each of which points to one or more data buffers for 54 * the device to read from or fill. Driver and device exchange status of each 55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 56 * entries in each circular buffer, to protect against confusing empty and full 57 * queue states. 58 * 59 * The device reads or writes the data in the queues via the device's several 60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 61 * 62 * For Tx queue, there are low mark and high mark limits. If, after queuing 63 * the packet for Tx, free space become < low mark, Tx queue stopped. When 64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 65 * Tx queue resumed. 66 * 67 ***************************************************/ 68static int iwl_queue_space(const struct iwl_queue *q) 69{ 70 unsigned int max; 71 unsigned int used; 72 73 /* 74 * To avoid ambiguity between empty and completely full queues, there 75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 77 * to reserve any queue entries for this purpose. 78 */ 79 if (q->n_window < TFD_QUEUE_SIZE_MAX) 80 max = q->n_window; 81 else 82 max = TFD_QUEUE_SIZE_MAX - 1; 83 84 /* 85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 87 */ 88 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 89 90 if (WARN_ON(used > max)) 91 return 0; 92 93 return max - used; 94} 95 96/* 97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 98 */ 99static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) 100{ 101 q->n_window = slots_num; 102 q->id = id; 103 104 /* slots_num must be power-of-two size, otherwise 105 * get_cmd_index is broken. */ 106 if (WARN_ON(!is_power_of_2(slots_num))) 107 return -EINVAL; 108 109 q->low_mark = q->n_window / 4; 110 if (q->low_mark < 4) 111 q->low_mark = 4; 112 113 q->high_mark = q->n_window / 8; 114 if (q->high_mark < 2) 115 q->high_mark = 2; 116 117 q->write_ptr = 0; 118 q->read_ptr = 0; 119 120 return 0; 121} 122 123static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 124 struct iwl_dma_ptr *ptr, size_t size) 125{ 126 if (WARN_ON(ptr->addr)) 127 return -EINVAL; 128 129 ptr->addr = dma_alloc_coherent(trans->dev, size, 130 &ptr->dma, GFP_KERNEL); 131 if (!ptr->addr) 132 return -ENOMEM; 133 ptr->size = size; 134 return 0; 135} 136 137static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, 138 struct iwl_dma_ptr *ptr) 139{ 140 if (unlikely(!ptr->addr)) 141 return; 142 143 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 144 memset(ptr, 0, sizeof(*ptr)); 145} 146 147static void iwl_pcie_txq_stuck_timer(unsigned long data) 148{ 149 struct iwl_txq *txq = (void *)data; 150 struct iwl_queue *q = &txq->q; 151 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 152 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 153 u32 scd_sram_addr = trans_pcie->scd_base_addr + 154 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 155 u8 buf[16]; 156 int i; 157 158 spin_lock(&txq->lock); 159 /* check if triggered erroneously */ 160 if (txq->q.read_ptr == txq->q.write_ptr) { 161 spin_unlock(&txq->lock); 162 return; 163 } 164 spin_unlock(&txq->lock); 165 166 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, 167 jiffies_to_msecs(trans_pcie->wd_timeout)); 168 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 169 txq->q.read_ptr, txq->q.write_ptr); 170 171 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 172 173 iwl_print_hex_error(trans, buf, sizeof(buf)); 174 175 for (i = 0; i < FH_TCSR_CHNL_NUM; i++) 176 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, 177 iwl_read_direct32(trans, FH_TX_TRB_REG(i))); 178 179 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 180 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); 181 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 182 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 183 u32 tbl_dw = 184 iwl_trans_read_mem32(trans, 185 trans_pcie->scd_base_addr + 186 SCD_TRANS_TBL_OFFSET_QUEUE(i)); 187 188 if (i & 0x1) 189 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 190 else 191 tbl_dw = tbl_dw & 0x0000FFFF; 192 193 IWL_ERR(trans, 194 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 195 i, active ? "" : "in", fifo, tbl_dw, 196 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) & 197 (TFD_QUEUE_SIZE_MAX - 1), 198 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); 199 } 200 201 for (i = q->read_ptr; i != q->write_ptr; 202 i = iwl_queue_inc_wrap(i)) 203 IWL_ERR(trans, "scratch %d = 0x%08x\n", i, 204 le32_to_cpu(txq->scratchbufs[i].scratch)); 205 206 iwl_force_nmi(trans); 207} 208 209/* 210 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 211 */ 212static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 213 struct iwl_txq *txq, u16 byte_cnt) 214{ 215 struct iwlagn_scd_bc_tbl *scd_bc_tbl; 216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 217 int write_ptr = txq->q.write_ptr; 218 int txq_id = txq->q.id; 219 u8 sec_ctl = 0; 220 u8 sta_id = 0; 221 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 222 __le16 bc_ent; 223 struct iwl_tx_cmd *tx_cmd = 224 (void *) txq->entries[txq->q.write_ptr].cmd->payload; 225 226 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 227 228 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 229 230 sta_id = tx_cmd->sta_id; 231 sec_ctl = tx_cmd->sec_ctl; 232 233 switch (sec_ctl & TX_CMD_SEC_MSK) { 234 case TX_CMD_SEC_CCM: 235 len += IEEE80211_CCMP_MIC_LEN; 236 break; 237 case TX_CMD_SEC_TKIP: 238 len += IEEE80211_TKIP_ICV_LEN; 239 break; 240 case TX_CMD_SEC_WEP: 241 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 242 break; 243 } 244 245 if (trans_pcie->bc_table_dword) 246 len = DIV_ROUND_UP(len, 4); 247 248 bc_ent = cpu_to_le16(len | (sta_id << 12)); 249 250 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 251 252 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 253 scd_bc_tbl[txq_id]. 254 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 255} 256 257static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 258 struct iwl_txq *txq) 259{ 260 struct iwl_trans_pcie *trans_pcie = 261 IWL_TRANS_GET_PCIE_TRANS(trans); 262 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 263 int txq_id = txq->q.id; 264 int read_ptr = txq->q.read_ptr; 265 u8 sta_id = 0; 266 __le16 bc_ent; 267 struct iwl_tx_cmd *tx_cmd = 268 (void *)txq->entries[txq->q.read_ptr].cmd->payload; 269 270 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 271 272 if (txq_id != trans_pcie->cmd_queue) 273 sta_id = tx_cmd->sta_id; 274 275 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 276 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 277 278 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 279 scd_bc_tbl[txq_id]. 280 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 281} 282 283/* 284 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 285 */ 286static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 287 struct iwl_txq *txq) 288{ 289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 290 u32 reg = 0; 291 int txq_id = txq->q.id; 292 293 lockdep_assert_held(&txq->lock); 294 295 /* 296 * explicitly wake up the NIC if: 297 * 1. shadow registers aren't enabled 298 * 2. NIC is woken up for CMD regardless of shadow outside this function 299 * 3. there is a chance that the NIC is asleep 300 */ 301 if (!trans->cfg->base_params->shadow_reg_enable && 302 txq_id != trans_pcie->cmd_queue && 303 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 304 /* 305 * wake up nic if it's powered down ... 306 * uCode will wake up, and interrupt us again, so next 307 * time we'll skip this part. 308 */ 309 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 310 311 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 312 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 313 txq_id, reg); 314 iwl_set_bit(trans, CSR_GP_CNTRL, 315 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 316 txq->need_update = true; 317 return; 318 } 319 } 320 321 /* 322 * if not in power-save mode, uCode will never sleep when we're 323 * trying to tx (during RFKILL, we're not trying to tx). 324 */ 325 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); 326 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); 327} 328 329void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 330{ 331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 332 int i; 333 334 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 335 struct iwl_txq *txq = &trans_pcie->txq[i]; 336 337 spin_lock_bh(&txq->lock); 338 if (trans_pcie->txq[i].need_update) { 339 iwl_pcie_txq_inc_wr_ptr(trans, txq); 340 trans_pcie->txq[i].need_update = false; 341 } 342 spin_unlock_bh(&txq->lock); 343 } 344} 345 346static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) 347{ 348 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 349 350 dma_addr_t addr = get_unaligned_le32(&tb->lo); 351 if (sizeof(dma_addr_t) > sizeof(u32)) 352 addr |= 353 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; 354 355 return addr; 356} 357 358static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, 359 dma_addr_t addr, u16 len) 360{ 361 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 362 u16 hi_n_len = len << 4; 363 364 put_unaligned_le32(addr, &tb->lo); 365 if (sizeof(dma_addr_t) > sizeof(u32)) 366 hi_n_len |= ((addr >> 16) >> 16) & 0xF; 367 368 tb->hi_n_len = cpu_to_le16(hi_n_len); 369 370 tfd->num_tbs = idx + 1; 371} 372 373static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) 374{ 375 return tfd->num_tbs & 0x1f; 376} 377 378static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 379 struct iwl_cmd_meta *meta, 380 struct iwl_tfd *tfd) 381{ 382 int i; 383 int num_tbs; 384 385 /* Sanity check on number of chunks */ 386 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 387 388 if (num_tbs >= IWL_NUM_OF_TBS) { 389 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 390 /* @todo issue fatal error, it is quite serious situation */ 391 return; 392 } 393 394 /* first TB is never freed - it's the scratchbuf data */ 395 396 for (i = 1; i < num_tbs; i++) 397 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), 398 iwl_pcie_tfd_tb_get_len(tfd, i), 399 DMA_TO_DEVICE); 400 401 tfd->num_tbs = 0; 402} 403 404/* 405 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 406 * @trans - transport private data 407 * @txq - tx queue 408 * @dma_dir - the direction of the DMA mapping 409 * 410 * Does NOT advance any TFD circular buffer read/write indexes 411 * Does NOT free the TFD itself (which is within circular buffer) 412 */ 413static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 414{ 415 struct iwl_tfd *tfd_tmp = txq->tfds; 416 417 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 418 * idx is bounded by n_window 419 */ 420 int rd_ptr = txq->q.read_ptr; 421 int idx = get_cmd_index(&txq->q, rd_ptr); 422 423 lockdep_assert_held(&txq->lock); 424 425 /* We have only q->n_window txq->entries, but we use 426 * TFD_QUEUE_SIZE_MAX tfds 427 */ 428 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); 429 430 /* free SKB */ 431 if (txq->entries) { 432 struct sk_buff *skb; 433 434 skb = txq->entries[idx].skb; 435 436 /* Can be called from irqs-disabled context 437 * If skb is not NULL, it means that the whole queue is being 438 * freed and that the queue is not empty - free the skb 439 */ 440 if (skb) { 441 iwl_op_mode_free_skb(trans->op_mode, skb); 442 txq->entries[idx].skb = NULL; 443 } 444 } 445} 446 447static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 448 dma_addr_t addr, u16 len, bool reset) 449{ 450 struct iwl_queue *q; 451 struct iwl_tfd *tfd, *tfd_tmp; 452 u32 num_tbs; 453 454 q = &txq->q; 455 tfd_tmp = txq->tfds; 456 tfd = &tfd_tmp[q->write_ptr]; 457 458 if (reset) 459 memset(tfd, 0, sizeof(*tfd)); 460 461 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 462 463 /* Each TFD can point to a maximum 20 Tx buffers */ 464 if (num_tbs >= IWL_NUM_OF_TBS) { 465 IWL_ERR(trans, "Error can not send more than %d chunks\n", 466 IWL_NUM_OF_TBS); 467 return -EINVAL; 468 } 469 470 if (WARN(addr & ~IWL_TX_DMA_MASK, 471 "Unaligned address = %llx\n", (unsigned long long)addr)) 472 return -EINVAL; 473 474 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); 475 476 return 0; 477} 478 479static int iwl_pcie_txq_alloc(struct iwl_trans *trans, 480 struct iwl_txq *txq, int slots_num, 481 u32 txq_id) 482{ 483 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 484 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; 485 size_t scratchbuf_sz; 486 int i; 487 488 if (WARN_ON(txq->entries || txq->tfds)) 489 return -EINVAL; 490 491 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 492 (unsigned long)txq); 493 txq->trans_pcie = trans_pcie; 494 495 txq->q.n_window = slots_num; 496 497 txq->entries = kcalloc(slots_num, 498 sizeof(struct iwl_pcie_txq_entry), 499 GFP_KERNEL); 500 501 if (!txq->entries) 502 goto error; 503 504 if (txq_id == trans_pcie->cmd_queue) 505 for (i = 0; i < slots_num; i++) { 506 txq->entries[i].cmd = 507 kmalloc(sizeof(struct iwl_device_cmd), 508 GFP_KERNEL); 509 if (!txq->entries[i].cmd) 510 goto error; 511 } 512 513 /* Circular buffer of transmit frame descriptors (TFDs), 514 * shared with device */ 515 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 516 &txq->q.dma_addr, GFP_KERNEL); 517 if (!txq->tfds) 518 goto error; 519 520 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); 521 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != 522 sizeof(struct iwl_cmd_header) + 523 offsetof(struct iwl_tx_cmd, scratch)); 524 525 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; 526 527 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, 528 &txq->scratchbufs_dma, 529 GFP_KERNEL); 530 if (!txq->scratchbufs) 531 goto err_free_tfds; 532 533 txq->q.id = txq_id; 534 535 return 0; 536err_free_tfds: 537 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); 538error: 539 if (txq->entries && txq_id == trans_pcie->cmd_queue) 540 for (i = 0; i < slots_num; i++) 541 kfree(txq->entries[i].cmd); 542 kfree(txq->entries); 543 txq->entries = NULL; 544 545 return -ENOMEM; 546 547} 548 549static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 550 int slots_num, u32 txq_id) 551{ 552 int ret; 553 554 txq->need_update = false; 555 556 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 557 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 558 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 559 560 /* Initialize queue's high/low-water marks, and head/tail indexes */ 561 ret = iwl_queue_init(&txq->q, slots_num, txq_id); 562 if (ret) 563 return ret; 564 565 spin_lock_init(&txq->lock); 566 567 /* 568 * Tell nic where to find circular buffer of Tx Frame Descriptors for 569 * given Tx queue, and enable the DMA channel used for that queue. 570 * Circular buffer (TFD queue in DRAM) physical base address */ 571 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), 572 txq->q.dma_addr >> 8); 573 574 return 0; 575} 576 577/* 578 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 579 */ 580static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 581{ 582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 583 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 584 struct iwl_queue *q = &txq->q; 585 586 spin_lock_bh(&txq->lock); 587 while (q->write_ptr != q->read_ptr) { 588 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 589 txq_id, q->read_ptr); 590 iwl_pcie_txq_free_tfd(trans, txq); 591 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); 592 } 593 txq->active = false; 594 spin_unlock_bh(&txq->lock); 595 596 /* just in case - this queue may have been stopped */ 597 iwl_wake_queue(trans, txq); 598} 599 600/* 601 * iwl_pcie_txq_free - Deallocate DMA queue. 602 * @txq: Transmit queue to deallocate. 603 * 604 * Empty queue by removing and destroying all BD's. 605 * Free all buffers. 606 * 0-fill, but do not free "txq" descriptor structure. 607 */ 608static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 609{ 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 612 struct device *dev = trans->dev; 613 int i; 614 615 if (WARN_ON(!txq)) 616 return; 617 618 iwl_pcie_txq_unmap(trans, txq_id); 619 620 /* De-alloc array of command/tx buffers */ 621 if (txq_id == trans_pcie->cmd_queue) 622 for (i = 0; i < txq->q.n_window; i++) { 623 kzfree(txq->entries[i].cmd); 624 kzfree(txq->entries[i].free_buf); 625 } 626 627 /* De-alloc circular buffer of TFDs */ 628 if (txq->tfds) { 629 dma_free_coherent(dev, 630 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, 631 txq->tfds, txq->q.dma_addr); 632 txq->q.dma_addr = 0; 633 txq->tfds = NULL; 634 635 dma_free_coherent(dev, 636 sizeof(*txq->scratchbufs) * txq->q.n_window, 637 txq->scratchbufs, txq->scratchbufs_dma); 638 } 639 640 kfree(txq->entries); 641 txq->entries = NULL; 642 643 del_timer_sync(&txq->stuck_timer); 644 645 /* 0-fill queue descriptor structure */ 646 memset(txq, 0, sizeof(*txq)); 647} 648 649void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 650{ 651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 652 int nq = trans->cfg->base_params->num_of_queues; 653 int chan; 654 u32 reg_val; 655 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 656 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 657 658 /* make sure all queue are not stopped/used */ 659 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 660 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 661 662 trans_pcie->scd_base_addr = 663 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 664 665 WARN_ON(scd_base_addr != 0 && 666 scd_base_addr != trans_pcie->scd_base_addr); 667 668 /* reset context data, TX status and translation data */ 669 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 670 SCD_CONTEXT_MEM_LOWER_BOUND, 671 NULL, clear_dwords); 672 673 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 674 trans_pcie->scd_bc_tbls.dma >> 10); 675 676 /* The chain extension of the SCD doesn't work well. This feature is 677 * enabled by default by the HW, so we need to disable it manually. 678 */ 679 if (trans->cfg->base_params->scd_chain_ext_wa) 680 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 681 682 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 683 trans_pcie->cmd_fifo); 684 685 /* Activate all Tx DMA/FIFO channels */ 686 iwl_scd_activate_fifos(trans); 687 688 /* Enable DMA channel */ 689 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 690 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 692 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 693 694 /* Update FH chicken bits */ 695 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 696 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 697 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 698 699 /* Enable L1-Active */ 700 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 701 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 702 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 703} 704 705void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 706{ 707 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 708 int txq_id; 709 710 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 711 txq_id++) { 712 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 713 714 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), 715 txq->q.dma_addr >> 8); 716 iwl_pcie_txq_unmap(trans, txq_id); 717 txq->q.read_ptr = 0; 718 txq->q.write_ptr = 0; 719 } 720 721 /* Tell NIC where to find the "keep warm" buffer */ 722 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 723 trans_pcie->kw.dma >> 4); 724 725 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); 726} 727 728/* 729 * iwl_pcie_tx_stop - Stop all Tx DMA channels 730 */ 731int iwl_pcie_tx_stop(struct iwl_trans *trans) 732{ 733 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 734 int ch, txq_id, ret; 735 736 /* Turn off all Tx DMA fifos */ 737 spin_lock(&trans_pcie->irq_lock); 738 739 iwl_scd_deactivate_fifos(trans); 740 741 /* Stop each Tx DMA channel, and wait for it to be idle */ 742 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 743 iwl_write_direct32(trans, 744 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 745 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, 746 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); 747 if (ret < 0) 748 IWL_ERR(trans, 749 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 750 ch, 751 iwl_read_direct32(trans, 752 FH_TSSR_TX_STATUS_REG)); 753 } 754 spin_unlock(&trans_pcie->irq_lock); 755 756 /* 757 * This function can be called before the op_mode disabled the 758 * queues. This happens when we have an rfkill interrupt. 759 * Since we stop Tx altogether - mark the queues as stopped. 760 */ 761 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 762 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 763 764 /* This can happen: start_hw, stop_device */ 765 if (!trans_pcie->txq) 766 return 0; 767 768 /* Unmap DMA from host system and free skb's */ 769 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 770 txq_id++) 771 iwl_pcie_txq_unmap(trans, txq_id); 772 773 return 0; 774} 775 776/* 777 * iwl_trans_tx_free - Free TXQ Context 778 * 779 * Destroy all TX DMA queues and structures 780 */ 781void iwl_pcie_tx_free(struct iwl_trans *trans) 782{ 783 int txq_id; 784 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 785 786 /* Tx queues */ 787 if (trans_pcie->txq) { 788 for (txq_id = 0; 789 txq_id < trans->cfg->base_params->num_of_queues; txq_id++) 790 iwl_pcie_txq_free(trans, txq_id); 791 } 792 793 kfree(trans_pcie->txq); 794 trans_pcie->txq = NULL; 795 796 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 797 798 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 799} 800 801/* 802 * iwl_pcie_tx_alloc - allocate TX context 803 * Allocate all Tx DMA structures and initialize them 804 */ 805static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 806{ 807 int ret; 808 int txq_id, slots_num; 809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 810 811 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 812 sizeof(struct iwlagn_scd_bc_tbl); 813 814 /*It is not allowed to alloc twice, so warn when this happens. 815 * We cannot rely on the previous allocation, so free and fail */ 816 if (WARN_ON(trans_pcie->txq)) { 817 ret = -EINVAL; 818 goto error; 819 } 820 821 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 822 scd_bc_tbls_size); 823 if (ret) { 824 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 825 goto error; 826 } 827 828 /* Alloc keep-warm buffer */ 829 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 830 if (ret) { 831 IWL_ERR(trans, "Keep Warm allocation failed\n"); 832 goto error; 833 } 834 835 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, 836 sizeof(struct iwl_txq), GFP_KERNEL); 837 if (!trans_pcie->txq) { 838 IWL_ERR(trans, "Not enough memory for txq\n"); 839 ret = -ENOMEM; 840 goto error; 841 } 842 843 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 844 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 845 txq_id++) { 846 slots_num = (txq_id == trans_pcie->cmd_queue) ? 847 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 848 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], 849 slots_num, txq_id); 850 if (ret) { 851 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 852 goto error; 853 } 854 } 855 856 return 0; 857 858error: 859 iwl_pcie_tx_free(trans); 860 861 return ret; 862} 863int iwl_pcie_tx_init(struct iwl_trans *trans) 864{ 865 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 866 int ret; 867 int txq_id, slots_num; 868 bool alloc = false; 869 870 if (!trans_pcie->txq) { 871 ret = iwl_pcie_tx_alloc(trans); 872 if (ret) 873 goto error; 874 alloc = true; 875 } 876 877 spin_lock(&trans_pcie->irq_lock); 878 879 /* Turn off all Tx DMA fifos */ 880 iwl_scd_deactivate_fifos(trans); 881 882 /* Tell NIC where to find the "keep warm" buffer */ 883 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 884 trans_pcie->kw.dma >> 4); 885 886 spin_unlock(&trans_pcie->irq_lock); 887 888 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 889 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 890 txq_id++) { 891 slots_num = (txq_id == trans_pcie->cmd_queue) ? 892 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 893 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], 894 slots_num, txq_id); 895 if (ret) { 896 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 897 goto error; 898 } 899 } 900 901 return 0; 902error: 903 /*Upon error, free only if we allocated something */ 904 if (alloc) 905 iwl_pcie_tx_free(trans); 906 return ret; 907} 908 909static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, 910 struct iwl_txq *txq) 911{ 912 if (!trans_pcie->wd_timeout) 913 return; 914 915 /* 916 * if empty delete timer, otherwise move timer forward 917 * since we're making progress on this queue 918 */ 919 if (txq->q.read_ptr == txq->q.write_ptr) 920 del_timer(&txq->stuck_timer); 921 else 922 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); 923} 924 925/* Frees buffers until index _not_ inclusive */ 926void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 927 struct sk_buff_head *skbs) 928{ 929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 930 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 931 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 932 struct iwl_queue *q = &txq->q; 933 int last_to_free; 934 935 /* This function is not meant to release cmd queue*/ 936 if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 937 return; 938 939 spin_lock_bh(&txq->lock); 940 941 if (!txq->active) { 942 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 943 txq_id, ssn); 944 goto out; 945 } 946 947 if (txq->q.read_ptr == tfd_num) 948 goto out; 949 950 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 951 txq_id, txq->q.read_ptr, tfd_num, ssn); 952 953 /*Since we free until index _not_ inclusive, the one before index is 954 * the last we will free. This one must be used */ 955 last_to_free = iwl_queue_dec_wrap(tfd_num); 956 957 if (!iwl_queue_used(q, last_to_free)) { 958 IWL_ERR(trans, 959 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 960 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 961 q->write_ptr, q->read_ptr); 962 goto out; 963 } 964 965 if (WARN_ON(!skb_queue_empty(skbs))) 966 goto out; 967 968 for (; 969 q->read_ptr != tfd_num; 970 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 971 972 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) 973 continue; 974 975 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); 976 977 txq->entries[txq->q.read_ptr].skb = NULL; 978 979 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 980 981 iwl_pcie_txq_free_tfd(trans, txq); 982 } 983 984 iwl_pcie_txq_progress(trans_pcie, txq); 985 986 if (iwl_queue_space(&txq->q) > txq->q.low_mark) 987 iwl_wake_queue(trans, txq); 988out: 989 spin_unlock_bh(&txq->lock); 990} 991 992/* 993 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 994 * 995 * When FW advances 'R' index, all entries between old and new 'R' index 996 * need to be reclaimed. As result, some free space forms. If there is 997 * enough free space (> low mark), wake the stack that feeds us. 998 */ 999static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1000{ 1001 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1002 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1003 struct iwl_queue *q = &txq->q; 1004 unsigned long flags; 1005 int nfreed = 0; 1006 1007 lockdep_assert_held(&txq->lock); 1008 1009 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { 1010 IWL_ERR(trans, 1011 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1012 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1013 q->write_ptr, q->read_ptr); 1014 return; 1015 } 1016 1017 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; 1018 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 1019 1020 if (nfreed++ > 0) { 1021 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1022 idx, q->write_ptr, q->read_ptr); 1023 iwl_force_nmi(trans); 1024 } 1025 } 1026 1027 if (trans->cfg->base_params->apmg_wake_up_wa && 1028 q->read_ptr == q->write_ptr) { 1029 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1030 WARN_ON(!trans_pcie->cmd_in_flight); 1031 trans_pcie->cmd_in_flight = false; 1032 __iwl_trans_pcie_clear_bit(trans, 1033 CSR_GP_CNTRL, 1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1035 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1036 } 1037 1038 iwl_pcie_txq_progress(trans_pcie, txq); 1039} 1040 1041static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1042 u16 txq_id) 1043{ 1044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1045 u32 tbl_dw_addr; 1046 u32 tbl_dw; 1047 u16 scd_q2ratid; 1048 1049 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1050 1051 tbl_dw_addr = trans_pcie->scd_base_addr + 1052 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1053 1054 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1055 1056 if (txq_id & 0x1) 1057 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1058 else 1059 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1060 1061 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1062 1063 return 0; 1064} 1065 1066/* Receiver address (actually, Rx station's index into station table), 1067 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1068#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1069 1070void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1071 const struct iwl_trans_txq_scd_cfg *cfg) 1072{ 1073 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1074 int fifo = -1; 1075 1076 if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1077 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1078 1079 if (cfg) { 1080 fifo = cfg->fifo; 1081 1082 /* Disable the scheduler prior configuring the cmd queue */ 1083 if (txq_id == trans_pcie->cmd_queue && 1084 trans_pcie->scd_set_active) 1085 iwl_scd_enable_set_active(trans, 0); 1086 1087 /* Stop this Tx queue before configuring it */ 1088 iwl_scd_txq_set_inactive(trans, txq_id); 1089 1090 /* Set this queue as a chain-building queue unless it is CMD */ 1091 if (txq_id != trans_pcie->cmd_queue) 1092 iwl_scd_txq_set_chain(trans, txq_id); 1093 1094 if (cfg->aggregate) { 1095 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1096 1097 /* Map receiver-address / traffic-ID to this queue */ 1098 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1099 1100 /* enable aggregations for the queue */ 1101 iwl_scd_txq_enable_agg(trans, txq_id); 1102 trans_pcie->txq[txq_id].ampdu = true; 1103 } else { 1104 /* 1105 * disable aggregations for the queue, this will also 1106 * make the ra_tid mapping configuration irrelevant 1107 * since it is now a non-AGG queue. 1108 */ 1109 iwl_scd_txq_disable_agg(trans, txq_id); 1110 1111 ssn = trans_pcie->txq[txq_id].q.read_ptr; 1112 } 1113 } 1114 1115 /* Place first TFD at index corresponding to start sequence number. 1116 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1117 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); 1118 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); 1119 1120 if (cfg) { 1121 u8 frame_limit = cfg->frame_limit; 1122 1123 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1124 (ssn & 0xff) | (txq_id << 8)); 1125 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1126 1127 /* Set up Tx window size and frame limit for this queue */ 1128 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1129 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1130 iwl_trans_write_mem32(trans, 1131 trans_pcie->scd_base_addr + 1132 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1133 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1134 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1135 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1136 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1137 1138 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1139 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1140 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1141 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1142 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1143 SCD_QUEUE_STTS_REG_MSK); 1144 1145 /* enable the scheduler for this queue (only) */ 1146 if (txq_id == trans_pcie->cmd_queue && 1147 trans_pcie->scd_set_active) 1148 iwl_scd_enable_set_active(trans, BIT(txq_id)); 1149 } 1150 1151 trans_pcie->txq[txq_id].active = true; 1152 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", 1153 txq_id, fifo, ssn & 0xff); 1154} 1155 1156void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1157 bool configure_scd) 1158{ 1159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1160 u32 stts_addr = trans_pcie->scd_base_addr + 1161 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1162 static const u32 zero_val[4] = {}; 1163 1164 /* 1165 * Upon HW Rfkill - we stop the device, and then stop the queues 1166 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1167 * allow the op_mode to call txq_disable after it already called 1168 * stop_device. 1169 */ 1170 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1171 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1172 "queue %d not used", txq_id); 1173 return; 1174 } 1175 1176 if (configure_scd) { 1177 iwl_scd_txq_set_inactive(trans, txq_id); 1178 1179 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1180 ARRAY_SIZE(zero_val)); 1181 } 1182 1183 iwl_pcie_txq_unmap(trans, txq_id); 1184 trans_pcie->txq[txq_id].ampdu = false; 1185 1186 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1187} 1188 1189/*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1190 1191/* 1192 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1193 * @priv: device private data point 1194 * @cmd: a pointer to the ucode command structure 1195 * 1196 * The function returns < 0 values to indicate the operation 1197 * failed. On success, it returns the index (>= 0) of command in the 1198 * command queue. 1199 */ 1200static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1201 struct iwl_host_cmd *cmd) 1202{ 1203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1204 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1205 struct iwl_queue *q = &txq->q; 1206 struct iwl_device_cmd *out_cmd; 1207 struct iwl_cmd_meta *out_meta; 1208 unsigned long flags; 1209 void *dup_buf = NULL; 1210 dma_addr_t phys_addr; 1211 int idx; 1212 u16 copy_size, cmd_size, scratch_size; 1213 bool had_nocopy = false; 1214 int i, ret; 1215 u32 cmd_pos; 1216 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1217 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1218 1219 copy_size = sizeof(out_cmd->hdr); 1220 cmd_size = sizeof(out_cmd->hdr); 1221 1222 /* need one for the header if the first is NOCOPY */ 1223 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1224 1225 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1226 cmddata[i] = cmd->data[i]; 1227 cmdlen[i] = cmd->len[i]; 1228 1229 if (!cmd->len[i]) 1230 continue; 1231 1232 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ 1233 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { 1234 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; 1235 1236 if (copy > cmdlen[i]) 1237 copy = cmdlen[i]; 1238 cmdlen[i] -= copy; 1239 cmddata[i] += copy; 1240 copy_size += copy; 1241 } 1242 1243 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1244 had_nocopy = true; 1245 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1246 idx = -EINVAL; 1247 goto free_dup_buf; 1248 } 1249 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1250 /* 1251 * This is also a chunk that isn't copied 1252 * to the static buffer so set had_nocopy. 1253 */ 1254 had_nocopy = true; 1255 1256 /* only allowed once */ 1257 if (WARN_ON(dup_buf)) { 1258 idx = -EINVAL; 1259 goto free_dup_buf; 1260 } 1261 1262 dup_buf = kmemdup(cmddata[i], cmdlen[i], 1263 GFP_ATOMIC); 1264 if (!dup_buf) 1265 return -ENOMEM; 1266 } else { 1267 /* NOCOPY must not be followed by normal! */ 1268 if (WARN_ON(had_nocopy)) { 1269 idx = -EINVAL; 1270 goto free_dup_buf; 1271 } 1272 copy_size += cmdlen[i]; 1273 } 1274 cmd_size += cmd->len[i]; 1275 } 1276 1277 /* 1278 * If any of the command structures end up being larger than 1279 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1280 * allocated into separate TFDs, then we will need to 1281 * increase the size of the buffers. 1282 */ 1283 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1284 "Command %s (%#x) is too large (%d bytes)\n", 1285 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { 1286 idx = -EINVAL; 1287 goto free_dup_buf; 1288 } 1289 1290 spin_lock_bh(&txq->lock); 1291 1292 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1293 spin_unlock_bh(&txq->lock); 1294 1295 IWL_ERR(trans, "No space in command queue\n"); 1296 iwl_op_mode_cmd_queue_full(trans->op_mode); 1297 idx = -ENOSPC; 1298 goto free_dup_buf; 1299 } 1300 1301 idx = get_cmd_index(q, q->write_ptr); 1302 out_cmd = txq->entries[idx].cmd; 1303 out_meta = &txq->entries[idx].meta; 1304 1305 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1306 if (cmd->flags & CMD_WANT_SKB) 1307 out_meta->source = cmd; 1308 1309 /* set up the header */ 1310 1311 out_cmd->hdr.cmd = cmd->id; 1312 out_cmd->hdr.flags = 0; 1313 out_cmd->hdr.sequence = 1314 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1315 INDEX_TO_SEQ(q->write_ptr)); 1316 1317 /* and copy the data that needs to be copied */ 1318 cmd_pos = offsetof(struct iwl_device_cmd, payload); 1319 copy_size = sizeof(out_cmd->hdr); 1320 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1321 int copy; 1322 1323 if (!cmd->len[i]) 1324 continue; 1325 1326 /* copy everything if not nocopy/dup */ 1327 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1328 IWL_HCMD_DFL_DUP))) { 1329 copy = cmd->len[i]; 1330 1331 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1332 cmd_pos += copy; 1333 copy_size += copy; 1334 continue; 1335 } 1336 1337 /* 1338 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied 1339 * in total (for the scratchbuf handling), but copy up to what 1340 * we can fit into the payload for debug dump purposes. 1341 */ 1342 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1343 1344 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1345 cmd_pos += copy; 1346 1347 /* However, treat copy_size the proper way, we need it below */ 1348 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { 1349 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; 1350 1351 if (copy > cmd->len[i]) 1352 copy = cmd->len[i]; 1353 copy_size += copy; 1354 } 1355 } 1356 1357 IWL_DEBUG_HC(trans, 1358 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1359 get_cmd_string(trans_pcie, out_cmd->hdr.cmd), 1360 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), 1361 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); 1362 1363 /* start the TFD with the scratchbuf */ 1364 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); 1365 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); 1366 iwl_pcie_txq_build_tfd(trans, txq, 1367 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), 1368 scratch_size, true); 1369 1370 /* map first command fragment, if any remains */ 1371 if (copy_size > scratch_size) { 1372 phys_addr = dma_map_single(trans->dev, 1373 ((u8 *)&out_cmd->hdr) + scratch_size, 1374 copy_size - scratch_size, 1375 DMA_TO_DEVICE); 1376 if (dma_mapping_error(trans->dev, phys_addr)) { 1377 iwl_pcie_tfd_unmap(trans, out_meta, 1378 &txq->tfds[q->write_ptr]); 1379 idx = -ENOMEM; 1380 goto out; 1381 } 1382 1383 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1384 copy_size - scratch_size, false); 1385 } 1386 1387 /* map the remaining (adjusted) nocopy/dup fragments */ 1388 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1389 const void *data = cmddata[i]; 1390 1391 if (!cmdlen[i]) 1392 continue; 1393 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1394 IWL_HCMD_DFL_DUP))) 1395 continue; 1396 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1397 data = dup_buf; 1398 phys_addr = dma_map_single(trans->dev, (void *)data, 1399 cmdlen[i], DMA_TO_DEVICE); 1400 if (dma_mapping_error(trans->dev, phys_addr)) { 1401 iwl_pcie_tfd_unmap(trans, out_meta, 1402 &txq->tfds[q->write_ptr]); 1403 idx = -ENOMEM; 1404 goto out; 1405 } 1406 1407 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1408 } 1409 1410 out_meta->flags = cmd->flags; 1411 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1412 kzfree(txq->entries[idx].free_buf); 1413 txq->entries[idx].free_buf = dup_buf; 1414 1415 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); 1416 1417 /* start timer if queue currently empty */ 1418 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) 1419 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); 1420 1421 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1422 1423 /* 1424 * wake up the NIC to make sure that the firmware will see the host 1425 * command - we will let the NIC sleep once all the host commands 1426 * returned. This needs to be done only on NICs that have 1427 * apmg_wake_up_wa set. 1428 */ 1429 if (trans->cfg->base_params->apmg_wake_up_wa && 1430 !trans_pcie->cmd_in_flight) { 1431 trans_pcie->cmd_in_flight = true; 1432 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1433 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1434 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1435 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1436 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1437 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1438 15000); 1439 if (ret < 0) { 1440 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1441 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1442 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1443 trans_pcie->cmd_in_flight = false; 1444 IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1445 idx = -EIO; 1446 goto out; 1447 } 1448 } 1449 1450 /* Increment and update queue's write index */ 1451 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 1452 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1453 1454 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1455 1456 out: 1457 spin_unlock_bh(&txq->lock); 1458 free_dup_buf: 1459 if (idx < 0) 1460 kfree(dup_buf); 1461 return idx; 1462} 1463 1464/* 1465 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1466 * @rxb: Rx buffer to reclaim 1467 * @handler_status: return value of the handler of the command 1468 * (put in setup_rx_handlers) 1469 * 1470 * If an Rx buffer has an async callback associated with it the callback 1471 * will be executed. The attached skb (if present) will only be freed 1472 * if the callback returns 1 1473 */ 1474void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1475 struct iwl_rx_cmd_buffer *rxb, int handler_status) 1476{ 1477 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1478 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1479 int txq_id = SEQ_TO_QUEUE(sequence); 1480 int index = SEQ_TO_INDEX(sequence); 1481 int cmd_index; 1482 struct iwl_device_cmd *cmd; 1483 struct iwl_cmd_meta *meta; 1484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1485 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1486 1487 /* If a Tx command is being handled and it isn't in the actual 1488 * command queue then there a command routing bug has been introduced 1489 * in the queue management code. */ 1490 if (WARN(txq_id != trans_pcie->cmd_queue, 1491 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1492 txq_id, trans_pcie->cmd_queue, sequence, 1493 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, 1494 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { 1495 iwl_print_hex_error(trans, pkt, 32); 1496 return; 1497 } 1498 1499 spin_lock_bh(&txq->lock); 1500 1501 cmd_index = get_cmd_index(&txq->q, index); 1502 cmd = txq->entries[cmd_index].cmd; 1503 meta = &txq->entries[cmd_index].meta; 1504 1505 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); 1506 1507 /* Input error checking is done when commands are added to queue. */ 1508 if (meta->flags & CMD_WANT_SKB) { 1509 struct page *p = rxb_steal_page(rxb); 1510 1511 meta->source->resp_pkt = pkt; 1512 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1513 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1514 meta->source->handler_status = handler_status; 1515 } 1516 1517 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1518 1519 if (!(meta->flags & CMD_ASYNC)) { 1520 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1521 IWL_WARN(trans, 1522 "HCMD_ACTIVE already clear for command %s\n", 1523 get_cmd_string(trans_pcie, cmd->hdr.cmd)); 1524 } 1525 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1526 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1527 get_cmd_string(trans_pcie, cmd->hdr.cmd)); 1528 wake_up(&trans_pcie->wait_command_queue); 1529 } 1530 1531 meta->flags = 0; 1532 1533 spin_unlock_bh(&txq->lock); 1534} 1535 1536#define HOST_COMPLETE_TIMEOUT (2 * HZ) 1537 1538static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1539 struct iwl_host_cmd *cmd) 1540{ 1541 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1542 int ret; 1543 1544 /* An asynchronous command can not expect an SKB to be set. */ 1545 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1546 return -EINVAL; 1547 1548 ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1549 if (ret < 0) { 1550 IWL_ERR(trans, 1551 "Error sending %s: enqueue_hcmd failed: %d\n", 1552 get_cmd_string(trans_pcie, cmd->id), ret); 1553 return ret; 1554 } 1555 return 0; 1556} 1557 1558static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1559 struct iwl_host_cmd *cmd) 1560{ 1561 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1562 int cmd_idx; 1563 int ret; 1564 1565 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 1566 get_cmd_string(trans_pcie, cmd->id)); 1567 1568 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1569 &trans->status), 1570 "Command %s: a command is already active!\n", 1571 get_cmd_string(trans_pcie, cmd->id))) 1572 return -EIO; 1573 1574 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 1575 get_cmd_string(trans_pcie, cmd->id)); 1576 1577 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1578 if (cmd_idx < 0) { 1579 ret = cmd_idx; 1580 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1581 IWL_ERR(trans, 1582 "Error sending %s: enqueue_hcmd failed: %d\n", 1583 get_cmd_string(trans_pcie, cmd->id), ret); 1584 return ret; 1585 } 1586 1587 ret = wait_event_timeout(trans_pcie->wait_command_queue, 1588 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1589 &trans->status), 1590 HOST_COMPLETE_TIMEOUT); 1591 if (!ret) { 1592 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1593 struct iwl_queue *q = &txq->q; 1594 1595 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 1596 get_cmd_string(trans_pcie, cmd->id), 1597 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1598 1599 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1600 q->read_ptr, q->write_ptr); 1601 1602 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1603 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1604 get_cmd_string(trans_pcie, cmd->id)); 1605 ret = -ETIMEDOUT; 1606 1607 iwl_force_nmi(trans); 1608 iwl_trans_fw_error(trans); 1609 1610 goto cancel; 1611 } 1612 1613 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1614 IWL_ERR(trans, "FW error in SYNC CMD %s\n", 1615 get_cmd_string(trans_pcie, cmd->id)); 1616 dump_stack(); 1617 ret = -EIO; 1618 goto cancel; 1619 } 1620 1621 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1622 test_bit(STATUS_RFKILL, &trans->status)) { 1623 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1624 ret = -ERFKILL; 1625 goto cancel; 1626 } 1627 1628 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1629 IWL_ERR(trans, "Error: Response NULL in '%s'\n", 1630 get_cmd_string(trans_pcie, cmd->id)); 1631 ret = -EIO; 1632 goto cancel; 1633 } 1634 1635 return 0; 1636 1637cancel: 1638 if (cmd->flags & CMD_WANT_SKB) { 1639 /* 1640 * Cancel the CMD_WANT_SKB flag for the cmd in the 1641 * TX cmd queue. Otherwise in case the cmd comes 1642 * in later, it will possibly set an invalid 1643 * address (cmd->meta.source). 1644 */ 1645 trans_pcie->txq[trans_pcie->cmd_queue]. 1646 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1647 } 1648 1649 if (cmd->resp_pkt) { 1650 iwl_free_resp(cmd); 1651 cmd->resp_pkt = NULL; 1652 } 1653 1654 return ret; 1655} 1656 1657int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1658{ 1659 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1660 test_bit(STATUS_RFKILL, &trans->status)) { 1661 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1662 cmd->id); 1663 return -ERFKILL; 1664 } 1665 1666 if (cmd->flags & CMD_ASYNC) 1667 return iwl_pcie_send_hcmd_async(trans, cmd); 1668 1669 /* We still can fail on RFKILL that can be asserted while we wait */ 1670 return iwl_pcie_send_hcmd_sync(trans, cmd); 1671} 1672 1673int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 1674 struct iwl_device_cmd *dev_cmd, int txq_id) 1675{ 1676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1677 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1678 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 1679 struct iwl_cmd_meta *out_meta; 1680 struct iwl_txq *txq; 1681 struct iwl_queue *q; 1682 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 1683 void *tb1_addr; 1684 u16 len, tb1_len, tb2_len; 1685 bool wait_write_ptr; 1686 __le16 fc = hdr->frame_control; 1687 u8 hdr_len = ieee80211_hdrlen(fc); 1688 u16 wifi_seq; 1689 1690 txq = &trans_pcie->txq[txq_id]; 1691 q = &txq->q; 1692 1693 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 1694 "TX on unused queue %d\n", txq_id)) 1695 return -EINVAL; 1696 1697 spin_lock(&txq->lock); 1698 1699 /* In AGG mode, the index in the ring must correspond to the WiFi 1700 * sequence number. This is a HW requirements to help the SCD to parse 1701 * the BA. 1702 * Check here that the packets are in the right place on the ring. 1703 */ 1704 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 1705 WARN_ONCE(txq->ampdu && 1706 (wifi_seq & 0xff) != q->write_ptr, 1707 "Q: %d WiFi Seq %d tfdNum %d", 1708 txq_id, wifi_seq, q->write_ptr); 1709 1710 /* Set up driver data for this TFD */ 1711 txq->entries[q->write_ptr].skb = skb; 1712 txq->entries[q->write_ptr].cmd = dev_cmd; 1713 1714 dev_cmd->hdr.sequence = 1715 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 1716 INDEX_TO_SEQ(q->write_ptr))); 1717 1718 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); 1719 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 1720 offsetof(struct iwl_tx_cmd, scratch); 1721 1722 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1723 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 1724 1725 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 1726 out_meta = &txq->entries[q->write_ptr].meta; 1727 1728 /* 1729 * The second TB (tb1) points to the remainder of the TX command 1730 * and the 802.11 header - dword aligned size 1731 * (This calculation modifies the TX command, so do it before the 1732 * setup of the first TB) 1733 */ 1734 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 1735 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; 1736 tb1_len = ALIGN(len, 4); 1737 1738 /* Tell NIC about any 2-byte padding after MAC header */ 1739 if (tb1_len != len) 1740 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 1741 1742 /* The first TB points to the scratchbuf data - min_copy bytes */ 1743 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, 1744 IWL_HCMD_SCRATCHBUF_SIZE); 1745 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 1746 IWL_HCMD_SCRATCHBUF_SIZE, true); 1747 1748 /* there must be data left over for TB1 or this code must be changed */ 1749 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); 1750 1751 /* map the data for TB1 */ 1752 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; 1753 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 1754 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 1755 goto out_err; 1756 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 1757 1758 /* 1759 * Set up TFD's third entry to point directly to remainder 1760 * of skb, if any (802.11 null frames have no payload). 1761 */ 1762 tb2_len = skb->len - hdr_len; 1763 if (tb2_len > 0) { 1764 dma_addr_t tb2_phys = dma_map_single(trans->dev, 1765 skb->data + hdr_len, 1766 tb2_len, DMA_TO_DEVICE); 1767 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 1768 iwl_pcie_tfd_unmap(trans, out_meta, 1769 &txq->tfds[q->write_ptr]); 1770 goto out_err; 1771 } 1772 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 1773 } 1774 1775 /* Set up entry for this TFD in Tx byte-count array */ 1776 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); 1777 1778 trace_iwlwifi_dev_tx(trans->dev, skb, 1779 &txq->tfds[txq->q.write_ptr], 1780 sizeof(struct iwl_tfd), 1781 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, 1782 skb->data + hdr_len, tb2_len); 1783 trace_iwlwifi_dev_tx_data(trans->dev, skb, 1784 skb->data + hdr_len, tb2_len); 1785 1786 wait_write_ptr = ieee80211_has_morefrags(fc); 1787 1788 /* start timer if queue currently empty */ 1789 if (txq->need_update && q->read_ptr == q->write_ptr && 1790 trans_pcie->wd_timeout) 1791 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); 1792 1793 /* Tell device the write index *just past* this latest filled TFD */ 1794 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 1795 if (!wait_write_ptr) 1796 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1797 1798 /* 1799 * At this point the frame is "transmitted" successfully 1800 * and we will get a TX status notification eventually. 1801 */ 1802 if (iwl_queue_space(q) < q->high_mark) { 1803 if (wait_write_ptr) 1804 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1805 else 1806 iwl_stop_queue(trans, txq); 1807 } 1808 spin_unlock(&txq->lock); 1809 return 0; 1810out_err: 1811 spin_unlock(&txq->lock); 1812 return -1; 1813} 1814