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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013  Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../core.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "hw.h"
34#include "sw.h"
35#include "trx.h"
36#include "led.h"
37#include "table.h"
38
39#include <linux/vmalloc.h>
40#include <linux/module.h>
41
42static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
43{
44	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
45
46	/*close ASPM for AMD defaultly */
47	rtlpci->const_amdpci_aspm = 0;
48
49	/* ASPM PS mode.
50	 * 0 - Disable ASPM,
51	 * 1 - Enable ASPM without Clock Req,
52	 * 2 - Enable ASPM with Clock Req,
53	 * 3 - Alwyas Enable ASPM with Clock Req,
54	 * 4 - Always Enable ASPM without Clock Req.
55	 * set defult to RTL8192CE:3 RTL8192E:2
56	 */
57	rtlpci->const_pci_aspm = 3;
58
59	/*Setting for PCI-E device */
60	rtlpci->const_devicepci_aspm_setting = 0x03;
61
62	/*Setting for PCI-E bridge */
63	rtlpci->const_hostpci_aspm_setting = 0x02;
64
65	/* In Hw/Sw Radio Off situation.
66	 * 0 - Default,
67	 * 1 - From ASPM setting without low Mac Pwr,
68	 * 2 - From ASPM setting with low Mac Pwr,
69	 * 3 - Bus D3
70	 * set default to RTL8192CE:0 RTL8192SE:2
71	 */
72	rtlpci->const_hwsw_rfoff_d3 = 0;
73
74	/* This setting works for those device with
75	 * backdoor ASPM setting such as EPHY setting.
76	 * 0 - Not support ASPM,
77	 * 1 - Support ASPM,
78	 * 2 - According to chipset.
79	 */
80	rtlpci->const_support_pciaspm = 1;
81}
82
83int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
84{
85	int err = 0;
86	struct rtl_priv *rtlpriv = rtl_priv(hw);
87	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
88	u8 tid;
89
90	rtl8188ee_bt_reg_init(hw);
91	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
92
93	rtlpriv->dm.dm_initialgain_enable = 1;
94	rtlpriv->dm.dm_flag = 0;
95	rtlpriv->dm.disable_framebursting = 0;
96	rtlpriv->dm.thermalvalue = 0;
97	rtlpci->transmit_config = CFENDFORM | BIT(15);
98
99	/* compatible 5G band 88ce just 2.4G band & smsp */
100	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
101	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
102	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
103
104	rtlpci->receive_config = (RCR_APPFCS |
105				  RCR_APP_MIC |
106				  RCR_APP_ICV |
107				  RCR_APP_PHYST_RXFF |
108				  RCR_HTC_LOC_CTRL |
109				  RCR_AMF |
110				  RCR_ACF |
111				  RCR_ADF |
112				  RCR_AICV |
113				  RCR_ACRC32 |
114				  RCR_AB |
115				  RCR_AM |
116				  RCR_APM |
117				  0);
118
119	rtlpci->irq_mask[0] =
120				(u32)(IMR_PSTIMEOUT	|
121				IMR_HSISR_IND_ON_INT	|
122				IMR_C2HCMD		|
123				IMR_HIGHDOK		|
124				IMR_MGNTDOK		|
125				IMR_BKDOK		|
126				IMR_BEDOK		|
127				IMR_VIDOK		|
128				IMR_VODOK		|
129				IMR_RDU			|
130				IMR_ROK			|
131				0);
132	rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
133	rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
134
135	/* for debug level */
136	rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
137	/* for LPS & IPS */
138	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
139	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
140	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
141	if (rtlpriv->cfg->mod_params->disable_watchdog)
142		pr_info("watchdog disabled\n");
143	if (!rtlpriv->psc.inactiveps)
144		pr_info("rtl8188ee: Power Save off (module option)\n");
145	if (!rtlpriv->psc.fwctrl_lps)
146		pr_info("rtl8188ee: FW Power Save off (module option)\n");
147	rtlpriv->psc.reg_fwctrl_lps = 3;
148	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
149	/* for ASPM, you can close aspm through
150	 * set const_support_pciaspm = 0
151	 */
152	rtl88e_init_aspm_vars(hw);
153
154	if (rtlpriv->psc.reg_fwctrl_lps == 1)
155		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
156	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
157		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
158	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
159		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
160
161	/* for firmware buf */
162	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
163	if (!rtlpriv->rtlhal.pfirmware) {
164		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
165			 "Can't alloc buffer for fw.\n");
166		return 1;
167	}
168
169	rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
170	rtlpriv->max_fw_size = 0x8000;
171	pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
172	err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
173				      rtlpriv->io.dev, GFP_KERNEL, hw,
174				      rtl_fw_cb);
175	if (err) {
176		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
177			 "Failed to request firmware!\n");
178		return 1;
179	}
180
181	/* for early mode */
182	rtlpriv->rtlhal.earlymode_enable = false;
183	rtlpriv->rtlhal.max_earlymode_num = 10;
184	for (tid = 0; tid < 8; tid++)
185		skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
186
187	/*low power */
188	rtlpriv->psc.low_power_enable = false;
189	if (rtlpriv->psc.low_power_enable) {
190		init_timer(&rtlpriv->works.fw_clockoff_timer);
191		setup_timer(&rtlpriv->works.fw_clockoff_timer,
192			    rtl88ee_fw_clk_off_timer_callback,
193			    (unsigned long)hw);
194	}
195
196	init_timer(&rtlpriv->works.fast_antenna_training_timer);
197	setup_timer(&rtlpriv->works.fast_antenna_training_timer,
198		    rtl88e_dm_fast_antenna_training_callback,
199			(unsigned long)hw);
200	return err;
201}
202
203void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
204{
205	struct rtl_priv *rtlpriv = rtl_priv(hw);
206
207	if (rtlpriv->rtlhal.pfirmware) {
208		vfree(rtlpriv->rtlhal.pfirmware);
209		rtlpriv->rtlhal.pfirmware = NULL;
210	}
211
212	if (rtlpriv->psc.low_power_enable)
213		del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
214
215	del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
216}
217
218/* get bt coexist status */
219bool rtl88e_get_btc_status(void)
220{
221	return false;
222}
223
224static struct rtl_hal_ops rtl8188ee_hal_ops = {
225	.init_sw_vars = rtl88e_init_sw_vars,
226	.deinit_sw_vars = rtl88e_deinit_sw_vars,
227	.read_eeprom_info = rtl88ee_read_eeprom_info,
228	.interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
229	.hw_init = rtl88ee_hw_init,
230	.hw_disable = rtl88ee_card_disable,
231	.hw_suspend = rtl88ee_suspend,
232	.hw_resume = rtl88ee_resume,
233	.enable_interrupt = rtl88ee_enable_interrupt,
234	.disable_interrupt = rtl88ee_disable_interrupt,
235	.set_network_type = rtl88ee_set_network_type,
236	.set_chk_bssid = rtl88ee_set_check_bssid,
237	.set_qos = rtl88ee_set_qos,
238	.set_bcn_reg = rtl88ee_set_beacon_related_registers,
239	.set_bcn_intv = rtl88ee_set_beacon_interval,
240	.update_interrupt_mask = rtl88ee_update_interrupt_mask,
241	.get_hw_reg = rtl88ee_get_hw_reg,
242	.set_hw_reg = rtl88ee_set_hw_reg,
243	.update_rate_tbl = rtl88ee_update_hal_rate_tbl,
244	.fill_tx_desc = rtl88ee_tx_fill_desc,
245	.fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
246	.query_rx_desc = rtl88ee_rx_query_desc,
247	.set_channel_access = rtl88ee_update_channel_access_setting,
248	.radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
249	.set_bw_mode = rtl88e_phy_set_bw_mode,
250	.switch_channel = rtl88e_phy_sw_chnl,
251	.dm_watchdog = rtl88e_dm_watchdog,
252	.scan_operation_backup = rtl88e_phy_scan_operation_backup,
253	.set_rf_power_state = rtl88e_phy_set_rf_power_state,
254	.led_control = rtl88ee_led_control,
255	.set_desc = rtl88ee_set_desc,
256	.get_desc = rtl88ee_get_desc,
257	.is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
258	.tx_polling = rtl88ee_tx_polling,
259	.enable_hw_sec = rtl88ee_enable_hw_security_config,
260	.set_key = rtl88ee_set_key,
261	.init_sw_leds = rtl88ee_init_sw_leds,
262	.get_bbreg = rtl88e_phy_query_bb_reg,
263	.set_bbreg = rtl88e_phy_set_bb_reg,
264	.get_rfreg = rtl88e_phy_query_rf_reg,
265	.set_rfreg = rtl88e_phy_set_rf_reg,
266	.get_btc_status = rtl88e_get_btc_status,
267	.rx_command_packet = rtl88ee_rx_command_packet,
268
269};
270
271static struct rtl_mod_params rtl88ee_mod_params = {
272	.sw_crypto = false,
273	.inactiveps = false,
274	.swctrl_lps = false,
275	.fwctrl_lps = false,
276	.msi_support = true,
277	.debug = DBG_EMERG,
278};
279
280static struct rtl_hal_cfg rtl88ee_hal_cfg = {
281	.bar_id = 2,
282	.write_readback = true,
283	.name = "rtl88e_pci",
284	.fw_name = "rtlwifi/rtl8188efw.bin",
285	.ops = &rtl8188ee_hal_ops,
286	.mod_params = &rtl88ee_mod_params,
287
288	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
289	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
290	.maps[SYS_CLK] = REG_SYS_CLKR,
291	.maps[MAC_RCR_AM] = AM,
292	.maps[MAC_RCR_AB] = AB,
293	.maps[MAC_RCR_ACRC32] = ACRC32,
294	.maps[MAC_RCR_ACF] = ACF,
295	.maps[MAC_RCR_AAP] = AAP,
296	.maps[MAC_HIMR] = REG_HIMR,
297	.maps[MAC_HIMRE] = REG_HIMRE,
298	.maps[MAC_HSISR] = REG_HSISR,
299
300	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
301
302	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
303	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
304	.maps[EFUSE_CLK] = 0,
305	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
306	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
307	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
308	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
309	.maps[EFUSE_ANA8M] = ANA8M,
310	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
311	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
312	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
313	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
314
315	.maps[RWCAM] = REG_CAMCMD,
316	.maps[WCAMI] = REG_CAMWRITE,
317	.maps[RCAMO] = REG_CAMREAD,
318	.maps[CAMDBG] = REG_CAMDBG,
319	.maps[SECR] = REG_SECCFG,
320	.maps[SEC_CAM_NONE] = CAM_NONE,
321	.maps[SEC_CAM_WEP40] = CAM_WEP40,
322	.maps[SEC_CAM_TKIP] = CAM_TKIP,
323	.maps[SEC_CAM_AES] = CAM_AES,
324	.maps[SEC_CAM_WEP104] = CAM_WEP104,
325
326	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
327	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
328	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
329	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
330	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
331	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
332/*	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
333	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
334	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
335	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
336	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
337	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
338	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
339	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
340/*	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
341/*	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
342
343	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
344	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
345	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
346	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
347	.maps[RTL_IMR_RDU] = IMR_RDU,
348	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
349	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
350	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
351	.maps[RTL_IMR_TBDER] = IMR_TBDER,
352	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
353	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
354	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
355	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
356	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
357	.maps[RTL_IMR_VODOK] = IMR_VODOK,
358	.maps[RTL_IMR_ROK] = IMR_ROK,
359	.maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
360	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
361
362	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
363	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
364	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
365	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
366	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
367	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
368	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
369	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
370	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
371	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
372	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
373	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
374
375	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
376	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
377};
378
379static struct pci_device_id rtl88ee_pci_ids[] = {
380	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
381	{},
382};
383
384MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
385
386MODULE_AUTHOR("zhiyuan_yang	<zhiyuan_yang@realsil.com.cn>");
387MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
388MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
389MODULE_LICENSE("GPL");
390MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
391MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
392
393module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
394module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
395module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
396module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
397module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
398module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
399module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
400		   bool, 0444);
401MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
402MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
403MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
404MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
405MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
406MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
407MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
408
409static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
410
411static struct pci_driver rtl88ee_driver = {
412	.name = KBUILD_MODNAME,
413	.id_table = rtl88ee_pci_ids,
414	.probe = rtl_pci_probe,
415	.remove = rtl_pci_disconnect,
416	.driver.pm = &rtlwifi_pm_ops,
417};
418
419module_pci_driver(rtl88ee_driver);
420