1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../pci.h" 32#include "../ps.h" 33#include "../core.h" 34#include "reg.h" 35#include "def.h" 36#include "phy.h" 37#include "rf.h" 38#include "dm.h" 39#include "table.h" 40#include "sw.h" 41#include "hw.h" 42 43#define MAX_RF_IMR_INDEX 12 44#define MAX_RF_IMR_INDEX_NORMAL 13 45#define RF_REG_NUM_FOR_C_CUT_5G 6 46#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 47#define RF_REG_NUM_FOR_C_CUT_2G 5 48#define RF_CHNL_NUM_5G 19 49#define RF_CHNL_NUM_5G_40M 17 50#define TARGET_CHNL_NUM_5G 221 51#define TARGET_CHNL_NUM_2G 14 52#define CV_CURVE_CNT 64 53 54static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { 55 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 56}; 57 58static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { 59 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 60}; 61 62static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 63 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 64}; 65 66static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 67 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E 68}; 69 70static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 71 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), 72 BIT(10) | BIT(9), 73 BIT(18) | BIT(17) | BIT(16) | BIT(1), 74 BIT(2) | BIT(1), 75 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) 76}; 77 78static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { 79 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 80 112, 116, 120, 124, 128, 132, 136, 140 81}; 82 83static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { 84 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, 85 118, 122, 126, 130, 134, 138 86}; 87static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { 88 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, 89 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, 90 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, 91 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, 92 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} 93}; 94 95static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { 96 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, 97 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, 98 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} 99}; 100 101static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; 102 103static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 104 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, 105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, 106 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} 107}; 108 109/* [mode][patha+b][reg] */ 110static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = { 111 { 112 /* channel 1-14. */ 113 { 114 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, 115 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff 116 }, 117 /* path 36-64 */ 118 { 119 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 120 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, 121 0x32c9a 122 }, 123 /* 100 -165 */ 124 { 125 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 126 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a 127 } 128 } 129}; 130 131static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0}; 132 133static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0}; 134 135static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { 136 25141, 25116, 25091, 25066, 25041, 137 25016, 24991, 24966, 24941, 24917, 138 24892, 24867, 24843, 24818, 24794, 139 24770, 24765, 24721, 24697, 24672, 140 24648, 24624, 24600, 24576, 24552, 141 24528, 24504, 24480, 24457, 24433, 142 24409, 24385, 24362, 24338, 24315, 143 24291, 24268, 24245, 24221, 24198, 144 24175, 24151, 24128, 24105, 24082, 145 24059, 24036, 24013, 23990, 23967, 146 23945, 23922, 23899, 23876, 23854, 147 23831, 23809, 23786, 23764, 23741, 148 23719, 23697, 23674, 23652, 23630, 149 23608, 23586, 23564, 23541, 23519, 150 23498, 23476, 23454, 23432, 23410, 151 23388, 23367, 23345, 23323, 23302, 152 23280, 23259, 23237, 23216, 23194, 153 23173, 23152, 23130, 23109, 23088, 154 23067, 23046, 23025, 23003, 22982, 155 22962, 22941, 22920, 22899, 22878, 156 22857, 22837, 22816, 22795, 22775, 157 22754, 22733, 22713, 22692, 22672, 158 22652, 22631, 22611, 22591, 22570, 159 22550, 22530, 22510, 22490, 22469, 160 22449, 22429, 22409, 22390, 22370, 161 22350, 22336, 22310, 22290, 22271, 162 22251, 22231, 22212, 22192, 22173, 163 22153, 22134, 22114, 22095, 22075, 164 22056, 22037, 22017, 21998, 21979, 165 21960, 21941, 21921, 21902, 21883, 166 21864, 21845, 21826, 21807, 21789, 167 21770, 21751, 21732, 21713, 21695, 168 21676, 21657, 21639, 21620, 21602, 169 21583, 21565, 21546, 21528, 21509, 170 21491, 21473, 21454, 21436, 21418, 171 21400, 21381, 21363, 21345, 21327, 172 21309, 21291, 21273, 21255, 21237, 173 21219, 21201, 21183, 21166, 21148, 174 21130, 21112, 21095, 21077, 21059, 175 21042, 21024, 21007, 20989, 20972, 176 25679, 25653, 25627, 25601, 25575, 177 25549, 25523, 25497, 25471, 25446, 178 25420, 25394, 25369, 25343, 25318, 179 25292, 25267, 25242, 25216, 25191, 180 25166 181}; 182 183/* channel 1~14 */ 184static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { 185 26084, 26030, 25976, 25923, 25869, 25816, 25764, 186 25711, 25658, 25606, 25554, 25502, 25451, 25328 187}; 188 189static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask) 190{ 191 u32 i; 192 193 for (i = 0; i <= 31; i++) { 194 if (((bitmask >> i) & 0x1) == 1) 195 break; 196 } 197 198 return i; 199} 200 201u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 202{ 203 struct rtl_priv *rtlpriv = rtl_priv(hw); 204 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 205 u32 returnvalue, originalvalue, bitshift; 206 207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 208 regaddr, bitmask); 209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) { 210 u8 dbi_direct = 0; 211 212 /* mac1 use phy0 read radio_b. */ 213 /* mac0 use phy1 read radio_b. */ 214 if (rtlhal->during_mac1init_radioa) 215 dbi_direct = BIT(3); 216 else if (rtlhal->during_mac0init_radiob) 217 dbi_direct = BIT(3) | BIT(2); 218 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, 219 dbi_direct); 220 } else { 221 originalvalue = rtl_read_dword(rtlpriv, regaddr); 222 } 223 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 224 returnvalue = (originalvalue & bitmask) >> bitshift; 225 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 226 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 227 bitmask, regaddr, originalvalue); 228 return returnvalue; 229} 230 231void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, 232 u32 regaddr, u32 bitmask, u32 data) 233{ 234 struct rtl_priv *rtlpriv = rtl_priv(hw); 235 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 236 u8 dbi_direct = 0; 237 u32 originalvalue, bitshift; 238 239 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 240 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 241 regaddr, bitmask, data); 242 if (rtlhal->during_mac1init_radioa) 243 dbi_direct = BIT(3); 244 else if (rtlhal->during_mac0init_radiob) 245 /* mac0 use phy1 write radio_b. */ 246 dbi_direct = BIT(3) | BIT(2); 247 if (bitmask != MASKDWORD) { 248 if (rtlhal->during_mac1init_radioa || 249 rtlhal->during_mac0init_radiob) 250 originalvalue = rtl92de_read_dword_dbi(hw, 251 (u16) regaddr, 252 dbi_direct); 253 else 254 originalvalue = rtl_read_dword(rtlpriv, regaddr); 255 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 256 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 257 } 258 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) 259 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); 260 else 261 rtl_write_dword(rtlpriv, regaddr, data); 262 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 263 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 264 regaddr, bitmask, data); 265} 266 267static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, 268 enum radio_path rfpath, u32 offset) 269{ 270 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 struct rtl_phy *rtlphy = &(rtlpriv->phy); 273 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 274 u32 newoffset; 275 u32 tmplong, tmplong2; 276 u8 rfpi_enable = 0; 277 u32 retvalue; 278 279 newoffset = offset; 280 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 281 if (rfpath == RF90_PATH_A) 282 tmplong2 = tmplong; 283 else 284 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 285 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 286 (newoffset << 23) | BLSSIREADEDGE; 287 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 288 tmplong & (~BLSSIREADEDGE)); 289 udelay(10); 290 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 291 udelay(50); 292 udelay(50); 293 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 294 tmplong | BLSSIREADEDGE); 295 udelay(10); 296 if (rfpath == RF90_PATH_A) 297 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 298 BIT(8)); 299 else if (rfpath == RF90_PATH_B) 300 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 301 BIT(8)); 302 if (rfpi_enable) 303 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 304 BLSSIREADBACKDATA); 305 else 306 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 307 BLSSIREADBACKDATA); 308 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", 309 rfpath, pphyreg->rf_rb, retvalue); 310 return retvalue; 311} 312 313static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, 314 enum radio_path rfpath, 315 u32 offset, u32 data) 316{ 317 u32 data_and_addr; 318 u32 newoffset; 319 struct rtl_priv *rtlpriv = rtl_priv(hw); 320 struct rtl_phy *rtlphy = &(rtlpriv->phy); 321 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 322 323 newoffset = offset; 324 /* T65 RF */ 325 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 326 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 327 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 328 rfpath, pphyreg->rf3wire_offset, data_and_addr); 329} 330 331u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, 332 enum radio_path rfpath, u32 regaddr, u32 bitmask) 333{ 334 struct rtl_priv *rtlpriv = rtl_priv(hw); 335 u32 original_value, readback_value, bitshift; 336 unsigned long flags; 337 338 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 339 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 340 regaddr, rfpath, bitmask); 341 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 342 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); 343 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 344 readback_value = (original_value & bitmask) >> bitshift; 345 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 346 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 347 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 348 regaddr, rfpath, bitmask, original_value); 349 return readback_value; 350} 351 352void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 353 u32 regaddr, u32 bitmask, u32 data) 354{ 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 struct rtl_phy *rtlphy = &(rtlpriv->phy); 357 u32 original_value, bitshift; 358 unsigned long flags; 359 360 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 361 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 362 regaddr, bitmask, data, rfpath); 363 if (bitmask == 0) 364 return; 365 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 366 if (rtlphy->rf_mode != RF_OP_BY_FW) { 367 if (bitmask != RFREG_OFFSET_MASK) { 368 original_value = _rtl92d_phy_rf_serial_read(hw, 369 rfpath, regaddr); 370 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 371 data = ((original_value & (~bitmask)) | 372 (data << bitshift)); 373 } 374 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); 375 } 376 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 377 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 378 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 379 regaddr, bitmask, data, rfpath); 380} 381 382bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) 383{ 384 struct rtl_priv *rtlpriv = rtl_priv(hw); 385 u32 i; 386 u32 arraylength; 387 u32 *ptrarray; 388 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 390 arraylength = MAC_2T_ARRAYLENGTH; 391 ptrarray = rtl8192de_mac_2tarray; 392 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n"); 393 for (i = 0; i < arraylength; i = i + 2) 394 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 395 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 396 /* improve 2-stream TX EVM */ 397 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ 398 /* AMPDU aggregation number 9 */ 399 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ 400 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); 401 } else { 402 /* 92D need to test to decide the num. */ 403 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); 404 } 405 return true; 406} 407 408static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 409{ 410 struct rtl_priv *rtlpriv = rtl_priv(hw); 411 struct rtl_phy *rtlphy = &(rtlpriv->phy); 412 413 /* RF Interface Sowrtware Control */ 414 /* 16 LSBs if read 32-bit from 0x870 */ 415 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 416 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 417 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 418 /* 16 LSBs if read 32-bit from 0x874 */ 419 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 420 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 421 422 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 423 /* RF Interface Readback Value */ 424 /* 16 LSBs if read 32-bit from 0x8E0 */ 425 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 426 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 427 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 428 /* 16 LSBs if read 32-bit from 0x8E4 */ 429 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 430 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 431 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 432 433 /* RF Interface Output (and Enable) */ 434 /* 16 LSBs if read 32-bit from 0x860 */ 435 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 436 /* 16 LSBs if read 32-bit from 0x864 */ 437 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 438 439 /* RF Interface (Output and) Enable */ 440 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 441 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 442 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 443 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 444 445 /* Addr of LSSI. Wirte RF register by driver */ 446 /* LSSI Parameter */ 447 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 448 RFPGA0_XA_LSSIPARAMETER; 449 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 450 RFPGA0_XB_LSSIPARAMETER; 451 452 /* RF parameter */ 453 /* BB Band Select */ 454 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 455 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 456 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 457 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 458 459 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 460 /* Tx gain stage */ 461 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 462 /* Tx gain stage */ 463 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 464 /* Tx gain stage */ 465 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 466 /* Tx gain stage */ 467 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 468 469 /* Tranceiver A~D HSSI Parameter-1 */ 470 /* wire control parameter1 */ 471 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 472 /* wire control parameter1 */ 473 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 474 475 /* Tranceiver A~D HSSI Parameter-2 */ 476 /* wire control parameter2 */ 477 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 478 /* wire control parameter2 */ 479 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 480 481 /* RF switch Control */ 482 /* TR/Ant switch control */ 483 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 484 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 485 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 486 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 487 488 /* AGC control 1 */ 489 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 490 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 491 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 492 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 493 494 /* AGC control 2 */ 495 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 496 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 497 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 498 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 499 500 /* RX AFE control 1 */ 501 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 503 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 504 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 505 506 /*RX AFE control 1 */ 507 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 508 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 509 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 510 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 511 512 /* Tx AFE control 1 */ 513 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE; 514 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE; 515 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE; 516 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE; 517 518 /* Tx AFE control 2 */ 519 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE; 520 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE; 521 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE; 522 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE; 523 524 /* Tranceiver LSSI Readback SI mode */ 525 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 526 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 527 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 528 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 529 530 /* Tranceiver LSSI Readback PI mode */ 531 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 532 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 533} 534 535static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 536 u8 configtype) 537{ 538 int i; 539 u32 *phy_regarray_table; 540 u32 *agctab_array_table = NULL; 541 u32 *agctab_5garray_table; 542 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; 543 struct rtl_priv *rtlpriv = rtl_priv(hw); 544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 545 546 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */ 547 if (rtlhal->interfaceindex == 0) { 548 agctab_arraylen = AGCTAB_ARRAYLENGTH; 549 agctab_array_table = rtl8192de_agctab_array; 550 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 551 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); 552 } else { 553 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 554 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; 555 agctab_array_table = rtl8192de_agctab_2garray; 556 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 557 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); 558 } else { 559 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH; 560 agctab_5garray_table = rtl8192de_agctab_5garray; 561 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 562 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); 563 564 } 565 } 566 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; 567 phy_regarray_table = rtl8192de_phy_reg_2tarray; 568 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 569 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 570 if (configtype == BASEBAND_CONFIG_PHY_REG) { 571 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 572 rtl_addr_delay(phy_regarray_table[i]); 573 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 574 phy_regarray_table[i + 1]); 575 udelay(1); 576 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 577 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 578 phy_regarray_table[i], 579 phy_regarray_table[i + 1]); 580 } 581 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 582 if (rtlhal->interfaceindex == 0) { 583 for (i = 0; i < agctab_arraylen; i = i + 2) { 584 rtl_set_bbreg(hw, agctab_array_table[i], 585 MASKDWORD, 586 agctab_array_table[i + 1]); 587 /* Add 1us delay between BB/RF register 588 * setting. */ 589 udelay(1); 590 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 591 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n", 592 agctab_array_table[i], 593 agctab_array_table[i + 1]); 594 } 595 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 596 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n"); 597 } else { 598 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 599 for (i = 0; i < agctab_arraylen; i = i + 2) { 600 rtl_set_bbreg(hw, agctab_array_table[i], 601 MASKDWORD, 602 agctab_array_table[i + 1]); 603 /* Add 1us delay between BB/RF register 604 * setting. */ 605 udelay(1); 606 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 607 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n", 608 agctab_array_table[i], 609 agctab_array_table[i + 1]); 610 } 611 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 612 "Load Rtl819XAGCTAB_2GArray\n"); 613 } else { 614 for (i = 0; i < agctab_5garraylen; i = i + 2) { 615 rtl_set_bbreg(hw, 616 agctab_5garray_table[i], 617 MASKDWORD, 618 agctab_5garray_table[i + 1]); 619 /* Add 1us delay between BB/RF registeri 620 * setting. */ 621 udelay(1); 622 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 623 "The Rtl819XAGCTAB_5GArray_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n", 624 agctab_5garray_table[i], 625 agctab_5garray_table[i + 1]); 626 } 627 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 628 "Load Rtl819XAGCTAB_5GArray\n"); 629 } 630 } 631 } 632 return true; 633} 634 635static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 636 u32 regaddr, u32 bitmask, 637 u32 data) 638{ 639 struct rtl_priv *rtlpriv = rtl_priv(hw); 640 struct rtl_phy *rtlphy = &(rtlpriv->phy); 641 int index; 642 643 if (regaddr == RTXAGC_A_RATE18_06) 644 index = 0; 645 else if (regaddr == RTXAGC_A_RATE54_24) 646 index = 1; 647 else if (regaddr == RTXAGC_A_CCK1_MCS32) 648 index = 6; 649 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) 650 index = 7; 651 else if (regaddr == RTXAGC_A_MCS03_MCS00) 652 index = 2; 653 else if (regaddr == RTXAGC_A_MCS07_MCS04) 654 index = 3; 655 else if (regaddr == RTXAGC_A_MCS11_MCS08) 656 index = 4; 657 else if (regaddr == RTXAGC_A_MCS15_MCS12) 658 index = 5; 659 else if (regaddr == RTXAGC_B_RATE18_06) 660 index = 8; 661 else if (regaddr == RTXAGC_B_RATE54_24) 662 index = 9; 663 else if (regaddr == RTXAGC_B_CCK1_55_MCS32) 664 index = 14; 665 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) 666 index = 15; 667 else if (regaddr == RTXAGC_B_MCS03_MCS00) 668 index = 10; 669 else if (regaddr == RTXAGC_B_MCS07_MCS04) 670 index = 11; 671 else if (regaddr == RTXAGC_B_MCS11_MCS08) 672 index = 12; 673 else if (regaddr == RTXAGC_B_MCS15_MCS12) 674 index = 13; 675 else 676 return; 677 678 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 679 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 680 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 681 rtlphy->pwrgroup_cnt, index, 682 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); 683 if (index == 13) 684 rtlphy->pwrgroup_cnt++; 685} 686 687static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 688 u8 configtype) 689{ 690 struct rtl_priv *rtlpriv = rtl_priv(hw); 691 int i; 692 u32 *phy_regarray_table_pg; 693 u16 phy_regarray_pg_len; 694 695 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; 696 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 697 if (configtype == BASEBAND_CONFIG_PHY_REG) { 698 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 699 rtl_addr_delay(phy_regarray_table_pg[i]); 700 _rtl92d_store_pwrindex_diffrate_offset(hw, 701 phy_regarray_table_pg[i], 702 phy_regarray_table_pg[i + 1], 703 phy_regarray_table_pg[i + 2]); 704 } 705 } else { 706 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 707 "configtype != BaseBand_Config_PHY_REG\n"); 708 } 709 return true; 710} 711 712static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) 713{ 714 struct rtl_priv *rtlpriv = rtl_priv(hw); 715 struct rtl_phy *rtlphy = &(rtlpriv->phy); 716 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 717 bool rtstatus = true; 718 719 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 720 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 721 BASEBAND_CONFIG_PHY_REG); 722 if (!rtstatus) { 723 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n"); 724 return false; 725 } 726 727 /* if (rtlphy->rf_type == RF_1T2R) { 728 * _rtl92c_phy_bb_config_1t(hw); 729 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 730 *} */ 731 732 if (rtlefuse->autoload_failflag == false) { 733 rtlphy->pwrgroup_cnt = 0; 734 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, 735 BASEBAND_CONFIG_PHY_REG); 736 } 737 if (!rtstatus) { 738 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n"); 739 return false; 740 } 741 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 742 BASEBAND_CONFIG_AGC_TAB); 743 if (!rtstatus) { 744 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 745 return false; 746 } 747 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 748 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 749 750 return true; 751} 752 753bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) 754{ 755 struct rtl_priv *rtlpriv = rtl_priv(hw); 756 u16 regval; 757 u32 regvaldw; 758 u8 value; 759 760 _rtl92d_phy_init_bb_rf_register_definition(hw); 761 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 762 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 763 regval | BIT(13) | BIT(0) | BIT(1)); 764 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 765 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 766 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ 767 value = rtl_read_byte(rtlpriv, REG_RF_CTRL); 768 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | 769 RF_SDMRSTB); 770 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | 771 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB); 772 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 773 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) { 774 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 775 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 776 } 777 778 return _rtl92d_phy_bb_config(hw); 779} 780 781bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) 782{ 783 return rtl92d_phy_rf6052_config(hw); 784} 785 786bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 787 enum rf_content content, 788 enum radio_path rfpath) 789{ 790 int i; 791 u32 *radioa_array_table; 792 u32 *radiob_array_table; 793 u16 radioa_arraylen, radiob_arraylen; 794 struct rtl_priv *rtlpriv = rtl_priv(hw); 795 796 radioa_arraylen = RADIOA_2T_ARRAYLENGTH; 797 radioa_array_table = rtl8192de_radioa_2tarray; 798 radiob_arraylen = RADIOB_2T_ARRAYLENGTH; 799 radiob_array_table = rtl8192de_radiob_2tarray; 800 if (rtlpriv->efuse.internal_pa_5g[0]) { 801 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; 802 radioa_array_table = rtl8192de_radioa_2t_int_paarray; 803 } 804 if (rtlpriv->efuse.internal_pa_5g[1]) { 805 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; 806 radiob_array_table = rtl8192de_radiob_2t_int_paarray; 807 } 808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 809 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); 810 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 811 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); 812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 813 814 /* this only happens when DMDP, mac0 start on 2.4G, 815 * mac1 start on 5G, mac 0 has to set phy0&phy1 816 * pathA or mac1 has to set phy0&phy1 pathA */ 817 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) { 818 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 819 " ===> althougth Path A, we load radiob.txt\n"); 820 radioa_arraylen = radiob_arraylen; 821 radioa_array_table = radiob_array_table; 822 } 823 switch (rfpath) { 824 case RF90_PATH_A: 825 for (i = 0; i < radioa_arraylen; i = i + 2) { 826 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 827 RFREG_OFFSET_MASK, 828 radioa_array_table[i + 1]); 829 } 830 break; 831 case RF90_PATH_B: 832 for (i = 0; i < radiob_arraylen; i = i + 2) { 833 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 834 RFREG_OFFSET_MASK, 835 radiob_array_table[i + 1]); 836 } 837 break; 838 case RF90_PATH_C: 839 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 840 "switch case not processed\n"); 841 break; 842 case RF90_PATH_D: 843 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 844 "switch case not processed\n"); 845 break; 846 } 847 return true; 848} 849 850void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 851{ 852 struct rtl_priv *rtlpriv = rtl_priv(hw); 853 struct rtl_phy *rtlphy = &(rtlpriv->phy); 854 855 rtlphy->default_initialgain[0] = 856 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 857 rtlphy->default_initialgain[1] = 858 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 859 rtlphy->default_initialgain[2] = 860 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 861 rtlphy->default_initialgain[3] = 862 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 863 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 864 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 865 rtlphy->default_initialgain[0], 866 rtlphy->default_initialgain[1], 867 rtlphy->default_initialgain[2], 868 rtlphy->default_initialgain[3]); 869 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 870 MASKBYTE0); 871 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 872 MASKDWORD); 873 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 874 "Default framesync (0x%x) = 0x%x\n", 875 ROFDM0_RXDETECTOR3, rtlphy->framesync); 876} 877 878static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 879 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 880{ 881 struct rtl_priv *rtlpriv = rtl_priv(hw); 882 struct rtl_phy *rtlphy = &(rtlpriv->phy); 883 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 884 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 885 u8 index = (channel - 1); 886 887 /* 1. CCK */ 888 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 889 /* RF-A */ 890 cckpowerlevel[RF90_PATH_A] = 891 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 892 /* RF-B */ 893 cckpowerlevel[RF90_PATH_B] = 894 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 895 } else { 896 cckpowerlevel[RF90_PATH_A] = 0; 897 cckpowerlevel[RF90_PATH_B] = 0; 898 } 899 /* 2. OFDM for 1S or 2S */ 900 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 901 /* Read HT 40 OFDM TX power */ 902 ofdmpowerlevel[RF90_PATH_A] = 903 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 904 ofdmpowerlevel[RF90_PATH_B] = 905 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 906 } else if (rtlphy->rf_type == RF_2T2R) { 907 /* Read HT 40 OFDM TX power */ 908 ofdmpowerlevel[RF90_PATH_A] = 909 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; 910 ofdmpowerlevel[RF90_PATH_B] = 911 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; 912 } 913} 914 915static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, 916 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 917{ 918 struct rtl_priv *rtlpriv = rtl_priv(hw); 919 struct rtl_phy *rtlphy = &(rtlpriv->phy); 920 921 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 922 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 923} 924 925static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) 926{ 927 u8 channel_5g[59] = { 928 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 929 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 930 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 931 114, 116, 118, 120, 122, 124, 126, 128, 932 130, 132, 134, 136, 138, 140, 149, 151, 933 153, 155, 157, 159, 161, 163, 165 934 }; 935 u8 place = chnl; 936 937 if (chnl > 14) { 938 for (place = 14; place < sizeof(channel_5g); place++) { 939 if (channel_5g[place] == chnl) { 940 place++; 941 break; 942 } 943 } 944 } 945 return place; 946} 947 948void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 949{ 950 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 951 struct rtl_priv *rtlpriv = rtl_priv(hw); 952 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 953 954 if (!rtlefuse->txpwr_fromeprom) 955 return; 956 channel = _rtl92c_phy_get_rightchnlplace(channel); 957 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], 958 &ofdmpowerlevel[0]); 959 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 960 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], 961 &ofdmpowerlevel[0]); 962 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 963 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 964 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); 965} 966 967void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, 968 enum nl80211_channel_type ch_type) 969{ 970 struct rtl_priv *rtlpriv = rtl_priv(hw); 971 struct rtl_phy *rtlphy = &(rtlpriv->phy); 972 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 973 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 974 unsigned long flag = 0; 975 u8 reg_prsr_rsc; 976 u8 reg_bw_opmode; 977 978 if (rtlphy->set_bwmode_inprogress) 979 return; 980 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 981 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 982 "FALSE driver sleep or unload\n"); 983 return; 984 } 985 rtlphy->set_bwmode_inprogress = true; 986 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 987 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 988 "20MHz" : "40MHz"); 989 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 990 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 991 switch (rtlphy->current_chan_bw) { 992 case HT_CHANNEL_WIDTH_20: 993 reg_bw_opmode |= BW_OPMODE_20MHZ; 994 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 995 break; 996 case HT_CHANNEL_WIDTH_20_40: 997 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 998 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 999 1000 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 1001 (mac->cur_40_prime_sc << 5); 1002 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 1003 break; 1004 default: 1005 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1006 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1007 break; 1008 } 1009 switch (rtlphy->current_chan_bw) { 1010 case HT_CHANNEL_WIDTH_20: 1011 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1012 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1013 /* SET BIT10 BIT11 for receive cck */ 1014 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1015 BIT(11), 3); 1016 break; 1017 case HT_CHANNEL_WIDTH_20_40: 1018 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1019 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1020 /* Set Control channel to upper or lower. 1021 * These settings are required only for 40MHz */ 1022 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1023 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1024 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, 1025 (mac->cur_40_prime_sc >> 1)); 1026 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1027 } 1028 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1029 /* SET BIT10 BIT11 for receive cck */ 1030 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1031 BIT(11), 0); 1032 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1033 (mac->cur_40_prime_sc == 1034 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1035 break; 1036 default: 1037 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1038 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1039 break; 1040 1041 } 1042 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1043 rtlphy->set_bwmode_inprogress = false; 1044 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 1045} 1046 1047static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) 1048{ 1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 1050 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 1051 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); 1052 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 1053} 1054 1055static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 1056{ 1057 struct rtl_priv *rtlpriv = rtl_priv(hw); 1058 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1059 u8 value8; 1060 1061 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 1062 rtlhal->bandset = band; 1063 rtlhal->current_bandtype = band; 1064 if (IS_92D_SINGLEPHY(rtlhal->version)) 1065 rtlhal->bandset = BAND_ON_BOTH; 1066 /* stop RX/Tx */ 1067 _rtl92d_phy_stop_trx_before_changeband(hw); 1068 /* reconfig BB/RF according to wireless mode */ 1069 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1070 /* BB & RF Config */ 1071 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); 1072 if (rtlhal->interfaceindex == 1) 1073 _rtl92d_phy_config_bb_with_headerfile(hw, 1074 BASEBAND_CONFIG_AGC_TAB); 1075 } else { 1076 /* 5G band */ 1077 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); 1078 if (rtlhal->interfaceindex == 1) 1079 _rtl92d_phy_config_bb_with_headerfile(hw, 1080 BASEBAND_CONFIG_AGC_TAB); 1081 } 1082 rtl92d_update_bbrf_configuration(hw); 1083 if (rtlhal->current_bandtype == BAND_ON_2_4G) 1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1085 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1086 1087 /* 20M BW. */ 1088 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ 1089 rtlhal->reloadtxpowerindex = true; 1090 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 1091 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1092 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1093 0 ? REG_MAC0 : REG_MAC1)); 1094 value8 |= BIT(1); 1095 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1096 0 ? REG_MAC0 : REG_MAC1), value8); 1097 } else { 1098 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1099 0 ? REG_MAC0 : REG_MAC1)); 1100 value8 &= (~BIT(1)); 1101 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1102 0 ? REG_MAC0 : REG_MAC1), value8); 1103 } 1104 mdelay(1); 1105 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); 1106} 1107 1108static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, 1109 u8 channel, u8 rfpath) 1110{ 1111 struct rtl_priv *rtlpriv = rtl_priv(hw); 1112 u32 imr_num = MAX_RF_IMR_INDEX; 1113 u32 rfmask = RFREG_OFFSET_MASK; 1114 u8 group, i; 1115 unsigned long flag = 0; 1116 1117 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); 1118 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 1119 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1120 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1121 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1122 /* fc area 0xd2c */ 1123 if (channel > 99) 1124 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1125 BIT(14), 2); 1126 else 1127 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1128 BIT(14), 1); 1129 /* leave 0 for channel1-14. */ 1130 group = channel <= 64 ? 1 : 2; 1131 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1132 for (i = 0; i < imr_num; i++) 1133 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1134 rf_reg_for_5g_swchnl_normal[i], rfmask, 1135 rf_imr_param_normal[0][group][i]); 1136 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 1137 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); 1138 } else { 1139 /* G band. */ 1140 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1141 "Load RF IMR parameters for G band. IMR already setting %d\n", 1142 rtlpriv->rtlhal.load_imrandiqk_setting_for2g); 1143 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1144 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { 1145 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1146 "Load RF IMR parameters for G band. %d\n", 1147 rfpath); 1148 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1149 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1150 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1151 0x00f00000, 0xf); 1152 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1153 for (i = 0; i < imr_num; i++) { 1154 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1155 rf_reg_for_5g_swchnl_normal[i], 1156 RFREG_OFFSET_MASK, 1157 rf_imr_param_normal[0][0][i]); 1158 } 1159 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1160 0x00f00000, 0); 1161 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); 1162 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1163 } 1164 } 1165 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1166} 1167 1168static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, 1169 u8 rfpath, u32 *pu4_regval) 1170{ 1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1173 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1174 1175 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); 1176 /*----Store original RFENV control type----*/ 1177 switch (rfpath) { 1178 case RF90_PATH_A: 1179 case RF90_PATH_C: 1180 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); 1181 break; 1182 case RF90_PATH_B: 1183 case RF90_PATH_D: 1184 *pu4_regval = 1185 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); 1186 break; 1187 } 1188 /*----Set RF_ENV enable----*/ 1189 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); 1190 udelay(1); 1191 /*----Set RF_ENV output high----*/ 1192 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); 1193 udelay(1); 1194 /* Set bit number of Address and Data for RF register */ 1195 /* Set 1 to 4 bits for 8255 */ 1196 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); 1197 udelay(1); 1198 /*Set 0 to 12 bits for 8255 */ 1199 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); 1200 udelay(1); 1201 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); 1202} 1203 1204static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, 1205 u32 *pu4_regval) 1206{ 1207 struct rtl_priv *rtlpriv = rtl_priv(hw); 1208 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1209 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1210 1211 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); 1212 /*----Restore RFENV control type----*/ 1213 switch (rfpath) { 1214 case RF90_PATH_A: 1215 case RF90_PATH_C: 1216 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); 1217 break; 1218 case RF90_PATH_B: 1219 case RF90_PATH_D: 1220 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, 1221 *pu4_regval); 1222 break; 1223 } 1224 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); 1225} 1226 1227static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) 1228{ 1229 struct rtl_priv *rtlpriv = rtl_priv(hw); 1230 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1231 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1232 u8 path = rtlhal->current_bandtype == 1233 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B; 1234 u8 index = 0, i = 0, rfpath = RF90_PATH_A; 1235 bool need_pwr_down = false, internal_pa = false; 1236 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; 1237 1238 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); 1239 /* config path A for 5G */ 1240 if (rtlhal->current_bandtype == BAND_ON_5G) { 1241 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1242 u4tmp = curveindex_5g[channel - 1]; 1243 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1244 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 1245 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 1246 if (channel == rf_chnl_5g[i] && channel <= 140) 1247 index = 0; 1248 } 1249 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { 1250 if (channel == rf_chnl_5g_40m[i] && channel <= 140) 1251 index = 1; 1252 } 1253 if (channel == 149 || channel == 155 || channel == 161) 1254 index = 2; 1255 else if (channel == 151 || channel == 153 || channel == 163 1256 || channel == 165) 1257 index = 3; 1258 else if (channel == 157 || channel == 159) 1259 index = 4; 1260 1261 if (rtlhal->macphymode == DUALMAC_DUALPHY 1262 && rtlhal->interfaceindex == 1) { 1263 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); 1264 rtlhal->during_mac1init_radioa = true; 1265 /* asume no this case */ 1266 if (need_pwr_down) 1267 _rtl92d_phy_enable_rf_env(hw, path, 1268 &u4regvalue); 1269 } 1270 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { 1271 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 1272 rtl_set_rfreg(hw, (enum radio_path)path, 1273 rf_reg_for_c_cut_5g[i], 1274 RFREG_OFFSET_MASK, 0xE439D); 1275 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 1276 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 1277 0x7FF) | (u4tmp << 11); 1278 if (channel == 36) 1279 u4tmp2 &= ~(BIT(7) | BIT(6)); 1280 rtl_set_rfreg(hw, (enum radio_path)path, 1281 rf_reg_for_c_cut_5g[i], 1282 RFREG_OFFSET_MASK, u4tmp2); 1283 } else { 1284 rtl_set_rfreg(hw, (enum radio_path)path, 1285 rf_reg_for_c_cut_5g[i], 1286 RFREG_OFFSET_MASK, 1287 rf_reg_pram_c_5g[index][i]); 1288 } 1289 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1290 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", 1291 rf_reg_for_c_cut_5g[i], 1292 rf_reg_pram_c_5g[index][i], 1293 path, index, 1294 rtl_get_rfreg(hw, (enum radio_path)path, 1295 rf_reg_for_c_cut_5g[i], 1296 RFREG_OFFSET_MASK)); 1297 } 1298 if (need_pwr_down) 1299 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1300 if (rtlhal->during_mac1init_radioa) 1301 rtl92d_phy_powerdown_anotherphy(hw, false); 1302 if (channel < 149) 1303 value = 0x07; 1304 else if (channel >= 149) 1305 value = 0x02; 1306 if (channel >= 36 && channel <= 64) 1307 index = 0; 1308 else if (channel >= 100 && channel <= 140) 1309 index = 1; 1310 else 1311 index = 2; 1312 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 1313 rfpath++) { 1314 if (rtlhal->macphymode == DUALMAC_DUALPHY && 1315 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 1316 internal_pa = rtlpriv->efuse.internal_pa_5g[1]; 1317 else 1318 internal_pa = 1319 rtlpriv->efuse.internal_pa_5g[rfpath]; 1320 if (internal_pa) { 1321 for (i = 0; 1322 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; 1323 i++) { 1324 rtl_set_rfreg(hw, rfpath, 1325 rf_for_c_cut_5g_internal_pa[i], 1326 RFREG_OFFSET_MASK, 1327 rf_pram_c_5g_int_pa[index][i]); 1328 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, 1329 "offset 0x%x value 0x%x path %d index %d\n", 1330 rf_for_c_cut_5g_internal_pa[i], 1331 rf_pram_c_5g_int_pa[index][i], 1332 rfpath, index); 1333 } 1334 } else { 1335 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 1336 mask, value); 1337 } 1338 } 1339 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1340 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1341 u4tmp = curveindex_2g[channel - 1]; 1342 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1343 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 1344 if (channel == 1 || channel == 2 || channel == 4 || channel == 9 1345 || channel == 10 || channel == 11 || channel == 12) 1346 index = 0; 1347 else if (channel == 3 || channel == 13 || channel == 14) 1348 index = 1; 1349 else if (channel >= 5 && channel <= 8) 1350 index = 2; 1351 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 1352 path = RF90_PATH_A; 1353 if (rtlhal->interfaceindex == 0) { 1354 need_pwr_down = 1355 rtl92d_phy_enable_anotherphy(hw, true); 1356 rtlhal->during_mac0init_radiob = true; 1357 1358 if (need_pwr_down) 1359 _rtl92d_phy_enable_rf_env(hw, path, 1360 &u4regvalue); 1361 } 1362 } 1363 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { 1364 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 1365 rtl_set_rfreg(hw, (enum radio_path)path, 1366 rf_reg_for_c_cut_2g[i], 1367 RFREG_OFFSET_MASK, 1368 (rf_reg_param_for_c_cut_2g[index][i] | 1369 BIT(17))); 1370 else 1371 rtl_set_rfreg(hw, (enum radio_path)path, 1372 rf_reg_for_c_cut_2g[i], 1373 RFREG_OFFSET_MASK, 1374 rf_reg_param_for_c_cut_2g 1375 [index][i]); 1376 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1377 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", 1378 rf_reg_for_c_cut_2g[i], 1379 rf_reg_param_for_c_cut_2g[index][i], 1380 rf_reg_mask_for_c_cut_2g[i], path, index, 1381 rtl_get_rfreg(hw, (enum radio_path)path, 1382 rf_reg_for_c_cut_2g[i], 1383 RFREG_OFFSET_MASK)); 1384 } 1385 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1386 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1387 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1388 1389 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1390 RFREG_OFFSET_MASK, 1391 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1392 if (need_pwr_down) 1393 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1394 if (rtlhal->during_mac0init_radiob) 1395 rtl92d_phy_powerdown_anotherphy(hw, true); 1396 } 1397 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1398} 1399 1400u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) 1401{ 1402 u8 channel_all[59] = { 1403 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 1404 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 1405 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 1406 114, 116, 118, 120, 122, 124, 126, 128, 130, 1407 132, 134, 136, 138, 140, 149, 151, 153, 155, 1408 157, 159, 161, 163, 165 1409 }; 1410 u8 place = chnl; 1411 1412 if (chnl > 14) { 1413 for (place = 14; place < sizeof(channel_all); place++) { 1414 if (channel_all[place] == chnl) 1415 return place - 13; 1416 } 1417 } 1418 1419 return 0; 1420} 1421 1422#define MAX_TOLERANCE 5 1423#define IQK_DELAY_TIME 1 /* ms */ 1424#define MAX_TOLERANCE_92D 3 1425 1426/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1427static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) 1428{ 1429 struct rtl_priv *rtlpriv = rtl_priv(hw); 1430 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1431 u32 regeac, rege94, rege9c, regea4; 1432 u8 result = 0; 1433 1434 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1435 /* path-A IQK setting */ 1436 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1437 if (rtlhal->interfaceindex == 0) { 1438 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); 1439 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); 1440 } else { 1441 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); 1442 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); 1443 } 1444 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); 1445 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); 1446 /* path-B IQK setting */ 1447 if (configpathb) { 1448 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); 1449 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); 1450 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); 1451 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); 1452 } 1453 /* LO calibration setting */ 1454 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1455 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1456 /* One shot, path A LOK & IQK */ 1457 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1459 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1460 /* delay x ms */ 1461 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1462 "Delay %d ms for One shot, path A LOK & IQK\n", 1463 IQK_DELAY_TIME); 1464 mdelay(IQK_DELAY_TIME); 1465 /* Check failed */ 1466 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1467 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1468 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1469 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1470 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1471 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1472 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1473 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1474 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1475 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1476 result |= 0x01; 1477 else /* if Tx not OK, ignore Rx */ 1478 return result; 1479 /* if Tx is OK, check whether Rx is OK */ 1480 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && 1481 (((regeac & 0x03FF0000) >> 16) != 0x36)) 1482 result |= 0x02; 1483 else 1484 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 1485 return result; 1486} 1487 1488/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1489static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, 1490 bool configpathb) 1491{ 1492 struct rtl_priv *rtlpriv = rtl_priv(hw); 1493 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1494 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1495 u32 regeac, rege94, rege9c, regea4; 1496 u8 result = 0; 1497 u8 i; 1498 u8 retrycount = 2; 1499 u32 TxOKBit = BIT(28), RxOKBit = BIT(27); 1500 1501 if (rtlhal->interfaceindex == 1) { /* PHY1 */ 1502 TxOKBit = BIT(31); 1503 RxOKBit = BIT(30); 1504 } 1505 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1506 /* path-A IQK setting */ 1507 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1508 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1509 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1510 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); 1511 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); 1512 /* path-B IQK setting */ 1513 if (configpathb) { 1514 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1515 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1516 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); 1517 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); 1518 } 1519 /* LO calibration setting */ 1520 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1521 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1522 /* path-A PA on */ 1523 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); 1524 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); 1525 for (i = 0; i < retrycount; i++) { 1526 /* One shot, path A LOK & IQK */ 1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1528 "One shot, path A LOK & IQK!\n"); 1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1530 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1531 /* delay x ms */ 1532 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1533 "Delay %d ms for One shot, path A LOK & IQK.\n", 1534 IQK_DELAY_TIME); 1535 mdelay(IQK_DELAY_TIME * 10); 1536 /* Check failed */ 1537 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1538 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1539 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1540 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1541 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1542 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1543 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1544 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1545 if (!(regeac & TxOKBit) && 1546 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1547 result |= 0x01; 1548 } else { /* if Tx not OK, ignore Rx */ 1549 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1550 "Path A Tx IQK fail!!\n"); 1551 continue; 1552 } 1553 1554 /* if Tx is OK, check whether Rx is OK */ 1555 if (!(regeac & RxOKBit) && 1556 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { 1557 result |= 0x02; 1558 break; 1559 } else { 1560 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1561 "Path A Rx IQK fail!!\n"); 1562 } 1563 } 1564 /* path A PA off */ 1565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1566 rtlphy->iqk_bb_backup[0]); 1567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 1568 rtlphy->iqk_bb_backup[1]); 1569 return result; 1570} 1571 1572/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1573static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) 1574{ 1575 struct rtl_priv *rtlpriv = rtl_priv(hw); 1576 u32 regeac, regeb4, regebc, regec4, regecc; 1577 u8 result = 0; 1578 1579 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1580 /* One shot, path B LOK & IQK */ 1581 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1583 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1584 /* delay x ms */ 1585 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1586 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1587 mdelay(IQK_DELAY_TIME); 1588 /* Check failed */ 1589 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1590 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1591 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1592 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1593 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1594 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1595 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1596 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1597 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1598 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1599 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1600 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1601 result |= 0x01; 1602 else 1603 return result; 1604 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && 1605 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1606 result |= 0x02; 1607 else 1608 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1609 return result; 1610} 1611 1612/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1613static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) 1614{ 1615 struct rtl_priv *rtlpriv = rtl_priv(hw); 1616 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1617 u32 regeac, regeb4, regebc, regec4, regecc; 1618 u8 result = 0; 1619 u8 i; 1620 u8 retrycount = 2; 1621 1622 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1623 /* path-A IQK setting */ 1624 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1625 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1626 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1627 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); 1628 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); 1629 1630 /* path-B IQK setting */ 1631 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1632 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1633 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); 1634 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); 1635 1636 /* LO calibration setting */ 1637 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1638 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1639 1640 /* path-B PA on */ 1641 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); 1642 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); 1643 1644 for (i = 0; i < retrycount; i++) { 1645 /* One shot, path B LOK & IQK */ 1646 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1647 "One shot, path A LOK & IQK!\n"); 1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); 1649 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1650 1651 /* delay x ms */ 1652 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1653 "Delay %d ms for One shot, path B LOK & IQK.\n", 10); 1654 mdelay(IQK_DELAY_TIME * 10); 1655 1656 /* Check failed */ 1657 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1658 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1659 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1660 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1661 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1662 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1663 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1664 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1665 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1666 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1667 if (!(regeac & BIT(31)) && 1668 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1669 result |= 0x01; 1670 else 1671 continue; 1672 if (!(regeac & BIT(30)) && 1673 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { 1674 result |= 0x02; 1675 break; 1676 } else { 1677 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1678 "Path B Rx IQK fail!!\n"); 1679 } 1680 } 1681 1682 /* path B PA off */ 1683 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1684 rtlphy->iqk_bb_backup[0]); 1685 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 1686 rtlphy->iqk_bb_backup[2]); 1687 return result; 1688} 1689 1690static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, 1691 u32 *adda_reg, u32 *adda_backup, 1692 u32 regnum) 1693{ 1694 struct rtl_priv *rtlpriv = rtl_priv(hw); 1695 u32 i; 1696 1697 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); 1698 for (i = 0; i < regnum; i++) 1699 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); 1700} 1701 1702static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, 1703 u32 *macreg, u32 *macbackup) 1704{ 1705 struct rtl_priv *rtlpriv = rtl_priv(hw); 1706 u32 i; 1707 1708 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); 1709 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1710 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1711 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1712} 1713 1714static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, 1715 u32 *adda_reg, u32 *adda_backup, 1716 u32 regnum) 1717{ 1718 struct rtl_priv *rtlpriv = rtl_priv(hw); 1719 u32 i; 1720 1721 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1722 "Reload ADDA power saving parameters !\n"); 1723 for (i = 0; i < regnum; i++) 1724 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); 1725} 1726 1727static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1728 u32 *macreg, u32 *macbackup) 1729{ 1730 struct rtl_priv *rtlpriv = rtl_priv(hw); 1731 u32 i; 1732 1733 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); 1734 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1735 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1736 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); 1737} 1738 1739static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, 1740 u32 *adda_reg, bool patha_on, bool is2t) 1741{ 1742 struct rtl_priv *rtlpriv = rtl_priv(hw); 1743 u32 pathon; 1744 u32 i; 1745 1746 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); 1747 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; 1748 if (patha_on) 1749 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1750 0x04db25a4 : 0x0b1b25a4; 1751 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1752 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); 1753} 1754 1755static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1756 u32 *macreg, u32 *macbackup) 1757{ 1758 struct rtl_priv *rtlpriv = rtl_priv(hw); 1759 u32 i; 1760 1761 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); 1762 rtl_write_byte(rtlpriv, macreg[0], 0x3F); 1763 1764 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1765 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & 1766 (~BIT(3)))); 1767 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1768} 1769 1770static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) 1771{ 1772 struct rtl_priv *rtlpriv = rtl_priv(hw); 1773 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1774 1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1776 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); 1777 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1778} 1779 1780static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1781{ 1782 struct rtl_priv *rtlpriv = rtl_priv(hw); 1783 u32 mode; 1784 1785 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1786 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1787 mode = pi_mode ? 0x01000100 : 0x01000000; 1788 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1789 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1790} 1791 1792static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1793 u8 t, bool is2t) 1794{ 1795 struct rtl_priv *rtlpriv = rtl_priv(hw); 1796 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1797 u32 i; 1798 u8 patha_ok, pathb_ok; 1799 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1800 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1801 0xe78, 0xe7c, 0xe80, 0xe84, 1802 0xe88, 0xe8c, 0xed0, 0xed4, 1803 0xed8, 0xedc, 0xee0, 0xeec 1804 }; 1805 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1806 0x522, 0x550, 0x551, 0x040 1807 }; 1808 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1809 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1810 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1811 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1812 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1813 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1814 }; 1815 const u32 retrycount = 2; 1816 u32 bbvalue; 1817 1818 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1819 if (t == 0) { 1820 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1821 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1822 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1823 is2t ? "2T2R" : "1T1R"); 1824 1825 /* Save ADDA parameters, turn Path A ADDA on */ 1826 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1827 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1828 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1829 rtlphy->iqk_mac_backup); 1830 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1831 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); 1832 } 1833 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1834 if (t == 0) 1835 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1836 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1837 1838 /* Switch BB to PI mode to do IQ Calibration. */ 1839 if (!rtlphy->rfpi_enable) 1840 _rtl92d_phy_pimode_switch(hw, true); 1841 1842 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1843 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1844 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1845 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); 1846 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1847 if (is2t) { 1848 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 1849 0x00010000); 1850 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, 1851 0x00010000); 1852 } 1853 /* MAC settings */ 1854 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1855 rtlphy->iqk_mac_backup); 1856 /* Page B init */ 1857 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1858 if (is2t) 1859 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1860 /* IQ calibration setting */ 1861 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1862 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1863 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1864 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1865 for (i = 0; i < retrycount; i++) { 1866 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1867 if (patha_ok == 0x03) { 1868 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1869 "Path A IQK Success!!\n"); 1870 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1871 0x3FF0000) >> 16; 1872 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1873 0x3FF0000) >> 16; 1874 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1875 0x3FF0000) >> 16; 1876 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1877 0x3FF0000) >> 16; 1878 break; 1879 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1880 /* Tx IQK OK */ 1881 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1882 "Path A IQK Only Tx Success!!\n"); 1883 1884 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1885 0x3FF0000) >> 16; 1886 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1887 0x3FF0000) >> 16; 1888 } 1889 } 1890 if (0x00 == patha_ok) 1891 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); 1892 if (is2t) { 1893 _rtl92d_phy_patha_standby(hw); 1894 /* Turn Path B ADDA on */ 1895 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1896 for (i = 0; i < retrycount; i++) { 1897 pathb_ok = _rtl92d_phy_pathb_iqk(hw); 1898 if (pathb_ok == 0x03) { 1899 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1900 "Path B IQK Success!!\n"); 1901 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1902 MASKDWORD) & 0x3FF0000) >> 16; 1903 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1904 MASKDWORD) & 0x3FF0000) >> 16; 1905 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1906 MASKDWORD) & 0x3FF0000) >> 16; 1907 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1908 MASKDWORD) & 0x3FF0000) >> 16; 1909 break; 1910 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1911 /* Tx IQK OK */ 1912 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1913 "Path B Only Tx IQK Success!!\n"); 1914 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1915 MASKDWORD) & 0x3FF0000) >> 16; 1916 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1917 MASKDWORD) & 0x3FF0000) >> 16; 1918 } 1919 } 1920 if (0x00 == pathb_ok) 1921 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1922 "Path B IQK failed!!\n"); 1923 } 1924 1925 /* Back to BB mode, load original value */ 1926 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1927 "IQK:Back to BB mode, load original value!\n"); 1928 1929 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1930 if (t != 0) { 1931 /* Switch back BB to SI mode after finish IQ Calibration. */ 1932 if (!rtlphy->rfpi_enable) 1933 _rtl92d_phy_pimode_switch(hw, false); 1934 /* Reload ADDA power saving parameters */ 1935 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 1936 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1937 /* Reload MAC parameters */ 1938 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 1939 rtlphy->iqk_mac_backup); 1940 if (is2t) 1941 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1942 rtlphy->iqk_bb_backup, 1943 IQK_BB_REG_NUM); 1944 else 1945 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1946 rtlphy->iqk_bb_backup, 1947 IQK_BB_REG_NUM - 1); 1948 /* load 0xe30 IQC default value */ 1949 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1950 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1951 } 1952 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1953} 1954 1955static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 1956 long result[][8], u8 t) 1957{ 1958 struct rtl_priv *rtlpriv = rtl_priv(hw); 1959 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1960 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1961 u8 patha_ok, pathb_ok; 1962 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1963 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1964 0xe78, 0xe7c, 0xe80, 0xe84, 1965 0xe88, 0xe8c, 0xed0, 0xed4, 1966 0xed8, 0xedc, 0xee0, 0xeec 1967 }; 1968 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1969 0x522, 0x550, 0x551, 0x040 1970 }; 1971 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1972 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1973 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1974 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1975 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1976 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1977 }; 1978 u32 bbvalue; 1979 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1980 1981 /* Note: IQ calibration must be performed after loading 1982 * PHY_REG.txt , and radio_a, radio_b.txt */ 1983 1984 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1985 mdelay(IQK_DELAY_TIME * 20); 1986 if (t == 0) { 1987 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1988 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1989 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1990 is2t ? "2T2R" : "1T1R"); 1991 /* Save ADDA parameters, turn Path A ADDA on */ 1992 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1993 rtlphy->adda_backup, 1994 IQK_ADDA_REG_NUM); 1995 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1996 rtlphy->iqk_mac_backup); 1997 if (is2t) 1998 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1999 rtlphy->iqk_bb_backup, 2000 IQK_BB_REG_NUM); 2001 else 2002 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 2003 rtlphy->iqk_bb_backup, 2004 IQK_BB_REG_NUM - 1); 2005 } 2006 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 2007 /* MAC settings */ 2008 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 2009 rtlphy->iqk_mac_backup); 2010 if (t == 0) 2011 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 2012 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 2013 /* Switch BB to PI mode to do IQ Calibration. */ 2014 if (!rtlphy->rfpi_enable) 2015 _rtl92d_phy_pimode_switch(hw, true); 2016 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2017 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 2018 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 2019 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); 2020 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 2021 2022 /* Page B init */ 2023 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 2024 if (is2t) 2025 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 2026 /* IQ calibration setting */ 2027 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 2028 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 2029 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); 2030 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 2031 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2032 if (patha_ok == 0x03) { 2033 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 2034 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2035 0x3FF0000) >> 16; 2036 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2037 0x3FF0000) >> 16; 2038 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 2039 0x3FF0000) >> 16; 2040 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 2041 0x3FF0000) >> 16; 2042 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2043 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2044 "Path A IQK Only Tx Success!!\n"); 2045 2046 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2047 0x3FF0000) >> 16; 2048 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2049 0x3FF0000) >> 16; 2050 } else { 2051 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 2052 } 2053 if (is2t) { 2054 /* _rtl92d_phy_patha_standby(hw); */ 2055 /* Turn Path B ADDA on */ 2056 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 2057 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); 2058 if (pathb_ok == 0x03) { 2059 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2060 "Path B IQK Success!!\n"); 2061 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2062 0x3FF0000) >> 16; 2063 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2064 0x3FF0000) >> 16; 2065 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 2066 0x3FF0000) >> 16; 2067 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 2068 0x3FF0000) >> 16; 2069 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2070 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2071 "Path B Only Tx IQK Success!!\n"); 2072 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2073 0x3FF0000) >> 16; 2074 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2075 0x3FF0000) >> 16; 2076 } else { 2077 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2078 "Path B IQK failed!!\n"); 2079 } 2080 } 2081 2082 /* Back to BB mode, load original value */ 2083 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2084 "IQK:Back to BB mode, load original value!\n"); 2085 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 2086 if (t != 0) { 2087 if (is2t) 2088 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2089 rtlphy->iqk_bb_backup, 2090 IQK_BB_REG_NUM); 2091 else 2092 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2093 rtlphy->iqk_bb_backup, 2094 IQK_BB_REG_NUM - 1); 2095 /* Reload MAC parameters */ 2096 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 2097 rtlphy->iqk_mac_backup); 2098 /* Switch back BB to SI mode after finish IQ Calibration. */ 2099 if (!rtlphy->rfpi_enable) 2100 _rtl92d_phy_pimode_switch(hw, false); 2101 /* Reload ADDA power saving parameters */ 2102 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 2103 rtlphy->adda_backup, 2104 IQK_ADDA_REG_NUM); 2105 } 2106 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 2107} 2108 2109static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, 2110 long result[][8], u8 c1, u8 c2) 2111{ 2112 struct rtl_priv *rtlpriv = rtl_priv(hw); 2113 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2114 u32 i, j, diff, sim_bitmap, bound; 2115 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 2116 bool bresult = true; 2117 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 2118 2119 if (is2t) 2120 bound = 8; 2121 else 2122 bound = 4; 2123 sim_bitmap = 0; 2124 for (i = 0; i < bound; i++) { 2125 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - 2126 result[c2][i]) : (result[c2][i] - result[c1][i]); 2127 if (diff > MAX_TOLERANCE_92D) { 2128 if ((i == 2 || i == 6) && !sim_bitmap) { 2129 if (result[c1][i] + result[c1][i + 1] == 0) 2130 final_candidate[(i / 4)] = c2; 2131 else if (result[c2][i] + result[c2][i + 1] == 0) 2132 final_candidate[(i / 4)] = c1; 2133 else 2134 sim_bitmap = sim_bitmap | (1 << i); 2135 } else { 2136 sim_bitmap = sim_bitmap | (1 << i); 2137 } 2138 } 2139 } 2140 if (sim_bitmap == 0) { 2141 for (i = 0; i < (bound / 4); i++) { 2142 if (final_candidate[i] != 0xFF) { 2143 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2144 result[3][j] = 2145 result[final_candidate[i]][j]; 2146 bresult = false; 2147 } 2148 } 2149 return bresult; 2150 } 2151 if (!(sim_bitmap & 0x0F)) { /* path A OK */ 2152 for (i = 0; i < 4; i++) 2153 result[3][i] = result[c1][i]; 2154 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ 2155 for (i = 0; i < 2; i++) 2156 result[3][i] = result[c1][i]; 2157 } 2158 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ 2159 for (i = 4; i < 8; i++) 2160 result[3][i] = result[c1][i]; 2161 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ 2162 for (i = 4; i < 6; i++) 2163 result[3][i] = result[c1][i]; 2164 } 2165 return false; 2166} 2167 2168static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, 2169 bool iqk_ok, long result[][8], 2170 u8 final_candidate, bool txonly) 2171{ 2172 struct rtl_priv *rtlpriv = rtl_priv(hw); 2173 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2174 u32 oldval_0, val_x, tx0_a, reg; 2175 long val_y, tx0_c; 2176 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || 2177 rtlhal->macphymode == DUALMAC_DUALPHY; 2178 2179 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2180 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 2181 if (final_candidate == 0xFF) { 2182 return; 2183 } else if (iqk_ok) { 2184 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2185 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 2186 val_x = result[final_candidate][0]; 2187 if ((val_x & 0x00000200) != 0) 2188 val_x = val_x | 0xFFFFFC00; 2189 tx0_a = (val_x * oldval_0) >> 8; 2190 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2191 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", 2192 val_x, tx0_a, oldval_0); 2193 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); 2194 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 2195 ((val_x * oldval_0 >> 7) & 0x1)); 2196 val_y = result[final_candidate][1]; 2197 if ((val_y & 0x00000200) != 0) 2198 val_y = val_y | 0xFFFFFC00; 2199 /* path B IQK result + 3 */ 2200 if (rtlhal->interfaceindex == 1 && 2201 rtlhal->current_bandtype == BAND_ON_5G) 2202 val_y += 3; 2203 tx0_c = (val_y * oldval_0) >> 8; 2204 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2205 "Y = 0x%lx, tx0_c = 0x%lx\n", 2206 val_y, tx0_c); 2207 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 2208 ((tx0_c & 0x3C0) >> 6)); 2209 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, 2210 (tx0_c & 0x3F)); 2211 if (is2t) 2212 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 2213 ((val_y * oldval_0 >> 7) & 0x1)); 2214 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 2215 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2216 MASKDWORD)); 2217 if (txonly) { 2218 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 2219 return; 2220 } 2221 reg = result[final_candidate][2]; 2222 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 2223 reg = result[final_candidate][3] & 0x3F; 2224 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 2225 reg = (result[final_candidate][3] >> 6) & 0xF; 2226 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 2227 } 2228} 2229 2230static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, 2231 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly) 2232{ 2233 struct rtl_priv *rtlpriv = rtl_priv(hw); 2234 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2235 u32 oldval_1, val_x, tx1_a, reg; 2236 long val_y, tx1_c; 2237 2238 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", 2239 iqk_ok ? "Success" : "Failed"); 2240 if (final_candidate == 0xFF) { 2241 return; 2242 } else if (iqk_ok) { 2243 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 2244 MASKDWORD) >> 22) & 0x3FF; 2245 val_x = result[final_candidate][4]; 2246 if ((val_x & 0x00000200) != 0) 2247 val_x = val_x | 0xFFFFFC00; 2248 tx1_a = (val_x * oldval_1) >> 8; 2249 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", 2250 val_x, tx1_a); 2251 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); 2252 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 2253 ((val_x * oldval_1 >> 7) & 0x1)); 2254 val_y = result[final_candidate][5]; 2255 if ((val_y & 0x00000200) != 0) 2256 val_y = val_y | 0xFFFFFC00; 2257 if (rtlhal->current_bandtype == BAND_ON_5G) 2258 val_y += 3; 2259 tx1_c = (val_y * oldval_1) >> 8; 2260 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", 2261 val_y, tx1_c); 2262 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 2263 ((tx1_c & 0x3C0) >> 6)); 2264 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, 2265 (tx1_c & 0x3F)); 2266 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 2267 ((val_y * oldval_1 >> 7) & 0x1)); 2268 if (txonly) 2269 return; 2270 reg = result[final_candidate][6]; 2271 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 2272 reg = result[final_candidate][7] & 0x3F; 2273 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 2274 reg = (result[final_candidate][7] >> 6) & 0xF; 2275 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 2276 } 2277} 2278 2279void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) 2280{ 2281 struct rtl_priv *rtlpriv = rtl_priv(hw); 2282 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2283 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2284 long result[4][8]; 2285 u8 i, final_candidate, indexforchannel; 2286 bool patha_ok, pathb_ok; 2287 long rege94, rege9c, regea4, regeac, regeb4; 2288 long regebc, regec4, regecc, regtmp = 0; 2289 bool is12simular, is13simular, is23simular; 2290 unsigned long flag = 0; 2291 2292 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2293 "IQK:Start!!!channel %d\n", rtlphy->current_channel); 2294 for (i = 0; i < 8; i++) { 2295 result[0][i] = 0; 2296 result[1][i] = 0; 2297 result[2][i] = 0; 2298 result[3][i] = 0; 2299 } 2300 final_candidate = 0xff; 2301 patha_ok = false; 2302 pathb_ok = false; 2303 is12simular = false; 2304 is23simular = false; 2305 is13simular = false; 2306 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2307 "IQK !!!currentband %d\n", rtlhal->current_bandtype); 2308 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 2309 for (i = 0; i < 3; i++) { 2310 if (rtlhal->current_bandtype == BAND_ON_5G) { 2311 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); 2312 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2313 if (IS_92D_SINGLEPHY(rtlhal->version)) 2314 _rtl92d_phy_iq_calibrate(hw, result, i, true); 2315 else 2316 _rtl92d_phy_iq_calibrate(hw, result, i, false); 2317 } 2318 if (i == 1) { 2319 is12simular = _rtl92d_phy_simularity_compare(hw, result, 2320 0, 1); 2321 if (is12simular) { 2322 final_candidate = 0; 2323 break; 2324 } 2325 } 2326 if (i == 2) { 2327 is13simular = _rtl92d_phy_simularity_compare(hw, result, 2328 0, 2); 2329 if (is13simular) { 2330 final_candidate = 0; 2331 break; 2332 } 2333 is23simular = _rtl92d_phy_simularity_compare(hw, result, 2334 1, 2); 2335 if (is23simular) { 2336 final_candidate = 1; 2337 } else { 2338 for (i = 0; i < 8; i++) 2339 regtmp += result[3][i]; 2340 2341 if (regtmp != 0) 2342 final_candidate = 3; 2343 else 2344 final_candidate = 0xFF; 2345 } 2346 } 2347 } 2348 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 2349 for (i = 0; i < 4; i++) { 2350 rege94 = result[i][0]; 2351 rege9c = result[i][1]; 2352 regea4 = result[i][2]; 2353 regeac = result[i][3]; 2354 regeb4 = result[i][4]; 2355 regebc = result[i][5]; 2356 regec4 = result[i][6]; 2357 regecc = result[i][7]; 2358 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2359 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2360 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2361 regecc); 2362 } 2363 if (final_candidate != 0xff) { 2364 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; 2365 rtlphy->reg_e9c = rege9c = result[final_candidate][1]; 2366 regea4 = result[final_candidate][2]; 2367 regeac = result[final_candidate][3]; 2368 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; 2369 rtlphy->reg_ebc = regebc = result[final_candidate][5]; 2370 regec4 = result[final_candidate][6]; 2371 regecc = result[final_candidate][7]; 2372 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2373 "IQK: final_candidate is %x\n", final_candidate); 2374 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2375 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2376 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2377 regecc); 2378 patha_ok = pathb_ok = true; 2379 } else { 2380 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ 2381 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ 2382 } 2383 if ((rege94 != 0) /*&&(regea4 != 0) */) 2384 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, 2385 final_candidate, (regea4 == 0)); 2386 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2387 if ((regeb4 != 0) /*&&(regec4 != 0) */) 2388 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, 2389 final_candidate, (regec4 == 0)); 2390 } 2391 if (final_candidate != 0xFF) { 2392 indexforchannel = rtl92d_get_rightchnlplace_for_iqk( 2393 rtlphy->current_channel); 2394 2395 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2396 rtlphy->iqk_matrix[indexforchannel]. 2397 value[0][i] = result[final_candidate][i]; 2398 rtlphy->iqk_matrix[indexforchannel].iqk_done = 2399 true; 2400 2401 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, 2402 "IQK OK indexforchannel %d\n", indexforchannel); 2403 } 2404} 2405 2406void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) 2407{ 2408 struct rtl_priv *rtlpriv = rtl_priv(hw); 2409 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2410 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2411 u8 indexforchannel; 2412 2413 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); 2414 /*------Do IQK for normal chip and test chip 5G band------- */ 2415 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 2416 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", 2417 indexforchannel, 2418 rtlphy->iqk_matrix[indexforchannel].iqk_done); 2419 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && 2420 rtlphy->need_iqk) { 2421 /* Re Do IQK. */ 2422 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, 2423 "Do IQK Matrix reg for channel:%d....\n", channel); 2424 rtl92d_phy_iq_calibrate(hw); 2425 } else { 2426 /* Just load the value. */ 2427 /* 2G band just load once. */ 2428 if (((!rtlhal->load_imrandiqk_setting_for2g) && 2429 indexforchannel == 0) || indexforchannel > 0) { 2430 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 2431 "Just Read IQK Matrix reg for channel:%d....\n", 2432 channel); 2433 if ((rtlphy->iqk_matrix[indexforchannel]. 2434 value[0] != NULL) 2435 /*&&(regea4 != 0) */) 2436 _rtl92d_phy_patha_fill_iqk_matrix(hw, true, 2437 rtlphy->iqk_matrix[ 2438 indexforchannel].value, 0, 2439 (rtlphy->iqk_matrix[ 2440 indexforchannel].value[0][2] == 0)); 2441 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2442 if ((rtlphy->iqk_matrix[ 2443 indexforchannel].value[0][4] != 0) 2444 /*&&(regec4 != 0) */) 2445 _rtl92d_phy_pathb_fill_iqk_matrix(hw, 2446 true, 2447 rtlphy->iqk_matrix[ 2448 indexforchannel].value, 0, 2449 (rtlphy->iqk_matrix[ 2450 indexforchannel].value[0][6] 2451 == 0)); 2452 } 2453 } 2454 } 2455 rtlphy->need_iqk = false; 2456 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2457} 2458 2459static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) 2460{ 2461 u32 ret; 2462 2463 if (val1 >= val2) 2464 ret = val1 - val2; 2465 else 2466 ret = val2 - val1; 2467 return ret; 2468} 2469 2470static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) 2471{ 2472 2473 int i; 2474 u8 channel_5g[45] = { 2475 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 2476 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 2477 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 2478 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 2479 161, 163, 165 2480 }; 2481 2482 for (i = 0; i < sizeof(channel_5g); i++) 2483 if (channel == channel_5g[i]) 2484 return true; 2485 return false; 2486} 2487 2488static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, 2489 u32 *targetchnl, u32 * curvecount_val, 2490 bool is5g, u32 *curveindex) 2491{ 2492 struct rtl_priv *rtlpriv = rtl_priv(hw); 2493 u32 smallest_abs_val = 0xffffffff, u4tmp; 2494 u8 i, j; 2495 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; 2496 2497 for (i = 0; i < chnl_num; i++) { 2498 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) 2499 continue; 2500 curveindex[i] = 0; 2501 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { 2502 u4tmp = _rtl92d_phy_get_abs(targetchnl[i], 2503 curvecount_val[j]); 2504 2505 if (u4tmp < smallest_abs_val) { 2506 curveindex[i] = j; 2507 smallest_abs_val = u4tmp; 2508 } 2509 } 2510 smallest_abs_val = 0xffffffff; 2511 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", 2512 i, curveindex[i]); 2513 } 2514} 2515 2516static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, 2517 u8 channel) 2518{ 2519 struct rtl_priv *rtlpriv = rtl_priv(hw); 2520 u8 erfpath = rtlpriv->rtlhal.current_bandtype == 2521 BAND_ON_5G ? RF90_PATH_A : 2522 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? 2523 RF90_PATH_B : RF90_PATH_A; 2524 u32 u4tmp = 0, u4regvalue = 0; 2525 bool bneed_powerdown_radio = false; 2526 2527 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 2528 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", 2529 rtlpriv->rtlhal.current_bandtype); 2530 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); 2531 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 2532 u4tmp = curveindex_5g[channel-1]; 2533 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2534 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 2535 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2536 rtlpriv->rtlhal.interfaceindex == 1) { 2537 bneed_powerdown_radio = 2538 rtl92d_phy_enable_anotherphy(hw, false); 2539 rtlpriv->rtlhal.during_mac1init_radioa = true; 2540 /* asume no this case */ 2541 if (bneed_powerdown_radio) 2542 _rtl92d_phy_enable_rf_env(hw, erfpath, 2543 &u4regvalue); 2544 } 2545 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2546 if (bneed_powerdown_radio) 2547 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2548 if (rtlpriv->rtlhal.during_mac1init_radioa) 2549 rtl92d_phy_powerdown_anotherphy(hw, false); 2550 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 2551 u4tmp = curveindex_2g[channel-1]; 2552 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2553 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 2554 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2555 rtlpriv->rtlhal.interfaceindex == 0) { 2556 bneed_powerdown_radio = 2557 rtl92d_phy_enable_anotherphy(hw, true); 2558 rtlpriv->rtlhal.during_mac0init_radiob = true; 2559 if (bneed_powerdown_radio) 2560 _rtl92d_phy_enable_rf_env(hw, erfpath, 2561 &u4regvalue); 2562 } 2563 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2564 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2565 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 2566 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); 2567 if (bneed_powerdown_radio) 2568 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2569 if (rtlpriv->rtlhal.during_mac0init_radiob) 2570 rtl92d_phy_powerdown_anotherphy(hw, true); 2571 } 2572 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2573} 2574 2575static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) 2576{ 2577 struct rtl_priv *rtlpriv = rtl_priv(hw); 2578 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2579 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2580 u8 tmpreg, index, rf_mode[2]; 2581 u8 path = is2t ? 2 : 1; 2582 u8 i; 2583 u32 u4tmp, offset; 2584 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; 2585 u16 timeout = 800, timecount = 0; 2586 2587 /* Check continuous TX and Packet TX */ 2588 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2589 /* if Deal with contisuous TX case, disable all continuous TX */ 2590 /* if Deal with Packet TX case, block all queues */ 2591 if ((tmpreg & 0x70) != 0) 2592 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 2593 else 2594 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2595 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); 2596 for (index = 0; index < path; index++) { 2597 /* 1. Read original RF mode */ 2598 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2599 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2600 /* 2. Set RF mode = standby mode */ 2601 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2602 RFREG_OFFSET_MASK, 0x010000); 2603 if (rtlpci->init_ready) { 2604 /* switch CV-curve control by LC-calibration */ 2605 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2606 BIT(17), 0x0); 2607 /* 4. Set LC calibration begin */ 2608 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2609 0x08000, 0x01); 2610 } 2611 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2612 RFREG_OFFSET_MASK); 2613 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2614 mdelay(50); 2615 timecount += 50; 2616 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2617 RF_SYN_G6, RFREG_OFFSET_MASK); 2618 } 2619 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2620 "PHY_LCK finish delay for %d ms=2\n", timecount); 2621 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); 2622 if (index == 0 && rtlhal->interfaceindex == 0) { 2623 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2624 "path-A / 5G LCK\n"); 2625 } else { 2626 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2627 "path-B / 2.4G LCK\n"); 2628 } 2629 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); 2630 /* Set LC calibration off */ 2631 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2632 0x08000, 0x0); 2633 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); 2634 /* save Curve-counting number */ 2635 for (i = 0; i < CV_CURVE_CNT; i++) { 2636 u32 readval = 0, readval2 = 0; 2637 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, 2638 0x7f, i); 2639 2640 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2641 RFREG_OFFSET_MASK, 0x0); 2642 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2643 0x4F, RFREG_OFFSET_MASK); 2644 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2645 /* reg 0x4f [4:0] */ 2646 /* reg 0x50 [19:10] */ 2647 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, 2648 0x50, 0xffc00); 2649 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | 2650 readval2); 2651 } 2652 if (index == 0 && rtlhal->interfaceindex == 0) 2653 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, 2654 curvecount_val, 2655 true, curveindex_5g); 2656 else 2657 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, 2658 curvecount_val, 2659 false, curveindex_2g); 2660 /* switch CV-curve control mode */ 2661 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2662 BIT(17), 0x1); 2663 } 2664 2665 /* Restore original situation */ 2666 for (index = 0; index < path; index++) { 2667 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2668 rtl_write_byte(rtlpriv, offset, 0x50); 2669 rtl_write_byte(rtlpriv, offset, rf_mode[index]); 2670 } 2671 if ((tmpreg & 0x70) != 0) 2672 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2673 else /*Deal with Packet TX case */ 2674 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2675 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); 2676 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); 2677} 2678 2679static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2680{ 2681 struct rtl_priv *rtlpriv = rtl_priv(hw); 2682 2683 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n"); 2684 _rtl92d_phy_lc_calibrate_sw(hw, is2t); 2685} 2686 2687void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) 2688{ 2689 struct rtl_priv *rtlpriv = rtl_priv(hw); 2690 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2691 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2692 u32 timeout = 2000, timecount = 0; 2693 2694 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2695 udelay(50); 2696 timecount += 50; 2697 } 2698 2699 rtlphy->lck_inprogress = true; 2700 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2701 "LCK:Start!!! currentband %x delay %d ms\n", 2702 rtlhal->current_bandtype, timecount); 2703 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2704 _rtl92d_phy_lc_calibrate(hw, true); 2705 } else { 2706 /* For 1T1R */ 2707 _rtl92d_phy_lc_calibrate(hw, false); 2708 } 2709 rtlphy->lck_inprogress = false; 2710 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); 2711} 2712 2713void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) 2714{ 2715 return; 2716} 2717 2718static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 2719 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 2720 u32 para1, u32 para2, u32 msdelay) 2721{ 2722 struct swchnlcmd *pcmd; 2723 2724 if (cmdtable == NULL) { 2725 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 2726 return false; 2727 } 2728 if (cmdtableidx >= cmdtablesz) 2729 return false; 2730 2731 pcmd = cmdtable + cmdtableidx; 2732 pcmd->cmdid = cmdid; 2733 pcmd->para1 = para1; 2734 pcmd->para2 = para2; 2735 pcmd->msdelay = msdelay; 2736 return true; 2737} 2738 2739void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) 2740{ 2741 struct rtl_priv *rtlpriv = rtl_priv(hw); 2742 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2743 u8 i; 2744 2745 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2746 "settings regs %d default regs %d\n", 2747 (int)(sizeof(rtlphy->iqk_matrix) / 2748 sizeof(struct iqk_matrix_regs)), 2749 IQK_MATRIX_REG_NUM); 2750 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ 2751 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { 2752 rtlphy->iqk_matrix[i].value[0][0] = 0x100; 2753 rtlphy->iqk_matrix[i].value[0][2] = 0x100; 2754 rtlphy->iqk_matrix[i].value[0][4] = 0x100; 2755 rtlphy->iqk_matrix[i].value[0][6] = 0x100; 2756 rtlphy->iqk_matrix[i].value[0][1] = 0x0; 2757 rtlphy->iqk_matrix[i].value[0][3] = 0x0; 2758 rtlphy->iqk_matrix[i].value[0][5] = 0x0; 2759 rtlphy->iqk_matrix[i].value[0][7] = 0x0; 2760 rtlphy->iqk_matrix[i].iqk_done = false; 2761 } 2762} 2763 2764static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 2765 u8 channel, u8 *stage, u8 *step, 2766 u32 *delay) 2767{ 2768 struct rtl_priv *rtlpriv = rtl_priv(hw); 2769 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2770 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 2771 u32 precommoncmdcnt; 2772 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 2773 u32 postcommoncmdcnt; 2774 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 2775 u32 rfdependcmdcnt; 2776 struct swchnlcmd *currentcmd = NULL; 2777 u8 rfpath; 2778 u8 num_total_rfpath = rtlphy->num_total_rfpath; 2779 2780 precommoncmdcnt = 0; 2781 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2782 MAX_PRECMD_CNT, 2783 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 2784 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2785 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 2786 postcommoncmdcnt = 0; 2787 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 2788 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 2789 rfdependcmdcnt = 0; 2790 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2791 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 2792 RF_CHNLBW, channel, 0); 2793 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2794 MAX_RFDEPENDCMD_CNT, CMDID_END, 2795 0, 0, 0); 2796 2797 do { 2798 switch (*stage) { 2799 case 0: 2800 currentcmd = &precommoncmd[*step]; 2801 break; 2802 case 1: 2803 currentcmd = &rfdependcmd[*step]; 2804 break; 2805 case 2: 2806 currentcmd = &postcommoncmd[*step]; 2807 break; 2808 } 2809 if (currentcmd->cmdid == CMDID_END) { 2810 if ((*stage) == 2) { 2811 return true; 2812 } else { 2813 (*stage)++; 2814 (*step) = 0; 2815 continue; 2816 } 2817 } 2818 switch (currentcmd->cmdid) { 2819 case CMDID_SET_TXPOWEROWER_LEVEL: 2820 rtl92d_phy_set_txpower_level(hw, channel); 2821 break; 2822 case CMDID_WRITEPORT_ULONG: 2823 rtl_write_dword(rtlpriv, currentcmd->para1, 2824 currentcmd->para2); 2825 break; 2826 case CMDID_WRITEPORT_USHORT: 2827 rtl_write_word(rtlpriv, currentcmd->para1, 2828 (u16)currentcmd->para2); 2829 break; 2830 case CMDID_WRITEPORT_UCHAR: 2831 rtl_write_byte(rtlpriv, currentcmd->para1, 2832 (u8)currentcmd->para2); 2833 break; 2834 case CMDID_RF_WRITEREG: 2835 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 2836 rtlphy->rfreg_chnlval[rfpath] = 2837 ((rtlphy->rfreg_chnlval[rfpath] & 2838 0xffffff00) | currentcmd->para2); 2839 if (rtlpriv->rtlhal.current_bandtype == 2840 BAND_ON_5G) { 2841 if (currentcmd->para2 > 99) 2842 rtlphy->rfreg_chnlval[rfpath] = 2843 rtlphy->rfreg_chnlval 2844 [rfpath] | (BIT(18)); 2845 else 2846 rtlphy->rfreg_chnlval[rfpath] = 2847 rtlphy->rfreg_chnlval 2848 [rfpath] & (~BIT(18)); 2849 rtlphy->rfreg_chnlval[rfpath] |= 2850 (BIT(16) | BIT(8)); 2851 } else { 2852 rtlphy->rfreg_chnlval[rfpath] &= 2853 ~(BIT(8) | BIT(16) | BIT(18)); 2854 } 2855 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2856 currentcmd->para1, 2857 RFREG_OFFSET_MASK, 2858 rtlphy->rfreg_chnlval[rfpath]); 2859 _rtl92d_phy_reload_imr_setting(hw, channel, 2860 rfpath); 2861 } 2862 _rtl92d_phy_switch_rf_setting(hw, channel); 2863 /* do IQK when all parameters are ready */ 2864 rtl92d_phy_reload_iqk_setting(hw, channel); 2865 break; 2866 default: 2867 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2868 "switch case not processed\n"); 2869 break; 2870 } 2871 break; 2872 } while (true); 2873 (*delay) = currentcmd->msdelay; 2874 (*step)++; 2875 return false; 2876} 2877 2878u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) 2879{ 2880 struct rtl_priv *rtlpriv = rtl_priv(hw); 2881 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2883 u32 delay; 2884 u32 timeout = 1000, timecount = 0; 2885 u8 channel = rtlphy->current_channel; 2886 u32 ret_value; 2887 2888 if (rtlphy->sw_chnl_inprogress) 2889 return 0; 2890 if (rtlphy->set_bwmode_inprogress) 2891 return 0; 2892 2893 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 2894 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 2895 "sw_chnl_inprogress false driver sleep or unload\n"); 2896 return 0; 2897 } 2898 while (rtlphy->lck_inprogress && timecount < timeout) { 2899 mdelay(50); 2900 timecount += 50; 2901 } 2902 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2903 rtlhal->bandset == BAND_ON_BOTH) { 2904 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2905 MASKDWORD); 2906 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2907 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2908 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2909 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); 2910 } 2911 switch (rtlhal->current_bandtype) { 2912 case BAND_ON_5G: 2913 /* Get first channel error when change between 2914 * 5G and 2.4G band. */ 2915 if (channel <= 14) 2916 return 0; 2917 RT_ASSERT((channel > 14), "5G but channel<=14\n"); 2918 break; 2919 case BAND_ON_2_4G: 2920 /* Get first channel error when change between 2921 * 5G and 2.4G band. */ 2922 if (channel > 14) 2923 return 0; 2924 RT_ASSERT((channel <= 14), "2G but channel>14\n"); 2925 break; 2926 default: 2927 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n", 2928 rtlpriv->mac80211.mode); 2929 break; 2930 } 2931 rtlphy->sw_chnl_inprogress = true; 2932 if (channel == 0) 2933 channel = 1; 2934 rtlphy->sw_chnl_stage = 0; 2935 rtlphy->sw_chnl_step = 0; 2936 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 2937 "switch to channel%d\n", rtlphy->current_channel); 2938 2939 do { 2940 if (!rtlphy->sw_chnl_inprogress) 2941 break; 2942 if (!_rtl92d_phy_sw_chnl_step_by_step(hw, 2943 rtlphy->current_channel, 2944 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { 2945 if (delay > 0) 2946 mdelay(delay); 2947 else 2948 continue; 2949 } else { 2950 rtlphy->sw_chnl_inprogress = false; 2951 } 2952 break; 2953 } while (true); 2954 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 2955 rtlphy->sw_chnl_inprogress = false; 2956 return 1; 2957} 2958 2959static void rtl92d_phy_set_io(struct ieee80211_hw *hw) 2960{ 2961 struct rtl_priv *rtlpriv = rtl_priv(hw); 2962 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 2963 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2964 2965 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2966 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2967 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2968 switch (rtlphy->current_io_type) { 2969 case IO_CMD_RESUME_DM_BY_SCAN: 2970 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 2971 rtl92d_dm_write_dig(hw); 2972 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 2973 break; 2974 case IO_CMD_PAUSE_DM_BY_SCAN: 2975 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; 2976 de_digtable->cur_igvalue = 0x37; 2977 rtl92d_dm_write_dig(hw); 2978 break; 2979 default: 2980 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2981 "switch case not processed\n"); 2982 break; 2983 } 2984 rtlphy->set_io_inprogress = false; 2985 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", 2986 rtlphy->current_io_type); 2987} 2988 2989bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2990{ 2991 struct rtl_priv *rtlpriv = rtl_priv(hw); 2992 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2993 bool postprocessing = false; 2994 2995 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2996 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2997 iotype, rtlphy->set_io_inprogress); 2998 do { 2999 switch (iotype) { 3000 case IO_CMD_RESUME_DM_BY_SCAN: 3001 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 3002 "[IO CMD] Resume DM after scan\n"); 3003 postprocessing = true; 3004 break; 3005 case IO_CMD_PAUSE_DM_BY_SCAN: 3006 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 3007 "[IO CMD] Pause DM before scan\n"); 3008 postprocessing = true; 3009 break; 3010 default: 3011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 3012 "switch case not processed\n"); 3013 break; 3014 } 3015 } while (false); 3016 if (postprocessing && !rtlphy->set_io_inprogress) { 3017 rtlphy->set_io_inprogress = true; 3018 rtlphy->current_io_type = iotype; 3019 } else { 3020 return false; 3021 } 3022 rtl92d_phy_set_io(hw); 3023 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); 3024 return true; 3025} 3026 3027static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) 3028{ 3029 struct rtl_priv *rtlpriv = rtl_priv(hw); 3030 3031 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ 3032 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ 3033 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3034 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 3035 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ 3036 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3037 /* RF_ON_EXCEP(d~g): */ 3038 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ 3039 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3040 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ 3041 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ 3042 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3043 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3044 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ 3045 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3046} 3047 3048static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) 3049{ 3050 struct rtl_priv *rtlpriv = rtl_priv(hw); 3051 u32 u4btmp; 3052 u8 delay = 5; 3053 3054 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 3055 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3056 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 3057 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3058 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 3059 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3060 /* d. APSD_CTRL 0x600[7:0] = 0x00 3061 * APSD_CTRL 0x600[7:0] = 0x00 3062 * RF path 0 offset 0x00 = 0x00 3063 * APSD_CTRL 0x600[7:0] = 0x40 3064 * */ 3065 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3066 while (u4btmp != 0 && delay > 0) { 3067 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 3068 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3069 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3070 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3071 delay--; 3072 } 3073 if (delay == 0) { 3074 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ 3075 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3076 3077 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3078 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3079 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3080 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3081 "Fail !!! Switch RF timeout\n"); 3082 return; 3083 } 3084 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ 3085 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3086 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ 3087 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3088 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 3089 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ 3090} 3091 3092bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, 3093 enum rf_pwrstate rfpwr_state) 3094{ 3095 3096 bool bresult = true; 3097 struct rtl_priv *rtlpriv = rtl_priv(hw); 3098 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3099 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 3102 u8 i, queue_id; 3103 struct rtl8192_tx_ring *ring = NULL; 3104 3105 if (rfpwr_state == ppsc->rfpwr_state) 3106 return false; 3107 switch (rfpwr_state) { 3108 case ERFON: 3109 if ((ppsc->rfpwr_state == ERFOFF) && 3110 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 3111 bool rtstatus; 3112 u32 InitializeCount = 0; 3113 do { 3114 InitializeCount++; 3115 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3116 "IPS Set eRf nic enable\n"); 3117 rtstatus = rtl_ps_enable_nic(hw); 3118 } while (!rtstatus && (InitializeCount < 10)); 3119 3120 RT_CLEAR_PS_LEVEL(ppsc, 3121 RT_RF_OFF_LEVL_HALT_NIC); 3122 } else { 3123 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3124 "awake, sleeped:%d ms state_inap:%x\n", 3125 jiffies_to_msecs(jiffies - 3126 ppsc->last_sleep_jiffies), 3127 rtlpriv->psc.state_inap); 3128 ppsc->last_awake_jiffies = jiffies; 3129 _rtl92d_phy_set_rfon(hw); 3130 } 3131 3132 if (mac->link_state == MAC80211_LINKED) 3133 rtlpriv->cfg->ops->led_control(hw, 3134 LED_CTL_LINK); 3135 else 3136 rtlpriv->cfg->ops->led_control(hw, 3137 LED_CTL_NO_LINK); 3138 break; 3139 case ERFOFF: 3140 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 3141 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3142 "IPS Set eRf nic disable\n"); 3143 rtl_ps_disable_nic(hw); 3144 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3145 } else { 3146 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 3147 rtlpriv->cfg->ops->led_control(hw, 3148 LED_CTL_NO_LINK); 3149 else 3150 rtlpriv->cfg->ops->led_control(hw, 3151 LED_CTL_POWER_OFF); 3152 } 3153 break; 3154 case ERFSLEEP: 3155 if (ppsc->rfpwr_state == ERFOFF) 3156 return false; 3157 3158 for (queue_id = 0, i = 0; 3159 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 3160 ring = &pcipriv->dev.tx_ring[queue_id]; 3161 if (skb_queue_len(&ring->queue) == 0 || 3162 queue_id == BEACON_QUEUE) { 3163 queue_id++; 3164 continue; 3165 } else if (rtlpci->pdev->current_state != PCI_D0) { 3166 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3167 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", 3168 i + 1, queue_id); 3169 break; 3170 } else { 3171 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3172 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 3173 i + 1, queue_id, 3174 skb_queue_len(&ring->queue)); 3175 udelay(10); 3176 i++; 3177 } 3178 3179 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 3180 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3181 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 3182 MAX_DOZE_WAITING_TIMES_9x, queue_id, 3183 skb_queue_len(&ring->queue)); 3184 break; 3185 } 3186 } 3187 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3188 "Set rfsleep awaked:%d ms\n", 3189 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 3190 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3191 "sleep awaked:%d ms state_inap:%x\n", 3192 jiffies_to_msecs(jiffies - 3193 ppsc->last_awake_jiffies), 3194 rtlpriv->psc.state_inap); 3195 ppsc->last_sleep_jiffies = jiffies; 3196 _rtl92d_phy_set_rfsleep(hw); 3197 break; 3198 default: 3199 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 3200 "switch case not processed\n"); 3201 bresult = false; 3202 break; 3203 } 3204 if (bresult) 3205 ppsc->rfpwr_state = rfpwr_state; 3206 return bresult; 3207} 3208 3209void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) 3210{ 3211 struct rtl_priv *rtlpriv = rtl_priv(hw); 3212 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3213 u8 offset = REG_MAC_PHY_CTRL_NORMAL; 3214 3215 switch (rtlhal->macphymode) { 3216 case DUALMAC_DUALPHY: 3217 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3218 "MacPhyMode: DUALMAC_DUALPHY\n"); 3219 rtl_write_byte(rtlpriv, offset, 0xF3); 3220 break; 3221 case SINGLEMAC_SINGLEPHY: 3222 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3223 "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); 3224 rtl_write_byte(rtlpriv, offset, 0xF4); 3225 break; 3226 case DUALMAC_SINGLEPHY: 3227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3228 "MacPhyMode: DUALMAC_SINGLEPHY\n"); 3229 rtl_write_byte(rtlpriv, offset, 0xF1); 3230 break; 3231 } 3232} 3233 3234void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) 3235{ 3236 struct rtl_priv *rtlpriv = rtl_priv(hw); 3237 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3238 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3239 3240 switch (rtlhal->macphymode) { 3241 case DUALMAC_SINGLEPHY: 3242 rtlphy->rf_type = RF_2T2R; 3243 rtlhal->version |= RF_TYPE_2T2R; 3244 rtlhal->bandset = BAND_ON_BOTH; 3245 rtlhal->current_bandtype = BAND_ON_2_4G; 3246 break; 3247 3248 case SINGLEMAC_SINGLEPHY: 3249 rtlphy->rf_type = RF_2T2R; 3250 rtlhal->version |= RF_TYPE_2T2R; 3251 rtlhal->bandset = BAND_ON_BOTH; 3252 rtlhal->current_bandtype = BAND_ON_2_4G; 3253 break; 3254 3255 case DUALMAC_DUALPHY: 3256 rtlphy->rf_type = RF_1T1R; 3257 rtlhal->version &= RF_TYPE_1T1R; 3258 /* Now we let MAC0 run on 5G band. */ 3259 if (rtlhal->interfaceindex == 0) { 3260 rtlhal->bandset = BAND_ON_5G; 3261 rtlhal->current_bandtype = BAND_ON_5G; 3262 } else { 3263 rtlhal->bandset = BAND_ON_2_4G; 3264 rtlhal->current_bandtype = BAND_ON_2_4G; 3265 } 3266 break; 3267 default: 3268 break; 3269 } 3270} 3271 3272u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) 3273{ 3274 u8 group; 3275 u8 channel_info[59] = { 3276 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 3277 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 3278 58, 60, 62, 64, 100, 102, 104, 106, 108, 3279 110, 112, 114, 116, 118, 120, 122, 124, 3280 126, 128, 130, 132, 134, 136, 138, 140, 3281 149, 151, 153, 155, 157, 159, 161, 163, 3282 165 3283 }; 3284 3285 if (channel_info[chnl] <= 3) 3286 group = 0; 3287 else if (channel_info[chnl] <= 9) 3288 group = 1; 3289 else if (channel_info[chnl] <= 14) 3290 group = 2; 3291 else if (channel_info[chnl] <= 44) 3292 group = 3; 3293 else if (channel_info[chnl] <= 54) 3294 group = 4; 3295 else if (channel_info[chnl] <= 64) 3296 group = 5; 3297 else if (channel_info[chnl] <= 112) 3298 group = 6; 3299 else if (channel_info[chnl] <= 126) 3300 group = 7; 3301 else if (channel_info[chnl] <= 140) 3302 group = 8; 3303 else if (channel_info[chnl] <= 153) 3304 group = 9; 3305 else if (channel_info[chnl] <= 159) 3306 group = 10; 3307 else 3308 group = 11; 3309 return group; 3310} 3311 3312void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) 3313{ 3314 struct rtl_priv *rtlpriv = rtl_priv(hw); 3315 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3316 unsigned long flags; 3317 u8 value8; 3318 u16 i; 3319 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); 3320 3321 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 3322 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3323 value8 = rtl_read_byte(rtlpriv, mac_reg); 3324 value8 |= BIT(1); 3325 rtl_write_byte(rtlpriv, mac_reg, value8); 3326 } else { 3327 value8 = rtl_read_byte(rtlpriv, mac_reg); 3328 value8 &= (~BIT(1)); 3329 rtl_write_byte(rtlpriv, mac_reg, value8); 3330 } 3331 3332 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3333 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3334 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3335 } else { 3336 spin_lock_irqsave(&globalmutex_power, flags); 3337 if (rtlhal->interfaceindex == 0) { 3338 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3339 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3340 } else { 3341 value8 = rtl_read_byte(rtlpriv, REG_MAC1); 3342 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); 3343 } 3344 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3345 spin_unlock_irqrestore(&globalmutex_power, flags); 3346 for (i = 0; i < 200; i++) { 3347 if ((value8 & BIT(7)) == 0) { 3348 break; 3349 } else { 3350 udelay(500); 3351 spin_lock_irqsave(&globalmutex_power, flags); 3352 value8 = rtl_read_byte(rtlpriv, 3353 REG_POWER_OFF_IN_PROCESS); 3354 spin_unlock_irqrestore(&globalmutex_power, 3355 flags); 3356 } 3357 } 3358 if (i == 200) 3359 RT_ASSERT(false, "Another mac power off over time\n"); 3360 } 3361} 3362 3363void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) 3364{ 3365 struct rtl_priv *rtlpriv = rtl_priv(hw); 3366 3367 switch (rtlpriv->rtlhal.macphymode) { 3368 case DUALMAC_DUALPHY: 3369 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3370 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3371 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3372 break; 3373 case DUALMAC_SINGLEPHY: 3374 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); 3375 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3376 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3377 break; 3378 case SINGLEMAC_SINGLEPHY: 3379 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3380 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); 3381 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 3382 break; 3383 default: 3384 break; 3385 } 3386} 3387 3388void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) 3389{ 3390 struct rtl_priv *rtlpriv = rtl_priv(hw); 3391 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3392 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3393 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3394 u8 rfpath, i; 3395 3396 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 3397 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ 3398 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3399 /* r_select_5G for path_A/B,0x878 */ 3400 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); 3401 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); 3402 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); 3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); 3405 } 3406 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ 3407 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); 3408 /* fc_area 0xd2c */ 3409 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); 3410 /* 5G LAN ON */ 3411 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 3412 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 3413 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3414 0x40000100); 3415 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3416 0x40000100); 3417 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3418 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3419 BIT(10) | BIT(6) | BIT(5), 3420 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3421 (rtlefuse->eeprom_c9 & BIT(1)) | 3422 ((rtlefuse->eeprom_cc & BIT(1)) << 4)); 3423 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3424 BIT(10) | BIT(6) | BIT(5), 3425 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3426 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3427 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3428 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); 3429 } else { 3430 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3431 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3432 BIT(6) | BIT(5), 3433 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3434 (rtlefuse->eeprom_c9 & BIT(1)) | 3435 ((rtlefuse->eeprom_cc & BIT(1)) << 4) | 3436 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | 3437 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | 3438 ((rtlefuse->eeprom_cc & BIT(3)) << 18)); 3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3440 BIT(10) | BIT(6) | BIT(5), 3441 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3442 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3443 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3444 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 3445 BIT(10) | BIT(6) | BIT(5), 3446 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | 3447 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | 3448 ((rtlefuse->eeprom_cc & BIT(2)) << 3)); 3449 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3450 BIT(31) | BIT(15), 0); 3451 } 3452 /* 1.5V_LDO */ 3453 } else { 3454 /* r_select_5G for path_A/B */ 3455 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); 3456 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); 3457 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); 3459 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); 3460 } 3461 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ 3462 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); 3463 /* fc_area */ 3464 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); 3465 /* 5G LAN ON */ 3466 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 3467 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 3468 if (rtlefuse->internal_pa_5g[0]) 3469 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3470 0x2d4000b5); 3471 else 3472 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3473 0x20000080); 3474 if (rtlefuse->internal_pa_5g[1]) 3475 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3476 0x2d4000b5); 3477 else 3478 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3479 0x20000080); 3480 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3481 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3482 BIT(10) | BIT(6) | BIT(5), 3483 (rtlefuse->eeprom_cc & BIT(5))); 3484 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3485 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 3487 (rtlefuse->eeprom_cc & BIT(4)) >> 4); 3488 } else { 3489 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3490 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3491 BIT(6) | BIT(5), 3492 (rtlefuse->eeprom_cc & BIT(5)) | 3493 ((rtlefuse->eeprom_cc & BIT(7)) << 14)); 3494 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3495 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3496 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 3497 ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); 3498 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3499 BIT(31) | BIT(15), 3500 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | 3501 ((rtlefuse->eeprom_cc & BIT(6)) << 10)); 3502 } 3503 } 3504 /* update IQK related settings */ 3505 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 3506 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 3507 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); 3508 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 3509 BIT(26) | BIT(24), 0x00); 3510 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00); 3511 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); 3512 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); 3513 3514 /* Update RF */ 3515 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3516 rfpath++) { 3517 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3518 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */ 3519 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | 3520 BIT(18), 0); 3521 /* RF0x0b[16:14] =3b'111 */ 3522 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 3523 0x1c000, 0x07); 3524 } else { 3525 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */ 3526 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | 3527 BIT(16) | BIT(18), 3528 (BIT(16) | BIT(8)) >> 8); 3529 } 3530 } 3531 /* Update for all band. */ 3532 /* DMDP */ 3533 if (rtlphy->rf_type == RF_1T1R) { 3534 /* Use antenna 0,0xc04,0xd04 */ 3535 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); 3536 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 3537 3538 /* enable ad/da clock1 for dual-phy reg0x888 */ 3539 if (rtlhal->interfaceindex == 0) { 3540 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | 3541 BIT(13), 0x3); 3542 } else { 3543 rtl92d_phy_enable_anotherphy(hw, false); 3544 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3545 "MAC1 use DBI to update 0x888\n"); 3546 /* 0x888 */ 3547 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, 3548 rtl92de_read_dword_dbi(hw, 3549 RFPGA0_ADDALLOCKEN, 3550 BIT(3)) | BIT(12) | BIT(13), 3551 BIT(3)); 3552 rtl92d_phy_powerdown_anotherphy(hw, false); 3553 } 3554 } else { 3555 /* Single PHY */ 3556 /* Use antenna 0 & 1,0xc04,0xd04 */ 3557 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); 3558 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 3559 /* disable ad/da clock1,0x888 */ 3560 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 3561 } 3562 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3563 rfpath++) { 3564 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 3565 RF_CHNLBW, RFREG_OFFSET_MASK); 3566 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 3567 RFREG_OFFSET_MASK); 3568 } 3569 for (i = 0; i < 2; i++) 3570 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 3571 rtlphy->rfreg_chnlval[i]); 3572 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); 3573 3574} 3575 3576bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) 3577{ 3578 struct rtl_priv *rtlpriv = rtl_priv(hw); 3579 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3580 u8 u1btmp; 3581 unsigned long flags; 3582 3583 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3584 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3585 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3586 return true; 3587 } 3588 spin_lock_irqsave(&globalmutex_power, flags); 3589 if (rtlhal->interfaceindex == 0) { 3590 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3591 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3592 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3593 u1btmp &= MAC1_ON; 3594 } else { 3595 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3596 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); 3597 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3598 u1btmp &= MAC0_ON; 3599 } 3600 if (u1btmp) { 3601 spin_unlock_irqrestore(&globalmutex_power, flags); 3602 return false; 3603 } 3604 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3605 u1btmp |= BIT(7); 3606 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); 3607 spin_unlock_irqrestore(&globalmutex_power, flags); 3608 return true; 3609} 3610