1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL_WIFI_H__ 27#define __RTL_WIFI_H__ 28 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31#include <linux/sched.h> 32#include <linux/firmware.h> 33#include <linux/etherdevice.h> 34#include <linux/vmalloc.h> 35#include <linux/usb.h> 36#include <net/mac80211.h> 37#include <linux/completion.h> 38#include "debug.h" 39 40#define MASKBYTE0 0xff 41#define MASKBYTE1 0xff00 42#define MASKBYTE2 0xff0000 43#define MASKBYTE3 0xff000000 44#define MASKHWORD 0xffff0000 45#define MASKLWORD 0x0000ffff 46#define MASKDWORD 0xffffffff 47#define MASK12BITS 0xfff 48#define MASKH4BITS 0xf0000000 49#define MASKOFDM_D 0xffc00000 50#define MASKCCK 0x3f3f3f3f 51 52#define MASK4BITS 0x0f 53#define MASK20BITS 0xfffff 54#define RFREG_OFFSET_MASK 0xfffff 55 56#define MASKBYTE0 0xff 57#define MASKBYTE1 0xff00 58#define MASKBYTE2 0xff0000 59#define MASKBYTE3 0xff000000 60#define MASKHWORD 0xffff0000 61#define MASKLWORD 0x0000ffff 62#define MASKDWORD 0xffffffff 63#define MASK12BITS 0xfff 64#define MASKH4BITS 0xf0000000 65#define MASKOFDM_D 0xffc00000 66#define MASKCCK 0x3f3f3f3f 67 68#define MASK4BITS 0x0f 69#define MASK20BITS 0xfffff 70#define RFREG_OFFSET_MASK 0xfffff 71 72#define RF_CHANGE_BY_INIT 0 73#define RF_CHANGE_BY_IPS BIT(28) 74#define RF_CHANGE_BY_PS BIT(29) 75#define RF_CHANGE_BY_HW BIT(30) 76#define RF_CHANGE_BY_SW BIT(31) 77 78#define IQK_ADDA_REG_NUM 16 79#define IQK_MAC_REG_NUM 4 80#define IQK_THRESHOLD 8 81 82#define MAX_KEY_LEN 61 83#define KEY_BUF_SIZE 5 84 85/* QoS related. */ 86/*aci: 0x00 Best Effort*/ 87/*aci: 0x01 Background*/ 88/*aci: 0x10 Video*/ 89/*aci: 0x11 Voice*/ 90/*Max: define total number.*/ 91#define AC0_BE 0 92#define AC1_BK 1 93#define AC2_VI 2 94#define AC3_VO 3 95#define AC_MAX 4 96#define QOS_QUEUE_NUM 4 97#define RTL_MAC80211_NUM_QUEUE 5 98#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99#define RTL_USB_MAX_RX_COUNT 100 100#define QBSS_LOAD_SIZE 5 101#define MAX_WMMELE_LENGTH 64 102 103#define TOTAL_CAM_ENTRY 32 104 105/*slot time for 11g. */ 106#define RTL_SLOT_TIME_9 9 107#define RTL_SLOT_TIME_20 20 108 109/*related to tcp/ip. */ 110#define SNAP_SIZE 6 111#define PROTOC_TYPE_SIZE 2 112 113/*related with 802.11 frame*/ 114#define MAC80211_3ADDR_LEN 24 115#define MAC80211_4ADDR_LEN 30 116 117#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118#define CHANNEL_MAX_NUMBER_2G 14 119#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123#define CHANNEL_MAX_NUMBER_5G_80M 7 124#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to 126 *"phy_GetChnlGroup8812A" and 127 * "Hal_ReadTxPowerInfo8812A" 128 */ 129#define CHANNEL_MAX_NUMBER_5G_80M 7 130#define MAX_PG_GROUP 13 131#define CHANNEL_GROUP_MAX_2G 3 132#define CHANNEL_GROUP_IDX_5GL 3 133#define CHANNEL_GROUP_IDX_5GM 6 134#define CHANNEL_GROUP_IDX_5GH 9 135#define CHANNEL_GROUP_MAX_5G 9 136#define CHANNEL_MAX_NUMBER_2G 14 137#define AVG_THERMAL_NUM 8 138#define AVG_THERMAL_NUM_88E 4 139#define AVG_THERMAL_NUM_8723BE 4 140#define MAX_TID_COUNT 9 141 142/* for early mode */ 143#define FCS_LEN 4 144#define EM_HDR_LEN 8 145 146enum rtl8192c_h2c_cmd { 147 H2C_AP_OFFLOAD = 0, 148 H2C_SETPWRMODE = 1, 149 H2C_JOINBSSRPT = 2, 150 H2C_RSVDPAGE = 3, 151 H2C_RSSI_REPORT = 5, 152 H2C_RA_MASK = 6, 153 H2C_MACID_PS_MODE = 7, 154 H2C_P2P_PS_OFFLOAD = 8, 155 H2C_MAC_MODE_SEL = 9, 156 H2C_PWRM = 15, 157 H2C_P2P_PS_CTW_CMD = 24, 158 MAX_H2CCMD 159}; 160 161#define MAX_TX_COUNT 4 162#define MAX_REGULATION_NUM 4 163#define MAX_RF_PATH_NUM 4 164#define MAX_RATE_SECTION_NUM 6 165#define MAX_2_4G_BANDWITH_NUM 4 166#define MAX_5G_BANDWITH_NUM 4 167#define MAX_RF_PATH 4 168#define MAX_CHNL_GROUP_24G 6 169#define MAX_CHNL_GROUP_5G 14 170 171#define TX_PWR_BY_RATE_NUM_BAND 2 172#define TX_PWR_BY_RATE_NUM_RF 4 173#define TX_PWR_BY_RATE_NUM_SECTION 12 174#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 175#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 176 177#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 178 179#define DEL_SW_IDX_SZ 30 180#define BAND_NUM 3 181 182/* For now, it's just for 8192ee 183 * but not OK yet, keep it 0 184 */ 185#define DMA_IS_64BIT 0 186#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 187 188enum rf_tx_num { 189 RF_1TX = 0, 190 RF_2TX, 191 RF_MAX_TX_NUM, 192 RF_TX_NUM_NONIMPLEMENT, 193}; 194 195#define PACKET_NORMAL 0 196#define PACKET_DHCP 1 197#define PACKET_ARP 2 198#define PACKET_EAPOL 3 199 200#define MAX_SUPPORT_WOL_PATTERN_NUM 16 201#define RSVD_WOL_PATTERN_NUM 1 202#define WKFMCAM_ADDR_NUM 6 203#define WKFMCAM_SIZE 24 204 205#define MAX_WOL_BIT_MASK_SIZE 16 206/* MIN LEN keeps 13 here */ 207#define MIN_WOL_PATTERN_SIZE 13 208#define MAX_WOL_PATTERN_SIZE 128 209 210#define WAKE_ON_MAGIC_PACKET BIT(0) 211#define WAKE_ON_PATTERN_MATCH BIT(1) 212 213#define WOL_REASON_PTK_UPDATE BIT(0) 214#define WOL_REASON_GTK_UPDATE BIT(1) 215#define WOL_REASON_DISASSOC BIT(2) 216#define WOL_REASON_DEAUTH BIT(3) 217#define WOL_REASON_AP_LOST BIT(4) 218#define WOL_REASON_MAGIC_PKT BIT(5) 219#define WOL_REASON_UNICAST_PKT BIT(6) 220#define WOL_REASON_PATTERN_PKT BIT(7) 221#define WOL_REASON_RTD3_SSID_MATCH BIT(8) 222#define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 223#define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 224 225struct txpower_info_2g { 226 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 227 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 228 /*If only one tx, only BW20 and OFDM are used.*/ 229 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 230 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 231 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 232 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 233 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 234 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 235}; 236 237struct txpower_info_5g { 238 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 239 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 240 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 241 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 242 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 243 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 245}; 246 247enum rate_section { 248 CCK = 0, 249 OFDM, 250 HT_MCS0_MCS7, 251 HT_MCS8_MCS15, 252 VHT_1SSMCS0_1SSMCS9, 253 VHT_2SSMCS0_2SSMCS9, 254}; 255 256enum intf_type { 257 INTF_PCI = 0, 258 INTF_USB = 1, 259}; 260 261enum radio_path { 262 RF90_PATH_A = 0, 263 RF90_PATH_B = 1, 264 RF90_PATH_C = 2, 265 RF90_PATH_D = 3, 266}; 267 268enum regulation_txpwr_lmt { 269 TXPWR_LMT_FCC = 0, 270 TXPWR_LMT_MKK = 1, 271 TXPWR_LMT_ETSI = 2, 272 TXPWR_LMT_WW = 3, 273 274 TXPWR_LMT_MAX_REGULATION_NUM = 4 275}; 276 277enum rt_eeprom_type { 278 EEPROM_93C46, 279 EEPROM_93C56, 280 EEPROM_BOOT_EFUSE, 281}; 282 283enum ttl_status { 284 RTL_STATUS_INTERFACE_START = 0, 285}; 286 287enum hardware_type { 288 HARDWARE_TYPE_RTL8192E, 289 HARDWARE_TYPE_RTL8192U, 290 HARDWARE_TYPE_RTL8192SE, 291 HARDWARE_TYPE_RTL8192SU, 292 HARDWARE_TYPE_RTL8192CE, 293 HARDWARE_TYPE_RTL8192CU, 294 HARDWARE_TYPE_RTL8192DE, 295 HARDWARE_TYPE_RTL8192DU, 296 HARDWARE_TYPE_RTL8723AE, 297 HARDWARE_TYPE_RTL8723U, 298 HARDWARE_TYPE_RTL8188EE, 299 HARDWARE_TYPE_RTL8723BE, 300 HARDWARE_TYPE_RTL8192EE, 301 HARDWARE_TYPE_RTL8821AE, 302 HARDWARE_TYPE_RTL8812AE, 303 304 /* keep it last */ 305 HARDWARE_TYPE_NUM 306}; 307 308#define IS_HARDWARE_TYPE_8192SU(rtlhal) \ 309 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) 310#define IS_HARDWARE_TYPE_8192SE(rtlhal) \ 311 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 312#define IS_HARDWARE_TYPE_8192CE(rtlhal) \ 313 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) 314#define IS_HARDWARE_TYPE_8192CU(rtlhal) \ 315 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) 316#define IS_HARDWARE_TYPE_8192DE(rtlhal) \ 317 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) 318#define IS_HARDWARE_TYPE_8192DU(rtlhal) \ 319 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) 320#define IS_HARDWARE_TYPE_8723E(rtlhal) \ 321 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) 322#define IS_HARDWARE_TYPE_8723U(rtlhal) \ 323 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) 324#define IS_HARDWARE_TYPE_8192S(rtlhal) \ 325(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) 326#define IS_HARDWARE_TYPE_8192C(rtlhal) \ 327(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) 328#define IS_HARDWARE_TYPE_8192D(rtlhal) \ 329(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) 330#define IS_HARDWARE_TYPE_8723(rtlhal) \ 331(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) 332 333#define RX_HAL_IS_CCK_RATE(rxmcs) \ 334 ((rxmcs) == DESC92_RATE1M || \ 335 (rxmcs) == DESC92_RATE2M || \ 336 (rxmcs) == DESC92_RATE5_5M || \ 337 (rxmcs) == DESC92_RATE11M) 338 339enum scan_operation_backup_opt { 340 SCAN_OPT_BACKUP = 0, 341 SCAN_OPT_BACKUP_BAND0 = 0, 342 SCAN_OPT_BACKUP_BAND1, 343 SCAN_OPT_RESTORE, 344 SCAN_OPT_MAX 345}; 346 347/*RF state.*/ 348enum rf_pwrstate { 349 ERFON, 350 ERFSLEEP, 351 ERFOFF 352}; 353 354struct bb_reg_def { 355 u32 rfintfs; 356 u32 rfintfi; 357 u32 rfintfo; 358 u32 rfintfe; 359 u32 rf3wire_offset; 360 u32 rflssi_select; 361 u32 rftxgain_stage; 362 u32 rfhssi_para1; 363 u32 rfhssi_para2; 364 u32 rfsw_ctrl; 365 u32 rfagc_control1; 366 u32 rfagc_control2; 367 u32 rfrxiq_imbal; 368 u32 rfrx_afe; 369 u32 rftxiq_imbal; 370 u32 rftx_afe; 371 u32 rf_rb; /* rflssi_readback */ 372 u32 rf_rbpi; /* rflssi_readbackpi */ 373}; 374 375enum io_type { 376 IO_CMD_PAUSE_DM_BY_SCAN = 0, 377 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 378 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 379 IO_CMD_RESUME_DM_BY_SCAN = 2, 380}; 381 382enum hw_variables { 383 HW_VAR_ETHER_ADDR, 384 HW_VAR_MULTICAST_REG, 385 HW_VAR_BASIC_RATE, 386 HW_VAR_BSSID, 387 HW_VAR_MEDIA_STATUS, 388 HW_VAR_SECURITY_CONF, 389 HW_VAR_BEACON_INTERVAL, 390 HW_VAR_ATIM_WINDOW, 391 HW_VAR_LISTEN_INTERVAL, 392 HW_VAR_CS_COUNTER, 393 HW_VAR_DEFAULTKEY0, 394 HW_VAR_DEFAULTKEY1, 395 HW_VAR_DEFAULTKEY2, 396 HW_VAR_DEFAULTKEY3, 397 HW_VAR_SIFS, 398 HW_VAR_R2T_SIFS, 399 HW_VAR_DIFS, 400 HW_VAR_EIFS, 401 HW_VAR_SLOT_TIME, 402 HW_VAR_ACK_PREAMBLE, 403 HW_VAR_CW_CONFIG, 404 HW_VAR_CW_VALUES, 405 HW_VAR_RATE_FALLBACK_CONTROL, 406 HW_VAR_CONTENTION_WINDOW, 407 HW_VAR_RETRY_COUNT, 408 HW_VAR_TR_SWITCH, 409 HW_VAR_COMMAND, 410 HW_VAR_WPA_CONFIG, 411 HW_VAR_AMPDU_MIN_SPACE, 412 HW_VAR_SHORTGI_DENSITY, 413 HW_VAR_AMPDU_FACTOR, 414 HW_VAR_MCS_RATE_AVAILABLE, 415 HW_VAR_AC_PARAM, 416 HW_VAR_ACM_CTRL, 417 HW_VAR_DIS_Req_Qsize, 418 HW_VAR_CCX_CHNL_LOAD, 419 HW_VAR_CCX_NOISE_HISTOGRAM, 420 HW_VAR_CCX_CLM_NHM, 421 HW_VAR_TxOPLimit, 422 HW_VAR_TURBO_MODE, 423 HW_VAR_RF_STATE, 424 HW_VAR_RF_OFF_BY_HW, 425 HW_VAR_BUS_SPEED, 426 HW_VAR_SET_DEV_POWER, 427 428 HW_VAR_RCR, 429 HW_VAR_RATR_0, 430 HW_VAR_RRSR, 431 HW_VAR_CPU_RST, 432 HW_VAR_CHECK_BSSID, 433 HW_VAR_LBK_MODE, 434 HW_VAR_AES_11N_FIX, 435 HW_VAR_USB_RX_AGGR, 436 HW_VAR_USER_CONTROL_TURBO_MODE, 437 HW_VAR_RETRY_LIMIT, 438 HW_VAR_INIT_TX_RATE, 439 HW_VAR_TX_RATE_REG, 440 HW_VAR_EFUSE_USAGE, 441 HW_VAR_EFUSE_BYTES, 442 HW_VAR_AUTOLOAD_STATUS, 443 HW_VAR_RF_2R_DISABLE, 444 HW_VAR_SET_RPWM, 445 HW_VAR_H2C_FW_PWRMODE, 446 HW_VAR_H2C_FW_JOINBSSRPT, 447 HW_VAR_H2C_FW_MEDIASTATUSRPT, 448 HW_VAR_H2C_FW_P2P_PS_OFFLOAD, 449 HW_VAR_FW_PSMODE_STATUS, 450 HW_VAR_INIT_RTS_RATE, 451 HW_VAR_RESUME_CLK_ON, 452 HW_VAR_FW_LPS_ACTION, 453 HW_VAR_1X1_RECV_COMBINE, 454 HW_VAR_STOP_SEND_BEACON, 455 HW_VAR_TSF_TIMER, 456 HW_VAR_IO_CMD, 457 458 HW_VAR_RF_RECOVERY, 459 HW_VAR_H2C_FW_UPDATE_GTK, 460 HW_VAR_WF_MASK, 461 HW_VAR_WF_CRC, 462 HW_VAR_WF_IS_MAC_ADDR, 463 HW_VAR_H2C_FW_OFFLOAD, 464 HW_VAR_RESET_WFCRC, 465 466 HW_VAR_HANDLE_FW_C2H, 467 HW_VAR_DL_FW_RSVD_PAGE, 468 HW_VAR_AID, 469 HW_VAR_HW_SEQ_ENABLE, 470 HW_VAR_CORRECT_TSF, 471 HW_VAR_BCN_VALID, 472 HW_VAR_FWLPS_RF_ON, 473 HW_VAR_DUAL_TSF_RST, 474 HW_VAR_SWITCH_EPHY_WoWLAN, 475 HW_VAR_INT_MIGRATION, 476 HW_VAR_INT_AC, 477 HW_VAR_RF_TIMING, 478 479 HAL_DEF_WOWLAN, 480 HW_VAR_MRC, 481 HW_VAR_KEEP_ALIVE, 482 HW_VAR_NAV_UPPER, 483 484 HW_VAR_MGT_FILTER, 485 HW_VAR_CTRL_FILTER, 486 HW_VAR_DATA_FILTER, 487}; 488 489enum rt_media_status { 490 RT_MEDIA_DISCONNECT = 0, 491 RT_MEDIA_CONNECT = 1 492}; 493 494enum rt_oem_id { 495 RT_CID_DEFAULT = 0, 496 RT_CID_8187_ALPHA0 = 1, 497 RT_CID_8187_SERCOMM_PS = 2, 498 RT_CID_8187_HW_LED = 3, 499 RT_CID_8187_NETGEAR = 4, 500 RT_CID_WHQL = 5, 501 RT_CID_819X_CAMEO = 6, 502 RT_CID_819X_RUNTOP = 7, 503 RT_CID_819X_SENAO = 8, 504 RT_CID_TOSHIBA = 9, 505 RT_CID_819X_NETCORE = 10, 506 RT_CID_NETTRONIX = 11, 507 RT_CID_DLINK = 12, 508 RT_CID_PRONET = 13, 509 RT_CID_COREGA = 14, 510 RT_CID_819X_ALPHA = 15, 511 RT_CID_819X_SITECOM = 16, 512 RT_CID_CCX = 17, 513 RT_CID_819X_LENOVO = 18, 514 RT_CID_819X_QMI = 19, 515 RT_CID_819X_EDIMAX_BELKIN = 20, 516 RT_CID_819X_SERCOMM_BELKIN = 21, 517 RT_CID_819X_CAMEO1 = 22, 518 RT_CID_819X_MSI = 23, 519 RT_CID_819X_ACER = 24, 520 RT_CID_819X_HP = 27, 521 RT_CID_819X_CLEVO = 28, 522 RT_CID_819X_ARCADYAN_BELKIN = 29, 523 RT_CID_819X_SAMSUNG = 30, 524 RT_CID_819X_WNC_COREGA = 31, 525 RT_CID_819X_FOXCOON = 32, 526 RT_CID_819X_DELL = 33, 527 RT_CID_819X_PRONETS = 34, 528 RT_CID_819X_EDIMAX_ASUS = 35, 529 RT_CID_NETGEAR = 36, 530 RT_CID_PLANEX = 37, 531 RT_CID_CC_C = 38, 532}; 533 534enum hw_descs { 535 HW_DESC_OWN, 536 HW_DESC_RXOWN, 537 HW_DESC_TX_NEXTDESC_ADDR, 538 HW_DESC_TXBUFF_ADDR, 539 HW_DESC_RXBUFF_ADDR, 540 HW_DESC_RXPKT_LEN, 541 HW_DESC_RXERO, 542 HW_DESC_RX_PREPARE, 543}; 544 545enum prime_sc { 546 PRIME_CHNL_OFFSET_DONT_CARE = 0, 547 PRIME_CHNL_OFFSET_LOWER = 1, 548 PRIME_CHNL_OFFSET_UPPER = 2, 549}; 550 551enum rf_type { 552 RF_1T1R = 0, 553 RF_1T2R = 1, 554 RF_2T2R = 2, 555 RF_2T2R_GREEN = 3, 556}; 557 558enum ht_channel_width { 559 HT_CHANNEL_WIDTH_20 = 0, 560 HT_CHANNEL_WIDTH_20_40 = 1, 561 HT_CHANNEL_WIDTH_80 = 2, 562}; 563 564/* Ref: 802.11i sepc D10.0 7.3.2.25.1 565Cipher Suites Encryption Algorithms */ 566enum rt_enc_alg { 567 NO_ENCRYPTION = 0, 568 WEP40_ENCRYPTION = 1, 569 TKIP_ENCRYPTION = 2, 570 RSERVED_ENCRYPTION = 3, 571 AESCCMP_ENCRYPTION = 4, 572 WEP104_ENCRYPTION = 5, 573 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 574}; 575 576enum rtl_hal_state { 577 _HAL_STATE_STOP = 0, 578 _HAL_STATE_START = 1, 579}; 580 581enum rtl_desc92_rate { 582 DESC92_RATE1M = 0x00, 583 DESC92_RATE2M = 0x01, 584 DESC92_RATE5_5M = 0x02, 585 DESC92_RATE11M = 0x03, 586 587 DESC92_RATE6M = 0x04, 588 DESC92_RATE9M = 0x05, 589 DESC92_RATE12M = 0x06, 590 DESC92_RATE18M = 0x07, 591 DESC92_RATE24M = 0x08, 592 DESC92_RATE36M = 0x09, 593 DESC92_RATE48M = 0x0a, 594 DESC92_RATE54M = 0x0b, 595 596 DESC92_RATEMCS0 = 0x0c, 597 DESC92_RATEMCS1 = 0x0d, 598 DESC92_RATEMCS2 = 0x0e, 599 DESC92_RATEMCS3 = 0x0f, 600 DESC92_RATEMCS4 = 0x10, 601 DESC92_RATEMCS5 = 0x11, 602 DESC92_RATEMCS6 = 0x12, 603 DESC92_RATEMCS7 = 0x13, 604 DESC92_RATEMCS8 = 0x14, 605 DESC92_RATEMCS9 = 0x15, 606 DESC92_RATEMCS10 = 0x16, 607 DESC92_RATEMCS11 = 0x17, 608 DESC92_RATEMCS12 = 0x18, 609 DESC92_RATEMCS13 = 0x19, 610 DESC92_RATEMCS14 = 0x1a, 611 DESC92_RATEMCS15 = 0x1b, 612 DESC92_RATEMCS15_SG = 0x1c, 613 DESC92_RATEMCS32 = 0x20, 614}; 615 616enum rtl_var_map { 617 /*reg map */ 618 SYS_ISO_CTRL = 0, 619 SYS_FUNC_EN, 620 SYS_CLK, 621 MAC_RCR_AM, 622 MAC_RCR_AB, 623 MAC_RCR_ACRC32, 624 MAC_RCR_ACF, 625 MAC_RCR_AAP, 626 MAC_HIMR, 627 MAC_HIMRE, 628 MAC_HSISR, 629 630 /*efuse map */ 631 EFUSE_TEST, 632 EFUSE_CTRL, 633 EFUSE_CLK, 634 EFUSE_CLK_CTRL, 635 EFUSE_PWC_EV12V, 636 EFUSE_FEN_ELDR, 637 EFUSE_LOADER_CLK_EN, 638 EFUSE_ANA8M, 639 EFUSE_HWSET_MAX_SIZE, 640 EFUSE_MAX_SECTION_MAP, 641 EFUSE_REAL_CONTENT_SIZE, 642 EFUSE_OOB_PROTECT_BYTES_LEN, 643 EFUSE_ACCESS, 644 645 /*CAM map */ 646 RWCAM, 647 WCAMI, 648 RCAMO, 649 CAMDBG, 650 SECR, 651 SEC_CAM_NONE, 652 SEC_CAM_WEP40, 653 SEC_CAM_TKIP, 654 SEC_CAM_AES, 655 SEC_CAM_WEP104, 656 657 /*IMR map */ 658 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 659 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 660 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 661 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 662 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 663 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 664 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 665 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 666 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 667 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 668 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 669 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 670 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 671 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 672 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 673 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 674 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 675 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 676 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 677 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 678 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 679 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 680 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 681 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 682 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 683 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 684 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 685 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 686 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 687 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 688 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 689 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 690 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 691 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 692 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 693 * RTL_IMR_TBDER) */ 694 RTL_IMR_C2HCMD, /*fw interrupt*/ 695 696 /*CCK Rates, TxHT = 0 */ 697 RTL_RC_CCK_RATE1M, 698 RTL_RC_CCK_RATE2M, 699 RTL_RC_CCK_RATE5_5M, 700 RTL_RC_CCK_RATE11M, 701 702 /*OFDM Rates, TxHT = 0 */ 703 RTL_RC_OFDM_RATE6M, 704 RTL_RC_OFDM_RATE9M, 705 RTL_RC_OFDM_RATE12M, 706 RTL_RC_OFDM_RATE18M, 707 RTL_RC_OFDM_RATE24M, 708 RTL_RC_OFDM_RATE36M, 709 RTL_RC_OFDM_RATE48M, 710 RTL_RC_OFDM_RATE54M, 711 712 RTL_RC_HT_RATEMCS7, 713 RTL_RC_HT_RATEMCS15, 714 715 RTL_RC_VHT_RATE_1SS_MCS7, 716 RTL_RC_VHT_RATE_1SS_MCS8, 717 RTL_RC_VHT_RATE_1SS_MCS9, 718 RTL_RC_VHT_RATE_2SS_MCS7, 719 RTL_RC_VHT_RATE_2SS_MCS8, 720 RTL_RC_VHT_RATE_2SS_MCS9, 721 722 /*keep it last */ 723 RTL_VAR_MAP_MAX, 724}; 725 726/*Firmware PS mode for control LPS.*/ 727enum _fw_ps_mode { 728 FW_PS_ACTIVE_MODE = 0, 729 FW_PS_MIN_MODE = 1, 730 FW_PS_MAX_MODE = 2, 731 FW_PS_DTIM_MODE = 3, 732 FW_PS_VOIP_MODE = 4, 733 FW_PS_UAPSD_WMM_MODE = 5, 734 FW_PS_UAPSD_MODE = 6, 735 FW_PS_IBSS_MODE = 7, 736 FW_PS_WWLAN_MODE = 8, 737 FW_PS_PM_Radio_Off = 9, 738 FW_PS_PM_Card_Disable = 10, 739}; 740 741enum rt_psmode { 742 EACTIVE, /*Active/Continuous access. */ 743 EMAXPS, /*Max power save mode. */ 744 EFASTPS, /*Fast power save mode. */ 745 EAUTOPS, /*Auto power save mode. */ 746}; 747 748/*LED related.*/ 749enum led_ctl_mode { 750 LED_CTL_POWER_ON = 1, 751 LED_CTL_LINK = 2, 752 LED_CTL_NO_LINK = 3, 753 LED_CTL_TX = 4, 754 LED_CTL_RX = 5, 755 LED_CTL_SITE_SURVEY = 6, 756 LED_CTL_POWER_OFF = 7, 757 LED_CTL_START_TO_LINK = 8, 758 LED_CTL_START_WPS = 9, 759 LED_CTL_STOP_WPS = 10, 760}; 761 762enum rtl_led_pin { 763 LED_PIN_GPIO0, 764 LED_PIN_LED0, 765 LED_PIN_LED1, 766 LED_PIN_LED2 767}; 768 769/*QoS related.*/ 770/*acm implementation method.*/ 771enum acm_method { 772 eAcmWay0_SwAndHw = 0, 773 eAcmWay1_HW = 1, 774 EACMWAY2_SW = 2, 775}; 776 777enum macphy_mode { 778 SINGLEMAC_SINGLEPHY = 0, 779 DUALMAC_DUALPHY, 780 DUALMAC_SINGLEPHY, 781}; 782 783enum band_type { 784 BAND_ON_2_4G = 0, 785 BAND_ON_5G, 786 BAND_ON_BOTH, 787 BANDMAX 788}; 789 790/*aci/aifsn Field. 791Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 792union aci_aifsn { 793 u8 char_data; 794 795 struct { 796 u8 aifsn:4; 797 u8 acm:1; 798 u8 aci:2; 799 u8 reserved:1; 800 } f; /* Field */ 801}; 802 803/*mlme related.*/ 804enum wireless_mode { 805 WIRELESS_MODE_UNKNOWN = 0x00, 806 WIRELESS_MODE_A = 0x01, 807 WIRELESS_MODE_B = 0x02, 808 WIRELESS_MODE_G = 0x04, 809 WIRELESS_MODE_AUTO = 0x08, 810 WIRELESS_MODE_N_24G = 0x10, 811 WIRELESS_MODE_N_5G = 0x20, 812 WIRELESS_MODE_AC_5G = 0x40, 813 WIRELESS_MODE_AC_24G = 0x80, 814 WIRELESS_MODE_AC_ONLY = 0x100, 815 WIRELESS_MODE_MAX = 0x800 816}; 817 818#define IS_WIRELESS_MODE_A(wirelessmode) \ 819 (wirelessmode == WIRELESS_MODE_A) 820#define IS_WIRELESS_MODE_B(wirelessmode) \ 821 (wirelessmode == WIRELESS_MODE_B) 822#define IS_WIRELESS_MODE_G(wirelessmode) \ 823 (wirelessmode == WIRELESS_MODE_G) 824#define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 825 (wirelessmode == WIRELESS_MODE_N_24G) 826#define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 827 (wirelessmode == WIRELESS_MODE_N_5G) 828 829enum ratr_table_mode { 830 RATR_INX_WIRELESS_NGB = 0, 831 RATR_INX_WIRELESS_NG = 1, 832 RATR_INX_WIRELESS_NB = 2, 833 RATR_INX_WIRELESS_N = 3, 834 RATR_INX_WIRELESS_GB = 4, 835 RATR_INX_WIRELESS_G = 5, 836 RATR_INX_WIRELESS_B = 6, 837 RATR_INX_WIRELESS_MC = 7, 838 RATR_INX_WIRELESS_A = 8, 839 RATR_INX_WIRELESS_AC_5N = 8, 840 RATR_INX_WIRELESS_AC_24N = 9, 841}; 842 843enum rtl_link_state { 844 MAC80211_NOLINK = 0, 845 MAC80211_LINKING = 1, 846 MAC80211_LINKED = 2, 847 MAC80211_LINKED_SCANNING = 3, 848}; 849 850enum act_category { 851 ACT_CAT_QOS = 1, 852 ACT_CAT_DLS = 2, 853 ACT_CAT_BA = 3, 854 ACT_CAT_HT = 7, 855 ACT_CAT_WMM = 17, 856}; 857 858enum ba_action { 859 ACT_ADDBAREQ = 0, 860 ACT_ADDBARSP = 1, 861 ACT_DELBA = 2, 862}; 863 864enum rt_polarity_ctl { 865 RT_POLARITY_LOW_ACT = 0, 866 RT_POLARITY_HIGH_ACT = 1, 867}; 868 869/* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 870enum fw_wow_reason_v2 { 871 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 872 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 873 FW_WOW_V2_DISASSOC_EVENT = 0x04, 874 FW_WOW_V2_DEAUTH_EVENT = 0x08, 875 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 876 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 877 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 878 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 879 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 880 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 881 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 882 FW_WOW_V2_REASON_MAX = 0xff, 883}; 884 885enum wolpattern_type { 886 UNICAST_PATTERN = 0, 887 MULTICAST_PATTERN = 1, 888 BROADCAST_PATTERN = 2, 889 DONT_CARE_DA = 3, 890 UNKNOWN_TYPE = 4, 891}; 892 893struct octet_string { 894 u8 *octet; 895 u16 length; 896}; 897 898struct rtl_hdr_3addr { 899 __le16 frame_ctl; 900 __le16 duration_id; 901 u8 addr1[ETH_ALEN]; 902 u8 addr2[ETH_ALEN]; 903 u8 addr3[ETH_ALEN]; 904 __le16 seq_ctl; 905 u8 payload[0]; 906} __packed; 907 908struct rtl_info_element { 909 u8 id; 910 u8 len; 911 u8 data[0]; 912} __packed; 913 914struct rtl_probe_rsp { 915 struct rtl_hdr_3addr header; 916 u32 time_stamp[2]; 917 __le16 beacon_interval; 918 __le16 capability; 919 /*SSID, supported rates, FH params, DS params, 920 CF params, IBSS params, TIM (if beacon), RSN */ 921 struct rtl_info_element info_element[0]; 922} __packed; 923 924/*LED related.*/ 925/*ledpin Identify how to implement this SW led.*/ 926struct rtl_led { 927 void *hw; 928 enum rtl_led_pin ledpin; 929 bool ledon; 930}; 931 932struct rtl_led_ctl { 933 bool led_opendrain; 934 struct rtl_led sw_led0; 935 struct rtl_led sw_led1; 936}; 937 938struct rtl_qos_parameters { 939 __le16 cw_min; 940 __le16 cw_max; 941 u8 aifs; 942 u8 flag; 943 __le16 tx_op; 944} __packed; 945 946struct rt_smooth_data { 947 u32 elements[100]; /*array to store values */ 948 u32 index; /*index to current array to store */ 949 u32 total_num; /*num of valid elements */ 950 u32 total_val; /*sum of valid elements */ 951}; 952 953struct false_alarm_statistics { 954 u32 cnt_parity_fail; 955 u32 cnt_rate_illegal; 956 u32 cnt_crc8_fail; 957 u32 cnt_mcs_fail; 958 u32 cnt_fast_fsync_fail; 959 u32 cnt_sb_search_fail; 960 u32 cnt_ofdm_fail; 961 u32 cnt_cck_fail; 962 u32 cnt_all; 963 u32 cnt_ofdm_cca; 964 u32 cnt_cck_cca; 965 u32 cnt_cca_all; 966 u32 cnt_bw_usc; 967 u32 cnt_bw_lsc; 968}; 969 970struct init_gain { 971 u8 xaagccore1; 972 u8 xbagccore1; 973 u8 xcagccore1; 974 u8 xdagccore1; 975 u8 cca; 976 977}; 978 979struct wireless_stats { 980 unsigned long txbytesunicast; 981 unsigned long txbytesmulticast; 982 unsigned long txbytesbroadcast; 983 unsigned long rxbytesunicast; 984 985 long rx_snr_db[4]; 986 /*Correct smoothed ss in Dbm, only used 987 in driver to report real power now. */ 988 long recv_signal_power; 989 long signal_quality; 990 long last_sigstrength_inpercent; 991 992 u32 rssi_calculate_cnt; 993 u32 pwdb_all_cnt; 994 995 /*Transformed, in dbm. Beautified signal 996 strength for UI, not correct. */ 997 long signal_strength; 998 999 u8 rx_rssi_percentage[4]; 1000 u8 rx_evm_dbm[4]; 1001 u8 rx_evm_percentage[2]; 1002 1003 u16 rx_cfo_short[4]; 1004 u16 rx_cfo_tail[4]; 1005 1006 struct rt_smooth_data ui_rssi; 1007 struct rt_smooth_data ui_link_quality; 1008}; 1009 1010struct rate_adaptive { 1011 u8 rate_adaptive_disabled; 1012 u8 ratr_state; 1013 u16 reserve; 1014 1015 u32 high_rssi_thresh_for_ra; 1016 u32 high2low_rssi_thresh_for_ra; 1017 u8 low2high_rssi_thresh_for_ra40m; 1018 u32 low_rssi_thresh_for_ra40m; 1019 u8 low2high_rssi_thresh_for_ra20m; 1020 u32 low_rssi_thresh_for_ra20m; 1021 u32 upper_rssi_threshold_ratr; 1022 u32 middleupper_rssi_threshold_ratr; 1023 u32 middle_rssi_threshold_ratr; 1024 u32 middlelow_rssi_threshold_ratr; 1025 u32 low_rssi_threshold_ratr; 1026 u32 ultralow_rssi_threshold_ratr; 1027 u32 low_rssi_threshold_ratr_40m; 1028 u32 low_rssi_threshold_ratr_20m; 1029 u8 ping_rssi_enable; 1030 u32 ping_rssi_ratr; 1031 u32 ping_rssi_thresh_for_ra; 1032 u32 last_ratr; 1033 u8 pre_ratr_state; 1034 u8 ldpc_thres; 1035 bool use_ldpc; 1036 bool lower_rts_rate; 1037 bool is_special_data; 1038}; 1039 1040struct regd_pair_mapping { 1041 u16 reg_dmnenum; 1042 u16 reg_5ghz_ctl; 1043 u16 reg_2ghz_ctl; 1044}; 1045 1046struct dynamic_primary_cca { 1047 u8 pricca_flag; 1048 u8 intf_flag; 1049 u8 intf_type; 1050 u8 dup_rts_flag; 1051 u8 monitor_flag; 1052 u8 ch_offset; 1053 u8 mf_state; 1054}; 1055 1056struct rtl_regulatory { 1057 char alpha2[2]; 1058 u16 country_code; 1059 u16 max_power_level; 1060 u32 tp_scale; 1061 u16 current_rd; 1062 u16 current_rd_ext; 1063 int16_t power_limit; 1064 struct regd_pair_mapping *regpair; 1065}; 1066 1067struct rtl_rfkill { 1068 bool rfkill_state; /*0 is off, 1 is on */ 1069}; 1070 1071/*for P2P PS**/ 1072#define P2P_MAX_NOA_NUM 2 1073 1074enum p2p_role { 1075 P2P_ROLE_DISABLE = 0, 1076 P2P_ROLE_DEVICE = 1, 1077 P2P_ROLE_CLIENT = 2, 1078 P2P_ROLE_GO = 3 1079}; 1080 1081enum p2p_ps_state { 1082 P2P_PS_DISABLE = 0, 1083 P2P_PS_ENABLE = 1, 1084 P2P_PS_SCAN = 2, 1085 P2P_PS_SCAN_DONE = 3, 1086 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1087}; 1088 1089enum p2p_ps_mode { 1090 P2P_PS_NONE = 0, 1091 P2P_PS_CTWINDOW = 1, 1092 P2P_PS_NOA = 2, 1093 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1094}; 1095 1096struct rtl_p2p_ps_info { 1097 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1098 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1099 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1100 /* Client traffic window. A period of time in TU after TBTT. */ 1101 u8 ctwindow; 1102 u8 opp_ps; /* opportunistic power save. */ 1103 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1104 /* Count for owner, Type of client. */ 1105 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1106 /* Max duration for owner, preferred or min acceptable duration 1107 * for client. 1108 */ 1109 u32 noa_duration[P2P_MAX_NOA_NUM]; 1110 /* Length of interval for owner, preferred or max acceptable intervali 1111 * of client. 1112 */ 1113 u32 noa_interval[P2P_MAX_NOA_NUM]; 1114 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1115 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1116}; 1117 1118struct p2p_ps_offload_t { 1119 u8 offload_en:1; 1120 u8 role:1; /* 1: Owner, 0: Client */ 1121 u8 ctwindow_en:1; 1122 u8 noa0_en:1; 1123 u8 noa1_en:1; 1124 u8 allstasleep:1; 1125 u8 discovery:1; 1126 u8 reserved:1; 1127}; 1128 1129#define IQK_MATRIX_REG_NUM 8 1130#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1131 1132struct iqk_matrix_regs { 1133 bool iqk_done; 1134 long value[1][IQK_MATRIX_REG_NUM]; 1135}; 1136 1137struct phy_parameters { 1138 u16 length; 1139 u32 *pdata; 1140}; 1141 1142enum hw_param_tab_index { 1143 PHY_REG_2T, 1144 PHY_REG_1T, 1145 PHY_REG_PG, 1146 RADIOA_2T, 1147 RADIOB_2T, 1148 RADIOA_1T, 1149 RADIOB_1T, 1150 MAC_REG, 1151 AGCTAB_2T, 1152 AGCTAB_1T, 1153 MAX_TAB 1154}; 1155 1156struct rtl_phy { 1157 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1158 struct init_gain initgain_backup; 1159 enum io_type current_io_type; 1160 1161 u8 rf_mode; 1162 u8 rf_type; 1163 u8 current_chan_bw; 1164 u8 set_bwmode_inprogress; 1165 u8 sw_chnl_inprogress; 1166 u8 sw_chnl_stage; 1167 u8 sw_chnl_step; 1168 u8 current_channel; 1169 u8 h2c_box_num; 1170 u8 set_io_inprogress; 1171 u8 lck_inprogress; 1172 1173 /* record for power tracking */ 1174 s32 reg_e94; 1175 s32 reg_e9c; 1176 s32 reg_ea4; 1177 s32 reg_eac; 1178 s32 reg_eb4; 1179 s32 reg_ebc; 1180 s32 reg_ec4; 1181 s32 reg_ecc; 1182 u8 rfpienable; 1183 u8 reserve_0; 1184 u16 reserve_1; 1185 u32 reg_c04, reg_c08, reg_874; 1186 u32 adda_backup[16]; 1187 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1188 u32 iqk_bb_backup[10]; 1189 bool iqk_initialized; 1190 1191 bool rfpath_rx_enable[MAX_RF_PATH]; 1192 u8 reg_837; 1193 /* Dual mac */ 1194 bool need_iqk; 1195 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1196 1197 bool rfpi_enable; 1198 bool iqk_in_progress; 1199 1200 u8 pwrgroup_cnt; 1201 u8 cck_high_power; 1202 /* this is for 88E & 8723A */ 1203 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1204 /* MAX_PG_GROUP groups of pwr diff by rates */ 1205 u32 mcs_offset[MAX_PG_GROUP][16]; 1206 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1207 [TX_PWR_BY_RATE_NUM_RF] 1208 [TX_PWR_BY_RATE_NUM_RF] 1209 [TX_PWR_BY_RATE_NUM_SECTION]; 1210 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1211 [TX_PWR_BY_RATE_NUM_RF] 1212 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1213 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1214 [TX_PWR_BY_RATE_NUM_RF] 1215 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1216 u8 default_initialgain[4]; 1217 1218 /* the current Tx power level */ 1219 u8 cur_cck_txpwridx; 1220 u8 cur_ofdm24g_txpwridx; 1221 u8 cur_bw20_txpwridx; 1222 u8 cur_bw40_txpwridx; 1223 1224 char txpwr_limit_2_4g[MAX_REGULATION_NUM] 1225 [MAX_2_4G_BANDWITH_NUM] 1226 [MAX_RATE_SECTION_NUM] 1227 [CHANNEL_MAX_NUMBER_2G] 1228 [MAX_RF_PATH_NUM]; 1229 char txpwr_limit_5g[MAX_REGULATION_NUM] 1230 [MAX_5G_BANDWITH_NUM] 1231 [MAX_RATE_SECTION_NUM] 1232 [CHANNEL_MAX_NUMBER_5G] 1233 [MAX_RF_PATH_NUM]; 1234 1235 u32 rfreg_chnlval[2]; 1236 bool apk_done; 1237 u32 reg_rf3c[2]; /* pathA / pathB */ 1238 1239 u32 backup_rf_0x1a;/*92ee*/ 1240 /* bfsync */ 1241 u8 framesync; 1242 u32 framesync_c34; 1243 1244 u8 num_total_rfpath; 1245 struct phy_parameters hwparam_tables[MAX_TAB]; 1246 u16 rf_pathmap; 1247 1248 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1249 enum rt_polarity_ctl polarity_ctl; 1250}; 1251 1252#define MAX_TID_COUNT 9 1253#define RTL_AGG_STOP 0 1254#define RTL_AGG_PROGRESS 1 1255#define RTL_AGG_START 2 1256#define RTL_AGG_OPERATIONAL 3 1257#define RTL_AGG_OFF 0 1258#define RTL_AGG_ON 1 1259#define RTL_RX_AGG_START 1 1260#define RTL_RX_AGG_STOP 0 1261#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1262#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1263 1264struct rtl_ht_agg { 1265 u16 txq_id; 1266 u16 wait_for_ba; 1267 u16 start_idx; 1268 u64 bitmap; 1269 u32 rate_n_flags; 1270 u8 agg_state; 1271 u8 rx_agg_state; 1272}; 1273 1274struct rssi_sta { 1275 long undec_sm_pwdb; 1276 long undec_sm_cck; 1277}; 1278 1279struct rtl_tid_data { 1280 u16 seq_number; 1281 struct rtl_ht_agg agg; 1282}; 1283 1284struct rtl_sta_info { 1285 struct list_head list; 1286 u8 ratr_index; 1287 u8 wireless_mode; 1288 u8 mimo_ps; 1289 u8 mac_addr[ETH_ALEN]; 1290 struct rtl_tid_data tids[MAX_TID_COUNT]; 1291 1292 /* just used for ap adhoc or mesh*/ 1293 struct rssi_sta rssi_stat; 1294} __packed; 1295 1296struct rtl_priv; 1297struct rtl_io { 1298 struct device *dev; 1299 struct mutex bb_mutex; 1300 1301 /*PCI MEM map */ 1302 unsigned long pci_mem_end; /*shared mem end */ 1303 unsigned long pci_mem_start; /*shared mem start */ 1304 1305 /*PCI IO map */ 1306 unsigned long pci_base_addr; /*device I/O address */ 1307 1308 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1309 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1310 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1311 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1312 u16 len); 1313 1314 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1315 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1316 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1317 1318}; 1319 1320struct rtl_mac { 1321 u8 mac_addr[ETH_ALEN]; 1322 u8 mac80211_registered; 1323 u8 beacon_enabled; 1324 1325 u32 tx_ss_num; 1326 u32 rx_ss_num; 1327 1328 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 1329 struct ieee80211_hw *hw; 1330 struct ieee80211_vif *vif; 1331 enum nl80211_iftype opmode; 1332 1333 /*Probe Beacon management */ 1334 struct rtl_tid_data tids[MAX_TID_COUNT]; 1335 enum rtl_link_state link_state; 1336 1337 int n_channels; 1338 int n_bitrates; 1339 1340 bool offchan_delay; 1341 u8 p2p; /*using p2p role*/ 1342 bool p2p_in_use; 1343 1344 /*filters */ 1345 u32 rx_conf; 1346 u16 rx_mgt_filter; 1347 u16 rx_ctrl_filter; 1348 u16 rx_data_filter; 1349 1350 bool act_scanning; 1351 u8 cnt_after_linked; 1352 bool skip_scan; 1353 1354 /* early mode */ 1355 /* skb wait queue */ 1356 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1357 1358 u8 ht_stbc_cap; 1359 u8 ht_cur_stbc; 1360 1361 /*vht support*/ 1362 u8 vht_enable; 1363 u8 bw_80; 1364 u8 vht_cur_ldpc; 1365 u8 vht_cur_stbc; 1366 u8 vht_stbc_cap; 1367 u8 vht_ldpc_cap; 1368 1369 /*RDG*/ 1370 bool rdg_en; 1371 1372 /*AP*/ 1373 u8 bssid[ETH_ALEN] __aligned(2); 1374 u32 vendor; 1375 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1376 u32 basic_rates; /* b/g rates */ 1377 u8 ht_enable; 1378 u8 sgi_40; 1379 u8 sgi_20; 1380 u8 bw_40; 1381 u16 mode; /* wireless mode */ 1382 u8 slot_time; 1383 u8 short_preamble; 1384 u8 use_cts_protect; 1385 u8 cur_40_prime_sc; 1386 u8 cur_40_prime_sc_bk; 1387 u8 cur_80_prime_sc; 1388 u64 tsf; 1389 u8 retry_short; 1390 u8 retry_long; 1391 u16 assoc_id; 1392 bool hiddenssid; 1393 1394 /*IBSS*/ 1395 int beacon_interval; 1396 1397 /*AMPDU*/ 1398 u8 min_space_cfg; /*For Min spacing configurations */ 1399 u8 max_mss_density; 1400 u8 current_ampdu_factor; 1401 u8 current_ampdu_density; 1402 1403 /*QOS & EDCA */ 1404 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1405 struct rtl_qos_parameters ac[AC_MAX]; 1406 1407 /* counters */ 1408 u64 last_txok_cnt; 1409 u64 last_rxok_cnt; 1410 u32 last_bt_edca_ul; 1411 u32 last_bt_edca_dl; 1412}; 1413 1414struct btdm_8723 { 1415 bool all_off; 1416 bool agc_table_en; 1417 bool adc_back_off_on; 1418 bool b2_ant_hid_en; 1419 bool low_penalty_rate_adaptive; 1420 bool rf_rx_lpf_shrink; 1421 bool reject_aggre_pkt; 1422 bool tra_tdma_on; 1423 u8 tra_tdma_nav; 1424 u8 tra_tdma_ant; 1425 bool tdma_on; 1426 u8 tdma_ant; 1427 u8 tdma_nav; 1428 u8 tdma_dac_swing; 1429 u8 fw_dac_swing_lvl; 1430 bool ps_tdma_on; 1431 u8 ps_tdma_byte[5]; 1432 bool pta_on; 1433 u32 val_0x6c0; 1434 u32 val_0x6c8; 1435 u32 val_0x6cc; 1436 bool sw_dac_swing_on; 1437 u32 sw_dac_swing_lvl; 1438 u32 wlan_act_hi; 1439 u32 wlan_act_lo; 1440 u32 bt_retry_index; 1441 bool dec_bt_pwr; 1442 bool ignore_wlan_act; 1443}; 1444 1445struct bt_coexist_8723 { 1446 u32 high_priority_tx; 1447 u32 high_priority_rx; 1448 u32 low_priority_tx; 1449 u32 low_priority_rx; 1450 u8 c2h_bt_info; 1451 bool c2h_bt_info_req_sent; 1452 bool c2h_bt_inquiry_page; 1453 u32 bt_inq_page_start_time; 1454 u8 bt_retry_cnt; 1455 u8 c2h_bt_info_original; 1456 u8 bt_inquiry_page_cnt; 1457 struct btdm_8723 btdm; 1458}; 1459 1460struct rtl_hal { 1461 struct ieee80211_hw *hw; 1462 bool driver_is_goingto_unload; 1463 bool up_first_time; 1464 bool first_init; 1465 bool being_init_adapter; 1466 bool bbrf_ready; 1467 bool mac_func_enable; 1468 bool pre_edcca_enable; 1469 struct bt_coexist_8723 hal_coex_8723; 1470 1471 enum intf_type interface; 1472 u16 hw_type; /*92c or 92d or 92s and so on */ 1473 u8 ic_class; 1474 u8 oem_id; 1475 u32 version; /*version of chip */ 1476 u8 state; /*stop 0, start 1 */ 1477 u8 board_type; 1478 u8 external_pa; 1479 1480 u8 pa_mode; 1481 u8 pa_type_2g; 1482 u8 pa_type_5g; 1483 u8 lna_type_2g; 1484 u8 lna_type_5g; 1485 u8 external_pa_2g; 1486 u8 external_lna_2g; 1487 u8 external_pa_5g; 1488 u8 external_lna_5g; 1489 u8 rfe_type; 1490 1491 /*firmware */ 1492 u32 fwsize; 1493 u8 *pfirmware; 1494 u16 fw_version; 1495 u16 fw_subversion; 1496 bool h2c_setinprogress; 1497 u8 last_hmeboxnum; 1498 bool fw_ready; 1499 /*Reserve page start offset except beacon in TxQ. */ 1500 u8 fw_rsvdpage_startoffset; 1501 u8 h2c_txcmd_seq; 1502 u8 current_ra_rate; 1503 1504 /* FW Cmd IO related */ 1505 u16 fwcmd_iomap; 1506 u32 fwcmd_ioparam; 1507 bool set_fwcmd_inprogress; 1508 u8 current_fwcmd_io; 1509 1510 struct p2p_ps_offload_t p2p_ps_offload; 1511 bool fw_clk_change_in_progress; 1512 bool allow_sw_to_change_hwclc; 1513 u8 fw_ps_state; 1514 /**/ 1515 bool driver_going2unload; 1516 1517 /*AMPDU init min space*/ 1518 u8 minspace_cfg; /*For Min spacing configurations */ 1519 1520 /* Dual mac */ 1521 enum macphy_mode macphymode; 1522 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1523 enum band_type current_bandtypebackup; 1524 enum band_type bandset; 1525 /* dual MAC 0--Mac0 1--Mac1 */ 1526 u32 interfaceindex; 1527 /* just for DualMac S3S4 */ 1528 u8 macphyctl_reg; 1529 bool earlymode_enable; 1530 u8 max_earlymode_num; 1531 /* Dual mac*/ 1532 bool during_mac0init_radiob; 1533 bool during_mac1init_radioa; 1534 bool reloadtxpowerindex; 1535 /* True if IMR or IQK have done 1536 for 2.4G in scan progress */ 1537 bool load_imrandiqk_setting_for2g; 1538 1539 bool disable_amsdu_8k; 1540 bool master_of_dmsp; 1541 bool slave_of_dmsp; 1542 1543 u16 rx_tag;/*for 92ee*/ 1544 u8 rts_en; 1545 1546 /*for wowlan*/ 1547 bool wow_enable; 1548 bool enter_pnp_sleep; 1549 bool wake_from_pnp_sleep; 1550 bool wow_enabled; 1551 __kernel_time_t last_suspend_sec; 1552 u32 wowlan_fwsize; 1553 u8 *wowlan_firmware; 1554 1555 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1556 1557 bool real_wow_v2_enable; 1558 bool re_init_llt_table; 1559}; 1560 1561struct rtl_security { 1562 /*default 0 */ 1563 bool use_sw_sec; 1564 1565 bool being_setkey; 1566 bool use_defaultkey; 1567 /*Encryption Algorithm for Unicast Packet */ 1568 enum rt_enc_alg pairwise_enc_algorithm; 1569 /*Encryption Algorithm for Brocast/Multicast */ 1570 enum rt_enc_alg group_enc_algorithm; 1571 /*Cam Entry Bitmap */ 1572 u32 hwsec_cam_bitmap; 1573 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1574 /*local Key buffer, indx 0 is for 1575 pairwise key 1-4 is for agoup key. */ 1576 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1577 u8 key_len[KEY_BUF_SIZE]; 1578 1579 /*The pointer of Pairwise Key, 1580 it always points to KeyBuf[4] */ 1581 u8 *pairwise_key; 1582}; 1583 1584#define ASSOCIATE_ENTRY_NUM 33 1585 1586struct fast_ant_training { 1587 u8 bssid[6]; 1588 u8 antsel_rx_keep_0; 1589 u8 antsel_rx_keep_1; 1590 u8 antsel_rx_keep_2; 1591 u32 ant_sum[7]; 1592 u32 ant_cnt[7]; 1593 u32 ant_ave[7]; 1594 u8 fat_state; 1595 u32 train_idx; 1596 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1597 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1598 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1599 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1600 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1601 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1602 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1603 u8 rx_idle_ant; 1604 bool becomelinked; 1605}; 1606 1607struct dm_phy_dbg_info { 1608 char rx_snrdb[4]; 1609 u64 num_qry_phy_status; 1610 u64 num_qry_phy_status_cck; 1611 u64 num_qry_phy_status_ofdm; 1612 u16 num_qry_beacon_pkt; 1613 u16 num_non_be_pkt; 1614 s32 rx_evm[4]; 1615}; 1616 1617struct rtl_dm { 1618 /*PHY status for Dynamic Management */ 1619 long entry_min_undec_sm_pwdb; 1620 long undec_sm_cck; 1621 long undec_sm_pwdb; /*out dm */ 1622 long entry_max_undec_sm_pwdb; 1623 s32 ofdm_pkt_cnt; 1624 bool dm_initialgain_enable; 1625 bool dynamic_txpower_enable; 1626 bool current_turbo_edca; 1627 bool is_any_nonbepkts; /*out dm */ 1628 bool is_cur_rdlstate; 1629 bool txpower_trackinginit; 1630 bool disable_framebursting; 1631 bool cck_inch14; 1632 bool txpower_tracking; 1633 bool useramask; 1634 bool rfpath_rxenable[4]; 1635 bool inform_fw_driverctrldm; 1636 bool current_mrc_switch; 1637 u8 txpowercount; 1638 u8 powerindex_backup[6]; 1639 1640 u8 thermalvalue_rxgain; 1641 u8 thermalvalue_iqk; 1642 u8 thermalvalue_lck; 1643 u8 thermalvalue; 1644 u8 last_dtp_lvl; 1645 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1646 u8 thermalvalue_avg_index; 1647 bool done_txpower; 1648 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1649 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1650 u8 dm_flag_tmp; 1651 u8 dm_type; 1652 u8 dm_rssi_sel; 1653 u8 txpower_track_control; 1654 bool interrupt_migration; 1655 bool disable_tx_int; 1656 char ofdm_index[MAX_RF_PATH]; 1657 u8 default_ofdm_index; 1658 u8 default_cck_index; 1659 char cck_index; 1660 char delta_power_index[MAX_RF_PATH]; 1661 char delta_power_index_last[MAX_RF_PATH]; 1662 char power_index_offset[MAX_RF_PATH]; 1663 char absolute_ofdm_swing_idx[MAX_RF_PATH]; 1664 char remnant_ofdm_swing_idx[MAX_RF_PATH]; 1665 char remnant_cck_idx; 1666 bool modify_txagc_flag_path_a; 1667 bool modify_txagc_flag_path_b; 1668 1669 bool one_entry_only; 1670 struct dm_phy_dbg_info dbginfo; 1671 1672 /* Dynamic ATC switch */ 1673 bool atc_status; 1674 bool large_cfo_hit; 1675 bool is_freeze; 1676 int cfo_tail[2]; 1677 int cfo_ave_pre; 1678 int crystal_cap; 1679 u8 cfo_threshold; 1680 u32 packet_count; 1681 u32 packet_count_pre; 1682 u8 tx_rate; 1683 1684 /*88e tx power tracking*/ 1685 u8 swing_idx_ofdm[MAX_RF_PATH]; 1686 u8 swing_idx_ofdm_cur; 1687 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1688 bool swing_flag_ofdm; 1689 u8 swing_idx_cck; 1690 u8 swing_idx_cck_cur; 1691 u8 swing_idx_cck_base; 1692 bool swing_flag_cck; 1693 1694 char swing_diff_2g; 1695 char swing_diff_5g; 1696 1697 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ]; 1698 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ]; 1699 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ]; 1700 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ]; 1701 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ]; 1702 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ]; 1703 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ]; 1704 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ]; 1705 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ]; 1706 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ]; 1707 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ]; 1708 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ]; 1709 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ]; 1710 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ]; 1711 1712 /* DMSP */ 1713 bool supp_phymode_switch; 1714 1715 /* DulMac */ 1716 struct fast_ant_training fat_table; 1717 1718 u8 resp_tx_path; 1719 u8 path_sel; 1720 u32 patha_sum; 1721 u32 pathb_sum; 1722 u32 patha_cnt; 1723 u32 pathb_cnt; 1724 1725 u8 pre_channel; 1726 u8 *p_channel; 1727 u8 linked_interval; 1728 1729 u64 last_tx_ok_cnt; 1730 u64 last_rx_ok_cnt; 1731}; 1732 1733#define EFUSE_MAX_LOGICAL_SIZE 512 1734 1735struct rtl_efuse { 1736 bool autoLoad_ok; 1737 bool bootfromefuse; 1738 u16 max_physical_size; 1739 1740 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1741 u16 efuse_usedbytes; 1742 u8 efuse_usedpercentage; 1743#ifdef EFUSE_REPG_WORKAROUND 1744 bool efuse_re_pg_sec1flag; 1745 u8 efuse_re_pg_data[8]; 1746#endif 1747 1748 u8 autoload_failflag; 1749 u8 autoload_status; 1750 1751 short epromtype; 1752 u16 eeprom_vid; 1753 u16 eeprom_did; 1754 u16 eeprom_svid; 1755 u16 eeprom_smid; 1756 u8 eeprom_oemid; 1757 u16 eeprom_channelplan; 1758 u8 eeprom_version; 1759 u8 board_type; 1760 u8 external_pa; 1761 1762 u8 dev_addr[6]; 1763 u8 wowlan_enable; 1764 u8 antenna_div_cfg; 1765 u8 antenna_div_type; 1766 1767 bool txpwr_fromeprom; 1768 u8 eeprom_crystalcap; 1769 u8 eeprom_tssi[2]; 1770 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1771 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1772 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1773 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1774 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1775 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1776 1777 u8 internal_pa_5g[2]; /* pathA / pathB */ 1778 u8 eeprom_c9; 1779 u8 eeprom_cc; 1780 1781 /*For power group */ 1782 u8 eeprom_pwrgroup[2][3]; 1783 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1784 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1785 1786 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1787 /*For HT 40MHZ pwr */ 1788 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1789 /*For HT 40MHZ pwr */ 1790 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1791 1792 /*--------------------------------------------------------* 1793 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1794 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1795 * define new arrays in Windows code. 1796 * BUT, in linux code, we use the same array for all ICs. 1797 * 1798 * The Correspondance relation between two arrays is: 1799 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1800 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1801 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1802 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1803 * 1804 * Sizes of these arrays are decided by the larger ones. 1805 */ 1806 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1807 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1808 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1809 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1810 1811 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1812 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1813 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1814 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1815 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1816 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1817 1818 u8 txpwr_safetyflag; /* Band edge enable flag */ 1819 u16 eeprom_txpowerdiff; 1820 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1821 u8 antenna_txpwdiff[3]; 1822 1823 u8 eeprom_regulatory; 1824 u8 eeprom_thermalmeter; 1825 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1826 u16 tssi_13dbm; 1827 u8 crystalcap; /* CrystalCap. */ 1828 u8 delta_iqk; 1829 u8 delta_lck; 1830 1831 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1832 bool apk_thermalmeterignore; 1833 1834 bool b1x1_recvcombine; 1835 bool b1ss_support; 1836 1837 /*channel plan */ 1838 u8 channel_plan; 1839}; 1840 1841struct rtl_ps_ctl { 1842 bool pwrdomain_protect; 1843 bool in_powersavemode; 1844 bool rfchange_inprogress; 1845 bool swrf_processing; 1846 bool hwradiooff; 1847 /* 1848 * just for PCIE ASPM 1849 * If it supports ASPM, Offset[560h] = 0x40, 1850 * otherwise Offset[560h] = 0x00. 1851 * */ 1852 bool support_aspm; 1853 bool support_backdoor; 1854 1855 /*for LPS */ 1856 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1857 bool swctrl_lps; 1858 bool leisure_ps; 1859 bool fwctrl_lps; 1860 u8 fwctrl_psmode; 1861 /*For Fw control LPS mode */ 1862 u8 reg_fwctrl_lps; 1863 /*Record Fw PS mode status. */ 1864 bool fw_current_inpsmode; 1865 u8 reg_max_lps_awakeintvl; 1866 bool report_linked; 1867 bool low_power_enable;/*for 32k*/ 1868 1869 /*for IPS */ 1870 bool inactiveps; 1871 1872 u32 rfoff_reason; 1873 1874 /*RF OFF Level */ 1875 u32 cur_ps_level; 1876 u32 reg_rfps_level; 1877 1878 /*just for PCIE ASPM */ 1879 u8 const_amdpci_aspm; 1880 bool pwrdown_mode; 1881 1882 enum rf_pwrstate inactive_pwrstate; 1883 enum rf_pwrstate rfpwr_state; /*cur power state */ 1884 1885 /* for SW LPS*/ 1886 bool sw_ps_enabled; 1887 bool state; 1888 bool state_inap; 1889 bool multi_buffered; 1890 u16 nullfunc_seq; 1891 unsigned int dtim_counter; 1892 unsigned int sleep_ms; 1893 unsigned long last_sleep_jiffies; 1894 unsigned long last_awake_jiffies; 1895 unsigned long last_delaylps_stamp_jiffies; 1896 unsigned long last_dtim; 1897 unsigned long last_beacon; 1898 unsigned long last_action; 1899 unsigned long last_slept; 1900 1901 /*For P2P PS */ 1902 struct rtl_p2p_ps_info p2p_ps_info; 1903 u8 pwr_mode; 1904 u8 smart_ps; 1905 1906 /* wake up on line */ 1907 u8 wo_wlan_mode; 1908 u8 arp_offload_enable; 1909 u8 gtk_offload_enable; 1910 /* Used for WOL, indicates the reason for waking event.*/ 1911 u32 wakeup_reason; 1912 /* Record the last waking time for comparison with setting key. */ 1913 u64 last_wakeup_time; 1914}; 1915 1916struct rtl_stats { 1917 u8 psaddr[ETH_ALEN]; 1918 u32 mac_time[2]; 1919 s8 rssi; 1920 u8 signal; 1921 u8 noise; 1922 u8 rate; /* hw desc rate */ 1923 u8 received_channel; 1924 u8 control; 1925 u8 mask; 1926 u8 freq; 1927 u16 len; 1928 u64 tsf; 1929 u32 beacon_time; 1930 u8 nic_type; 1931 u16 length; 1932 u8 signalquality; /*in 0-100 index. */ 1933 /* 1934 * Real power in dBm for this packet, 1935 * no beautification and aggregation. 1936 * */ 1937 s32 recvsignalpower; 1938 s8 rxpower; /*in dBm Translate from PWdB */ 1939 u8 signalstrength; /*in 0-100 index. */ 1940 u16 hwerror:1; 1941 u16 crc:1; 1942 u16 icv:1; 1943 u16 shortpreamble:1; 1944 u16 antenna:1; 1945 u16 decrypted:1; 1946 u16 wakeup:1; 1947 u32 timestamp_low; 1948 u32 timestamp_high; 1949 bool shift; 1950 1951 u8 rx_drvinfo_size; 1952 u8 rx_bufshift; 1953 bool isampdu; 1954 bool isfirst_ampdu; 1955 bool rx_is40Mhzpacket; 1956 u8 rx_packet_bw; 1957 u32 rx_pwdb_all; 1958 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 1959 s8 rx_mimo_signalquality[4]; 1960 u8 rx_mimo_evm_dbm[4]; 1961 u16 cfo_short[4]; /* per-path's Cfo_short */ 1962 u16 cfo_tail[4]; 1963 1964 s8 rx_mimo_sig_qual[4]; 1965 u8 rx_pwr[4]; /* per-path's pwdb */ 1966 u8 rx_snr[4]; /* per-path's SNR */ 1967 u8 bandwidth; 1968 u8 bt_coex_pwr_adjust; 1969 bool packet_matchbssid; 1970 bool is_cck; 1971 bool is_ht; 1972 bool packet_toself; 1973 bool packet_beacon; /*for rssi */ 1974 char cck_adc_pwdb[4]; /*for rx path selection */ 1975 1976 bool is_vht; 1977 bool is_short_gi; 1978 u8 vht_nss; 1979 1980 u8 packet_report_type; 1981 1982 u32 macid; 1983 u8 wake_match; 1984 u32 bt_rx_rssi_percentage; 1985 u32 macid_valid_entry[2]; 1986}; 1987 1988 1989struct rt_link_detect { 1990 /* count for roaming */ 1991 u32 bcn_rx_inperiod; 1992 u32 roam_times; 1993 1994 u32 num_tx_in4period[4]; 1995 u32 num_rx_in4period[4]; 1996 1997 u32 num_tx_inperiod; 1998 u32 num_rx_inperiod; 1999 2000 bool busytraffic; 2001 bool tx_busy_traffic; 2002 bool rx_busy_traffic; 2003 bool higher_busytraffic; 2004 bool higher_busyrxtraffic; 2005 2006 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2007 u32 tidtx_inperiod[MAX_TID_COUNT]; 2008 bool higher_busytxtraffic[MAX_TID_COUNT]; 2009}; 2010 2011struct rtl_tcb_desc { 2012 u8 packet_bw:2; 2013 u8 multicast:1; 2014 u8 broadcast:1; 2015 2016 u8 rts_stbc:1; 2017 u8 rts_enable:1; 2018 u8 cts_enable:1; 2019 u8 rts_use_shortpreamble:1; 2020 u8 rts_use_shortgi:1; 2021 u8 rts_sc:1; 2022 u8 rts_bw:1; 2023 u8 rts_rate; 2024 2025 u8 use_shortgi:1; 2026 u8 use_shortpreamble:1; 2027 u8 use_driver_rate:1; 2028 u8 disable_ratefallback:1; 2029 2030 u8 ratr_index; 2031 u8 mac_id; 2032 u8 hw_rate; 2033 2034 u8 last_inipkt:1; 2035 u8 cmd_or_init:1; 2036 u8 queue_index; 2037 2038 /* early mode */ 2039 u8 empkt_num; 2040 /* The max value by HW */ 2041 u32 empkt_len[10]; 2042 bool tx_enable_sw_calc_duration; 2043}; 2044 2045struct rtl92c_firmware_header; 2046 2047struct rtl_wow_pattern { 2048 u8 type; 2049 u16 crc; 2050 u32 mask[4]; 2051}; 2052 2053struct rtl8723e_firmware_header; 2054 2055struct rtl_hal_ops { 2056 int (*init_sw_vars) (struct ieee80211_hw *hw); 2057 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2058 void (*read_chip_version)(struct ieee80211_hw *hw); 2059 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2060 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2061 u32 *p_inta, u32 *p_intb); 2062 int (*hw_init) (struct ieee80211_hw *hw); 2063 void (*hw_disable) (struct ieee80211_hw *hw); 2064 void (*hw_suspend) (struct ieee80211_hw *hw); 2065 void (*hw_resume) (struct ieee80211_hw *hw); 2066 void (*enable_interrupt) (struct ieee80211_hw *hw); 2067 void (*disable_interrupt) (struct ieee80211_hw *hw); 2068 int (*set_network_type) (struct ieee80211_hw *hw, 2069 enum nl80211_iftype type); 2070 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2071 bool check_bssid); 2072 void (*set_bw_mode) (struct ieee80211_hw *hw, 2073 enum nl80211_channel_type ch_type); 2074 u8(*switch_channel) (struct ieee80211_hw *hw); 2075 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2076 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2077 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2078 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2079 u32 add_msr, u32 rm_msr); 2080 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2081 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2082 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2083 struct ieee80211_sta *sta, u8 rssi_level); 2084 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2085 u8 *desc, u8 queue_index, 2086 struct sk_buff *skb, dma_addr_t addr); 2087 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2088 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2089 u8 queue_index); 2090 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2091 u8 queue_index); 2092 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2093 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2094 u8 *pbd_desc_tx, 2095 struct ieee80211_tx_info *info, 2096 struct ieee80211_sta *sta, 2097 struct sk_buff *skb, u8 hw_queue, 2098 struct rtl_tcb_desc *ptcb_desc); 2099 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2100 u32 buffer_len, bool bIsPsPoll); 2101 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2102 bool firstseg, bool lastseg, 2103 struct sk_buff *skb); 2104 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2105 struct rtl_stats *stats, 2106 struct ieee80211_rx_status *rx_status, 2107 u8 *pdesc, struct sk_buff *skb); 2108 void (*set_channel_access) (struct ieee80211_hw *hw); 2109 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2110 void (*dm_watchdog) (struct ieee80211_hw *hw); 2111 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2112 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2113 enum rf_pwrstate rfpwr_state); 2114 void (*led_control) (struct ieee80211_hw *hw, 2115 enum led_ctl_mode ledaction); 2116 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2117 u8 desc_name, u8 *val); 2118 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 2119 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2120 u8 hw_queue, u16 index); 2121 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2122 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2123 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2124 u8 *macaddr, bool is_group, u8 enc_algo, 2125 bool is_wepkey, bool clear_all); 2126 void (*init_sw_leds) (struct ieee80211_hw *hw); 2127 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2128 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2129 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2130 u32 data); 2131 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2132 u32 regaddr, u32 bitmask); 2133 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2134 u32 regaddr, u32 bitmask, u32 data); 2135 void (*linked_set_reg) (struct ieee80211_hw *hw); 2136 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2137 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2138 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2139 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2140 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2141 u8 *powerlevel); 2142 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2143 u8 *ppowerlevel, u8 channel); 2144 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2145 u8 configtype); 2146 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2147 u8 configtype); 2148 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2149 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2150 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2151 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2152 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2153 bool mstate); 2154 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2155 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2156 u32 cmd_len, u8 *p_cmdbuffer); 2157 bool (*get_btc_status) (void); 2158 bool (*is_fw_header)(struct rtl8723e_firmware_header *hdr); 2159 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2160 struct rtl_stats status, struct sk_buff *skb); 2161 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2162 struct rtl_wow_pattern *rtl_pattern, 2163 u8 index); 2164}; 2165 2166struct rtl_intf_ops { 2167 /*com */ 2168 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2169 int (*adapter_start) (struct ieee80211_hw *hw); 2170 void (*adapter_stop) (struct ieee80211_hw *hw); 2171 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2172 struct rtl_priv **buddy_priv); 2173 2174 int (*adapter_tx) (struct ieee80211_hw *hw, 2175 struct ieee80211_sta *sta, 2176 struct sk_buff *skb, 2177 struct rtl_tcb_desc *ptcb_desc); 2178 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2179 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2180 bool (*waitq_insert) (struct ieee80211_hw *hw, 2181 struct ieee80211_sta *sta, 2182 struct sk_buff *skb); 2183 2184 /*pci */ 2185 void (*disable_aspm) (struct ieee80211_hw *hw); 2186 void (*enable_aspm) (struct ieee80211_hw *hw); 2187 2188 /*usb */ 2189}; 2190 2191struct rtl_mod_params { 2192 /* default: 0 = using hardware encryption */ 2193 bool sw_crypto; 2194 2195 /* default: 0 = DBG_EMERG (0)*/ 2196 int debug; 2197 2198 /* default: 1 = using no linked power save */ 2199 bool inactiveps; 2200 2201 /* default: 1 = using linked sw power save */ 2202 bool swctrl_lps; 2203 2204 /* default: 1 = using linked fw power save */ 2205 bool fwctrl_lps; 2206 2207 /* default: 0 = not using MSI interrupts mode 2208 * submodules should set their own default value 2209 */ 2210 bool msi_support; 2211 2212 /* default 0: 1 means disable */ 2213 bool disable_watchdog; 2214}; 2215 2216struct rtl_hal_usbint_cfg { 2217 /* data - rx */ 2218 u32 in_ep_num; 2219 u32 rx_urb_num; 2220 u32 rx_max_size; 2221 2222 /* op - rx */ 2223 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2224 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2225 struct sk_buff_head *); 2226 2227 /* tx */ 2228 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2229 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2230 struct sk_buff *); 2231 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2232 struct sk_buff_head *); 2233 2234 /* endpoint mapping */ 2235 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2236 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2237}; 2238 2239struct rtl_hal_cfg { 2240 u8 bar_id; 2241 bool write_readback; 2242 char *name; 2243 char *fw_name; 2244 char *alt_fw_name; 2245 struct rtl_hal_ops *ops; 2246 struct rtl_mod_params *mod_params; 2247 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2248 2249 /*this map used for some registers or vars 2250 defined int HAL but used in MAIN */ 2251 u32 maps[RTL_VAR_MAP_MAX]; 2252 2253}; 2254 2255struct rtl_locks { 2256 /* mutex */ 2257 struct mutex conf_mutex; 2258 struct mutex ps_mutex; 2259 2260 /*spin lock */ 2261 spinlock_t ips_lock; 2262 spinlock_t irq_th_lock; 2263 spinlock_t irq_pci_lock; 2264 spinlock_t tx_lock; 2265 spinlock_t h2c_lock; 2266 spinlock_t rf_ps_lock; 2267 spinlock_t rf_lock; 2268 spinlock_t lps_lock; 2269 spinlock_t waitq_lock; 2270 spinlock_t entry_list_lock; 2271 spinlock_t usb_lock; 2272 2273 /*FW clock change */ 2274 spinlock_t fw_ps_lock; 2275 2276 /*Dual mac*/ 2277 spinlock_t cck_and_rw_pagea_lock; 2278 2279 /*Easy concurrent*/ 2280 spinlock_t check_sendpkt_lock; 2281 2282 spinlock_t iqk_lock; 2283}; 2284 2285struct rtl_works { 2286 struct ieee80211_hw *hw; 2287 2288 /*timer */ 2289 struct timer_list watchdog_timer; 2290 struct timer_list dualmac_easyconcurrent_retrytimer; 2291 struct timer_list fw_clockoff_timer; 2292 struct timer_list fast_antenna_training_timer; 2293 /*task */ 2294 struct tasklet_struct irq_tasklet; 2295 struct tasklet_struct irq_prepare_bcn_tasklet; 2296 2297 /*work queue */ 2298 struct workqueue_struct *rtl_wq; 2299 struct delayed_work watchdog_wq; 2300 struct delayed_work ips_nic_off_wq; 2301 2302 /* For SW LPS */ 2303 struct delayed_work ps_work; 2304 struct delayed_work ps_rfon_wq; 2305 struct delayed_work fwevt_wq; 2306 2307 struct work_struct lps_change_work; 2308 struct work_struct fill_h2c_cmd; 2309}; 2310 2311struct rtl_debug { 2312 u32 dbgp_type[DBGP_TYPE_MAX]; 2313 int global_debuglevel; 2314 u64 global_debugcomponents; 2315 2316 /* add for proc debug */ 2317 struct proc_dir_entry *proc_dir; 2318 char proc_name[20]; 2319}; 2320 2321#define MIMO_PS_STATIC 0 2322#define MIMO_PS_DYNAMIC 1 2323#define MIMO_PS_NOLIMIT 3 2324 2325struct rtl_dualmac_easy_concurrent_ctl { 2326 enum band_type currentbandtype_backfordmdp; 2327 bool close_bbandrf_for_dmsp; 2328 bool change_to_dmdp; 2329 bool change_to_dmsp; 2330 bool switch_in_process; 2331}; 2332 2333struct rtl_dmsp_ctl { 2334 bool activescan_for_slaveofdmsp; 2335 bool scan_for_anothermac_fordmsp; 2336 bool scan_for_itself_fordmsp; 2337 bool writedig_for_anothermacofdmsp; 2338 u32 curdigvalue_for_anothermacofdmsp; 2339 bool changecckpdstate_for_anothermacofdmsp; 2340 u8 curcckpdstate_for_anothermacofdmsp; 2341 bool changetxhighpowerlvl_for_anothermacofdmsp; 2342 u8 curtxhighlvl_for_anothermacofdmsp; 2343 long rssivalmin_for_anothermacofdmsp; 2344}; 2345 2346struct ps_t { 2347 u8 pre_ccastate; 2348 u8 cur_ccasate; 2349 u8 pre_rfstate; 2350 u8 cur_rfstate; 2351 u8 initialize; 2352 long rssi_val_min; 2353}; 2354 2355struct dig_t { 2356 u32 rssi_lowthresh; 2357 u32 rssi_highthresh; 2358 u32 fa_lowthresh; 2359 u32 fa_highthresh; 2360 long last_min_undec_pwdb_for_dm; 2361 long rssi_highpower_lowthresh; 2362 long rssi_highpower_highthresh; 2363 u32 recover_cnt; 2364 u32 pre_igvalue; 2365 u32 cur_igvalue; 2366 long rssi_val; 2367 u8 dig_enable_flag; 2368 u8 dig_ext_port_stage; 2369 u8 dig_algorithm; 2370 u8 dig_twoport_algorithm; 2371 u8 dig_dbgmode; 2372 u8 dig_slgorithm_switch; 2373 u8 cursta_cstate; 2374 u8 presta_cstate; 2375 u8 curmultista_cstate; 2376 u8 stop_dig; 2377 char back_val; 2378 char back_range_max; 2379 char back_range_min; 2380 u8 rx_gain_max; 2381 u8 rx_gain_min; 2382 u8 min_undec_pwdb_for_dm; 2383 u8 rssi_val_min; 2384 u8 pre_cck_cca_thres; 2385 u8 cur_cck_cca_thres; 2386 u8 pre_cck_pd_state; 2387 u8 cur_cck_pd_state; 2388 u8 pre_cck_fa_state; 2389 u8 cur_cck_fa_state; 2390 u8 pre_ccastate; 2391 u8 cur_ccasate; 2392 u8 large_fa_hit; 2393 u8 dig_dynamic_min; 2394 u8 dig_dynamic_min_1; 2395 u8 forbidden_igi; 2396 u8 dig_state; 2397 u8 dig_highpwrstate; 2398 u8 cur_sta_cstate; 2399 u8 pre_sta_cstate; 2400 u8 cur_ap_cstate; 2401 u8 pre_ap_cstate; 2402 u8 cur_pd_thstate; 2403 u8 pre_pd_thstate; 2404 u8 cur_cs_ratiostate; 2405 u8 pre_cs_ratiostate; 2406 u8 backoff_enable_flag; 2407 char backoffval_range_max; 2408 char backoffval_range_min; 2409 u8 dig_min_0; 2410 u8 dig_min_1; 2411 u8 bt30_cur_igi; 2412 bool media_connect_0; 2413 bool media_connect_1; 2414 2415 u32 antdiv_rssi_max; 2416 u32 rssi_max; 2417}; 2418 2419struct rtl_global_var { 2420 /* from this list we can get 2421 * other adapter's rtl_priv */ 2422 struct list_head glb_priv_list; 2423 spinlock_t glb_list_lock; 2424}; 2425 2426struct rtl_btc_info { 2427 u8 bt_type; 2428 u8 btcoexist; 2429 u8 ant_num; 2430}; 2431 2432struct bt_coexist_info { 2433 struct rtl_btc_ops *btc_ops; 2434 struct rtl_btc_info btc_info; 2435 /* EEPROM BT info. */ 2436 u8 eeprom_bt_coexist; 2437 u8 eeprom_bt_type; 2438 u8 eeprom_bt_ant_num; 2439 u8 eeprom_bt_ant_isol; 2440 u8 eeprom_bt_radio_shared; 2441 2442 u8 bt_coexistence; 2443 u8 bt_ant_num; 2444 u8 bt_coexist_type; 2445 u8 bt_state; 2446 u8 bt_cur_state; /* 0:on, 1:off */ 2447 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2448 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2449 u8 bt_service; 2450 u8 bt_radio_shared_type; 2451 u8 bt_rfreg_origin_1e; 2452 u8 bt_rfreg_origin_1f; 2453 u8 bt_rssi_state; 2454 u32 ratio_tx; 2455 u32 ratio_pri; 2456 u32 bt_edca_ul; 2457 u32 bt_edca_dl; 2458 2459 bool init_set; 2460 bool bt_busy_traffic; 2461 bool bt_traffic_mode_set; 2462 bool bt_non_traffic_mode_set; 2463 2464 bool fw_coexist_all_off; 2465 bool sw_coexist_all_off; 2466 bool hw_coexist_all_off; 2467 u32 cstate; 2468 u32 previous_state; 2469 u32 cstate_h; 2470 u32 previous_state_h; 2471 2472 u8 bt_pre_rssi_state; 2473 u8 bt_pre_rssi_state1; 2474 2475 u8 reg_bt_iso; 2476 u8 reg_bt_sco; 2477 bool balance_on; 2478 u8 bt_active_zero_cnt; 2479 bool cur_bt_disabled; 2480 bool pre_bt_disabled; 2481 2482 u8 bt_profile_case; 2483 u8 bt_profile_action; 2484 bool bt_busy; 2485 bool hold_for_bt_operation; 2486 u8 lps_counter; 2487}; 2488 2489struct rtl_btc_ops { 2490 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2491 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2492 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2493 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2494 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2495 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2496 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2497 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2498 enum rt_media_status mstatus); 2499 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2500 void (*btc_halt_notify) (void); 2501 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2502 u8 *tmp_buf, u8 length); 2503 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2504 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2505 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2506 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2507 u8 pkt_type); 2508}; 2509 2510struct proxim { 2511 bool proxim_on; 2512 2513 void *proximity_priv; 2514 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2515 struct sk_buff *skb); 2516 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2517}; 2518 2519struct rtl_priv { 2520 struct ieee80211_hw *hw; 2521 /* Used to load a second firmware */ 2522 void (*rtl_fw_second_cb)(struct rtl_priv *rtlpriv); 2523 struct completion firmware_loading_complete; 2524 struct list_head list; 2525 struct rtl_priv *buddy_priv; 2526 struct rtl_global_var *glb_var; 2527 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2528 struct rtl_dmsp_ctl dmsp_ctl; 2529 struct rtl_locks locks; 2530 struct rtl_works works; 2531 struct rtl_mac mac80211; 2532 struct rtl_hal rtlhal; 2533 struct rtl_regulatory regd; 2534 struct rtl_rfkill rfkill; 2535 struct rtl_io io; 2536 struct rtl_phy phy; 2537 struct rtl_dm dm; 2538 struct rtl_security sec; 2539 struct rtl_efuse efuse; 2540 2541 struct rtl_ps_ctl psc; 2542 struct rate_adaptive ra; 2543 struct dynamic_primary_cca primarycca; 2544 struct wireless_stats stats; 2545 struct rt_link_detect link_info; 2546 struct false_alarm_statistics falsealm_cnt; 2547 2548 struct rtl_rate_priv *rate_priv; 2549 2550 /* sta entry list for ap adhoc or mesh */ 2551 struct list_head entry_list; 2552 2553 struct rtl_debug dbg; 2554 int max_fw_size; 2555 2556 /* 2557 *hal_cfg : for diff cards 2558 *intf_ops : for diff interrface usb/pcie 2559 */ 2560 struct rtl_hal_cfg *cfg; 2561 struct rtl_intf_ops *intf_ops; 2562 2563 /*this var will be set by set_bit, 2564 and was used to indicate status of 2565 interface or hardware */ 2566 unsigned long status; 2567 2568 /* tables for dm */ 2569 struct dig_t dm_digtable; 2570 struct ps_t dm_pstable; 2571 2572 u32 reg_874; 2573 u32 reg_c70; 2574 u32 reg_85c; 2575 u32 reg_a74; 2576 bool reg_init; /* true if regs saved */ 2577 bool bt_operation_on; 2578 __le32 *usb_data; 2579 int usb_data_index; 2580 bool initialized; 2581 bool enter_ps; /* true when entering PS */ 2582 u8 rate_mask[5]; 2583 2584 /* intel Proximity, should be alloc mem 2585 * in intel Proximity module and can only 2586 * be used in intel Proximity mode 2587 */ 2588 struct proxim proximity; 2589 2590 /*for bt coexist use*/ 2591 struct bt_coexist_info btcoexist; 2592 2593 /* separate 92ee from other ICs, 2594 * 92ee use new trx flow. 2595 */ 2596 bool use_new_trx_flow; 2597 2598#ifdef CONFIG_PM 2599 struct wiphy_wowlan_support wowlan; 2600#endif 2601 /*This must be the last item so 2602 that it points to the data allocated 2603 beyond this structure like: 2604 rtl_pci_priv or rtl_usb_priv */ 2605 u8 priv[0] __aligned(sizeof(void *)); 2606}; 2607 2608#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2609#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2610#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2611#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2612#define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2613 2614 2615/*************************************** 2616 Bluetooth Co-existence Related 2617****************************************/ 2618 2619enum bt_ant_num { 2620 ANT_X2 = 0, 2621 ANT_X1 = 1, 2622}; 2623 2624enum bt_co_type { 2625 BT_2WIRE = 0, 2626 BT_ISSC_3WIRE = 1, 2627 BT_ACCEL = 2, 2628 BT_CSR_BC4 = 3, 2629 BT_CSR_BC8 = 4, 2630 BT_RTL8756 = 5, 2631 BT_RTL8723A = 6, 2632 BT_RTL8821A = 7, 2633 BT_RTL8723B = 8, 2634 BT_RTL8192E = 9, 2635 BT_RTL8812A = 11, 2636}; 2637 2638enum bt_total_ant_num { 2639 ANT_TOTAL_X2 = 0, 2640 ANT_TOTAL_X1 = 1 2641}; 2642 2643enum bt_cur_state { 2644 BT_OFF = 0, 2645 BT_ON = 1, 2646}; 2647 2648enum bt_service_type { 2649 BT_SCO = 0, 2650 BT_A2DP = 1, 2651 BT_HID = 2, 2652 BT_HID_IDLE = 3, 2653 BT_SCAN = 4, 2654 BT_IDLE = 5, 2655 BT_OTHER_ACTION = 6, 2656 BT_BUSY = 7, 2657 BT_OTHERBUSY = 8, 2658 BT_PAN = 9, 2659}; 2660 2661enum bt_radio_shared { 2662 BT_RADIO_SHARED = 0, 2663 BT_RADIO_INDIVIDUAL = 1, 2664}; 2665 2666 2667/**************************************** 2668 mem access macro define start 2669 Call endian free function when 2670 1. Read/write packet content. 2671 2. Before write integer to IO. 2672 3. After read integer from IO. 2673****************************************/ 2674/* Convert little data endian to host ordering */ 2675#define EF1BYTE(_val) \ 2676 ((u8)(_val)) 2677#define EF2BYTE(_val) \ 2678 (le16_to_cpu(_val)) 2679#define EF4BYTE(_val) \ 2680 (le32_to_cpu(_val)) 2681 2682/* Read data from memory */ 2683#define READEF1BYTE(_ptr) \ 2684 EF1BYTE(*((u8 *)(_ptr))) 2685/* Read le16 data from memory and convert to host ordering */ 2686#define READEF2BYTE(_ptr) \ 2687 EF2BYTE(*(_ptr)) 2688#define READEF4BYTE(_ptr) \ 2689 EF4BYTE(*(_ptr)) 2690 2691/* Write data to memory */ 2692#define WRITEEF1BYTE(_ptr, _val) \ 2693 (*((u8 *)(_ptr))) = EF1BYTE(_val) 2694/* Write le16 data to memory in host ordering */ 2695#define WRITEEF2BYTE(_ptr, _val) \ 2696 (*((u16 *)(_ptr))) = EF2BYTE(_val) 2697#define WRITEEF4BYTE(_ptr, _val) \ 2698 (*((u32 *)(_ptr))) = EF2BYTE(_val) 2699 2700/* Create a bit mask 2701 * Examples: 2702 * BIT_LEN_MASK_32(0) => 0x00000000 2703 * BIT_LEN_MASK_32(1) => 0x00000001 2704 * BIT_LEN_MASK_32(2) => 0x00000003 2705 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2706 */ 2707#define BIT_LEN_MASK_32(__bitlen) \ 2708 (0xFFFFFFFF >> (32 - (__bitlen))) 2709#define BIT_LEN_MASK_16(__bitlen) \ 2710 (0xFFFF >> (16 - (__bitlen))) 2711#define BIT_LEN_MASK_8(__bitlen) \ 2712 (0xFF >> (8 - (__bitlen))) 2713 2714/* Create an offset bit mask 2715 * Examples: 2716 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2717 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2718 */ 2719#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2720 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2721#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2722 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2723#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2724 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2725 2726/*Description: 2727 * Return 4-byte value in host byte ordering from 2728 * 4-byte pointer in little-endian system. 2729 */ 2730#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2731 (EF4BYTE(*((__le32 *)(__pstart)))) 2732#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2733 (EF2BYTE(*((__le16 *)(__pstart)))) 2734#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2735 (EF1BYTE(*((u8 *)(__pstart)))) 2736 2737/*Description: 2738Translate subfield (continuous bits in little-endian) of 4-byte 2739value to host byte ordering.*/ 2740#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2741 ( \ 2742 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2743 BIT_LEN_MASK_32(__bitlen) \ 2744 ) 2745#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2746 ( \ 2747 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2748 BIT_LEN_MASK_16(__bitlen) \ 2749 ) 2750#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2751 ( \ 2752 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2753 BIT_LEN_MASK_8(__bitlen) \ 2754 ) 2755 2756/* Description: 2757 * Mask subfield (continuous bits in little-endian) of 4-byte value 2758 * and return the result in 4-byte value in host byte ordering. 2759 */ 2760#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2761 ( \ 2762 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2763 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2764 ) 2765#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2766 ( \ 2767 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2768 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2769 ) 2770#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2771 ( \ 2772 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2773 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2774 ) 2775 2776/* Description: 2777 * Set subfield of little-endian 4-byte value to specified value. 2778 */ 2779#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2780 *((u32 *)(__pstart)) = \ 2781 ( \ 2782 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2783 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2784 ); 2785#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2786 *((u16 *)(__pstart)) = \ 2787 ( \ 2788 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2789 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2790 ); 2791#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2792 *((u8 *)(__pstart)) = EF1BYTE \ 2793 ( \ 2794 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2795 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2796 ); 2797 2798#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2799 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2800 2801/**************************************** 2802 mem access macro define end 2803****************************************/ 2804 2805#define byte(x, n) ((x >> (8 * n)) & 0xff) 2806 2807#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2808#define RTL_WATCH_DOG_TIME 2000 2809#define MSECS(t) msecs_to_jiffies(t) 2810#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2811#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2812#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2813#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2814#define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2815 2816#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2817#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2818#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2819/*NIC halt, re-initialize hw parameters*/ 2820#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2821#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2822#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2823/*Always enable ASPM and Clock Req in initialization.*/ 2824#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2825/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2826#define RT_PS_LEVEL_ASPM BIT(7) 2827/*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2828#define RT_RF_LPS_DISALBE_2R BIT(30) 2829#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2830#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2831 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2832#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2833 (ppsc->cur_ps_level &= (~(_ps_flg))) 2834#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2835 (ppsc->cur_ps_level |= _ps_flg) 2836 2837#define container_of_dwork_rtl(x, y, z) \ 2838 container_of(container_of(x, struct delayed_work, work), y, z) 2839 2840#define FILL_OCTET_STRING(_os, _octet, _len) \ 2841 (_os).octet = (u8 *)(_octet); \ 2842 (_os).length = (_len); 2843 2844#define CP_MACADDR(des, src) \ 2845 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2846 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2847 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2848 2849#define LDPC_HT_ENABLE_RX BIT(0) 2850#define LDPC_HT_ENABLE_TX BIT(1) 2851#define LDPC_HT_TEST_TX_ENABLE BIT(2) 2852#define LDPC_HT_CAP_TX BIT(3) 2853 2854#define STBC_HT_ENABLE_RX BIT(0) 2855#define STBC_HT_ENABLE_TX BIT(1) 2856#define STBC_HT_TEST_TX_ENABLE BIT(2) 2857#define STBC_HT_CAP_TX BIT(3) 2858 2859#define LDPC_VHT_ENABLE_RX BIT(0) 2860#define LDPC_VHT_ENABLE_TX BIT(1) 2861#define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2862#define LDPC_VHT_CAP_TX BIT(3) 2863 2864#define STBC_VHT_ENABLE_RX BIT(0) 2865#define STBC_VHT_ENABLE_TX BIT(1) 2866#define STBC_VHT_TEST_TX_ENABLE BIT(2) 2867#define STBC_VHT_CAP_TX BIT(3) 2868 2869static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2870{ 2871 return rtlpriv->io.read8_sync(rtlpriv, addr); 2872} 2873 2874static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 2875{ 2876 return rtlpriv->io.read16_sync(rtlpriv, addr); 2877} 2878 2879static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 2880{ 2881 return rtlpriv->io.read32_sync(rtlpriv, addr); 2882} 2883 2884static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 2885{ 2886 rtlpriv->io.write8_async(rtlpriv, addr, val8); 2887 2888 if (rtlpriv->cfg->write_readback) 2889 rtlpriv->io.read8_sync(rtlpriv, addr); 2890} 2891 2892static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 2893{ 2894 rtlpriv->io.write16_async(rtlpriv, addr, val16); 2895 2896 if (rtlpriv->cfg->write_readback) 2897 rtlpriv->io.read16_sync(rtlpriv, addr); 2898} 2899 2900static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 2901 u32 addr, u32 val32) 2902{ 2903 rtlpriv->io.write32_async(rtlpriv, addr, val32); 2904 2905 if (rtlpriv->cfg->write_readback) 2906 rtlpriv->io.read32_sync(rtlpriv, addr); 2907} 2908 2909static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 2910 u32 regaddr, u32 bitmask) 2911{ 2912 struct rtl_priv *rtlpriv = hw->priv; 2913 2914 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 2915} 2916 2917static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 2918 u32 bitmask, u32 data) 2919{ 2920 struct rtl_priv *rtlpriv = hw->priv; 2921 2922 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 2923} 2924 2925static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 2926 enum radio_path rfpath, u32 regaddr, 2927 u32 bitmask) 2928{ 2929 struct rtl_priv *rtlpriv = hw->priv; 2930 2931 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 2932} 2933 2934static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 2935 enum radio_path rfpath, u32 regaddr, 2936 u32 bitmask, u32 data) 2937{ 2938 struct rtl_priv *rtlpriv = hw->priv; 2939 2940 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 2941} 2942 2943static inline bool is_hal_stop(struct rtl_hal *rtlhal) 2944{ 2945 return (_HAL_STATE_STOP == rtlhal->state); 2946} 2947 2948static inline void set_hal_start(struct rtl_hal *rtlhal) 2949{ 2950 rtlhal->state = _HAL_STATE_START; 2951} 2952 2953static inline void set_hal_stop(struct rtl_hal *rtlhal) 2954{ 2955 rtlhal->state = _HAL_STATE_STOP; 2956} 2957 2958static inline u8 get_rf_type(struct rtl_phy *rtlphy) 2959{ 2960 return rtlphy->rf_type; 2961} 2962 2963static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 2964{ 2965 return (struct ieee80211_hdr *)(skb->data); 2966} 2967 2968static inline __le16 rtl_get_fc(struct sk_buff *skb) 2969{ 2970 return rtl_get_hdr(skb)->frame_control; 2971} 2972 2973static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 2974{ 2975 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 2976} 2977 2978static inline u16 rtl_get_tid(struct sk_buff *skb) 2979{ 2980 return rtl_get_tid_h(rtl_get_hdr(skb)); 2981} 2982 2983static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 2984 struct ieee80211_vif *vif, 2985 const u8 *bssid) 2986{ 2987 return ieee80211_find_sta(vif, bssid); 2988} 2989 2990static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 2991 u8 *mac_addr) 2992{ 2993 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2994 return ieee80211_find_sta(mac->vif, mac_addr); 2995} 2996 2997#endif 2998