1/* 2 * Copyright (c) 2000-2014 LSI Corporation. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.26 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 18 * Added Manufacturing Page 11. 19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 20 * define. 21 * 06-26-07 02.00.02 Adding generic structure for product-specific 22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 23 * Rework of BIOS Page 2 configuration page. 24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 25 * forms. 26 * Added configuration pages IOC Page 8 and Driver 27 * Persistent Mapping Page 0. 28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 30 * RAID Physical Disk Pages 0 and 1, RAID Configuration 31 * Page 0). 32 * Added new value for AccessStatus field of SAS Device 33 * Page 0 (_SATA_NEEDS_INITIALIZATION). 34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 37 * NVDATA. 38 * Modified IOC Page 7 to use masks and added field for 39 * SASBroadcastPrimitiveMasks. 40 * Added MPI2_CONFIG_PAGE_BIOS_4. 41 * Added MPI2_CONFIG_PAGE_LOG_0. 42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 43 * Added SAS Device IDs. 44 * Updated Integrated RAID configuration pages including 45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 46 * Page 0. 47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 50 * Added missing MaxNumRoutedSasAddresses field to 51 * MPI2_CONFIG_PAGE_EXPANDER_0. 52 * Added SAS Port Page 0. 53 * Modified structure layout for 54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 58 * to 0x000000FF. 59 * Added two new values for the Physical Disk Coercion Size 60 * bits in the Flags field of Manufacturing Page 4. 61 * Added product-specific Manufacturing pages 16 to 31. 62 * Modified Flags bits for controlling write cache on SATA 63 * drives in IO Unit Page 1. 64 * Added new bit to AdditionalControlFlags of SAS IO Unit 65 * Page 1 to control Invalid Topology Correction. 66 * Added additional defines for RAID Volume Page 0 67 * VolumeStatusFlags field. 68 * Modified meaning of RAID Volume Page 0 VolumeSettings 69 * define for auto-configure of hot-swap drives. 70 * Added SupportedPhysDisks field to RAID Volume Page 1 and 71 * added related defines. 72 * Added PhysDiskAttributes field (and related defines) to 73 * RAID Physical Disk Page 0. 74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 75 * Added three new DiscoveryStatus bits for SAS IO Unit 76 * Page 0 and SAS Expander Page 0. 77 * Removed multiplexing information from SAS IO Unit pages. 78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 79 * Removed Zone Address Resolved bit from PhyInfo and from 80 * Expander Page 0 Flags field. 81 * Added two new AccessStatus values to SAS Device Page 0 82 * for indicating routing problems. Added 3 reserved words 83 * to this page. 84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 85 * Inserted missing reserved field into structure for IOC 86 * Page 6. 87 * Added more pending task bits to RAID Volume Page 0 88 * VolumeStatusFlags defines. 89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 91 * and SAS Expander Page 0 to flag a downstream initiator 92 * when in simplified routing mode. 93 * Removed SATA Init Failure defines for DiscoveryStatus 94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 96 * Added PortGroups, DmaGroup, and ControlGroup fields to 97 * SAS Device Page 0. 98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 99 * Unit Page 6. 100 * Added expander reduced functionality data to SAS 101 * Expander Page 0. 102 * Added SAS PHY Page 2 and SAS PHY Page 3. 103 * 07-30-09 02.00.12 Added IO Unit Page 7. 104 * Added new device ids. 105 * Added SAS IO Unit Page 5. 106 * Added partial and slumber power management capable flags 107 * to SAS Device Page 0 Flags field. 108 * Added PhyInfo defines for power condition. 109 * Added Ethernet configuration pages. 110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 111 * Added SAS PHY Page 4 structure and defines. 112 * 02-10-10 02.00.14 Modified the comments for the configuration page 113 * structures that contain an array of data. The host 114 * should use the "count" field in the page data (e.g. the 115 * NumPhys field) to determine the number of valid elements 116 * in the array. 117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 118 * Added PowerManagementCapabilities to IO Unit Page 7. 119 * Added PortWidthModGroup field to 120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 125 * define. 126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 129 * defines. 130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 132 * the Pinout field. 133 * Added BoardTemperature and BoardTemperatureUnits fields 134 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 138 * Added IO Unit Page 8, IO Unit Page 9, 139 * and IO Unit Page 10. 140 * Added SASNotifyPrimitiveMasks field to 141 * MPI2_CONFIG_PAGE_IOC_7. 142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 143 * 05-25-11 02.00.20 Cleaned up a few comments. 144 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 145 * for PCIe link as obsolete. 146 * Added SpinupFlags field containing a Disable Spin-up 147 * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of 148 * SAS IO Unit Page 4. 149 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 150 * Added UEFIVersion field to BIOS Page 1 and defined new 151 * BiosOptions bits. 152 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 153 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 154 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 155 * obsolete for MPI v2.5 and later. 156 * Added some defines for 12G SAS speeds. 157 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 158 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 159 * match the specification. 160 * -------------------------------------------------------------------------- 161 */ 162 163#ifndef MPI2_CNFG_H 164#define MPI2_CNFG_H 165 166/***************************************************************************** 167* Configuration Page Header and defines 168*****************************************************************************/ 169 170/* Config Page Header */ 171typedef struct _MPI2_CONFIG_PAGE_HEADER 172{ 173 U8 PageVersion; /* 0x00 */ 174 U8 PageLength; /* 0x01 */ 175 U8 PageNumber; /* 0x02 */ 176 U8 PageType; /* 0x03 */ 177} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 178 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 179 180typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 181{ 182 MPI2_CONFIG_PAGE_HEADER Struct; 183 U8 Bytes[4]; 184 U16 Word16[2]; 185 U32 Word32; 186} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 187 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 188 189/* Extended Config Page Header */ 190typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 191{ 192 U8 PageVersion; /* 0x00 */ 193 U8 Reserved1; /* 0x01 */ 194 U8 PageNumber; /* 0x02 */ 195 U8 PageType; /* 0x03 */ 196 U16 ExtPageLength; /* 0x04 */ 197 U8 ExtPageType; /* 0x06 */ 198 U8 Reserved2; /* 0x07 */ 199} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 200 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 201 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 202 203typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 204{ 205 MPI2_CONFIG_PAGE_HEADER Struct; 206 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 207 U8 Bytes[8]; 208 U16 Word16[4]; 209 U32 Word32[2]; 210} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 211 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 212 213 214/* PageType field values */ 215#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 216#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 217#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 218#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 219 220#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 221#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 222#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 223#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 224#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 225#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 226#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 227#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 228 229#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 230 231 232/* ExtPageType field values */ 233#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 234#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 235#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 236#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 237#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 238#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 239#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 240#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 241#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 242#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 243#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 244 245 246/***************************************************************************** 247* PageAddress defines 248*****************************************************************************/ 249 250/* RAID Volume PageAddress format */ 251#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 252#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 253#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 254 255#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 256 257 258/* RAID Physical Disk PageAddress format */ 259#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 260#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 261#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 262#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 263 264#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 265#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 266 267 268/* SAS Expander PageAddress format */ 269#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 270#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 271#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 272#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 273 274#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 275#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 276#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 277 278 279/* SAS Device PageAddress format */ 280#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 281#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 282#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 283 284#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 285 286 287/* SAS PHY PageAddress format */ 288#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 289#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 290#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 291 292#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 293#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 294 295 296/* SAS Port PageAddress format */ 297#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 298#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 299#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 300 301#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 302 303 304/* SAS Enclosure PageAddress format */ 305#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 306#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 307#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 308 309#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 310 311 312/* RAID Configuration PageAddress format */ 313#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 314#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 315#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 316#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 317 318#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 319 320 321/* Driver Persistent Mapping PageAddress format */ 322#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 323#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 324 325#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 326#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 327#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 328 329 330/* Ethernet PageAddress format */ 331#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 332#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 333 334#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 335 336 337 338/**************************************************************************** 339* Configuration messages 340****************************************************************************/ 341 342/* Configuration Request Message */ 343typedef struct _MPI2_CONFIG_REQUEST 344{ 345 U8 Action; /* 0x00 */ 346 U8 SGLFlags; /* 0x01 */ 347 U8 ChainOffset; /* 0x02 */ 348 U8 Function; /* 0x03 */ 349 U16 ExtPageLength; /* 0x04 */ 350 U8 ExtPageType; /* 0x06 */ 351 U8 MsgFlags; /* 0x07 */ 352 U8 VP_ID; /* 0x08 */ 353 U8 VF_ID; /* 0x09 */ 354 U16 Reserved1; /* 0x0A */ 355 U8 Reserved2; /* 0x0C */ 356 U8 ProxyVF_ID; /* 0x0D */ 357 U16 Reserved4; /* 0x0E */ 358 U32 Reserved3; /* 0x10 */ 359 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 360 U32 PageAddress; /* 0x18 */ 361 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 362} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 363 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 364 365/* values for the Action field */ 366#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 367#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 368#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 369#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 370#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 371#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 372#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 373#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 374 375/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 376 377 378/* Config Reply Message */ 379typedef struct _MPI2_CONFIG_REPLY 380{ 381 U8 Action; /* 0x00 */ 382 U8 SGLFlags; /* 0x01 */ 383 U8 MsgLength; /* 0x02 */ 384 U8 Function; /* 0x03 */ 385 U16 ExtPageLength; /* 0x04 */ 386 U8 ExtPageType; /* 0x06 */ 387 U8 MsgFlags; /* 0x07 */ 388 U8 VP_ID; /* 0x08 */ 389 U8 VF_ID; /* 0x09 */ 390 U16 Reserved1; /* 0x0A */ 391 U16 Reserved2; /* 0x0C */ 392 U16 IOCStatus; /* 0x0E */ 393 U32 IOCLogInfo; /* 0x10 */ 394 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 395} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 396 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 397 398 399 400/***************************************************************************** 401* 402* C o n f i g u r a t i o n P a g e s 403* 404*****************************************************************************/ 405 406/**************************************************************************** 407* Manufacturing Config pages 408****************************************************************************/ 409 410#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 411 412/* SAS */ 413#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 414#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 415#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 416#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 417#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 418#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 419#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 420 421#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 422 423#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 424#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 425#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 426#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 427#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 428#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 429#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 430#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 431#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 432 433 434 435 436/* Manufacturing Page 0 */ 437 438typedef struct _MPI2_CONFIG_PAGE_MAN_0 439{ 440 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 441 U8 ChipName[16]; /* 0x04 */ 442 U8 ChipRevision[8]; /* 0x14 */ 443 U8 BoardName[16]; /* 0x1C */ 444 U8 BoardAssembly[16]; /* 0x2C */ 445 U8 BoardTracerNumber[16]; /* 0x3C */ 446} MPI2_CONFIG_PAGE_MAN_0, 447 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 448 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 449 450#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 451 452 453/* Manufacturing Page 1 */ 454 455typedef struct _MPI2_CONFIG_PAGE_MAN_1 456{ 457 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 458 U8 VPD[256]; /* 0x04 */ 459} MPI2_CONFIG_PAGE_MAN_1, 460 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 461 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 462 463#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 464 465 466typedef struct _MPI2_CHIP_REVISION_ID 467{ 468 U16 DeviceID; /* 0x00 */ 469 U8 PCIRevisionID; /* 0x02 */ 470 U8 Reserved; /* 0x03 */ 471} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 472 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 473 474 475/* Manufacturing Page 2 */ 476 477/* 478 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 479 * one and check Header.PageLength at runtime. 480 */ 481#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 482#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 483#endif 484 485typedef struct _MPI2_CONFIG_PAGE_MAN_2 486{ 487 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 488 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 489 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 490} MPI2_CONFIG_PAGE_MAN_2, 491 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 492 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 493 494#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 495 496 497/* Manufacturing Page 3 */ 498 499/* 500 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 501 * one and check Header.PageLength at runtime. 502 */ 503#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 504#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 505#endif 506 507typedef struct _MPI2_CONFIG_PAGE_MAN_3 508{ 509 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 510 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 511 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 512} MPI2_CONFIG_PAGE_MAN_3, 513 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 514 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 515 516#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 517 518 519/* Manufacturing Page 4 */ 520 521typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 522{ 523 U8 PowerSaveFlags; /* 0x00 */ 524 U8 InternalOperationsSleepTime; /* 0x01 */ 525 U8 InternalOperationsRunTime; /* 0x02 */ 526 U8 HostIdleTime; /* 0x03 */ 527} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 528 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 529 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 530 531/* defines for the PowerSaveFlags field */ 532#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 533#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 534#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 535#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 536 537typedef struct _MPI2_CONFIG_PAGE_MAN_4 538{ 539 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 540 U32 Reserved1; /* 0x04 */ 541 U32 Flags; /* 0x08 */ 542 U8 InquirySize; /* 0x0C */ 543 U8 Reserved2; /* 0x0D */ 544 U16 Reserved3; /* 0x0E */ 545 U8 InquiryData[56]; /* 0x10 */ 546 U32 RAID0VolumeSettings; /* 0x48 */ 547 U32 RAID1EVolumeSettings; /* 0x4C */ 548 U32 RAID1VolumeSettings; /* 0x50 */ 549 U32 RAID10VolumeSettings; /* 0x54 */ 550 U32 Reserved4; /* 0x58 */ 551 U32 Reserved5; /* 0x5C */ 552 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 553 U8 MaxOCEDisks; /* 0x64 */ 554 U8 ResyncRate; /* 0x65 */ 555 U16 DataScrubDuration; /* 0x66 */ 556 U8 MaxHotSpares; /* 0x68 */ 557 U8 MaxPhysDisksPerVol; /* 0x69 */ 558 U8 MaxPhysDisks; /* 0x6A */ 559 U8 MaxVolumes; /* 0x6B */ 560} MPI2_CONFIG_PAGE_MAN_4, 561 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 562 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 563 564#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 565 566/* Manufacturing Page 4 Flags field */ 567#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 568#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 569 570#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 571#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 572#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 573 574#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 575#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 576#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 577#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 578#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 579 580#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 581#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 582#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 583#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 584 585#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 586#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 587#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 588#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 589#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 590#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 591#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 592#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 593 594 595/* Manufacturing Page 5 */ 596 597/* 598 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 599 * one and check the value returned for NumPhys at runtime. 600 */ 601#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 602#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 603#endif 604 605typedef struct _MPI2_MANUFACTURING5_ENTRY 606{ 607 U64 WWID; /* 0x00 */ 608 U64 DeviceName; /* 0x08 */ 609} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 610 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 611 612typedef struct _MPI2_CONFIG_PAGE_MAN_5 613{ 614 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 615 U8 NumPhys; /* 0x04 */ 616 U8 Reserved1; /* 0x05 */ 617 U16 Reserved2; /* 0x06 */ 618 U32 Reserved3; /* 0x08 */ 619 U32 Reserved4; /* 0x0C */ 620 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 621} MPI2_CONFIG_PAGE_MAN_5, 622 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 623 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 624 625#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 626 627 628/* Manufacturing Page 6 */ 629 630typedef struct _MPI2_CONFIG_PAGE_MAN_6 631{ 632 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 633 U32 ProductSpecificInfo;/* 0x04 */ 634} MPI2_CONFIG_PAGE_MAN_6, 635 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 636 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 637 638#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 639 640 641/* Manufacturing Page 7 */ 642 643typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 644{ 645 U32 Pinout; /* 0x00 */ 646 U8 Connector[16]; /* 0x04 */ 647 U8 Location; /* 0x14 */ 648 U8 ReceptacleID; /* 0x15 */ 649 U16 Slot; /* 0x16 */ 650 U32 Reserved2; /* 0x18 */ 651} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 652 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 653 654/* defines for the Pinout field */ 655#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 656#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 657 658#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 659#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 660#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 661#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 662#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 663#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 664#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 665#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 666#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 667#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 668#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 669#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 670#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 671#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 672#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 673 674/* defines for the Location field */ 675#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 676#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 677#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 678#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 679#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 680#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 681#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 682 683/* 684 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 685 * one and check the value returned for NumPhys at runtime. 686 */ 687#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 688#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 689#endif 690 691typedef struct _MPI2_CONFIG_PAGE_MAN_7 692{ 693 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 694 U32 Reserved1; /* 0x04 */ 695 U32 Reserved2; /* 0x08 */ 696 U32 Flags; /* 0x0C */ 697 U8 EnclosureName[16]; /* 0x10 */ 698 U8 NumPhys; /* 0x20 */ 699 U8 Reserved3; /* 0x21 */ 700 U16 Reserved4; /* 0x22 */ 701 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 702} MPI2_CONFIG_PAGE_MAN_7, 703 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 704 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 705 706#define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 707 708/* defines for the Flags field */ 709#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 710#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 711 712 713/* 714 * Generic structure to use for product-specific manufacturing pages 715 * (currently Manufacturing Page 8 through Manufacturing Page 31). 716 */ 717 718typedef struct _MPI2_CONFIG_PAGE_MAN_PS 719{ 720 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 721 U32 ProductSpecificInfo;/* 0x04 */ 722} MPI2_CONFIG_PAGE_MAN_PS, 723 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 724 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 725 726#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 727#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 728#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 729#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 730#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 731#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 732#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 733#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 734#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 735#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 736#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 737#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 738#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 739#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 740#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 741#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 742#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 743#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 744#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 745#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 746#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 747#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 748#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 749#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 750 751 752/**************************************************************************** 753* IO Unit Config Pages 754****************************************************************************/ 755 756/* IO Unit Page 0 */ 757 758typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 759{ 760 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 761 U64 UniqueValue; /* 0x04 */ 762 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 763 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 764} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 765 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 766 767#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 768 769 770/* IO Unit Page 1 */ 771 772typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 773{ 774 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 775 U32 Flags; /* 0x04 */ 776} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 777 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 778 779#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 780 781/* IO Unit Page 1 Flags defines */ 782#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 783#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 784#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 785#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 786#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 787#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 788#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 789#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 790#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 791#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 792#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 793 794 795/* IO Unit Page 3 */ 796 797/* 798 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 799 * one and check the value returned for GPIOCount at runtime. 800 */ 801#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 802#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 803#endif 804 805typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 806{ 807 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 808 U8 GPIOCount; /* 0x04 */ 809 U8 Reserved1; /* 0x05 */ 810 U16 Reserved2; /* 0x06 */ 811 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 812} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 813 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 814 815#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 816 817/* defines for IO Unit Page 3 GPIOVal field */ 818#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 819#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 820#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 821#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 822 823 824/* IO Unit Page 5 */ 825 826/* 827 * Upper layer code (drivers, utilities, etc.) should leave this define set to 828 * one and check the value returned for NumDmaEngines at runtime. 829 */ 830#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 831#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 832#endif 833 834typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 835 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 836 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 837 U64 RaidAcceleratorBufferSize; /* 0x0C */ 838 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 839 U8 RAControlSize; /* 0x1C */ 840 U8 NumDmaEngines; /* 0x1D */ 841 U8 RAMinControlSize; /* 0x1E */ 842 U8 RAMaxControlSize; /* 0x1F */ 843 U32 Reserved1; /* 0x20 */ 844 U32 Reserved2; /* 0x24 */ 845 U32 Reserved3; /* 0x28 */ 846 U32 DmaEngineCapabilities 847 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 848} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 849 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 850 851#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 852 853/* defines for IO Unit Page 5 DmaEngineCapabilities field */ 854#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 855#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 856 857#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 858#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 859#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 860#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 861 862 863/* IO Unit Page 6 */ 864 865typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 866 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 867 U16 Flags; /* 0x04 */ 868 U8 RAHostControlSize; /* 0x06 */ 869 U8 Reserved0; /* 0x07 */ 870 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 871 U32 Reserved1; /* 0x10 */ 872 U32 Reserved2; /* 0x14 */ 873 U32 Reserved3; /* 0x18 */ 874} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 875 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 876 877#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 878 879/* defines for IO Unit Page 6 Flags field */ 880#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 881 882 883/* IO Unit Page 7 */ 884 885typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 886 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 887 U16 Reserved1; /* 0x04 */ 888 U8 PCIeWidth; /* 0x06 */ 889 U8 PCIeSpeed; /* 0x07 */ 890 U32 ProcessorState; /* 0x08 */ 891 U32 PowerManagementCapabilities; /* 0x0C */ 892 U16 IOCTemperature; /* 0x10 */ 893 U8 IOCTemperatureUnits; /* 0x12 */ 894 U8 IOCSpeed; /* 0x13 */ 895 U16 BoardTemperature; /* 0x14 */ 896 U8 BoardTemperatureUnits; /* 0x16 */ 897 U8 Reserved3; /* 0x17 */ 898 U32 Reserved4; /* 0x18 */ 899 U32 Reserved5; /* 0x1C */ 900 U32 Reserved6; /* 0x20 */ 901 U32 Reserved7; /* 0x24 */ 902} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 903 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 904 905#define MPI2_IOUNITPAGE7_PAGEVERSION (0x04) 906 907/* defines for IO Unit Page 7 PCIeWidth field */ 908#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 909#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 910#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 911#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 912 913/* defines for IO Unit Page 7 PCIeSpeed field */ 914#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 915#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 916#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 917 918/* defines for IO Unit Page 7 ProcessorState field */ 919#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 920#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 921 922#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 923#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 924#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 925 926/* defines for IO Unit Page 7 PowerManagementCapabilities field */ 927#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 928#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 929#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 930#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 931#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 932 933/* defines for IO Unit Page 7 IOCTemperatureUnits field */ 934#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 935#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 936#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 937 938/* defines for IO Unit Page 7 IOCSpeed field */ 939#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 940#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 941#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 942#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 943 944/* defines for IO Unit Page 7 BoardTemperatureUnits field */ 945#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 946#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 947#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 948 949/* IO Unit Page 8 */ 950 951#define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 952 953typedef struct _MPI2_IOUNIT8_SENSOR { 954 U16 Flags; /* 0x00 */ 955 U16 Reserved1; /* 0x02 */ 956 U16 957 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 958 U32 Reserved2; /* 0x0C */ 959 U32 Reserved3; /* 0x10 */ 960 U32 Reserved4; /* 0x14 */ 961} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 962Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 963 964/* defines for IO Unit Page 8 Sensor Flags field */ 965#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 966#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 967#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 968#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 969 970/* 971 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 972 * one and check the value returned for NumSensors at runtime. 973 */ 974#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 975#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 976#endif 977 978typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 979 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 980 U32 Reserved1; /* 0x04 */ 981 U32 Reserved2; /* 0x08 */ 982 U8 NumSensors; /* 0x0C */ 983 U8 PollingInterval; /* 0x0D */ 984 U16 Reserved3; /* 0x0E */ 985 MPI2_IOUNIT8_SENSOR 986 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 987} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 988Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 989 990#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 991 992 993/* IO Unit Page 9 */ 994 995typedef struct _MPI2_IOUNIT9_SENSOR { 996 U16 CurrentTemperature; /* 0x00 */ 997 U16 Reserved1; /* 0x02 */ 998 U8 Flags; /* 0x04 */ 999 U8 Reserved2; /* 0x05 */ 1000 U16 Reserved3; /* 0x06 */ 1001 U32 Reserved4; /* 0x08 */ 1002 U32 Reserved5; /* 0x0C */ 1003} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1004Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1005 1006/* defines for IO Unit Page 9 Sensor Flags field */ 1007#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1008 1009/* 1010 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1011 * one and check the value returned for NumSensors at runtime. 1012 */ 1013#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1014#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1015#endif 1016 1017typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1018 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1019 U32 Reserved1; /* 0x04 */ 1020 U32 Reserved2; /* 0x08 */ 1021 U8 NumSensors; /* 0x0C */ 1022 U8 Reserved4; /* 0x0D */ 1023 U16 Reserved3; /* 0x0E */ 1024 MPI2_IOUNIT9_SENSOR 1025 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1026} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1027Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1028 1029#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1030 1031 1032/* IO Unit Page 10 */ 1033 1034typedef struct _MPI2_IOUNIT10_FUNCTION { 1035 U8 CreditPercent; /* 0x00 */ 1036 U8 Reserved1; /* 0x01 */ 1037 U16 Reserved2; /* 0x02 */ 1038} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1039Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1040 1041/* 1042 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1043 * one and check the value returned for NumFunctions at runtime. 1044 */ 1045#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1046#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1047#endif 1048 1049typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1050 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1051 U8 NumFunctions; /* 0x04 */ 1052 U8 Reserved1; /* 0x05 */ 1053 U16 Reserved2; /* 0x06 */ 1054 U32 Reserved3; /* 0x08 */ 1055 U32 Reserved4; /* 0x0C */ 1056 MPI2_IOUNIT10_FUNCTION 1057 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */ 1058} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1059Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1060 1061#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1062 1063 1064 1065/**************************************************************************** 1066* IOC Config Pages 1067****************************************************************************/ 1068 1069/* IOC Page 0 */ 1070 1071typedef struct _MPI2_CONFIG_PAGE_IOC_0 1072{ 1073 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1074 U32 Reserved1; /* 0x04 */ 1075 U32 Reserved2; /* 0x08 */ 1076 U16 VendorID; /* 0x0C */ 1077 U16 DeviceID; /* 0x0E */ 1078 U8 RevisionID; /* 0x10 */ 1079 U8 Reserved3; /* 0x11 */ 1080 U16 Reserved4; /* 0x12 */ 1081 U32 ClassCode; /* 0x14 */ 1082 U16 SubsystemVendorID; /* 0x18 */ 1083 U16 SubsystemID; /* 0x1A */ 1084} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1085 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1086 1087#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1088 1089 1090/* IOC Page 1 */ 1091 1092typedef struct _MPI2_CONFIG_PAGE_IOC_1 1093{ 1094 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1095 U32 Flags; /* 0x04 */ 1096 U32 CoalescingTimeout; /* 0x08 */ 1097 U8 CoalescingDepth; /* 0x0C */ 1098 U8 PCISlotNum; /* 0x0D */ 1099 U8 PCIBusNum; /* 0x0E */ 1100 U8 PCIDomainSegment; /* 0x0F */ 1101 U32 Reserved1; /* 0x10 */ 1102 U32 Reserved2; /* 0x14 */ 1103} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1104 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1105 1106#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1107 1108/* defines for IOC Page 1 Flags field */ 1109#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1110 1111#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1112#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1113#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1114 1115/* IOC Page 6 */ 1116 1117typedef struct _MPI2_CONFIG_PAGE_IOC_6 1118{ 1119 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1120 U32 CapabilitiesFlags; /* 0x04 */ 1121 U8 MaxDrivesRAID0; /* 0x08 */ 1122 U8 MaxDrivesRAID1; /* 0x09 */ 1123 U8 MaxDrivesRAID1E; /* 0x0A */ 1124 U8 MaxDrivesRAID10; /* 0x0B */ 1125 U8 MinDrivesRAID0; /* 0x0C */ 1126 U8 MinDrivesRAID1; /* 0x0D */ 1127 U8 MinDrivesRAID1E; /* 0x0E */ 1128 U8 MinDrivesRAID10; /* 0x0F */ 1129 U32 Reserved1; /* 0x10 */ 1130 U8 MaxGlobalHotSpares; /* 0x14 */ 1131 U8 MaxPhysDisks; /* 0x15 */ 1132 U8 MaxVolumes; /* 0x16 */ 1133 U8 MaxConfigs; /* 0x17 */ 1134 U8 MaxOCEDisks; /* 0x18 */ 1135 U8 Reserved2; /* 0x19 */ 1136 U16 Reserved3; /* 0x1A */ 1137 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1138 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1139 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1140 U32 Reserved4; /* 0x28 */ 1141 U32 Reserved5; /* 0x2C */ 1142 U16 DefaultMetadataSize; /* 0x30 */ 1143 U16 Reserved6; /* 0x32 */ 1144 U16 MaxBadBlockTableEntries; /* 0x34 */ 1145 U16 Reserved7; /* 0x36 */ 1146 U32 IRNvsramVersion; /* 0x38 */ 1147} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1148 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1149 1150#define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1151 1152/* defines for IOC Page 6 CapabilitiesFlags */ 1153#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1154#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1155#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1156#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1157#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1158#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1159 1160 1161/* IOC Page 7 */ 1162 1163#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1164 1165typedef struct _MPI2_CONFIG_PAGE_IOC_7 1166{ 1167 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1168 U32 Reserved1; /* 0x04 */ 1169 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1170 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1171 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1172 U32 Reserved3; /* 0x1C */ 1173} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1174 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1175 1176#define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1177 1178 1179/* IOC Page 8 */ 1180 1181typedef struct _MPI2_CONFIG_PAGE_IOC_8 1182{ 1183 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1184 U8 NumDevsPerEnclosure; /* 0x04 */ 1185 U8 Reserved1; /* 0x05 */ 1186 U16 Reserved2; /* 0x06 */ 1187 U16 MaxPersistentEntries; /* 0x08 */ 1188 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1189 U16 Flags; /* 0x0C */ 1190 U16 Reserved3; /* 0x0E */ 1191 U16 IRVolumeMappingFlags; /* 0x10 */ 1192 U16 Reserved4; /* 0x12 */ 1193 U32 Reserved5; /* 0x14 */ 1194} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1195 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1196 1197#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1198 1199/* defines for IOC Page 8 Flags field */ 1200#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1201#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1202 1203#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1204#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1205#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1206 1207#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1208#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1209 1210/* defines for IOC Page 8 IRVolumeMappingFlags */ 1211#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1212#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1213#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1214 1215 1216/**************************************************************************** 1217* BIOS Config Pages 1218****************************************************************************/ 1219 1220/* BIOS Page 1 */ 1221 1222typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1223{ 1224 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1225 U32 BiosOptions; /* 0x04 */ 1226 U32 IOCSettings; /* 0x08 */ 1227 U32 Reserved1; /* 0x0C */ 1228 U32 DeviceSettings; /* 0x10 */ 1229 U16 NumberOfDevices; /* 0x14 */ 1230 U16 UEFIVersion; /* 0x16 */ 1231 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1232 U16 IOTimeoutSequential; /* 0x1A */ 1233 U16 IOTimeoutOther; /* 0x1C */ 1234 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1235} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1236 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1237 1238#define MPI2_BIOSPAGE1_PAGEVERSION (0x05) 1239 1240/* values for BIOS Page 1 BiosOptions field */ 1241#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1242#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1243 1244#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1245#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1246#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1247#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1248 1249#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1250 1251/* values for BIOS Page 1 IOCSettings field */ 1252#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1253#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1254#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1255 1256#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1257#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1258#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1259#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1260 1261#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1262#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1263#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1264#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1265#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1266 1267#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1268 1269/* values for BIOS Page 1 DeviceSettings field */ 1270#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1271#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1272#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1273#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1274#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1275 1276/* defines for BIOS Page 1 UEFIVersion field */ 1277#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1278#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1279#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1280#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1281 1282 1283 1284/* BIOS Page 2 */ 1285 1286typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1287{ 1288 U32 Reserved1; /* 0x00 */ 1289 U32 Reserved2; /* 0x04 */ 1290 U32 Reserved3; /* 0x08 */ 1291 U32 Reserved4; /* 0x0C */ 1292 U32 Reserved5; /* 0x10 */ 1293 U32 Reserved6; /* 0x14 */ 1294} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1295 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1296 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1297 1298typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1299{ 1300 U64 SASAddress; /* 0x00 */ 1301 U8 LUN[8]; /* 0x08 */ 1302 U32 Reserved1; /* 0x10 */ 1303 U32 Reserved2; /* 0x14 */ 1304} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1305 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1306 1307typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1308{ 1309 U64 EnclosureLogicalID; /* 0x00 */ 1310 U32 Reserved1; /* 0x08 */ 1311 U32 Reserved2; /* 0x0C */ 1312 U16 SlotNumber; /* 0x10 */ 1313 U16 Reserved3; /* 0x12 */ 1314 U32 Reserved4; /* 0x14 */ 1315} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1316 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1317 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1318 1319typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1320{ 1321 U64 DeviceName; /* 0x00 */ 1322 U8 LUN[8]; /* 0x08 */ 1323 U32 Reserved1; /* 0x10 */ 1324 U32 Reserved2; /* 0x14 */ 1325} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1326 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1327 1328typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1329{ 1330 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1331 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1332 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1333 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1334} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1335 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1336 1337typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1338{ 1339 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1340 U32 Reserved1; /* 0x04 */ 1341 U32 Reserved2; /* 0x08 */ 1342 U32 Reserved3; /* 0x0C */ 1343 U32 Reserved4; /* 0x10 */ 1344 U32 Reserved5; /* 0x14 */ 1345 U32 Reserved6; /* 0x18 */ 1346 U8 ReqBootDeviceForm; /* 0x1C */ 1347 U8 Reserved7; /* 0x1D */ 1348 U16 Reserved8; /* 0x1E */ 1349 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1350 U8 ReqAltBootDeviceForm; /* 0x38 */ 1351 U8 Reserved9; /* 0x39 */ 1352 U16 Reserved10; /* 0x3A */ 1353 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1354 U8 CurrentBootDeviceForm; /* 0x58 */ 1355 U8 Reserved11; /* 0x59 */ 1356 U16 Reserved12; /* 0x5A */ 1357 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1358} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1359 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1360 1361#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1362 1363/* values for BIOS Page 2 BootDeviceForm fields */ 1364#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1365#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1366#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1367#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1368#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1369 1370 1371/* BIOS Page 3 */ 1372 1373typedef struct _MPI2_ADAPTER_INFO 1374{ 1375 U8 PciBusNumber; /* 0x00 */ 1376 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1377 U16 AdapterFlags; /* 0x02 */ 1378} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1379 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1380 1381#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1382#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1383 1384typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1385{ 1386 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1387 U32 GlobalFlags; /* 0x04 */ 1388 U32 BiosVersion; /* 0x08 */ 1389 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1390 U32 Reserved1; /* 0x1C */ 1391} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1392 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1393 1394#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1395 1396/* values for BIOS Page 3 GlobalFlags */ 1397#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1398#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1399#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1400 1401#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1402#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1403#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1404#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1405 1406 1407/* BIOS Page 4 */ 1408 1409/* 1410 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1411 * one and check the value returned for NumPhys at runtime. 1412 */ 1413#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1414#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1415#endif 1416 1417typedef struct _MPI2_BIOS4_ENTRY 1418{ 1419 U64 ReassignmentWWID; /* 0x00 */ 1420 U64 ReassignmentDeviceName; /* 0x08 */ 1421} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1422 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1423 1424typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1425{ 1426 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1427 U8 NumPhys; /* 0x04 */ 1428 U8 Reserved1; /* 0x05 */ 1429 U16 Reserved2; /* 0x06 */ 1430 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1431} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1432 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1433 1434#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1435 1436 1437/**************************************************************************** 1438* RAID Volume Config Pages 1439****************************************************************************/ 1440 1441/* RAID Volume Page 0 */ 1442 1443typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1444{ 1445 U8 RAIDSetNum; /* 0x00 */ 1446 U8 PhysDiskMap; /* 0x01 */ 1447 U8 PhysDiskNum; /* 0x02 */ 1448 U8 Reserved; /* 0x03 */ 1449} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1450 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1451 1452/* defines for the PhysDiskMap field */ 1453#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1454#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1455 1456typedef struct _MPI2_RAIDVOL0_SETTINGS 1457{ 1458 U16 Settings; /* 0x00 */ 1459 U8 HotSparePool; /* 0x01 */ 1460 U8 Reserved; /* 0x02 */ 1461} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1462 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1463 1464/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1465#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1466#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1467#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1468#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1469#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1470#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1471#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1472#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1473 1474/* RAID Volume Page 0 VolumeSettings defines */ 1475#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1476#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1477 1478#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1479#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1480#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1481#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1482 1483/* 1484 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1485 * one and check the value returned for NumPhysDisks at runtime. 1486 */ 1487#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1488#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1489#endif 1490 1491typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1492{ 1493 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1494 U16 DevHandle; /* 0x04 */ 1495 U8 VolumeState; /* 0x06 */ 1496 U8 VolumeType; /* 0x07 */ 1497 U32 VolumeStatusFlags; /* 0x08 */ 1498 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1499 U64 MaxLBA; /* 0x10 */ 1500 U32 StripeSize; /* 0x18 */ 1501 U16 BlockSize; /* 0x1C */ 1502 U16 Reserved1; /* 0x1E */ 1503 U8 SupportedPhysDisks; /* 0x20 */ 1504 U8 ResyncRate; /* 0x21 */ 1505 U16 DataScrubDuration; /* 0x22 */ 1506 U8 NumPhysDisks; /* 0x24 */ 1507 U8 Reserved2; /* 0x25 */ 1508 U8 Reserved3; /* 0x26 */ 1509 U8 InactiveStatus; /* 0x27 */ 1510 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1511} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1512 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1513 1514#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1515 1516/* values for RAID VolumeState */ 1517#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1518#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1519#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1520#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1521#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1522#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1523 1524/* values for RAID VolumeType */ 1525#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1526#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1527#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1528#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1529#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1530 1531/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1532#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1533#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1534#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1535#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1536#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1537#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1538#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1539#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1540#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1541#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1542#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1543#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1544#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1545#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1546#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1547#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1548#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1549#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1550#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1551 1552/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1553#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1554#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1555#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1556#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1557 1558/* values for RAID Volume Page 0 InactiveStatus field */ 1559#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1560#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1561#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1562#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1563#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1564#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1565#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1566 1567 1568/* RAID Volume Page 1 */ 1569 1570typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1571{ 1572 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1573 U16 DevHandle; /* 0x04 */ 1574 U16 Reserved0; /* 0x06 */ 1575 U8 GUID[24]; /* 0x08 */ 1576 U8 Name[16]; /* 0x20 */ 1577 U64 WWID; /* 0x30 */ 1578 U32 Reserved1; /* 0x38 */ 1579 U32 Reserved2; /* 0x3C */ 1580} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1581 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1582 1583#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1584 1585 1586/**************************************************************************** 1587* RAID Physical Disk Config Pages 1588****************************************************************************/ 1589 1590/* RAID Physical Disk Page 0 */ 1591 1592typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1593{ 1594 U16 Reserved1; /* 0x00 */ 1595 U8 HotSparePool; /* 0x02 */ 1596 U8 Reserved2; /* 0x03 */ 1597} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1598 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1599 1600/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1601 1602typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1603{ 1604 U8 VendorID[8]; /* 0x00 */ 1605 U8 ProductID[16]; /* 0x08 */ 1606 U8 ProductRevLevel[4]; /* 0x18 */ 1607 U8 SerialNum[32]; /* 0x1C */ 1608} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1609 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1610 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1611 1612typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1613{ 1614 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1615 U16 DevHandle; /* 0x04 */ 1616 U8 Reserved1; /* 0x06 */ 1617 U8 PhysDiskNum; /* 0x07 */ 1618 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1619 U32 Reserved2; /* 0x0C */ 1620 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1621 U32 Reserved3; /* 0x4C */ 1622 U8 PhysDiskState; /* 0x50 */ 1623 U8 OfflineReason; /* 0x51 */ 1624 U8 IncompatibleReason; /* 0x52 */ 1625 U8 PhysDiskAttributes; /* 0x53 */ 1626 U32 PhysDiskStatusFlags; /* 0x54 */ 1627 U64 DeviceMaxLBA; /* 0x58 */ 1628 U64 HostMaxLBA; /* 0x60 */ 1629 U64 CoercedMaxLBA; /* 0x68 */ 1630 U16 BlockSize; /* 0x70 */ 1631 U16 Reserved5; /* 0x72 */ 1632 U32 Reserved6; /* 0x74 */ 1633} MPI2_CONFIG_PAGE_RD_PDISK_0, 1634 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1635 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1636 1637#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1638 1639/* PhysDiskState defines */ 1640#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1641#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1642#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1643#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1644#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1645#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1646#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1647#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1648 1649/* OfflineReason defines */ 1650#define MPI2_PHYSDISK0_ONLINE (0x00) 1651#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1652#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1653#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1654#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1655#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1656#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1657 1658/* IncompatibleReason defines */ 1659#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1660#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1661#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1662#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1663#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1664#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1665#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1666#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1667 1668/* PhysDiskAttributes defines */ 1669#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1670#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1671#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1672 1673#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1674#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1675#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1676 1677/* PhysDiskStatusFlags defines */ 1678#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1679#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1680#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1681#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1682#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1683#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1684#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1685#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1686 1687 1688/* RAID Physical Disk Page 1 */ 1689 1690/* 1691 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1692 * one and check the value returned for NumPhysDiskPaths at runtime. 1693 */ 1694#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1695#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1696#endif 1697 1698typedef struct _MPI2_RAIDPHYSDISK1_PATH 1699{ 1700 U16 DevHandle; /* 0x00 */ 1701 U16 Reserved1; /* 0x02 */ 1702 U64 WWID; /* 0x04 */ 1703 U64 OwnerWWID; /* 0x0C */ 1704 U8 OwnerIdentifier; /* 0x14 */ 1705 U8 Reserved2; /* 0x15 */ 1706 U16 Flags; /* 0x16 */ 1707} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1708 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1709 1710/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1711#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1712#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1713#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1714 1715typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1716{ 1717 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1718 U8 NumPhysDiskPaths; /* 0x04 */ 1719 U8 PhysDiskNum; /* 0x05 */ 1720 U16 Reserved1; /* 0x06 */ 1721 U32 Reserved2; /* 0x08 */ 1722 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1723} MPI2_CONFIG_PAGE_RD_PDISK_1, 1724 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1725 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1726 1727#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1728 1729 1730/**************************************************************************** 1731* values for fields used by several types of SAS Config Pages 1732****************************************************************************/ 1733 1734/* values for NegotiatedLinkRates fields */ 1735#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1736#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1737#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1738/* link rates used for Negotiated Physical and Logical Link Rate */ 1739#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1740#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1741#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1742#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1743#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1744#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1745#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1746#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1747#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1748#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1749 1750 1751/* values for AttachedPhyInfo fields */ 1752#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1753#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1754#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1755 1756#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1757#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1758#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1759#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1760#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1761#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1762#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1763#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1764#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1765#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1766 1767 1768/* values for PhyInfo fields */ 1769#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1770 1771#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1772#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1773#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1774#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1775#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1776 1777#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1778#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1779#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1780#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1781#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1782#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1783 1784#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1785#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1786#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1787#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1788#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1789#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1790#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1791#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1792#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1793#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1794 1795#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1796#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1797#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1798#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1799 1800#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1801#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1802 1803#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1804#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1805#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1806#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1807 1808 1809/* values for SAS ProgrammedLinkRate fields */ 1810#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1811#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1812#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1813#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1814#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1815#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 1816#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1817#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1818#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1819#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1820#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1821 1822 1823/* values for SAS HwLinkRate fields */ 1824#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1825#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1826#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1827#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1828#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 1829#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1830#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1831#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1832#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1833 1834 1835 1836/**************************************************************************** 1837* SAS IO Unit Config Pages 1838****************************************************************************/ 1839 1840/* SAS IO Unit Page 0 */ 1841 1842typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1843{ 1844 U8 Port; /* 0x00 */ 1845 U8 PortFlags; /* 0x01 */ 1846 U8 PhyFlags; /* 0x02 */ 1847 U8 NegotiatedLinkRate; /* 0x03 */ 1848 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1849 U16 AttachedDevHandle; /* 0x08 */ 1850 U16 ControllerDevHandle; /* 0x0A */ 1851 U32 DiscoveryStatus; /* 0x0C */ 1852 U32 Reserved; /* 0x10 */ 1853} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1854 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1855 1856/* 1857 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1858 * one and check the value returned for NumPhys at runtime. 1859 */ 1860#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1861#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1862#endif 1863 1864typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1865{ 1866 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1867 U32 Reserved1; /* 0x08 */ 1868 U8 NumPhys; /* 0x0C */ 1869 U8 Reserved2; /* 0x0D */ 1870 U16 Reserved3; /* 0x0E */ 1871 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1872} MPI2_CONFIG_PAGE_SASIOUNIT_0, 1873 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1874 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1875 1876#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1877 1878/* values for SAS IO Unit Page 0 PortFlags */ 1879#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1880#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1881 1882/* values for SAS IO Unit Page 0 PhyFlags */ 1883#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1884#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1885 1886/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1887 1888/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1889 1890/* values for SAS IO Unit Page 0 DiscoveryStatus */ 1891#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1892#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1893#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1894#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1895#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1896#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1897#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1898#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1899#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1900#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1901#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1902#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1903#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1904#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1905#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1906#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1907#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1908#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1909#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1910#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1911 1912 1913/* SAS IO Unit Page 1 */ 1914 1915typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1916{ 1917 U8 Port; /* 0x00 */ 1918 U8 PortFlags; /* 0x01 */ 1919 U8 PhyFlags; /* 0x02 */ 1920 U8 MaxMinLinkRate; /* 0x03 */ 1921 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1922 U16 MaxTargetPortConnectTime; /* 0x08 */ 1923 U16 Reserved1; /* 0x0A */ 1924} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1925 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1926 1927/* 1928 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1929 * one and check the value returned for NumPhys at runtime. 1930 */ 1931#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1932#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1933#endif 1934 1935typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1936{ 1937 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1938 U16 ControlFlags; /* 0x08 */ 1939 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1940 U16 AdditionalControlFlags; /* 0x0C */ 1941 U16 SASWideMaxQueueDepth; /* 0x0E */ 1942 U8 NumPhys; /* 0x10 */ 1943 U8 SATAMaxQDepth; /* 0x11 */ 1944 U8 ReportDeviceMissingDelay; /* 0x12 */ 1945 U8 IODeviceMissingDelay; /* 0x13 */ 1946 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1947} MPI2_CONFIG_PAGE_SASIOUNIT_1, 1948 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1949 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1950 1951#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1952 1953/* values for SAS IO Unit Page 1 ControlFlags */ 1954#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1955#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1956#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1957#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1958 1959#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1960#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1961#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1962#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1963#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1964 1965#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1966#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1967#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1968#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1969#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1970#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1971#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1972#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1973 1974/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1975#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1976#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1977#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1978#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1979#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1980#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1981#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1982#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1983 1984/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1985#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1986#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1987 1988/* values for SAS IO Unit Page 1 PortFlags */ 1989#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1990 1991/* values for SAS IO Unit Page 1 PhyFlags */ 1992#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1993#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1994 1995/* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1996#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1997#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1998#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1999#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2000#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2001#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2002#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2003#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2004 2005/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2006 2007 2008/* SAS IO Unit Page 4 */ 2009 2010typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2011{ 2012 U8 MaxTargetSpinup; /* 0x00 */ 2013 U8 SpinupDelay; /* 0x01 */ 2014 U8 SpinupFlags; /* 0x02 */ 2015 U8 Reserved1; /* 0x03 */ 2016} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2017 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2018 2019/* defines for SAS IO Unit Page 4 SpinupFlags */ 2020#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2021 2022/* 2023 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2024 * one and check the value returned for NumPhys at runtime. 2025 */ 2026#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2027#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2028#endif 2029 2030typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2031{ 2032 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2033 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2034 U32 Reserved1; /* 0x18 */ 2035 U32 Reserved2; /* 0x1C */ 2036 U32 Reserved3; /* 0x20 */ 2037 U8 BootDeviceWaitTime; /* 0x24 */ 2038 U8 Reserved4; /* 0x25 */ 2039 U16 Reserved5; /* 0x26 */ 2040 U8 NumPhys; /* 0x28 */ 2041 U8 PEInitialSpinupDelay; /* 0x29 */ 2042 U8 PEReplyDelay; /* 0x2A */ 2043 U8 Flags; /* 0x2B */ 2044 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2045} MPI2_CONFIG_PAGE_SASIOUNIT_4, 2046 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2047 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2048 2049#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2050 2051/* defines for Flags field */ 2052#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2053 2054/* defines for PHY field */ 2055#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2056 2057 2058/* SAS IO Unit Page 5 */ 2059 2060typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2061 U8 ControlFlags; /* 0x00 */ 2062 U8 PortWidthModGroup; /* 0x01 */ 2063 U16 InactivityTimerExponent; /* 0x02 */ 2064 U8 SATAPartialTimeout; /* 0x04 */ 2065 U8 Reserved2; /* 0x05 */ 2066 U8 SATASlumberTimeout; /* 0x06 */ 2067 U8 Reserved3; /* 0x07 */ 2068 U8 SASPartialTimeout; /* 0x08 */ 2069 U8 Reserved4; /* 0x09 */ 2070 U8 SASSlumberTimeout; /* 0x0A */ 2071 U8 Reserved5; /* 0x0B */ 2072} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2073 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2074 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2075 2076/* defines for ControlFlags field */ 2077#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2078#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2079#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2080#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2081 2082/* defines for PortWidthModeGroup field */ 2083#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2084 2085/* defines for InactivityTimerExponent field */ 2086#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2087#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2088#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2089#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2090#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2091#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2092#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2093#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2094 2095#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2096#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2097#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2098#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2099#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2100#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2101#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2102#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2103 2104/* 2105 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2106 * one and check the value returned for NumPhys at runtime. 2107 */ 2108#ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2109#define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2110#endif 2111 2112typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2113 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2114 U8 NumPhys; /* 0x08 */ 2115 U8 Reserved1; /* 0x09 */ 2116 U16 Reserved2; /* 0x0A */ 2117 U32 Reserved3; /* 0x0C */ 2118 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings 2119 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2120} MPI2_CONFIG_PAGE_SASIOUNIT_5, 2121 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2122 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2123 2124#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2125 2126 2127/* SAS IO Unit Page 6 */ 2128 2129typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2130 U8 CurrentStatus; /* 0x00 */ 2131 U8 CurrentModulation; /* 0x01 */ 2132 U8 CurrentUtilization; /* 0x02 */ 2133 U8 Reserved1; /* 0x03 */ 2134 U32 Reserved2; /* 0x04 */ 2135} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2136 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2137 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2138 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2139 2140/* defines for CurrentStatus field */ 2141#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2142#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2143#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2144#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2145#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2146#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2147#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2148#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2149 2150/* defines for CurrentModulation field */ 2151#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2152#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2153#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2154#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2155 2156/* 2157 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2158 * one and check the value returned for NumGroups at runtime. 2159 */ 2160#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2161#define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2162#endif 2163 2164typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2165 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2166 U32 Reserved1; /* 0x08 */ 2167 U32 Reserved2; /* 0x0C */ 2168 U8 NumGroups; /* 0x10 */ 2169 U8 Reserved3; /* 0x11 */ 2170 U16 Reserved4; /* 0x12 */ 2171 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2172 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2173} MPI2_CONFIG_PAGE_SASIOUNIT_6, 2174 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2175 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2176 2177#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2178 2179 2180/* SAS IO Unit Page 7 */ 2181 2182typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2183 U8 Flags; /* 0x00 */ 2184 U8 Reserved1; /* 0x01 */ 2185 U16 Reserved2; /* 0x02 */ 2186 U8 Threshold75Pct; /* 0x04 */ 2187 U8 Threshold50Pct; /* 0x05 */ 2188 U8 Threshold25Pct; /* 0x06 */ 2189 U8 Reserved3; /* 0x07 */ 2190} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2191 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2192 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2193 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2194 2195/* defines for Flags field */ 2196#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2197 2198 2199/* 2200 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2201 * one and check the value returned for NumGroups at runtime. 2202 */ 2203#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2204#define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2205#endif 2206 2207typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2208 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2209 U8 SamplingInterval; /* 0x08 */ 2210 U8 WindowLength; /* 0x09 */ 2211 U16 Reserved1; /* 0x0A */ 2212 U32 Reserved2; /* 0x0C */ 2213 U32 Reserved3; /* 0x10 */ 2214 U8 NumGroups; /* 0x14 */ 2215 U8 Reserved4; /* 0x15 */ 2216 U16 Reserved5; /* 0x16 */ 2217 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2218 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2219} MPI2_CONFIG_PAGE_SASIOUNIT_7, 2220 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2221 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2222 2223#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2224 2225 2226/* SAS IO Unit Page 8 */ 2227 2228typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2229 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2230 U32 Reserved1; /* 0x08 */ 2231 U32 PowerManagementCapabilities;/* 0x0C */ 2232 U32 Reserved2; /* 0x10 */ 2233} MPI2_CONFIG_PAGE_SASIOUNIT_8, 2234 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2235 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2236 2237#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2238 2239/* defines for PowerManagementCapabilities field */ 2240#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2241#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2242#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2243#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2244#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2245#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2246#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2247#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2248#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2249#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2250 2251 2252 2253/* SAS IO Unit Page 16 */ 2254 2255typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2256 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2257 U64 TimeStamp; /* 0x08 */ 2258 U32 Reserved1; /* 0x10 */ 2259 U32 Reserved2; /* 0x14 */ 2260 U32 FastPathPendedRequests; /* 0x18 */ 2261 U32 FastPathUnPendedRequests; /* 0x1C */ 2262 U32 FastPathHostRequestStarts; /* 0x20 */ 2263 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2264 U32 FastPathHostCompletions; /* 0x28 */ 2265 U32 FastPathFirmwareCompletions; /* 0x2C */ 2266 U32 NonFastPathRequestStarts; /* 0x30 */ 2267 U32 NonFastPathHostCompletions; /* 0x30 */ 2268} MPI2_CONFIG_PAGE_SASIOUNIT16, 2269MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2270Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2271 2272#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2273 2274 2275/**************************************************************************** 2276* SAS Expander Config Pages 2277****************************************************************************/ 2278 2279/* SAS Expander Page 0 */ 2280 2281typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2282{ 2283 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2284 U8 PhysicalPort; /* 0x08 */ 2285 U8 ReportGenLength; /* 0x09 */ 2286 U16 EnclosureHandle; /* 0x0A */ 2287 U64 SASAddress; /* 0x0C */ 2288 U32 DiscoveryStatus; /* 0x14 */ 2289 U16 DevHandle; /* 0x18 */ 2290 U16 ParentDevHandle; /* 0x1A */ 2291 U16 ExpanderChangeCount; /* 0x1C */ 2292 U16 ExpanderRouteIndexes; /* 0x1E */ 2293 U8 NumPhys; /* 0x20 */ 2294 U8 SASLevel; /* 0x21 */ 2295 U16 Flags; /* 0x22 */ 2296 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2297 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2298 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2299 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2300 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2301 U16 ZoneLockInactivityLimit; /* 0x34 */ 2302 U16 Reserved1; /* 0x36 */ 2303 U8 TimeToReducedFunc; /* 0x38 */ 2304 U8 InitialTimeToReducedFunc; /* 0x39 */ 2305 U8 MaxReducedFuncTime; /* 0x3A */ 2306 U8 Reserved2; /* 0x3B */ 2307} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2308 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2309 2310#define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2311 2312/* values for SAS Expander Page 0 DiscoveryStatus field */ 2313#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2314#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2315#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2316#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2317#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2318#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2319#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2320#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2321#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2322#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2323#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2324#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2325#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2326#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2327#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2328#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2329#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2330#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2331#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2332#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2333 2334/* values for SAS Expander Page 0 Flags field */ 2335#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2336#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2337#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2338#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2339#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2340#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2341#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2342#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2343#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2344#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2345#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2346 2347 2348/* SAS Expander Page 1 */ 2349 2350typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2351{ 2352 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2353 U8 PhysicalPort; /* 0x08 */ 2354 U8 Reserved1; /* 0x09 */ 2355 U16 Reserved2; /* 0x0A */ 2356 U8 NumPhys; /* 0x0C */ 2357 U8 Phy; /* 0x0D */ 2358 U16 NumTableEntriesProgrammed; /* 0x0E */ 2359 U8 ProgrammedLinkRate; /* 0x10 */ 2360 U8 HwLinkRate; /* 0x11 */ 2361 U16 AttachedDevHandle; /* 0x12 */ 2362 U32 PhyInfo; /* 0x14 */ 2363 U32 AttachedDeviceInfo; /* 0x18 */ 2364 U16 ExpanderDevHandle; /* 0x1C */ 2365 U8 ChangeCount; /* 0x1E */ 2366 U8 NegotiatedLinkRate; /* 0x1F */ 2367 U8 PhyIdentifier; /* 0x20 */ 2368 U8 AttachedPhyIdentifier; /* 0x21 */ 2369 U8 Reserved3; /* 0x22 */ 2370 U8 DiscoveryInfo; /* 0x23 */ 2371 U32 AttachedPhyInfo; /* 0x24 */ 2372 U8 ZoneGroup; /* 0x28 */ 2373 U8 SelfConfigStatus; /* 0x29 */ 2374 U16 Reserved4; /* 0x2A */ 2375} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2376 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2377 2378#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2379 2380/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2381 2382/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2383 2384/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2385 2386/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2387 2388/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2389 2390/* values for SAS Expander Page 1 DiscoveryInfo field */ 2391#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2392#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2393#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2394 2395/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2396 2397/**************************************************************************** 2398* SAS Device Config Pages 2399****************************************************************************/ 2400 2401/* SAS Device Page 0 */ 2402 2403typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2404{ 2405 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2406 U16 Slot; /* 0x08 */ 2407 U16 EnclosureHandle; /* 0x0A */ 2408 U64 SASAddress; /* 0x0C */ 2409 U16 ParentDevHandle; /* 0x14 */ 2410 U8 PhyNum; /* 0x16 */ 2411 U8 AccessStatus; /* 0x17 */ 2412 U16 DevHandle; /* 0x18 */ 2413 U8 AttachedPhyIdentifier; /* 0x1A */ 2414 U8 ZoneGroup; /* 0x1B */ 2415 U32 DeviceInfo; /* 0x1C */ 2416 U16 Flags; /* 0x20 */ 2417 U8 PhysicalPort; /* 0x22 */ 2418 U8 MaxPortConnections; /* 0x23 */ 2419 U64 DeviceName; /* 0x24 */ 2420 U8 PortGroups; /* 0x2C */ 2421 U8 DmaGroup; /* 0x2D */ 2422 U8 ControlGroup; /* 0x2E */ 2423 U8 Reserved1; /* 0x2F */ 2424 U32 Reserved2; /* 0x30 */ 2425 U32 Reserved3; /* 0x34 */ 2426} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2427 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2428 2429#define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2430 2431/* values for SAS Device Page 0 AccessStatus field */ 2432#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2433#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2434#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2435#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2436#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2437#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2438#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2439#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2440/* specific values for SATA Init failures */ 2441#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2442#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2443#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2444#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2445#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2446#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2447#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2448#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2449#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2450#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2451#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2452 2453/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2454 2455/* values for SAS Device Page 0 Flags field */ 2456#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2457#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2458#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2459#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2460#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2461#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2462#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2463#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2464#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2465#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2466#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2467#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2468 2469 2470/* SAS Device Page 1 */ 2471 2472typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2473{ 2474 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2475 U32 Reserved1; /* 0x08 */ 2476 U64 SASAddress; /* 0x0C */ 2477 U32 Reserved2; /* 0x14 */ 2478 U16 DevHandle; /* 0x18 */ 2479 U16 Reserved3; /* 0x1A */ 2480 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2481} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2482 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2483 2484#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2485 2486 2487/**************************************************************************** 2488* SAS PHY Config Pages 2489****************************************************************************/ 2490 2491/* SAS PHY Page 0 */ 2492 2493typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2494{ 2495 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2496 U16 OwnerDevHandle; /* 0x08 */ 2497 U16 Reserved1; /* 0x0A */ 2498 U16 AttachedDevHandle; /* 0x0C */ 2499 U8 AttachedPhyIdentifier; /* 0x0E */ 2500 U8 Reserved2; /* 0x0F */ 2501 U32 AttachedPhyInfo; /* 0x10 */ 2502 U8 ProgrammedLinkRate; /* 0x14 */ 2503 U8 HwLinkRate; /* 0x15 */ 2504 U8 ChangeCount; /* 0x16 */ 2505 U8 Flags; /* 0x17 */ 2506 U32 PhyInfo; /* 0x18 */ 2507 U8 NegotiatedLinkRate; /* 0x1C */ 2508 U8 Reserved3; /* 0x1D */ 2509 U16 Reserved4; /* 0x1E */ 2510} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2511 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2512 2513#define MPI2_SASPHY0_PAGEVERSION (0x03) 2514 2515/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2516 2517/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2518 2519/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2520 2521/* values for SAS PHY Page 0 Flags field */ 2522#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2523 2524/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2525 2526/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2527 2528 2529/* SAS PHY Page 1 */ 2530 2531typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2532{ 2533 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2534 U32 Reserved1; /* 0x08 */ 2535 U32 InvalidDwordCount; /* 0x0C */ 2536 U32 RunningDisparityErrorCount; /* 0x10 */ 2537 U32 LossDwordSynchCount; /* 0x14 */ 2538 U32 PhyResetProblemCount; /* 0x18 */ 2539} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2540 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2541 2542#define MPI2_SASPHY1_PAGEVERSION (0x01) 2543 2544 2545/* SAS PHY Page 2 */ 2546 2547typedef struct _MPI2_SASPHY2_PHY_EVENT { 2548 U8 PhyEventCode; /* 0x00 */ 2549 U8 Reserved1; /* 0x01 */ 2550 U16 Reserved2; /* 0x02 */ 2551 U32 PhyEventInfo; /* 0x04 */ 2552} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2553 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2554 2555/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2556 2557 2558/* 2559 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2560 * one and check the value returned for NumPhyEvents at runtime. 2561 */ 2562#ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2563#define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2564#endif 2565 2566typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2567 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2568 U32 Reserved1; /* 0x08 */ 2569 U8 NumPhyEvents; /* 0x0C */ 2570 U8 Reserved2; /* 0x0D */ 2571 U16 Reserved3; /* 0x0E */ 2572 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; 2573 /* 0x10 */ 2574} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2575 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2576 2577#define MPI2_SASPHY2_PAGEVERSION (0x00) 2578 2579 2580/* SAS PHY Page 3 */ 2581 2582typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2583 U8 PhyEventCode; /* 0x00 */ 2584 U8 Reserved1; /* 0x01 */ 2585 U16 Reserved2; /* 0x02 */ 2586 U8 CounterType; /* 0x04 */ 2587 U8 ThresholdWindow; /* 0x05 */ 2588 U8 TimeUnits; /* 0x06 */ 2589 U8 Reserved3; /* 0x07 */ 2590 U32 EventThreshold; /* 0x08 */ 2591 U16 ThresholdFlags; /* 0x0C */ 2592 U16 Reserved4; /* 0x0E */ 2593} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2594 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2595 2596/* values for PhyEventCode field */ 2597#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2598#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2599#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2600#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2601#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2602#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2603#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2604#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2605#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2606#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2607#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2608#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2609#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2610#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2611#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2612#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2613#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2614#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2615#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2616#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2617#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2618#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2619#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2620#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2621#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2622#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2623#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2624#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2625#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2626#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2627#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2628#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2629#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2630#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2631#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2632#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2633#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2634 2635/* values for the CounterType field */ 2636#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2637#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2638#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2639 2640/* values for the TimeUnits field */ 2641#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2642#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2643#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2644#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2645 2646/* values for the ThresholdFlags field */ 2647#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2648#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2649 2650/* 2651 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2652 * one and check the value returned for NumPhyEvents at runtime. 2653 */ 2654#ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2655#define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2656#endif 2657 2658typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 2659 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2660 U32 Reserved1; /* 0x08 */ 2661 U8 NumPhyEvents; /* 0x0C */ 2662 U8 Reserved2; /* 0x0D */ 2663 U16 Reserved3; /* 0x0E */ 2664 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig 2665 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2666} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2667 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2668 2669#define MPI2_SASPHY3_PAGEVERSION (0x00) 2670 2671 2672/* SAS PHY Page 4 */ 2673 2674typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 2675 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2676 U16 Reserved1; /* 0x08 */ 2677 U8 Reserved2; /* 0x0A */ 2678 U8 Flags; /* 0x0B */ 2679 U8 InitialFrame[28]; /* 0x0C */ 2680} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2681 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2682 2683#define MPI2_SASPHY4_PAGEVERSION (0x00) 2684 2685/* values for the Flags field */ 2686#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2687#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2688 2689 2690 2691 2692/**************************************************************************** 2693* SAS Port Config Pages 2694****************************************************************************/ 2695 2696/* SAS Port Page 0 */ 2697 2698typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2699{ 2700 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2701 U8 PortNumber; /* 0x08 */ 2702 U8 PhysicalPort; /* 0x09 */ 2703 U8 PortWidth; /* 0x0A */ 2704 U8 PhysicalPortWidth; /* 0x0B */ 2705 U8 ZoneGroup; /* 0x0C */ 2706 U8 Reserved1; /* 0x0D */ 2707 U16 Reserved2; /* 0x0E */ 2708 U64 SASAddress; /* 0x10 */ 2709 U32 DeviceInfo; /* 0x18 */ 2710 U32 Reserved3; /* 0x1C */ 2711 U32 Reserved4; /* 0x20 */ 2712} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2713 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2714 2715#define MPI2_SASPORT0_PAGEVERSION (0x00) 2716 2717/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2718 2719 2720/**************************************************************************** 2721* SAS Enclosure Config Pages 2722****************************************************************************/ 2723 2724/* SAS Enclosure Page 0 */ 2725 2726typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2727{ 2728 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2729 U32 Reserved1; /* 0x08 */ 2730 U64 EnclosureLogicalID; /* 0x0C */ 2731 U16 Flags; /* 0x14 */ 2732 U16 EnclosureHandle; /* 0x16 */ 2733 U16 NumSlots; /* 0x18 */ 2734 U16 StartSlot; /* 0x1A */ 2735 U16 Reserved2; /* 0x1C */ 2736 U16 SEPDevHandle; /* 0x1E */ 2737 U32 Reserved3; /* 0x20 */ 2738 U32 Reserved4; /* 0x24 */ 2739} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2740 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2741 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2742 2743#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2744 2745/* values for SAS Enclosure Page 0 Flags field */ 2746#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2747#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2748#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2749#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2750#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2751#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2752#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2753 2754 2755/**************************************************************************** 2756* Log Config Page 2757****************************************************************************/ 2758 2759/* Log Page 0 */ 2760 2761/* 2762 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2763 * one and check the value returned for NumLogEntries at runtime. 2764 */ 2765#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2766#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2767#endif 2768 2769#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2770 2771typedef struct _MPI2_LOG_0_ENTRY 2772{ 2773 U64 TimeStamp; /* 0x00 */ 2774 U32 Reserved1; /* 0x08 */ 2775 U16 LogSequence; /* 0x0C */ 2776 U16 LogEntryQualifier; /* 0x0E */ 2777 U8 VP_ID; /* 0x10 */ 2778 U8 VF_ID; /* 0x11 */ 2779 U16 Reserved2; /* 0x12 */ 2780 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2781} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2782 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2783 2784/* values for Log Page 0 LogEntry LogEntryQualifier field */ 2785#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2786#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2787#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2788#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2789#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2790 2791typedef struct _MPI2_CONFIG_PAGE_LOG_0 2792{ 2793 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2794 U32 Reserved1; /* 0x08 */ 2795 U32 Reserved2; /* 0x0C */ 2796 U16 NumLogEntries; /* 0x10 */ 2797 U16 Reserved3; /* 0x12 */ 2798 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2799} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2800 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2801 2802#define MPI2_LOG_0_PAGEVERSION (0x02) 2803 2804 2805/**************************************************************************** 2806* RAID Config Page 2807****************************************************************************/ 2808 2809/* RAID Page 0 */ 2810 2811/* 2812 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2813 * one and check the value returned for NumElements at runtime. 2814 */ 2815#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2816#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2817#endif 2818 2819typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2820{ 2821 U16 ElementFlags; /* 0x00 */ 2822 U16 VolDevHandle; /* 0x02 */ 2823 U8 HotSparePool; /* 0x04 */ 2824 U8 PhysDiskNum; /* 0x05 */ 2825 U16 PhysDiskDevHandle; /* 0x06 */ 2826} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2827 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2828 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2829 2830/* values for the ElementFlags field */ 2831#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2832#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2833#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2834#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2835#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2836 2837 2838typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2839{ 2840 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2841 U8 NumHotSpares; /* 0x08 */ 2842 U8 NumPhysDisks; /* 0x09 */ 2843 U8 NumVolumes; /* 0x0A */ 2844 U8 ConfigNum; /* 0x0B */ 2845 U32 Flags; /* 0x0C */ 2846 U8 ConfigGUID[24]; /* 0x10 */ 2847 U32 Reserved1; /* 0x28 */ 2848 U8 NumElements; /* 0x2C */ 2849 U8 Reserved2; /* 0x2D */ 2850 U16 Reserved3; /* 0x2E */ 2851 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2852} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2853 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2854 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2855 2856#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2857 2858/* values for RAID Configuration Page 0 Flags field */ 2859#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2860 2861 2862/**************************************************************************** 2863* Driver Persistent Mapping Config Pages 2864****************************************************************************/ 2865 2866/* Driver Persistent Mapping Page 0 */ 2867 2868typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2869{ 2870 U64 PhysicalIdentifier; /* 0x00 */ 2871 U16 MappingInformation; /* 0x08 */ 2872 U16 DeviceIndex; /* 0x0A */ 2873 U32 PhysicalBitsMapping; /* 0x0C */ 2874 U32 Reserved1; /* 0x10 */ 2875} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2876 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2877 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2878 2879typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2880{ 2881 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2882 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2883} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2884 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2885 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2886 2887#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2888 2889/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2890#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2891#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2892#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2893 2894 2895/**************************************************************************** 2896* Ethernet Config Pages 2897****************************************************************************/ 2898 2899/* Ethernet Page 0 */ 2900 2901/* IP address (union of IPv4 and IPv6) */ 2902typedef union _MPI2_ETHERNET_IP_ADDR { 2903 U32 IPv4Addr; 2904 U32 IPv6Addr[4]; 2905} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2906 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2907 2908#define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2909 2910typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 2911 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2912 U8 NumInterfaces; /* 0x08 */ 2913 U8 Reserved0; /* 0x09 */ 2914 U16 Reserved1; /* 0x0A */ 2915 U32 Status; /* 0x0C */ 2916 U8 MediaState; /* 0x10 */ 2917 U8 Reserved2; /* 0x11 */ 2918 U16 Reserved3; /* 0x12 */ 2919 U8 MacAddress[6]; /* 0x14 */ 2920 U8 Reserved4; /* 0x1A */ 2921 U8 Reserved5; /* 0x1B */ 2922 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2923 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2924 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2925 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2926 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2927 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2928 U8 HostName 2929 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2930} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2931 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2932 2933#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2934 2935/* values for Ethernet Page 0 Status field */ 2936#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2937#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2938#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2939#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2940#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2941#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2942#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2943#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2944#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2945#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2946#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2947#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2948 2949/* values for Ethernet Page 0 MediaState field */ 2950#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2951#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2952#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2953 2954#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2955#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2956#define MPI2_ETHPG0_MS_10MBIT (0x01) 2957#define MPI2_ETHPG0_MS_100MBIT (0x02) 2958#define MPI2_ETHPG0_MS_1GBIT (0x03) 2959 2960 2961/* Ethernet Page 1 */ 2962 2963typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 2964 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2965 U32 Reserved0; /* 0x08 */ 2966 U32 Flags; /* 0x0C */ 2967 U8 MediaState; /* 0x10 */ 2968 U8 Reserved1; /* 0x11 */ 2969 U16 Reserved2; /* 0x12 */ 2970 U8 MacAddress[6]; /* 0x14 */ 2971 U8 Reserved3; /* 0x1A */ 2972 U8 Reserved4; /* 0x1B */ 2973 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2974 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2975 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2976 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2977 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2978 U32 Reserved5; /* 0x6C */ 2979 U32 Reserved6; /* 0x70 */ 2980 U32 Reserved7; /* 0x74 */ 2981 U32 Reserved8; /* 0x78 */ 2982 U8 HostName 2983 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2984} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2985 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2986 2987#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2988 2989/* values for Ethernet Page 1 Flags field */ 2990#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2991#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2992#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2993#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2994#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2995#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2996#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2997#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2998#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2999 3000/* values for Ethernet Page 1 MediaState field */ 3001#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3002#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3003#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3004 3005#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3006#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3007#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3008#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3009#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3010 3011 3012/**************************************************************************** 3013* Extended Manufacturing Config Pages 3014****************************************************************************/ 3015 3016/* 3017 * Generic structure to use for product-specific extended manufacturing pages 3018 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3019 * Page 60). 3020 */ 3021 3022typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3023 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3024 U32 ProductSpecificInfo; /* 0x08 */ 3025} MPI2_CONFIG_PAGE_EXT_MAN_PS, 3026 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3027 Mpi2ExtManufacturingPagePS_t, 3028 MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3029 3030/* PageVersion should be provided by product-specific code */ 3031 3032#endif 3033 3034