1/* 2 * Copyright (c) 2000-2014 LSI Corporation. 3 * 4 * 5 * Name: mpi2_ioc.h 6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 7 * Creation Date: October 11, 2006 8 * 9 * mpi2_ioc.h Version: 02.00.23 10 * 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * prefix are for use only on MPI v2.5 products, and must not be used 13 * with MPI v2.0 products. Unless otherwise noted, names beginning with 14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 15 * 16 * Version History 17 * --------------- 18 * 19 * Date Version Description 20 * -------- -------- ------------------------------------------------------ 21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 22 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 23 * MaxTargets. 24 * Added TotalImageSize field to FWDownload Request. 25 * Added reserved words to FWUpload Request. 26 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 27 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 28 * request and replaced it with 29 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 30 * Replaced the MinReplyQueueDepth field of the IOCFacts 31 * reply with MaxReplyDescriptorPostQueueDepth. 32 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 33 * depth for the Reply Descriptor Post Queue. 34 * Added SASAddress field to Initiator Device Table 35 * Overflow Event data. 36 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 37 * for SAS Initiator Device Status Change Event data. 38 * Modified Reason Code defines for SAS Topology Change 39 * List Event data, including adding a bit for PHY Vacant 40 * status, and adding a mask for the Reason Code. 41 * Added define for 42 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 43 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 44 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 45 * the IOCFacts Reply. 46 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 47 * Moved MPI2_VERSION_UNION to mpi2.h. 48 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 49 * instead of enables, and added SASBroadcastPrimitiveMasks 50 * field. 51 * Added Log Entry Added Event and related structure. 52 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 53 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 54 * Added MaxVolumes and MaxPersistentEntries fields to 55 * IOCFacts reply. 56 * Added ProtocalFlags and IOCCapabilities fields to 57 * MPI2_FW_IMAGE_HEADER. 58 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 59 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 60 * a U16 (from a U32). 61 * Removed extra 's' from EventMasks name. 62 * 06-27-08 02.00.08 Fixed an offset in a comment. 63 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 64 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 65 * renamed MinReplyFrameSize to ReplyFrameSize. 66 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 67 * Added two new RAIDOperation values for Integrated RAID 68 * Operations Status Event data. 69 * Added four new IR Configuration Change List Event data 70 * ReasonCode values. 71 * Added two new ReasonCode defines for SAS Device Status 72 * Change Event data. 73 * Added three new DiscoveryStatus bits for the SAS 74 * Discovery event data. 75 * Added Multiplexing Status Change bit to the PhyStatus 76 * field of the SAS Topology Change List event data. 77 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 78 * BootFlags are now product-specific. 79 * Added defines for the indivdual signature bytes 80 * for MPI2_INIT_IMAGE_FOOTER. 81 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 82 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 83 * define. 84 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 85 * define. 86 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 87 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 88 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 89 * Added two new reason codes for SAS Device Status Change 90 * Event. 91 * Added new event: SAS PHY Counter. 92 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 93 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 94 * Added new product id family for 2208. 95 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 96 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 97 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 98 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 99 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 100 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 101 * Added Host Based Discovery Phy Event data. 102 * Added defines for ProductID Product field 103 * (MPI2_FW_HEADER_PID_). 104 * Modified values for SAS ProductID Family 105 * (MPI2_FW_HEADER_PID_FAMILY_). 106 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 107 * Added PowerManagementControl Request structures and 108 * defines. 109 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 110 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 111 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 112 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 113 * SASNotifyPrimitiveMasks field to 114 * MPI2_EVENT_NOTIFICATION_REQUEST. 115 * Added Temperature Threshold Event. 116 * Added Host Message Event. 117 * Added Send Host Message request and reply. 118 * 05-25-11 02.00.18 For Extended Image Header, added 119 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 120 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 121 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 122 * 08-24-11 02.00.19 Added PhysicalPort field to 123 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 124 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 125 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 126 * 03-29-12 02.00.21 Added a product specific range to event values. 127 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 128 * Added ElapsedSeconds field to 129 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 130 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 131 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 132 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 133 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 134 * Added Encrypted Hash Extended Image. 135 * -------------------------------------------------------------------------- 136 */ 137 138#ifndef MPI2_IOC_H 139#define MPI2_IOC_H 140 141/***************************************************************************** 142* 143* IOC Messages 144* 145*****************************************************************************/ 146 147/**************************************************************************** 148* IOCInit message 149****************************************************************************/ 150 151/*IOCInit Request message */ 152typedef struct _MPI2_IOC_INIT_REQUEST { 153 U8 WhoInit; /*0x00 */ 154 U8 Reserved1; /*0x01 */ 155 U8 ChainOffset; /*0x02 */ 156 U8 Function; /*0x03 */ 157 U16 Reserved2; /*0x04 */ 158 U8 Reserved3; /*0x06 */ 159 U8 MsgFlags; /*0x07 */ 160 U8 VP_ID; /*0x08 */ 161 U8 VF_ID; /*0x09 */ 162 U16 Reserved4; /*0x0A */ 163 U16 MsgVersion; /*0x0C */ 164 U16 HeaderVersion; /*0x0E */ 165 U32 Reserved5; /*0x10 */ 166 U16 Reserved6; /*0x14 */ 167 U8 Reserved7; /*0x16 */ 168 U8 HostMSIxVectors; /*0x17 */ 169 U16 Reserved8; /*0x18 */ 170 U16 SystemRequestFrameSize; /*0x1A */ 171 U16 ReplyDescriptorPostQueueDepth; /*0x1C */ 172 U16 ReplyFreeQueueDepth; /*0x1E */ 173 U32 SenseBufferAddressHigh; /*0x20 */ 174 U32 SystemReplyAddressHigh; /*0x24 */ 175 U64 SystemRequestFrameBaseAddress; /*0x28 */ 176 U64 ReplyDescriptorPostQueueAddress; /*0x30 */ 177 U64 ReplyFreeQueueAddress; /*0x38 */ 178 U64 TimeStamp; /*0x40 */ 179} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST, 180 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t; 181 182/*WhoInit values */ 183#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 184#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 185#define MPI2_WHOINIT_ROM_BIOS (0x02) 186#define MPI2_WHOINIT_PCI_PEER (0x03) 187#define MPI2_WHOINIT_HOST_DRIVER (0x04) 188#define MPI2_WHOINIT_MANUFACTURER (0x05) 189 190/* MsgFlags */ 191#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 192 193 194/*MsgVersion */ 195#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 196#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 197#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 198#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 199 200/*HeaderVersion */ 201#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 202#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 203#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 204#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 205 206/*minimum depth for a Reply Descriptor Post Queue */ 207#define MPI2_RDPQ_DEPTH_MIN (16) 208 209/* Reply Descriptor Post Queue Array Entry */ 210typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY { 211 U64 RDPQBaseAddress; /* 0x00 */ 212 U32 Reserved1; /* 0x08 */ 213 U32 Reserved2; /* 0x0C */ 214} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 215*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 216Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry; 217 218 219/*IOCInit Reply message */ 220typedef struct _MPI2_IOC_INIT_REPLY { 221 U8 WhoInit; /*0x00 */ 222 U8 Reserved1; /*0x01 */ 223 U8 MsgLength; /*0x02 */ 224 U8 Function; /*0x03 */ 225 U16 Reserved2; /*0x04 */ 226 U8 Reserved3; /*0x06 */ 227 U8 MsgFlags; /*0x07 */ 228 U8 VP_ID; /*0x08 */ 229 U8 VF_ID; /*0x09 */ 230 U16 Reserved4; /*0x0A */ 231 U16 Reserved5; /*0x0C */ 232 U16 IOCStatus; /*0x0E */ 233 U32 IOCLogInfo; /*0x10 */ 234} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY, 235 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t; 236 237/**************************************************************************** 238* IOCFacts message 239****************************************************************************/ 240 241/*IOCFacts Request message */ 242typedef struct _MPI2_IOC_FACTS_REQUEST { 243 U16 Reserved1; /*0x00 */ 244 U8 ChainOffset; /*0x02 */ 245 U8 Function; /*0x03 */ 246 U16 Reserved2; /*0x04 */ 247 U8 Reserved3; /*0x06 */ 248 U8 MsgFlags; /*0x07 */ 249 U8 VP_ID; /*0x08 */ 250 U8 VF_ID; /*0x09 */ 251 U16 Reserved4; /*0x0A */ 252} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST, 253 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t; 254 255/*IOCFacts Reply message */ 256typedef struct _MPI2_IOC_FACTS_REPLY { 257 U16 MsgVersion; /*0x00 */ 258 U8 MsgLength; /*0x02 */ 259 U8 Function; /*0x03 */ 260 U16 HeaderVersion; /*0x04 */ 261 U8 IOCNumber; /*0x06 */ 262 U8 MsgFlags; /*0x07 */ 263 U8 VP_ID; /*0x08 */ 264 U8 VF_ID; /*0x09 */ 265 U16 Reserved1; /*0x0A */ 266 U16 IOCExceptions; /*0x0C */ 267 U16 IOCStatus; /*0x0E */ 268 U32 IOCLogInfo; /*0x10 */ 269 U8 MaxChainDepth; /*0x14 */ 270 U8 WhoInit; /*0x15 */ 271 U8 NumberOfPorts; /*0x16 */ 272 U8 MaxMSIxVectors; /*0x17 */ 273 U16 RequestCredit; /*0x18 */ 274 U16 ProductID; /*0x1A */ 275 U32 IOCCapabilities; /*0x1C */ 276 MPI2_VERSION_UNION FWVersion; /*0x20 */ 277 U16 IOCRequestFrameSize; /*0x24 */ 278 U16 IOCMaxChainSegmentSize; /*0x26 */ 279 U16 MaxInitiators; /*0x28 */ 280 U16 MaxTargets; /*0x2A */ 281 U16 MaxSasExpanders; /*0x2C */ 282 U16 MaxEnclosures; /*0x2E */ 283 U16 ProtocolFlags; /*0x30 */ 284 U16 HighPriorityCredit; /*0x32 */ 285 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */ 286 U8 ReplyFrameSize; /*0x36 */ 287 U8 MaxVolumes; /*0x37 */ 288 U16 MaxDevHandle; /*0x38 */ 289 U16 MaxPersistentEntries; /*0x3A */ 290 U16 MinDevHandle; /*0x3C */ 291 U16 Reserved4; /*0x3E */ 292} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY, 293 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t; 294 295/*MsgVersion */ 296#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 297#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 298#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 299#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 300 301/*HeaderVersion */ 302#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 303#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 304#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 305#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 306 307/*IOCExceptions */ 308#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 309#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 310 311#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 312#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 313#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 314#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 315#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 316 317#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 318#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 319#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 320#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 321#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 322 323/*defines for WhoInit field are after the IOCInit Request */ 324 325/*ProductID field uses MPI2_FW_HEADER_PID_ */ 326 327/*IOCCapabilities */ 328#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 329#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 330#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 331#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 332#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 333#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 334#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 335#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 336#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 337#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 338#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 339#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 340#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 341#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 342#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 343 344/*ProtocolFlags */ 345#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 346#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 347 348/**************************************************************************** 349* PortFacts message 350****************************************************************************/ 351 352/*PortFacts Request message */ 353typedef struct _MPI2_PORT_FACTS_REQUEST { 354 U16 Reserved1; /*0x00 */ 355 U8 ChainOffset; /*0x02 */ 356 U8 Function; /*0x03 */ 357 U16 Reserved2; /*0x04 */ 358 U8 PortNumber; /*0x06 */ 359 U8 MsgFlags; /*0x07 */ 360 U8 VP_ID; /*0x08 */ 361 U8 VF_ID; /*0x09 */ 362 U16 Reserved3; /*0x0A */ 363} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST, 364 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t; 365 366/*PortFacts Reply message */ 367typedef struct _MPI2_PORT_FACTS_REPLY { 368 U16 Reserved1; /*0x00 */ 369 U8 MsgLength; /*0x02 */ 370 U8 Function; /*0x03 */ 371 U16 Reserved2; /*0x04 */ 372 U8 PortNumber; /*0x06 */ 373 U8 MsgFlags; /*0x07 */ 374 U8 VP_ID; /*0x08 */ 375 U8 VF_ID; /*0x09 */ 376 U16 Reserved3; /*0x0A */ 377 U16 Reserved4; /*0x0C */ 378 U16 IOCStatus; /*0x0E */ 379 U32 IOCLogInfo; /*0x10 */ 380 U8 Reserved5; /*0x14 */ 381 U8 PortType; /*0x15 */ 382 U16 Reserved6; /*0x16 */ 383 U16 MaxPostedCmdBuffers; /*0x18 */ 384 U16 Reserved7; /*0x1A */ 385} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY, 386 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t; 387 388/*PortType values */ 389#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 390#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 391#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 392#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 393#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 394 395/**************************************************************************** 396* PortEnable message 397****************************************************************************/ 398 399/*PortEnable Request message */ 400typedef struct _MPI2_PORT_ENABLE_REQUEST { 401 U16 Reserved1; /*0x00 */ 402 U8 ChainOffset; /*0x02 */ 403 U8 Function; /*0x03 */ 404 U8 Reserved2; /*0x04 */ 405 U8 PortFlags; /*0x05 */ 406 U8 Reserved3; /*0x06 */ 407 U8 MsgFlags; /*0x07 */ 408 U8 VP_ID; /*0x08 */ 409 U8 VF_ID; /*0x09 */ 410 U16 Reserved4; /*0x0A */ 411} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST, 412 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t; 413 414/*PortEnable Reply message */ 415typedef struct _MPI2_PORT_ENABLE_REPLY { 416 U16 Reserved1; /*0x00 */ 417 U8 MsgLength; /*0x02 */ 418 U8 Function; /*0x03 */ 419 U8 Reserved2; /*0x04 */ 420 U8 PortFlags; /*0x05 */ 421 U8 Reserved3; /*0x06 */ 422 U8 MsgFlags; /*0x07 */ 423 U8 VP_ID; /*0x08 */ 424 U8 VF_ID; /*0x09 */ 425 U16 Reserved4; /*0x0A */ 426 U16 Reserved5; /*0x0C */ 427 U16 IOCStatus; /*0x0E */ 428 U32 IOCLogInfo; /*0x10 */ 429} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY, 430 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t; 431 432/**************************************************************************** 433* EventNotification message 434****************************************************************************/ 435 436/*EventNotification Request message */ 437#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 438 439typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST { 440 U16 Reserved1; /*0x00 */ 441 U8 ChainOffset; /*0x02 */ 442 U8 Function; /*0x03 */ 443 U16 Reserved2; /*0x04 */ 444 U8 Reserved3; /*0x06 */ 445 U8 MsgFlags; /*0x07 */ 446 U8 VP_ID; /*0x08 */ 447 U8 VF_ID; /*0x09 */ 448 U16 Reserved4; /*0x0A */ 449 U32 Reserved5; /*0x0C */ 450 U32 Reserved6; /*0x10 */ 451 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */ 452 U16 SASBroadcastPrimitiveMasks; /*0x24 */ 453 U16 SASNotifyPrimitiveMasks; /*0x26 */ 454 U32 Reserved8; /*0x28 */ 455} MPI2_EVENT_NOTIFICATION_REQUEST, 456 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 457 Mpi2EventNotificationRequest_t, 458 *pMpi2EventNotificationRequest_t; 459 460/*EventNotification Reply message */ 461typedef struct _MPI2_EVENT_NOTIFICATION_REPLY { 462 U16 EventDataLength; /*0x00 */ 463 U8 MsgLength; /*0x02 */ 464 U8 Function; /*0x03 */ 465 U16 Reserved1; /*0x04 */ 466 U8 AckRequired; /*0x06 */ 467 U8 MsgFlags; /*0x07 */ 468 U8 VP_ID; /*0x08 */ 469 U8 VF_ID; /*0x09 */ 470 U16 Reserved2; /*0x0A */ 471 U16 Reserved3; /*0x0C */ 472 U16 IOCStatus; /*0x0E */ 473 U32 IOCLogInfo; /*0x10 */ 474 U16 Event; /*0x14 */ 475 U16 Reserved4; /*0x16 */ 476 U32 EventContext; /*0x18 */ 477 U32 EventData[1]; /*0x1C */ 478} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY, 479 Mpi2EventNotificationReply_t, 480 *pMpi2EventNotificationReply_t; 481 482/*AckRequired */ 483#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 484#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 485 486/*Event */ 487#define MPI2_EVENT_LOG_DATA (0x0001) 488#define MPI2_EVENT_STATE_CHANGE (0x0002) 489#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 490#define MPI2_EVENT_EVENT_CHANGE (0x000A) 491#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */ 492#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 493#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 494#define MPI2_EVENT_SAS_DISCOVERY (0x0016) 495#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 496#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 497#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 498#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 499#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 500#define MPI2_EVENT_IR_VOLUME (0x001E) 501#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 502#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 503#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 504#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 505#define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 506#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 507#define MPI2_EVENT_SAS_QUIESCE (0x0025) 508#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 509#define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 510#define MPI2_EVENT_HOST_MESSAGE (0x0028) 511#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 512#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 513#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 514 515/*Log Entry Added Event data */ 516 517/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 518#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 519 520typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED { 521 U64 TimeStamp; /*0x00 */ 522 U32 Reserved1; /*0x08 */ 523 U16 LogSequence; /*0x0C */ 524 U16 LogEntryQualifier; /*0x0E */ 525 U8 VP_ID; /*0x10 */ 526 U8 VF_ID; /*0x11 */ 527 U16 Reserved2; /*0x12 */ 528 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */ 529} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 530 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 531 Mpi2EventDataLogEntryAdded_t, 532 *pMpi2EventDataLogEntryAdded_t; 533 534/*GPIO Interrupt Event data */ 535 536typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT { 537 U8 GPIONum; /*0x00 */ 538 U8 Reserved1; /*0x01 */ 539 U16 Reserved2; /*0x02 */ 540} MPI2_EVENT_DATA_GPIO_INTERRUPT, 541 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 542 Mpi2EventDataGpioInterrupt_t, 543 *pMpi2EventDataGpioInterrupt_t; 544 545/*Temperature Threshold Event data */ 546 547typedef struct _MPI2_EVENT_DATA_TEMPERATURE { 548 U16 Status; /*0x00 */ 549 U8 SensorNum; /*0x02 */ 550 U8 Reserved1; /*0x03 */ 551 U16 CurrentTemperature; /*0x04 */ 552 U16 Reserved2; /*0x06 */ 553 U32 Reserved3; /*0x08 */ 554 U32 Reserved4; /*0x0C */ 555} MPI2_EVENT_DATA_TEMPERATURE, 556 *PTR_MPI2_EVENT_DATA_TEMPERATURE, 557 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t; 558 559/*Temperature Threshold Event data Status bits */ 560#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 561#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 562#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 563#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 564 565/*Host Message Event data */ 566 567typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE { 568 U8 SourceVF_ID; /*0x00 */ 569 U8 Reserved1; /*0x01 */ 570 U16 Reserved2; /*0x02 */ 571 U32 Reserved3; /*0x04 */ 572 U32 HostData[1]; /*0x08 */ 573} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 574 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t; 575 576/*Power Performance Change Event */ 577 578typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE { 579 U8 CurrentPowerMode; /*0x00 */ 580 U8 PreviousPowerMode; /*0x01 */ 581 U16 Reserved1; /*0x02 */ 582} MPI2_EVENT_DATA_POWER_PERF_CHANGE, 583 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 584 Mpi2EventDataPowerPerfChange_t, 585 *pMpi2EventDataPowerPerfChange_t; 586 587/*defines for CurrentPowerMode and PreviousPowerMode fields */ 588#define MPI2_EVENT_PM_INIT_MASK (0xC0) 589#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 590#define MPI2_EVENT_PM_INIT_HOST (0x40) 591#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 592#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 593 594#define MPI2_EVENT_PM_MODE_MASK (0x07) 595#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 596#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 597#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 598#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 599#define MPI2_EVENT_PM_MODE_STANDBY (0x06) 600 601/*Hard Reset Received Event data */ 602 603typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED { 604 U8 Reserved1; /*0x00 */ 605 U8 Port; /*0x01 */ 606 U16 Reserved2; /*0x02 */ 607} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 608 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 609 Mpi2EventDataHardResetReceived_t, 610 *pMpi2EventDataHardResetReceived_t; 611 612/*Task Set Full Event data */ 613/* this event is obsolete */ 614 615typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL { 616 U16 DevHandle; /*0x00 */ 617 U16 CurrentDepth; /*0x02 */ 618} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 619 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t; 620 621/*SAS Device Status Change Event data */ 622 623typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE { 624 U16 TaskTag; /*0x00 */ 625 U8 ReasonCode; /*0x02 */ 626 U8 PhysicalPort; /*0x03 */ 627 U8 ASC; /*0x04 */ 628 U8 ASCQ; /*0x05 */ 629 U16 DevHandle; /*0x06 */ 630 U32 Reserved2; /*0x08 */ 631 U64 SASAddress; /*0x0C */ 632 U8 LUN[8]; /*0x14 */ 633} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 634 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 635 Mpi2EventDataSasDeviceStatusChange_t, 636 *pMpi2EventDataSasDeviceStatusChange_t; 637 638/*SAS Device Status Change Event data ReasonCode values */ 639#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 640#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 641#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 642#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 643#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 644#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 645#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 646#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 647#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 648#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 649#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 650#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 651#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 652 653/*Integrated RAID Operation Status Event data */ 654 655typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS { 656 U16 VolDevHandle; /*0x00 */ 657 U16 Reserved1; /*0x02 */ 658 U8 RAIDOperation; /*0x04 */ 659 U8 PercentComplete; /*0x05 */ 660 U16 Reserved2; /*0x06 */ 661 U32 ElapsedSeconds; /*0x08 */ 662} MPI2_EVENT_DATA_IR_OPERATION_STATUS, 663 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 664 Mpi2EventDataIrOperationStatus_t, 665 *pMpi2EventDataIrOperationStatus_t; 666 667/*Integrated RAID Operation Status Event data RAIDOperation values */ 668#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 669#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 670#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 671#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 672#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 673 674/*Integrated RAID Volume Event data */ 675 676typedef struct _MPI2_EVENT_DATA_IR_VOLUME { 677 U16 VolDevHandle; /*0x00 */ 678 U8 ReasonCode; /*0x02 */ 679 U8 Reserved1; /*0x03 */ 680 U32 NewValue; /*0x04 */ 681 U32 PreviousValue; /*0x08 */ 682} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME, 683 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t; 684 685/*Integrated RAID Volume Event data ReasonCode values */ 686#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 687#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 688#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 689 690/*Integrated RAID Physical Disk Event data */ 691 692typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK { 693 U16 Reserved1; /*0x00 */ 694 U8 ReasonCode; /*0x02 */ 695 U8 PhysDiskNum; /*0x03 */ 696 U16 PhysDiskDevHandle; /*0x04 */ 697 U16 Reserved2; /*0x06 */ 698 U16 Slot; /*0x08 */ 699 U16 EnclosureHandle; /*0x0A */ 700 U32 NewValue; /*0x0C */ 701 U32 PreviousValue; /*0x10 */ 702} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 703 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 704 Mpi2EventDataIrPhysicalDisk_t, 705 *pMpi2EventDataIrPhysicalDisk_t; 706 707/*Integrated RAID Physical Disk Event data ReasonCode values */ 708#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 709#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 710#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 711 712/*Integrated RAID Configuration Change List Event data */ 713 714/* 715 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 716 *one and check NumElements at runtime. 717 */ 718#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 719#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 720#endif 721 722typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT { 723 U16 ElementFlags; /*0x00 */ 724 U16 VolDevHandle; /*0x02 */ 725 U8 ReasonCode; /*0x04 */ 726 U8 PhysDiskNum; /*0x05 */ 727 U16 PhysDiskDevHandle; /*0x06 */ 728} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 729 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t; 730 731/*IR Configuration Change List Event data ElementFlags values */ 732#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 733#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 734#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 735#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 736 737/*IR Configuration Change List Event data ReasonCode values */ 738#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 739#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 740#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 741#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 742#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 743#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 744#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 745#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 746#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 747 748typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST { 749 U8 NumElements; /*0x00 */ 750 U8 Reserved1; /*0x01 */ 751 U8 Reserved2; /*0x02 */ 752 U8 ConfigNum; /*0x03 */ 753 U32 Flags; /*0x04 */ 754 MPI2_EVENT_IR_CONFIG_ELEMENT 755 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */ 756} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 757 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 758 Mpi2EventDataIrConfigChangeList_t, 759 *pMpi2EventDataIrConfigChangeList_t; 760 761/*IR Configuration Change List Event data Flags values */ 762#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 763 764/*SAS Discovery Event data */ 765 766typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY { 767 U8 Flags; /*0x00 */ 768 U8 ReasonCode; /*0x01 */ 769 U8 PhysicalPort; /*0x02 */ 770 U8 Reserved1; /*0x03 */ 771 U32 DiscoveryStatus; /*0x04 */ 772} MPI2_EVENT_DATA_SAS_DISCOVERY, 773 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 774 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t; 775 776/*SAS Discovery Event data Flags values */ 777#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 778#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 779 780/*SAS Discovery Event data ReasonCode values */ 781#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 782#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 783 784/*SAS Discovery Event data DiscoveryStatus values */ 785#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 786#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 787#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 788#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 789#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 790#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 791#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 792#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 793#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 794#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 795#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 796#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 797#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 798#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 799#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 800#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 801#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 802#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 803#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 804#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 805 806/*SAS Broadcast Primitive Event data */ 807 808typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE { 809 U8 PhyNum; /*0x00 */ 810 U8 Port; /*0x01 */ 811 U8 PortWidth; /*0x02 */ 812 U8 Primitive; /*0x03 */ 813} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 814 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 815 Mpi2EventDataSasBroadcastPrimitive_t, 816 *pMpi2EventDataSasBroadcastPrimitive_t; 817 818/*defines for the Primitive field */ 819#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 820#define MPI2_EVENT_PRIMITIVE_SES (0x02) 821#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 822#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 823#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 824#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 825#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 826#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 827 828/*SAS Notify Primitive Event data */ 829 830typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE { 831 U8 PhyNum; /*0x00 */ 832 U8 Port; /*0x01 */ 833 U8 Reserved1; /*0x02 */ 834 U8 Primitive; /*0x03 */ 835} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 836 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 837 Mpi2EventDataSasNotifyPrimitive_t, 838 *pMpi2EventDataSasNotifyPrimitive_t; 839 840/*defines for the Primitive field */ 841#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 842#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 843#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 844#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 845 846/*SAS Initiator Device Status Change Event data */ 847 848typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE { 849 U8 ReasonCode; /*0x00 */ 850 U8 PhysicalPort; /*0x01 */ 851 U16 DevHandle; /*0x02 */ 852 U64 SASAddress; /*0x04 */ 853} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 854 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 855 Mpi2EventDataSasInitDevStatusChange_t, 856 *pMpi2EventDataSasInitDevStatusChange_t; 857 858/*SAS Initiator Device Status Change event ReasonCode values */ 859#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 860#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 861 862/*SAS Initiator Device Table Overflow Event data */ 863 864typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW { 865 U16 MaxInit; /*0x00 */ 866 U16 CurrentInit; /*0x02 */ 867 U64 SASAddress; /*0x04 */ 868} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 869 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 870 Mpi2EventDataSasInitTableOverflow_t, 871 *pMpi2EventDataSasInitTableOverflow_t; 872 873/*SAS Topology Change List Event data */ 874 875/* 876 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 877 *one and check NumEntries at runtime. 878 */ 879#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 880#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 881#endif 882 883typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY { 884 U16 AttachedDevHandle; /*0x00 */ 885 U8 LinkRate; /*0x02 */ 886 U8 PhyStatus; /*0x03 */ 887} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 888 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t; 889 890typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST { 891 U16 EnclosureHandle; /*0x00 */ 892 U16 ExpanderDevHandle; /*0x02 */ 893 U8 NumPhys; /*0x04 */ 894 U8 Reserved1; /*0x05 */ 895 U16 Reserved2; /*0x06 */ 896 U8 NumEntries; /*0x08 */ 897 U8 StartPhyNum; /*0x09 */ 898 U8 ExpStatus; /*0x0A */ 899 U8 PhysicalPort; /*0x0B */ 900 MPI2_EVENT_SAS_TOPO_PHY_ENTRY 901 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */ 902} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 903 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 904 Mpi2EventDataSasTopologyChangeList_t, 905 *pMpi2EventDataSasTopologyChangeList_t; 906 907/*values for the ExpStatus field */ 908#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 909#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 910#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 911#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 912#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 913 914/*defines for the LinkRate field */ 915#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 916#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 917#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 918#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 919 920#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 921#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 922#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 923#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 924#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 925#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 926#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 927#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 928#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 929#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 930#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 931 932/*values for the PhyStatus field */ 933#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 934#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 935/*values for the PhyStatus ReasonCode sub-field */ 936#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 937#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 938#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 939#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 940#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 941#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 942 943/*SAS Enclosure Device Status Change Event data */ 944 945typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE { 946 U16 EnclosureHandle; /*0x00 */ 947 U8 ReasonCode; /*0x02 */ 948 U8 PhysicalPort; /*0x03 */ 949 U64 EnclosureLogicalID; /*0x04 */ 950 U16 NumSlots; /*0x0C */ 951 U16 StartSlot; /*0x0E */ 952 U32 PhyBits; /*0x10 */ 953} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 954 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 955 Mpi2EventDataSasEnclDevStatusChange_t, 956 *pMpi2EventDataSasEnclDevStatusChange_t; 957 958/*SAS Enclosure Device Status Change event ReasonCode values */ 959#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 960#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 961 962/*SAS PHY Counter Event data */ 963 964typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER { 965 U64 TimeStamp; /*0x00 */ 966 U32 Reserved1; /*0x08 */ 967 U8 PhyEventCode; /*0x0C */ 968 U8 PhyNum; /*0x0D */ 969 U16 Reserved2; /*0x0E */ 970 U32 PhyEventInfo; /*0x10 */ 971 U8 CounterType; /*0x14 */ 972 U8 ThresholdWindow; /*0x15 */ 973 U8 TimeUnits; /*0x16 */ 974 U8 Reserved3; /*0x17 */ 975 U32 EventThreshold; /*0x18 */ 976 U16 ThresholdFlags; /*0x1C */ 977 U16 Reserved4; /*0x1E */ 978} MPI2_EVENT_DATA_SAS_PHY_COUNTER, 979 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 980 Mpi2EventDataSasPhyCounter_t, 981 *pMpi2EventDataSasPhyCounter_t; 982 983/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h 984 *for the PhyEventCode field */ 985 986/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h 987 *for the CounterType field */ 988 989/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h 990 *for the TimeUnits field */ 991 992/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h 993 *for the ThresholdFlags field */ 994 995/*SAS Quiesce Event data */ 996 997typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE { 998 U8 ReasonCode; /*0x00 */ 999 U8 Reserved1; /*0x01 */ 1000 U16 Reserved2; /*0x02 */ 1001 U32 Reserved3; /*0x04 */ 1002} MPI2_EVENT_DATA_SAS_QUIESCE, 1003 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1004 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t; 1005 1006/*SAS Quiesce Event data ReasonCode values */ 1007#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1008#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1009 1010/*Host Based Discovery Phy Event data */ 1011 1012typedef struct _MPI2_EVENT_HBD_PHY_SAS { 1013 U8 Flags; /*0x00 */ 1014 U8 NegotiatedLinkRate; /*0x01 */ 1015 U8 PhyNum; /*0x02 */ 1016 U8 PhysicalPort; /*0x03 */ 1017 U32 Reserved1; /*0x04 */ 1018 U8 InitialFrame[28]; /*0x08 */ 1019} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS, 1020 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t; 1021 1022/*values for the Flags field */ 1023#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1024#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1025 1026/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h 1027 *for the NegotiatedLinkRate field */ 1028 1029typedef union _MPI2_EVENT_HBD_DESCRIPTOR { 1030 MPI2_EVENT_HBD_PHY_SAS Sas; 1031} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1032 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t; 1033 1034typedef struct _MPI2_EVENT_DATA_HBD_PHY { 1035 U8 DescriptorType; /*0x00 */ 1036 U8 Reserved1; /*0x01 */ 1037 U16 Reserved2; /*0x02 */ 1038 U32 Reserved3; /*0x04 */ 1039 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */ 1040} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY, 1041 Mpi2EventDataHbdPhy_t, 1042 *pMpi2EventDataMpi2EventDataHbdPhy_t; 1043 1044/*values for the DescriptorType field */ 1045#define MPI2_EVENT_HBD_DT_SAS (0x01) 1046 1047/**************************************************************************** 1048* EventAck message 1049****************************************************************************/ 1050 1051/*EventAck Request message */ 1052typedef struct _MPI2_EVENT_ACK_REQUEST { 1053 U16 Reserved1; /*0x00 */ 1054 U8 ChainOffset; /*0x02 */ 1055 U8 Function; /*0x03 */ 1056 U16 Reserved2; /*0x04 */ 1057 U8 Reserved3; /*0x06 */ 1058 U8 MsgFlags; /*0x07 */ 1059 U8 VP_ID; /*0x08 */ 1060 U8 VF_ID; /*0x09 */ 1061 U16 Reserved4; /*0x0A */ 1062 U16 Event; /*0x0C */ 1063 U16 Reserved5; /*0x0E */ 1064 U32 EventContext; /*0x10 */ 1065} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST, 1066 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t; 1067 1068/*EventAck Reply message */ 1069typedef struct _MPI2_EVENT_ACK_REPLY { 1070 U16 Reserved1; /*0x00 */ 1071 U8 MsgLength; /*0x02 */ 1072 U8 Function; /*0x03 */ 1073 U16 Reserved2; /*0x04 */ 1074 U8 Reserved3; /*0x06 */ 1075 U8 MsgFlags; /*0x07 */ 1076 U8 VP_ID; /*0x08 */ 1077 U8 VF_ID; /*0x09 */ 1078 U16 Reserved4; /*0x0A */ 1079 U16 Reserved5; /*0x0C */ 1080 U16 IOCStatus; /*0x0E */ 1081 U32 IOCLogInfo; /*0x10 */ 1082} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY, 1083 Mpi2EventAckReply_t, *pMpi2EventAckReply_t; 1084 1085/**************************************************************************** 1086* SendHostMessage message 1087****************************************************************************/ 1088 1089/*SendHostMessage Request message */ 1090typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST { 1091 U16 HostDataLength; /*0x00 */ 1092 U8 ChainOffset; /*0x02 */ 1093 U8 Function; /*0x03 */ 1094 U16 Reserved1; /*0x04 */ 1095 U8 Reserved2; /*0x06 */ 1096 U8 MsgFlags; /*0x07 */ 1097 U8 VP_ID; /*0x08 */ 1098 U8 VF_ID; /*0x09 */ 1099 U16 Reserved3; /*0x0A */ 1100 U8 Reserved4; /*0x0C */ 1101 U8 DestVF_ID; /*0x0D */ 1102 U16 Reserved5; /*0x0E */ 1103 U32 Reserved6; /*0x10 */ 1104 U32 Reserved7; /*0x14 */ 1105 U32 Reserved8; /*0x18 */ 1106 U32 Reserved9; /*0x1C */ 1107 U32 Reserved10; /*0x20 */ 1108 U32 HostData[1]; /*0x24 */ 1109} MPI2_SEND_HOST_MESSAGE_REQUEST, 1110 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1111 Mpi2SendHostMessageRequest_t, 1112 *pMpi2SendHostMessageRequest_t; 1113 1114/*SendHostMessage Reply message */ 1115typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY { 1116 U16 HostDataLength; /*0x00 */ 1117 U8 MsgLength; /*0x02 */ 1118 U8 Function; /*0x03 */ 1119 U16 Reserved1; /*0x04 */ 1120 U8 Reserved2; /*0x06 */ 1121 U8 MsgFlags; /*0x07 */ 1122 U8 VP_ID; /*0x08 */ 1123 U8 VF_ID; /*0x09 */ 1124 U16 Reserved3; /*0x0A */ 1125 U16 Reserved4; /*0x0C */ 1126 U16 IOCStatus; /*0x0E */ 1127 U32 IOCLogInfo; /*0x10 */ 1128} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1129 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t; 1130 1131/**************************************************************************** 1132* FWDownload message 1133****************************************************************************/ 1134 1135/*MPI v2.0 FWDownload Request message */ 1136typedef struct _MPI2_FW_DOWNLOAD_REQUEST { 1137 U8 ImageType; /*0x00 */ 1138 U8 Reserved1; /*0x01 */ 1139 U8 ChainOffset; /*0x02 */ 1140 U8 Function; /*0x03 */ 1141 U16 Reserved2; /*0x04 */ 1142 U8 Reserved3; /*0x06 */ 1143 U8 MsgFlags; /*0x07 */ 1144 U8 VP_ID; /*0x08 */ 1145 U8 VF_ID; /*0x09 */ 1146 U16 Reserved4; /*0x0A */ 1147 U32 TotalImageSize; /*0x0C */ 1148 U32 Reserved5; /*0x10 */ 1149 MPI2_MPI_SGE_UNION SGL; /*0x14 */ 1150} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST, 1151 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest; 1152 1153#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1154 1155#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1156#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1157#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1158#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1159#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1160#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1161#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1162#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1163#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) 1164#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1165 1166/*MPI v2.0 FWDownload TransactionContext Element */ 1167typedef struct _MPI2_FW_DOWNLOAD_TCSGE { 1168 U8 Reserved1; /*0x00 */ 1169 U8 ContextSize; /*0x01 */ 1170 U8 DetailsLength; /*0x02 */ 1171 U8 Flags; /*0x03 */ 1172 U32 Reserved2; /*0x04 */ 1173 U32 ImageOffset; /*0x08 */ 1174 U32 ImageSize; /*0x0C */ 1175} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE, 1176 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t; 1177 1178/*MPI v2.5 FWDownload Request message */ 1179typedef struct _MPI25_FW_DOWNLOAD_REQUEST { 1180 U8 ImageType; /*0x00 */ 1181 U8 Reserved1; /*0x01 */ 1182 U8 ChainOffset; /*0x02 */ 1183 U8 Function; /*0x03 */ 1184 U16 Reserved2; /*0x04 */ 1185 U8 Reserved3; /*0x06 */ 1186 U8 MsgFlags; /*0x07 */ 1187 U8 VP_ID; /*0x08 */ 1188 U8 VF_ID; /*0x09 */ 1189 U16 Reserved4; /*0x0A */ 1190 U32 TotalImageSize; /*0x0C */ 1191 U32 Reserved5; /*0x10 */ 1192 U32 Reserved6; /*0x14 */ 1193 U32 ImageOffset; /*0x18 */ 1194 U32 ImageSize; /*0x1C */ 1195 MPI25_SGE_IO_UNION SGL; /*0x20 */ 1196} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST, 1197 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest; 1198 1199/*FWDownload Reply message */ 1200typedef struct _MPI2_FW_DOWNLOAD_REPLY { 1201 U8 ImageType; /*0x00 */ 1202 U8 Reserved1; /*0x01 */ 1203 U8 MsgLength; /*0x02 */ 1204 U8 Function; /*0x03 */ 1205 U16 Reserved2; /*0x04 */ 1206 U8 Reserved3; /*0x06 */ 1207 U8 MsgFlags; /*0x07 */ 1208 U8 VP_ID; /*0x08 */ 1209 U8 VF_ID; /*0x09 */ 1210 U16 Reserved4; /*0x0A */ 1211 U16 Reserved5; /*0x0C */ 1212 U16 IOCStatus; /*0x0E */ 1213 U32 IOCLogInfo; /*0x10 */ 1214} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY, 1215 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t; 1216 1217/**************************************************************************** 1218* FWUpload message 1219****************************************************************************/ 1220 1221/*MPI v2.0 FWUpload Request message */ 1222typedef struct _MPI2_FW_UPLOAD_REQUEST { 1223 U8 ImageType; /*0x00 */ 1224 U8 Reserved1; /*0x01 */ 1225 U8 ChainOffset; /*0x02 */ 1226 U8 Function; /*0x03 */ 1227 U16 Reserved2; /*0x04 */ 1228 U8 Reserved3; /*0x06 */ 1229 U8 MsgFlags; /*0x07 */ 1230 U8 VP_ID; /*0x08 */ 1231 U8 VF_ID; /*0x09 */ 1232 U16 Reserved4; /*0x0A */ 1233 U32 Reserved5; /*0x0C */ 1234 U32 Reserved6; /*0x10 */ 1235 MPI2_MPI_SGE_UNION SGL; /*0x14 */ 1236} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST, 1237 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t; 1238 1239#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1240#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1241#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1242#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1243#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1244#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1245#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1246#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1247#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1248#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1249 1250/*MPI v2.0 FWUpload TransactionContext Element */ 1251typedef struct _MPI2_FW_UPLOAD_TCSGE { 1252 U8 Reserved1; /*0x00 */ 1253 U8 ContextSize; /*0x01 */ 1254 U8 DetailsLength; /*0x02 */ 1255 U8 Flags; /*0x03 */ 1256 U32 Reserved2; /*0x04 */ 1257 U32 ImageOffset; /*0x08 */ 1258 U32 ImageSize; /*0x0C */ 1259} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE, 1260 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t; 1261 1262/*MPI v2.5 FWUpload Request message */ 1263typedef struct _MPI25_FW_UPLOAD_REQUEST { 1264 U8 ImageType; /*0x00 */ 1265 U8 Reserved1; /*0x01 */ 1266 U8 ChainOffset; /*0x02 */ 1267 U8 Function; /*0x03 */ 1268 U16 Reserved2; /*0x04 */ 1269 U8 Reserved3; /*0x06 */ 1270 U8 MsgFlags; /*0x07 */ 1271 U8 VP_ID; /*0x08 */ 1272 U8 VF_ID; /*0x09 */ 1273 U16 Reserved4; /*0x0A */ 1274 U32 Reserved5; /*0x0C */ 1275 U32 Reserved6; /*0x10 */ 1276 U32 Reserved7; /*0x14 */ 1277 U32 ImageOffset; /*0x18 */ 1278 U32 ImageSize; /*0x1C */ 1279 MPI25_SGE_IO_UNION SGL; /*0x20 */ 1280} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST, 1281 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t; 1282 1283/*FWUpload Reply message */ 1284typedef struct _MPI2_FW_UPLOAD_REPLY { 1285 U8 ImageType; /*0x00 */ 1286 U8 Reserved1; /*0x01 */ 1287 U8 MsgLength; /*0x02 */ 1288 U8 Function; /*0x03 */ 1289 U16 Reserved2; /*0x04 */ 1290 U8 Reserved3; /*0x06 */ 1291 U8 MsgFlags; /*0x07 */ 1292 U8 VP_ID; /*0x08 */ 1293 U8 VF_ID; /*0x09 */ 1294 U16 Reserved4; /*0x0A */ 1295 U16 Reserved5; /*0x0C */ 1296 U16 IOCStatus; /*0x0E */ 1297 U32 IOCLogInfo; /*0x10 */ 1298 U32 ActualImageSize; /*0x14 */ 1299} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY, 1300 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t; 1301 1302/*FW Image Header */ 1303typedef struct _MPI2_FW_IMAGE_HEADER { 1304 U32 Signature; /*0x00 */ 1305 U32 Signature0; /*0x04 */ 1306 U32 Signature1; /*0x08 */ 1307 U32 Signature2; /*0x0C */ 1308 MPI2_VERSION_UNION MPIVersion; /*0x10 */ 1309 MPI2_VERSION_UNION FWVersion; /*0x14 */ 1310 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */ 1311 MPI2_VERSION_UNION PackageVersion; /*0x1C */ 1312 U16 VendorID; /*0x20 */ 1313 U16 ProductID; /*0x22 */ 1314 U16 ProtocolFlags; /*0x24 */ 1315 U16 Reserved26; /*0x26 */ 1316 U32 IOCCapabilities; /*0x28 */ 1317 U32 ImageSize; /*0x2C */ 1318 U32 NextImageHeaderOffset; /*0x30 */ 1319 U32 Checksum; /*0x34 */ 1320 U32 Reserved38; /*0x38 */ 1321 U32 Reserved3C; /*0x3C */ 1322 U32 Reserved40; /*0x40 */ 1323 U32 Reserved44; /*0x44 */ 1324 U32 Reserved48; /*0x48 */ 1325 U32 Reserved4C; /*0x4C */ 1326 U32 Reserved50; /*0x50 */ 1327 U32 Reserved54; /*0x54 */ 1328 U32 Reserved58; /*0x58 */ 1329 U32 Reserved5C; /*0x5C */ 1330 U32 Reserved60; /*0x60 */ 1331 U32 FirmwareVersionNameWhat; /*0x64 */ 1332 U8 FirmwareVersionName[32]; /*0x68 */ 1333 U32 VendorNameWhat; /*0x88 */ 1334 U8 VendorName[32]; /*0x8C */ 1335 U32 PackageNameWhat; /*0x88 */ 1336 U8 PackageName[32]; /*0x8C */ 1337 U32 ReservedD0; /*0xD0 */ 1338 U32 ReservedD4; /*0xD4 */ 1339 U32 ReservedD8; /*0xD8 */ 1340 U32 ReservedDC; /*0xDC */ 1341 U32 ReservedE0; /*0xE0 */ 1342 U32 ReservedE4; /*0xE4 */ 1343 U32 ReservedE8; /*0xE8 */ 1344 U32 ReservedEC; /*0xEC */ 1345 U32 ReservedF0; /*0xF0 */ 1346 U32 ReservedF4; /*0xF4 */ 1347 U32 ReservedF8; /*0xF8 */ 1348 U32 ReservedFC; /*0xFC */ 1349} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER, 1350 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t; 1351 1352/*Signature field */ 1353#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1354#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1355#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1356 1357/*Signature0 field */ 1358#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1359#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1360 1361/*Signature1 field */ 1362#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1363#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1364 1365/*Signature2 field */ 1366#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1367#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1368 1369/*defines for using the ProductID field */ 1370#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1371#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1372 1373#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1374#define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1375#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1376#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1377 1378#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1379/*SAS ProductID Family bits */ 1380#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1381#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1382#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1383 1384/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1385 1386/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1387 1388#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1389#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1390#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1391 1392#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1393 1394#define MPI2_FW_HEADER_SIZE (0x100) 1395 1396/*Extended Image Header */ 1397typedef struct _MPI2_EXT_IMAGE_HEADER { 1398 U8 ImageType; /*0x00 */ 1399 U8 Reserved1; /*0x01 */ 1400 U16 Reserved2; /*0x02 */ 1401 U32 Checksum; /*0x04 */ 1402 U32 ImageSize; /*0x08 */ 1403 U32 NextImageHeaderOffset; /*0x0C */ 1404 U32 PackageVersion; /*0x10 */ 1405 U32 Reserved3; /*0x14 */ 1406 U32 Reserved4; /*0x18 */ 1407 U32 Reserved5; /*0x1C */ 1408 U8 IdentifyString[32]; /*0x20 */ 1409} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER, 1410 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t; 1411 1412/*useful offsets */ 1413#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1414#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1415#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1416 1417#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1418 1419/*defines for the ImageType field */ 1420#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1421#define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1422#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1423#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1424#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1425#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1426#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1427#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1428#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) 1429#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1430#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1431 1432#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) 1433 1434/*FLASH Layout Extended Image Data */ 1435 1436/* 1437 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1438 *one and check RegionsPerLayout at runtime. 1439 */ 1440#ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1441#define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1442#endif 1443 1444/* 1445 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1446 *one and check NumberOfLayouts at runtime. 1447 */ 1448#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1449#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1450#endif 1451 1452typedef struct _MPI2_FLASH_REGION { 1453 U8 RegionType; /*0x00 */ 1454 U8 Reserved1; /*0x01 */ 1455 U16 Reserved2; /*0x02 */ 1456 U32 RegionOffset; /*0x04 */ 1457 U32 RegionSize; /*0x08 */ 1458 U32 Reserved3; /*0x0C */ 1459} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION, 1460 Mpi2FlashRegion_t, *pMpi2FlashRegion_t; 1461 1462typedef struct _MPI2_FLASH_LAYOUT { 1463 U32 FlashSize; /*0x00 */ 1464 U32 Reserved1; /*0x04 */ 1465 U32 Reserved2; /*0x08 */ 1466 U32 Reserved3; /*0x0C */ 1467 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */ 1468} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT, 1469 Mpi2FlashLayout_t, *pMpi2FlashLayout_t; 1470 1471typedef struct _MPI2_FLASH_LAYOUT_DATA { 1472 U8 ImageRevision; /*0x00 */ 1473 U8 Reserved1; /*0x01 */ 1474 U8 SizeOfRegion; /*0x02 */ 1475 U8 Reserved2; /*0x03 */ 1476 U16 NumberOfLayouts; /*0x04 */ 1477 U16 RegionsPerLayout; /*0x06 */ 1478 U16 MinimumSectorAlignment; /*0x08 */ 1479 U16 Reserved3; /*0x0A */ 1480 U32 Reserved4; /*0x0C */ 1481 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */ 1482} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA, 1483 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t; 1484 1485/*defines for the RegionType field */ 1486#define MPI2_FLASH_REGION_UNUSED (0x00) 1487#define MPI2_FLASH_REGION_FIRMWARE (0x01) 1488#define MPI2_FLASH_REGION_BIOS (0x02) 1489#define MPI2_FLASH_REGION_NVDATA (0x03) 1490#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1491#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1492#define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1493#define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1494#define MPI2_FLASH_REGION_MEGARAID (0x09) 1495#define MPI2_FLASH_REGION_INIT (0x0A) 1496 1497/*ImageRevision */ 1498#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1499 1500/*Supported Devices Extended Image Data */ 1501 1502/* 1503 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1504 *one and check NumberOfDevices at runtime. 1505 */ 1506#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1507#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1508#endif 1509 1510typedef struct _MPI2_SUPPORTED_DEVICE { 1511 U16 DeviceID; /*0x00 */ 1512 U16 VendorID; /*0x02 */ 1513 U16 DeviceIDMask; /*0x04 */ 1514 U16 Reserved1; /*0x06 */ 1515 U8 LowPCIRev; /*0x08 */ 1516 U8 HighPCIRev; /*0x09 */ 1517 U16 Reserved2; /*0x0A */ 1518 U32 Reserved3; /*0x0C */ 1519} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE, 1520 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t; 1521 1522typedef struct _MPI2_SUPPORTED_DEVICES_DATA { 1523 U8 ImageRevision; /*0x00 */ 1524 U8 Reserved1; /*0x01 */ 1525 U8 NumberOfDevices; /*0x02 */ 1526 U8 Reserved2; /*0x03 */ 1527 U32 Reserved3; /*0x04 */ 1528 MPI2_SUPPORTED_DEVICE 1529 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */ 1530} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA, 1531 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t; 1532 1533/*ImageRevision */ 1534#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1535 1536/*Init Extended Image Data */ 1537 1538typedef struct _MPI2_INIT_IMAGE_FOOTER { 1539 U32 BootFlags; /*0x00 */ 1540 U32 ImageSize; /*0x04 */ 1541 U32 Signature0; /*0x08 */ 1542 U32 Signature1; /*0x0C */ 1543 U32 Signature2; /*0x10 */ 1544 U32 ResetVector; /*0x14 */ 1545} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER, 1546 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t; 1547 1548/*defines for the BootFlags field */ 1549#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1550 1551/*defines for the ImageSize field */ 1552#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1553 1554/*defines for the Signature0 field */ 1555#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1556#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1557 1558/*defines for the Signature1 field */ 1559#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1560#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1561 1562/*defines for the Signature2 field */ 1563#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1564#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1565 1566/*Signature fields as individual bytes */ 1567#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1568#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1569#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1570#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1571 1572#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1573#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1574#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1575#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1576 1577#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1578#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1579#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1580#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1581 1582/*defines for the ResetVector field */ 1583#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1584 1585 1586/* Encrypted Hash Extended Image Data */ 1587 1588typedef struct _MPI25_ENCRYPTED_HASH_ENTRY { 1589 U8 HashImageType; /* 0x00 */ 1590 U8 HashAlgorithm; /* 0x01 */ 1591 U8 EncryptionAlgorithm; /* 0x02 */ 1592 U8 Reserved1; /* 0x03 */ 1593 U32 Reserved2; /* 0x04 */ 1594 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1595} MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1596Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t; 1597 1598/* values for HashImageType */ 1599#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 1600#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 1601 1602/* values for HashAlgorithm */ 1603#define MPI25_HASH_ALGORITHM_UNUSED (0x00) 1604#define MPI25_HASH_ALGORITHM_SHA256 (0x01) 1605 1606/* values for EncryptionAlgorithm */ 1607#define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 1608#define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 1609 1610typedef struct _MPI25_ENCRYPTED_HASH_DATA { 1611 U8 ImageVersion; /* 0x00 */ 1612 U8 NumHash; /* 0x01 */ 1613 U16 Reserved1; /* 0x02 */ 1614 U32 Reserved2; /* 0x04 */ 1615 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ 1616} MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA, 1617Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t; 1618 1619 1620 1621/**************************************************************************** 1622* PowerManagementControl message 1623****************************************************************************/ 1624 1625/*PowerManagementControl Request message */ 1626typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST { 1627 U8 Feature; /*0x00 */ 1628 U8 Reserved1; /*0x01 */ 1629 U8 ChainOffset; /*0x02 */ 1630 U8 Function; /*0x03 */ 1631 U16 Reserved2; /*0x04 */ 1632 U8 Reserved3; /*0x06 */ 1633 U8 MsgFlags; /*0x07 */ 1634 U8 VP_ID; /*0x08 */ 1635 U8 VF_ID; /*0x09 */ 1636 U16 Reserved4; /*0x0A */ 1637 U8 Parameter1; /*0x0C */ 1638 U8 Parameter2; /*0x0D */ 1639 U8 Parameter3; /*0x0E */ 1640 U8 Parameter4; /*0x0F */ 1641 U32 Reserved5; /*0x10 */ 1642 U32 Reserved6; /*0x14 */ 1643} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1644 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t; 1645 1646/*defines for the Feature field */ 1647#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1648#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1649#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */ 1650#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1651#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) 1652#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1653#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1654 1655/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1656/*Parameter1 contains a PHY number */ 1657/*Parameter2 indicates power condition action using these defines */ 1658#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1659#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1660#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1661/*Parameter3 and Parameter4 are reserved */ 1662 1663/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION 1664 * Feature */ 1665/*Parameter1 contains SAS port width modulation group number */ 1666/*Parameter2 indicates IOC action using these defines */ 1667#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1668#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1669#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1670/*Parameter3 indicates desired modulation level using these defines */ 1671#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1672#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1673#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1674#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1675/*Parameter4 is reserved */ 1676 1677/*this next set (_PCIE_LINK) is obsolete */ 1678/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1679/*Parameter1 indicates desired PCIe link speed using these defines */ 1680#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */ 1681#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */ 1682#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */ 1683/*Parameter2 indicates desired PCIe link width using these defines */ 1684#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */ 1685#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */ 1686#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */ 1687#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */ 1688/*Parameter3 and Parameter4 are reserved */ 1689 1690/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1691/*Parameter1 indicates desired IOC hardware clock speed using these defines */ 1692#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1693#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1694#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1695#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1696/*Parameter2, Parameter3, and Parameter4 are reserved */ 1697 1698/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/ 1699/*Parameter1 indicates host action regarding global power management mode */ 1700#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1701#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1702#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1703/*Parameter2 indicates the requested global power management mode */ 1704#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1705#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1706#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1707/*Parameter3 and Parameter4 are reserved */ 1708 1709/*PowerManagementControl Reply message */ 1710typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY { 1711 U8 Feature; /*0x00 */ 1712 U8 Reserved1; /*0x01 */ 1713 U8 MsgLength; /*0x02 */ 1714 U8 Function; /*0x03 */ 1715 U16 Reserved2; /*0x04 */ 1716 U8 Reserved3; /*0x06 */ 1717 U8 MsgFlags; /*0x07 */ 1718 U8 VP_ID; /*0x08 */ 1719 U8 VF_ID; /*0x09 */ 1720 U16 Reserved4; /*0x0A */ 1721 U16 Reserved5; /*0x0C */ 1722 U16 IOCStatus; /*0x0E */ 1723 U32 IOCLogInfo; /*0x10 */ 1724} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1725 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t; 1726 1727#endif 1728