1/* 2 * pmcraid.h -- PMC Sierra MaxRAID controller driver header file 3 * 4 * Written By: Anil Ravindranath<anil_ravindranath@pmc-sierra.com> 5 * PMC-Sierra Inc 6 * 7 * Copyright (C) 2008, 2009 PMC Sierra Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24#ifndef _PMCRAID_H 25#define _PMCRAID_H 26 27#include <linux/types.h> 28#include <linux/completion.h> 29#include <linux/list.h> 30#include <scsi/scsi.h> 31#include <scsi/scsi_cmnd.h> 32#include <linux/cdev.h> 33#include <net/netlink.h> 34#include <net/genetlink.h> 35#include <linux/connector.h> 36/* 37 * Driver name : string representing the driver name 38 * Device file : /dev file to be used for management interfaces 39 * Driver version: version string in major_version.minor_version.patch format 40 * Driver date : date information in "Mon dd yyyy" format 41 */ 42#define PMCRAID_DRIVER_NAME "PMC MaxRAID" 43#define PMCRAID_DEVFILE "pmcsas" 44#define PMCRAID_DRIVER_VERSION "1.0.3" 45 46#define PMCRAID_FW_VERSION_1 0x002 47 48/* Maximum number of adapters supported by current version of the driver */ 49#define PMCRAID_MAX_ADAPTERS 1024 50 51/* Bit definitions as per firmware, bit position [0][1][2].....[31] */ 52#define PMC_BIT8(n) (1 << (7-n)) 53#define PMC_BIT16(n) (1 << (15-n)) 54#define PMC_BIT32(n) (1 << (31-n)) 55 56/* PMC PCI vendor ID and device ID values */ 57#define PCI_VENDOR_ID_PMC 0x11F8 58#define PCI_DEVICE_ID_PMC_MAXRAID 0x5220 59 60/* 61 * MAX_CMD : maximum commands that can be outstanding with IOA 62 * MAX_IO_CMD : command blocks available for IO commands 63 * MAX_HCAM_CMD : command blocks avaibale for HCAMS 64 * MAX_INTERNAL_CMD : command blocks avaible for internal commands like reset 65 */ 66#define PMCRAID_MAX_CMD 1024 67#define PMCRAID_MAX_IO_CMD 1020 68#define PMCRAID_MAX_HCAM_CMD 2 69#define PMCRAID_MAX_INTERNAL_CMD 2 70 71/* MAX_IOADLS : max number of scatter-gather lists supported by IOA 72 * IOADLS_INTERNAL : number of ioadls included as part of IOARCB. 73 * IOADLS_EXTERNAL : number of ioadls allocated external to IOARCB 74 */ 75#define PMCRAID_IOADLS_INTERNAL 27 76#define PMCRAID_IOADLS_EXTERNAL 37 77#define PMCRAID_MAX_IOADLS PMCRAID_IOADLS_INTERNAL 78 79/* HRRQ_ENTRY_SIZE : size of hrrq buffer 80 * IOARCB_ALIGNMENT : alignment required for IOARCB 81 * IOADL_ALIGNMENT : alignment requirement for IOADLs 82 * MSIX_VECTORS : number of MSIX vectors supported 83 */ 84#define HRRQ_ENTRY_SIZE sizeof(__le32) 85#define PMCRAID_IOARCB_ALIGNMENT 32 86#define PMCRAID_IOADL_ALIGNMENT 16 87#define PMCRAID_IOASA_ALIGNMENT 4 88#define PMCRAID_NUM_MSIX_VECTORS 16 89 90/* various other limits */ 91#define PMCRAID_VENDOR_ID_LEN 8 92#define PMCRAID_PRODUCT_ID_LEN 16 93#define PMCRAID_SERIAL_NUM_LEN 8 94#define PMCRAID_LUN_LEN 8 95#define PMCRAID_MAX_CDB_LEN 16 96#define PMCRAID_DEVICE_ID_LEN 8 97#define PMCRAID_SENSE_DATA_LEN 256 98#define PMCRAID_ADD_CMD_PARAM_LEN 48 99 100#define PMCRAID_MAX_BUS_TO_SCAN 1 101#define PMCRAID_MAX_NUM_TARGETS_PER_BUS 256 102#define PMCRAID_MAX_NUM_LUNS_PER_TARGET 8 103 104/* IOA bus/target/lun number of IOA resources */ 105#define PMCRAID_IOA_BUS_ID 0xfe 106#define PMCRAID_IOA_TARGET_ID 0xff 107#define PMCRAID_IOA_LUN_ID 0xff 108#define PMCRAID_VSET_BUS_ID 0x1 109#define PMCRAID_VSET_LUN_ID 0x0 110#define PMCRAID_PHYS_BUS_ID 0x0 111#define PMCRAID_VIRTUAL_ENCL_BUS_ID 0x8 112#define PMCRAID_MAX_VSET_TARGETS 0x7F 113#define PMCRAID_MAX_VSET_LUNS_PER_TARGET 8 114 115#define PMCRAID_IOA_MAX_SECTORS 32767 116#define PMCRAID_VSET_MAX_SECTORS 512 117#define PMCRAID_MAX_CMD_PER_LUN 254 118 119/* Number of configuration table entries (resources), includes 1 FP, 120 * 1 Enclosure device 121 */ 122#define PMCRAID_MAX_RESOURCES 256 123 124/* Adapter Commands used by driver */ 125#define PMCRAID_QUERY_RESOURCE_STATE 0xC2 126#define PMCRAID_RESET_DEVICE 0xC3 127/* options to select reset target */ 128#define ENABLE_RESET_MODIFIER 0x80 129#define RESET_DEVICE_LUN 0x40 130#define RESET_DEVICE_TARGET 0x20 131#define RESET_DEVICE_BUS 0x10 132 133#define PMCRAID_IDENTIFY_HRRQ 0xC4 134#define PMCRAID_QUERY_IOA_CONFIG 0xC5 135#define PMCRAID_QUERY_CMD_STATUS 0xCB 136#define PMCRAID_ABORT_CMD 0xC7 137 138/* CANCEL ALL command, provides option for setting SYNC_COMPLETE 139 * on the target resources for which commands got cancelled 140 */ 141#define PMCRAID_CANCEL_ALL_REQUESTS 0xCE 142#define PMCRAID_SYNC_COMPLETE_AFTER_CANCEL PMC_BIT8(0) 143 144/* HCAM command and types of HCAM supported by IOA */ 145#define PMCRAID_HOST_CONTROLLED_ASYNC 0xCF 146#define PMCRAID_HCAM_CODE_CONFIG_CHANGE 0x01 147#define PMCRAID_HCAM_CODE_LOG_DATA 0x02 148 149/* IOA shutdown command and various shutdown types */ 150#define PMCRAID_IOA_SHUTDOWN 0xF7 151#define PMCRAID_SHUTDOWN_NORMAL 0x00 152#define PMCRAID_SHUTDOWN_PREPARE_FOR_NORMAL 0x40 153#define PMCRAID_SHUTDOWN_NONE 0x100 154#define PMCRAID_SHUTDOWN_ABBREV 0x80 155 156/* SET SUPPORTED DEVICES command and the option to select all the 157 * devices to be supported 158 */ 159#define PMCRAID_SET_SUPPORTED_DEVICES 0xFB 160#define ALL_DEVICES_SUPPORTED PMC_BIT8(0) 161 162/* This option is used with SCSI WRITE_BUFFER command */ 163#define PMCRAID_WR_BUF_DOWNLOAD_AND_SAVE 0x05 164 165/* IOASC Codes used by driver */ 166#define PMCRAID_IOASC_SENSE_MASK 0xFFFFFF00 167#define PMCRAID_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 168#define PMCRAID_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 169#define PMCRAID_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 170#define PMCRAID_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 171 172#define PMCRAID_IOASC_GOOD_COMPLETION 0x00000000 173#define PMCRAID_IOASC_GC_IOARCB_NOTFOUND 0x005A0000 174#define PMCRAID_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 175#define PMCRAID_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 176#define PMCRAID_IOASC_NR_SYNC_REQUIRED 0x023F0000 177#define PMCRAID_IOASC_ME_READ_ERROR_NO_REALLOC 0x03110C00 178#define PMCRAID_IOASC_HW_CANNOT_COMMUNICATE 0x04050000 179#define PMCRAID_IOASC_HW_DEVICE_TIMEOUT 0x04080100 180#define PMCRAID_IOASC_HW_DEVICE_BUS_STATUS_ERROR 0x04448500 181#define PMCRAID_IOASC_HW_IOA_RESET_REQUIRED 0x04448600 182#define PMCRAID_IOASC_IR_INVALID_RESOURCE_HANDLE 0x05250000 183#define PMCRAID_IOASC_AC_TERMINATED_BY_HOST 0x0B5A0000 184#define PMCRAID_IOASC_UA_BUS_WAS_RESET 0x06290000 185#define PMCRAID_IOASC_TIME_STAMP_OUT_OF_SYNC 0x06908B00 186#define PMCRAID_IOASC_UA_BUS_WAS_RESET_BY_OTHER 0x06298000 187 188/* Driver defined IOASCs */ 189#define PMCRAID_IOASC_IOA_WAS_RESET 0x10000001 190#define PMCRAID_IOASC_PCI_ACCESS_ERROR 0x10000002 191 192/* Various timeout values (in milliseconds) used. If any of these are chip 193 * specific, move them to pmcraid_chip_details structure. 194 */ 195#define PMCRAID_PCI_DEASSERT_TIMEOUT 2000 196#define PMCRAID_BIST_TIMEOUT 2000 197#define PMCRAID_AENWAIT_TIMEOUT 5000 198#define PMCRAID_TRANSOP_TIMEOUT 60000 199 200#define PMCRAID_RESET_TIMEOUT (2 * HZ) 201#define PMCRAID_CHECK_FOR_RESET_TIMEOUT ((HZ / 10)) 202#define PMCRAID_VSET_IO_TIMEOUT (60 * HZ) 203#define PMCRAID_INTERNAL_TIMEOUT (60 * HZ) 204#define PMCRAID_SHUTDOWN_TIMEOUT (150 * HZ) 205#define PMCRAID_RESET_BUS_TIMEOUT (60 * HZ) 206#define PMCRAID_RESET_HOST_TIMEOUT (150 * HZ) 207#define PMCRAID_REQUEST_SENSE_TIMEOUT (30 * HZ) 208#define PMCRAID_SET_SUP_DEV_TIMEOUT (2 * 60 * HZ) 209 210/* structure to represent a scatter-gather element (IOADL descriptor) */ 211struct pmcraid_ioadl_desc { 212 __le64 address; 213 __le32 data_len; 214 __u8 reserved[3]; 215 __u8 flags; 216} __attribute__((packed, aligned(PMCRAID_IOADL_ALIGNMENT))); 217 218/* pmcraid_ioadl_desc.flags values */ 219#define IOADL_FLAGS_CHAINED PMC_BIT8(0) 220#define IOADL_FLAGS_LAST_DESC PMC_BIT8(1) 221#define IOADL_FLAGS_READ_LAST PMC_BIT8(1) 222#define IOADL_FLAGS_WRITE_LAST PMC_BIT8(1) 223 224 225/* additional IOARCB data which can be CDB or additional request parameters 226 * or list of IOADLs. Firmware supports max of 512 bytes for IOARCB, hence then 227 * number of IOADLs are limted to 27. In case they are more than 27, they will 228 * be used in chained form 229 */ 230struct pmcraid_ioarcb_add_data { 231 union { 232 struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_INTERNAL]; 233 __u8 add_cmd_params[PMCRAID_ADD_CMD_PARAM_LEN]; 234 } u; 235}; 236 237/* 238 * IOA Request Control Block 239 */ 240struct pmcraid_ioarcb { 241 __le64 ioarcb_bus_addr; 242 __le32 resource_handle; 243 __le32 response_handle; 244 __le64 ioadl_bus_addr; 245 __le32 ioadl_length; 246 __le32 data_transfer_length; 247 __le64 ioasa_bus_addr; 248 __le16 ioasa_len; 249 __le16 cmd_timeout; 250 __le16 add_cmd_param_offset; 251 __le16 add_cmd_param_length; 252 __le32 reserved1[2]; 253 __le32 reserved2; 254 __u8 request_type; 255 __u8 request_flags0; 256 __u8 request_flags1; 257 __u8 hrrq_id; 258 __u8 cdb[PMCRAID_MAX_CDB_LEN]; 259 struct pmcraid_ioarcb_add_data add_data; 260} __attribute__((packed, aligned(PMCRAID_IOARCB_ALIGNMENT))); 261 262/* well known resource handle values */ 263#define PMCRAID_IOA_RES_HANDLE 0xffffffff 264#define PMCRAID_INVALID_RES_HANDLE 0 265 266/* pmcraid_ioarcb.request_type values */ 267#define REQ_TYPE_SCSI 0x00 268#define REQ_TYPE_IOACMD 0x01 269#define REQ_TYPE_HCAM 0x02 270 271/* pmcraid_ioarcb.flags0 values */ 272#define TRANSFER_DIR_WRITE PMC_BIT8(0) 273#define INHIBIT_UL_CHECK PMC_BIT8(2) 274#define SYNC_OVERRIDE PMC_BIT8(3) 275#define SYNC_COMPLETE PMC_BIT8(4) 276#define NO_LINK_DESCS PMC_BIT8(5) 277 278/* pmcraid_ioarcb.flags1 values */ 279#define DELAY_AFTER_RESET PMC_BIT8(0) 280#define TASK_TAG_SIMPLE 0x10 281#define TASK_TAG_ORDERED 0x20 282#define TASK_TAG_QUEUE_HEAD 0x30 283 284/* toggle bit offset in response handle */ 285#define HRRQ_TOGGLE_BIT 0x01 286#define HRRQ_RESPONSE_BIT 0x02 287 288/* IOA Status Area */ 289struct pmcraid_ioasa_vset { 290 __le32 failing_lba_hi; 291 __le32 failing_lba_lo; 292 __le32 reserved; 293} __attribute__((packed, aligned(4))); 294 295struct pmcraid_ioasa { 296 __le32 ioasc; 297 __le16 returned_status_length; 298 __le16 available_status_length; 299 __le32 residual_data_length; 300 __le32 ilid; 301 __le32 fd_ioasc; 302 __le32 fd_res_address; 303 __le32 fd_res_handle; 304 __le32 reserved; 305 306 /* resource specific sense information */ 307 union { 308 struct pmcraid_ioasa_vset vset; 309 } u; 310 311 /* IOA autosense data */ 312 __le16 auto_sense_length; 313 __le16 error_data_length; 314 __u8 sense_data[PMCRAID_SENSE_DATA_LEN]; 315} __attribute__((packed, aligned(4))); 316 317#define PMCRAID_DRIVER_ILID 0xffffffff 318 319/* Config Table Entry per Resource */ 320struct pmcraid_config_table_entry { 321 __u8 resource_type; 322 __u8 bus_protocol; 323 __le16 array_id; 324 __u8 common_flags0; 325 __u8 common_flags1; 326 __u8 unique_flags0; 327 __u8 unique_flags1; /*also used as vset target_id */ 328 __le32 resource_handle; 329 __le32 resource_address; 330 __u8 device_id[PMCRAID_DEVICE_ID_LEN]; 331 __u8 lun[PMCRAID_LUN_LEN]; 332} __attribute__((packed, aligned(4))); 333 334/* extended configuration table sizes are also of 32 bytes in size */ 335struct pmcraid_config_table_entry_ext { 336 struct pmcraid_config_table_entry cfgte; 337}; 338 339/* resource types (config_table_entry.resource_type values) */ 340#define RES_TYPE_AF_DASD 0x00 341#define RES_TYPE_GSCSI 0x01 342#define RES_TYPE_VSET 0x02 343#define RES_TYPE_IOA_FP 0xFF 344 345#define RES_IS_IOA(res) ((res).resource_type == RES_TYPE_IOA_FP) 346#define RES_IS_GSCSI(res) ((res).resource_type == RES_TYPE_GSCSI) 347#define RES_IS_VSET(res) ((res).resource_type == RES_TYPE_VSET) 348#define RES_IS_AFDASD(res) ((res).resource_type == RES_TYPE_AF_DASD) 349 350/* bus_protocol values used by driver */ 351#define RES_TYPE_VENCLOSURE 0x8 352 353/* config_table_entry.common_flags0 */ 354#define MULTIPATH_RESOURCE PMC_BIT32(0) 355 356/* unique_flags1 */ 357#define IMPORT_MODE_MANUAL PMC_BIT8(0) 358 359/* well known resource handle values */ 360#define RES_HANDLE_IOA 0xFFFFFFFF 361#define RES_HANDLE_NONE 0x00000000 362 363/* well known resource address values */ 364#define RES_ADDRESS_IOAFP 0xFEFFFFFF 365#define RES_ADDRESS_INVALID 0xFFFFFFFF 366 367/* BUS/TARGET/LUN values from resource_addrr */ 368#define RES_BUS(res_addr) (le32_to_cpu(res_addr) & 0xFF) 369#define RES_TARGET(res_addr) ((le32_to_cpu(res_addr) >> 16) & 0xFF) 370#define RES_LUN(res_addr) 0x0 371 372/* configuration table structure */ 373struct pmcraid_config_table { 374 __le16 num_entries; 375 __u8 table_format; 376 __u8 reserved1; 377 __u8 flags; 378 __u8 reserved2[11]; 379 union { 380 struct pmcraid_config_table_entry 381 entries[PMCRAID_MAX_RESOURCES]; 382 struct pmcraid_config_table_entry_ext 383 entries_ext[PMCRAID_MAX_RESOURCES]; 384 }; 385} __attribute__((packed, aligned(4))); 386 387/* config_table.flags value */ 388#define MICROCODE_UPDATE_REQUIRED PMC_BIT32(0) 389 390/* 391 * HCAM format 392 */ 393#define PMCRAID_HOSTRCB_LDNSIZE 4056 394 395/* Error log notification format */ 396struct pmcraid_hostrcb_error { 397 __le32 fd_ioasc; 398 __le32 fd_ra; 399 __le32 fd_rh; 400 __le32 prc; 401 union { 402 __u8 data[PMCRAID_HOSTRCB_LDNSIZE]; 403 } u; 404} __attribute__ ((packed, aligned(4))); 405 406struct pmcraid_hcam_hdr { 407 __u8 op_code; 408 __u8 notification_type; 409 __u8 notification_lost; 410 __u8 flags; 411 __u8 overlay_id; 412 __u8 reserved1[3]; 413 __le32 ilid; 414 __le32 timestamp1; 415 __le32 timestamp2; 416 __le32 data_len; 417} __attribute__((packed, aligned(4))); 418 419#define PMCRAID_AEN_GROUP 0x3 420 421struct pmcraid_hcam_ccn { 422 struct pmcraid_hcam_hdr header; 423 struct pmcraid_config_table_entry cfg_entry; 424 struct pmcraid_config_table_entry cfg_entry_old; 425} __attribute__((packed, aligned(4))); 426 427#define PMCRAID_CCN_EXT_SIZE 3944 428struct pmcraid_hcam_ccn_ext { 429 struct pmcraid_hcam_hdr header; 430 struct pmcraid_config_table_entry_ext cfg_entry; 431 struct pmcraid_config_table_entry_ext cfg_entry_old; 432 __u8 reserved[PMCRAID_CCN_EXT_SIZE]; 433} __attribute__((packed, aligned(4))); 434 435struct pmcraid_hcam_ldn { 436 struct pmcraid_hcam_hdr header; 437 struct pmcraid_hostrcb_error error_log; 438} __attribute__((packed, aligned(4))); 439 440/* pmcraid_hcam.op_code values */ 441#define HOSTRCB_TYPE_CCN 0xE1 442#define HOSTRCB_TYPE_LDN 0xE2 443 444/* pmcraid_hcam.notification_type values */ 445#define NOTIFICATION_TYPE_ENTRY_CHANGED 0x0 446#define NOTIFICATION_TYPE_ENTRY_NEW 0x1 447#define NOTIFICATION_TYPE_ENTRY_DELETED 0x2 448#define NOTIFICATION_TYPE_STATE_CHANGE 0x3 449#define NOTIFICATION_TYPE_ENTRY_STATECHANGED 0x4 450#define NOTIFICATION_TYPE_ERROR_LOG 0x10 451#define NOTIFICATION_TYPE_INFORMATION_LOG 0x11 452 453#define HOSTRCB_NOTIFICATIONS_LOST PMC_BIT8(0) 454 455/* pmcraid_hcam.flags values */ 456#define HOSTRCB_INTERNAL_OP_ERROR PMC_BIT8(0) 457#define HOSTRCB_ERROR_RESPONSE_SENT PMC_BIT8(1) 458 459/* pmcraid_hcam.overlay_id values */ 460#define HOSTRCB_OVERLAY_ID_08 0x08 461#define HOSTRCB_OVERLAY_ID_09 0x09 462#define HOSTRCB_OVERLAY_ID_11 0x11 463#define HOSTRCB_OVERLAY_ID_12 0x12 464#define HOSTRCB_OVERLAY_ID_13 0x13 465#define HOSTRCB_OVERLAY_ID_14 0x14 466#define HOSTRCB_OVERLAY_ID_16 0x16 467#define HOSTRCB_OVERLAY_ID_17 0x17 468#define HOSTRCB_OVERLAY_ID_20 0x20 469#define HOSTRCB_OVERLAY_ID_FF 0xFF 470 471/* Implementation specific card details */ 472struct pmcraid_chip_details { 473 /* hardware register offsets */ 474 unsigned long ioastatus; 475 unsigned long ioarrin; 476 unsigned long mailbox; 477 unsigned long global_intr_mask; 478 unsigned long ioa_host_intr; 479 unsigned long ioa_host_msix_intr; 480 unsigned long ioa_host_intr_clr; 481 unsigned long ioa_host_mask; 482 unsigned long ioa_host_mask_clr; 483 unsigned long host_ioa_intr; 484 unsigned long host_ioa_intr_clr; 485 486 /* timeout used during transitional to operational state */ 487 unsigned long transop_timeout; 488}; 489 490/* IOA to HOST doorbells (interrupts) */ 491#define INTRS_TRANSITION_TO_OPERATIONAL PMC_BIT32(0) 492#define INTRS_IOARCB_TRANSFER_FAILED PMC_BIT32(3) 493#define INTRS_IOA_UNIT_CHECK PMC_BIT32(4) 494#define INTRS_NO_HRRQ_FOR_CMD_RESPONSE PMC_BIT32(5) 495#define INTRS_CRITICAL_OP_IN_PROGRESS PMC_BIT32(6) 496#define INTRS_IO_DEBUG_ACK PMC_BIT32(7) 497#define INTRS_IOARRIN_LOST PMC_BIT32(27) 498#define INTRS_SYSTEM_BUS_MMIO_ERROR PMC_BIT32(28) 499#define INTRS_IOA_PROCESSOR_ERROR PMC_BIT32(29) 500#define INTRS_HRRQ_VALID PMC_BIT32(30) 501#define INTRS_OPERATIONAL_STATUS PMC_BIT32(0) 502#define INTRS_ALLOW_MSIX_VECTOR0 PMC_BIT32(31) 503 504/* Host to IOA Doorbells */ 505#define DOORBELL_RUNTIME_RESET PMC_BIT32(1) 506#define DOORBELL_IOA_RESET_ALERT PMC_BIT32(7) 507#define DOORBELL_IOA_DEBUG_ALERT PMC_BIT32(9) 508#define DOORBELL_ENABLE_DESTRUCTIVE_DIAGS PMC_BIT32(8) 509#define DOORBELL_IOA_START_BIST PMC_BIT32(23) 510#define DOORBELL_INTR_MODE_MSIX PMC_BIT32(25) 511#define DOORBELL_INTR_MSIX_CLR PMC_BIT32(26) 512#define DOORBELL_RESET_IOA PMC_BIT32(31) 513 514/* Global interrupt mask register value */ 515#define GLOBAL_INTERRUPT_MASK 0x5ULL 516 517#define PMCRAID_ERROR_INTERRUPTS (INTRS_IOARCB_TRANSFER_FAILED | \ 518 INTRS_IOA_UNIT_CHECK | \ 519 INTRS_NO_HRRQ_FOR_CMD_RESPONSE | \ 520 INTRS_IOARRIN_LOST | \ 521 INTRS_SYSTEM_BUS_MMIO_ERROR | \ 522 INTRS_IOA_PROCESSOR_ERROR) 523 524#define PMCRAID_PCI_INTERRUPTS (PMCRAID_ERROR_INTERRUPTS | \ 525 INTRS_HRRQ_VALID | \ 526 INTRS_TRANSITION_TO_OPERATIONAL |\ 527 INTRS_ALLOW_MSIX_VECTOR0) 528 529/* control_block, associated with each of the commands contains IOARCB, IOADLs 530 * memory for IOASA. Additional 3 * 16 bytes are allocated in order to support 531 * additional request parameters (of max size 48) any command. 532 */ 533struct pmcraid_control_block { 534 struct pmcraid_ioarcb ioarcb; 535 struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_EXTERNAL + 3]; 536 struct pmcraid_ioasa ioasa; 537} __attribute__ ((packed, aligned(PMCRAID_IOARCB_ALIGNMENT))); 538 539/* pmcraid_sglist - Scatter-gather list allocated for passthrough ioctls 540 */ 541struct pmcraid_sglist { 542 u32 order; 543 u32 num_sg; 544 u32 num_dma_sg; 545 u32 buffer_len; 546 struct scatterlist scatterlist[1]; 547}; 548 549/* page D0 inquiry data of focal point resource */ 550struct pmcraid_inquiry_data { 551 __u8 ph_dev_type; 552 __u8 page_code; 553 __u8 reserved1; 554 __u8 add_page_len; 555 __u8 length; 556 __u8 reserved2; 557 __le16 fw_version; 558 __u8 reserved3[16]; 559}; 560 561#define PMCRAID_TIMESTAMP_LEN 12 562#define PMCRAID_REQ_TM_STR_LEN 6 563#define PMCRAID_SCSI_SET_TIMESTAMP 0xA4 564#define PMCRAID_SCSI_SERVICE_ACTION 0x0F 565 566struct pmcraid_timestamp_data { 567 __u8 reserved1[4]; 568 __u8 timestamp[PMCRAID_REQ_TM_STR_LEN]; /* current time value */ 569 __u8 reserved2[2]; 570}; 571 572/* pmcraid_cmd - LLD representation of SCSI command */ 573struct pmcraid_cmd { 574 575 /* Ptr and bus address of DMA.able control block for this command */ 576 struct pmcraid_control_block *ioa_cb; 577 dma_addr_t ioa_cb_bus_addr; 578 dma_addr_t dma_handle; 579 580 /* pointer to mid layer structure of SCSI commands */ 581 struct scsi_cmnd *scsi_cmd; 582 583 struct list_head free_list; 584 struct completion wait_for_completion; 585 struct timer_list timer; /* needed for internal commands */ 586 u32 timeout; /* current timeout value */ 587 u32 index; /* index into the command list */ 588 u8 completion_req; /* for handling internal commands */ 589 u8 release; /* for handling completions */ 590 591 void (*cmd_done) (struct pmcraid_cmd *); 592 struct pmcraid_instance *drv_inst; 593 594 struct pmcraid_sglist *sglist; /* used for passthrough IOCTLs */ 595 596 /* scratch used */ 597 union { 598 /* during reset sequence */ 599 unsigned long time_left; 600 struct pmcraid_resource_entry *res; 601 int hrrq_index; 602 603 /* used during IO command error handling. Sense buffer 604 * for REQUEST SENSE command if firmware is not sending 605 * auto sense data 606 */ 607 struct { 608 u8 *sense_buffer; 609 dma_addr_t sense_buffer_dma; 610 }; 611 }; 612}; 613 614/* 615 * Interrupt registers of IOA 616 */ 617struct pmcraid_interrupts { 618 void __iomem *ioa_host_interrupt_reg; 619 void __iomem *ioa_host_msix_interrupt_reg; 620 void __iomem *ioa_host_interrupt_clr_reg; 621 void __iomem *ioa_host_interrupt_mask_reg; 622 void __iomem *ioa_host_interrupt_mask_clr_reg; 623 void __iomem *global_interrupt_mask_reg; 624 void __iomem *host_ioa_interrupt_reg; 625 void __iomem *host_ioa_interrupt_clr_reg; 626}; 627 628/* ISR parameters LLD allocates (one for each MSI-X if enabled) vectors */ 629struct pmcraid_isr_param { 630 struct pmcraid_instance *drv_inst; 631 u16 vector; /* allocated msi-x vector */ 632 u8 hrrq_id; /* hrrq entry index */ 633}; 634 635 636/* AEN message header sent as part of event data to applications */ 637struct pmcraid_aen_msg { 638 u32 hostno; 639 u32 length; 640 u8 reserved[8]; 641 u8 data[0]; 642}; 643 644/* Controller state event message type */ 645struct pmcraid_state_msg { 646 struct pmcraid_aen_msg msg; 647 u32 ioa_state; 648}; 649 650#define PMC_DEVICE_EVENT_RESET_START 0x11000000 651#define PMC_DEVICE_EVENT_RESET_SUCCESS 0x11000001 652#define PMC_DEVICE_EVENT_RESET_FAILED 0x11000002 653#define PMC_DEVICE_EVENT_SHUTDOWN_START 0x11000003 654#define PMC_DEVICE_EVENT_SHUTDOWN_SUCCESS 0x11000004 655#define PMC_DEVICE_EVENT_SHUTDOWN_FAILED 0x11000005 656 657struct pmcraid_hostrcb { 658 struct pmcraid_instance *drv_inst; 659 struct pmcraid_aen_msg *msg; 660 struct pmcraid_hcam_hdr *hcam; /* pointer to hcam buffer */ 661 struct pmcraid_cmd *cmd; /* pointer to command block used */ 662 dma_addr_t baddr; /* system address of hcam buffer */ 663 atomic_t ignore; /* process HCAM response ? */ 664}; 665 666#define PMCRAID_AEN_HDR_SIZE sizeof(struct pmcraid_aen_msg) 667 668 669 670/* 671 * Per adapter structure maintained by LLD 672 */ 673struct pmcraid_instance { 674 /* Array of allowed-to-be-exposed resources, initialized from 675 * Configutation Table, later updated with CCNs 676 */ 677 struct pmcraid_resource_entry *res_entries; 678 679 struct list_head free_res_q; /* res_entries lists for easy lookup */ 680 struct list_head used_res_q; /* List of to be exposed resources */ 681 spinlock_t resource_lock; /* spinlock to protect resource list */ 682 683 void __iomem *mapped_dma_addr; 684 void __iomem *ioa_status; /* Iomapped IOA status register */ 685 void __iomem *mailbox; /* Iomapped mailbox register */ 686 void __iomem *ioarrin; /* IOmapped IOARR IN register */ 687 688 struct pmcraid_interrupts int_regs; 689 struct pmcraid_chip_details *chip_cfg; 690 691 /* HostRCBs needed for HCAM */ 692 struct pmcraid_hostrcb ldn; 693 struct pmcraid_hostrcb ccn; 694 struct pmcraid_state_msg scn; /* controller state change msg */ 695 696 697 /* Bus address of start of HRRQ */ 698 dma_addr_t hrrq_start_bus_addr[PMCRAID_NUM_MSIX_VECTORS]; 699 700 /* Pointer to 1st entry of HRRQ */ 701 __be32 *hrrq_start[PMCRAID_NUM_MSIX_VECTORS]; 702 703 /* Pointer to last entry of HRRQ */ 704 __be32 *hrrq_end[PMCRAID_NUM_MSIX_VECTORS]; 705 706 /* Pointer to current pointer of hrrq */ 707 __be32 *hrrq_curr[PMCRAID_NUM_MSIX_VECTORS]; 708 709 /* Lock for HRRQ access */ 710 spinlock_t hrrq_lock[PMCRAID_NUM_MSIX_VECTORS]; 711 712 struct pmcraid_inquiry_data *inq_data; 713 dma_addr_t inq_data_baddr; 714 715 struct pmcraid_timestamp_data *timestamp_data; 716 dma_addr_t timestamp_data_baddr; 717 718 /* size of configuration table entry, varies based on the firmware */ 719 u32 config_table_entry_size; 720 721 /* Expected toggle bit at host */ 722 u8 host_toggle_bit[PMCRAID_NUM_MSIX_VECTORS]; 723 724 725 /* Wait Q for threads to wait for Reset IOA completion */ 726 wait_queue_head_t reset_wait_q; 727 struct pmcraid_cmd *reset_cmd; 728 729 /* structures for supporting SIGIO based AEN. */ 730 struct fasync_struct *aen_queue; 731 struct mutex aen_queue_lock; /* lock for aen subscribers list */ 732 struct cdev cdev; 733 734 struct Scsi_Host *host; /* mid layer interface structure handle */ 735 struct pci_dev *pdev; /* PCI device structure handle */ 736 737 /* No of Reset IOA retries . IOA marked dead if threshold exceeds */ 738 u8 ioa_reset_attempts; 739#define PMCRAID_RESET_ATTEMPTS 3 740 741 u8 current_log_level; /* default level for logging IOASC errors */ 742 743 u8 num_hrrq; /* Number of interrupt vectors allocated */ 744 u8 interrupt_mode; /* current interrupt mode legacy or msix */ 745 dev_t dev; /* Major-Minor numbers for Char device */ 746 747 /* Used as ISR handler argument */ 748 struct pmcraid_isr_param hrrq_vector[PMCRAID_NUM_MSIX_VECTORS]; 749 750 /* Message id as filled in last fired IOARCB, used to identify HRRQ */ 751 atomic_t last_message_id; 752 753 /* configuration table */ 754 struct pmcraid_config_table *cfg_table; 755 dma_addr_t cfg_table_bus_addr; 756 757 /* structures related to command blocks */ 758 struct kmem_cache *cmd_cachep; /* cache for cmd blocks */ 759 struct pci_pool *control_pool; /* pool for control blocks */ 760 char cmd_pool_name[64]; /* name of cmd cache */ 761 char ctl_pool_name[64]; /* name of control cache */ 762 763 struct pmcraid_cmd *cmd_list[PMCRAID_MAX_CMD]; 764 765 struct list_head free_cmd_pool; 766 struct list_head pending_cmd_pool; 767 spinlock_t free_pool_lock; /* free pool lock */ 768 spinlock_t pending_pool_lock; /* pending pool lock */ 769 770 /* Tasklet to handle deferred processing */ 771 struct tasklet_struct isr_tasklet[PMCRAID_NUM_MSIX_VECTORS]; 772 773 /* Work-queue (Shared) for deferred reset processing */ 774 struct work_struct worker_q; 775 776 /* No of IO commands pending with FW */ 777 atomic_t outstanding_cmds; 778 779 /* should add/delete resources to mid-layer now ?*/ 780 atomic_t expose_resources; 781 782 783 784 u32 ioa_state:4; /* For IOA Reset sequence FSM */ 785#define IOA_STATE_OPERATIONAL 0x0 786#define IOA_STATE_UNKNOWN 0x1 787#define IOA_STATE_DEAD 0x2 788#define IOA_STATE_IN_SOFT_RESET 0x3 789#define IOA_STATE_IN_HARD_RESET 0x4 790#define IOA_STATE_IN_RESET_ALERT 0x5 791#define IOA_STATE_IN_BRINGDOWN 0x6 792#define IOA_STATE_IN_BRINGUP 0x7 793 794 u32 ioa_reset_in_progress:1; /* true if IOA reset is in progress */ 795 u32 ioa_hard_reset:1; /* TRUE if Hard Reset is needed */ 796 u32 ioa_unit_check:1; /* Indicates Unit Check condition */ 797 u32 ioa_bringdown:1; /* whether IOA needs to be brought down */ 798 u32 force_ioa_reset:1; /* force adapter reset ? */ 799 u32 reinit_cfg_table:1; /* reinit config table due to lost CCN */ 800 u32 ioa_shutdown_type:2;/* shutdown type used during reset */ 801#define SHUTDOWN_NONE 0x0 802#define SHUTDOWN_NORMAL 0x1 803#define SHUTDOWN_ABBREV 0x2 804 u32 timestamp_error:1; /* indicate set timestamp for out of sync */ 805 806}; 807 808/* LLD maintained resource entry structure */ 809struct pmcraid_resource_entry { 810 struct list_head queue; /* link to "to be exposed" resources */ 811 union { 812 struct pmcraid_config_table_entry cfg_entry; 813 struct pmcraid_config_table_entry_ext cfg_entry_ext; 814 }; 815 struct scsi_device *scsi_dev; /* Link scsi_device structure */ 816 atomic_t read_failures; /* count of failed READ commands */ 817 atomic_t write_failures; /* count of failed WRITE commands */ 818 819 /* To indicate add/delete/modify during CCN */ 820 u8 change_detected; 821#define RES_CHANGE_ADD 0x1 /* add this to mid-layer */ 822#define RES_CHANGE_DEL 0x2 /* remove this from mid-layer */ 823 824 u8 reset_progress; /* Device is resetting */ 825 826 /* 827 * When IOA asks for sync (i.e. IOASC = Not Ready, Sync Required), this 828 * flag will be set, mid layer will be asked to retry. In the next 829 * attempt, this flag will be checked in queuecommand() to set 830 * SYNC_COMPLETE flag in IOARCB (flag_0). 831 */ 832 u8 sync_reqd; 833 834 /* target indicates the mapped target_id assigned to this resource if 835 * this is VSET resource. For non-VSET resources this will be un-used 836 * or zero 837 */ 838 u8 target; 839}; 840 841/* Data structures used in IOASC error code logging */ 842struct pmcraid_ioasc_error { 843 u32 ioasc_code; /* IOASC code */ 844 u8 log_level; /* default log level assignment. */ 845 char *error_string; 846}; 847 848/* Initial log_level assignments for various IOASCs */ 849#define IOASC_LOG_LEVEL_NONE 0x0 /* no logging */ 850#define IOASC_LOG_LEVEL_MUST 0x1 /* must log: all high-severity errors */ 851#define IOASC_LOG_LEVEL_HARD 0x2 /* optional – low severity errors */ 852 853/* Error information maintained by LLD. LLD initializes the pmcraid_error_table 854 * statically. 855 */ 856static struct pmcraid_ioasc_error pmcraid_ioasc_error_table[] = { 857 {0x01180600, IOASC_LOG_LEVEL_HARD, 858 "Recovered Error, soft media error, sector reassignment suggested"}, 859 {0x015D0000, IOASC_LOG_LEVEL_HARD, 860 "Recovered Error, failure prediction threshold exceeded"}, 861 {0x015D9200, IOASC_LOG_LEVEL_HARD, 862 "Recovered Error, soft Cache Card Battery error threshold"}, 863 {0x015D9200, IOASC_LOG_LEVEL_HARD, 864 "Recovered Error, soft Cache Card Battery error threshold"}, 865 {0x02048000, IOASC_LOG_LEVEL_HARD, 866 "Not Ready, IOA Reset Required"}, 867 {0x02408500, IOASC_LOG_LEVEL_HARD, 868 "Not Ready, IOA microcode download required"}, 869 {0x03110B00, IOASC_LOG_LEVEL_HARD, 870 "Medium Error, data unreadable, reassignment suggested"}, 871 {0x03110C00, IOASC_LOG_LEVEL_MUST, 872 "Medium Error, data unreadable do not reassign"}, 873 {0x03310000, IOASC_LOG_LEVEL_HARD, 874 "Medium Error, media corrupted"}, 875 {0x04050000, IOASC_LOG_LEVEL_HARD, 876 "Hardware Error, IOA can't communicate with device"}, 877 {0x04080000, IOASC_LOG_LEVEL_MUST, 878 "Hardware Error, device bus error"}, 879 {0x04088000, IOASC_LOG_LEVEL_MUST, 880 "Hardware Error, device bus is not functioning"}, 881 {0x04118000, IOASC_LOG_LEVEL_HARD, 882 "Hardware Error, IOA reserved area data check"}, 883 {0x04118100, IOASC_LOG_LEVEL_HARD, 884 "Hardware Error, IOA reserved area invalid data pattern"}, 885 {0x04118200, IOASC_LOG_LEVEL_HARD, 886 "Hardware Error, IOA reserved area LRC error"}, 887 {0x04320000, IOASC_LOG_LEVEL_HARD, 888 "Hardware Error, reassignment space exhausted"}, 889 {0x04330000, IOASC_LOG_LEVEL_HARD, 890 "Hardware Error, data transfer underlength error"}, 891 {0x04330000, IOASC_LOG_LEVEL_HARD, 892 "Hardware Error, data transfer overlength error"}, 893 {0x04418000, IOASC_LOG_LEVEL_MUST, 894 "Hardware Error, PCI bus error"}, 895 {0x04440000, IOASC_LOG_LEVEL_HARD, 896 "Hardware Error, device error"}, 897 {0x04448200, IOASC_LOG_LEVEL_MUST, 898 "Hardware Error, IOA error"}, 899 {0x04448300, IOASC_LOG_LEVEL_HARD, 900 "Hardware Error, undefined device response"}, 901 {0x04448400, IOASC_LOG_LEVEL_HARD, 902 "Hardware Error, IOA microcode error"}, 903 {0x04448600, IOASC_LOG_LEVEL_HARD, 904 "Hardware Error, IOA reset required"}, 905 {0x04449200, IOASC_LOG_LEVEL_HARD, 906 "Hardware Error, hard Cache Fearuee Card Battery error"}, 907 {0x0444A000, IOASC_LOG_LEVEL_HARD, 908 "Hardware Error, failed device altered"}, 909 {0x0444A200, IOASC_LOG_LEVEL_HARD, 910 "Hardware Error, data check after reassignment"}, 911 {0x0444A300, IOASC_LOG_LEVEL_HARD, 912 "Hardware Error, LRC error after reassignment"}, 913 {0x044A0000, IOASC_LOG_LEVEL_HARD, 914 "Hardware Error, device bus error (msg/cmd phase)"}, 915 {0x04670400, IOASC_LOG_LEVEL_HARD, 916 "Hardware Error, new device can't be used"}, 917 {0x04678000, IOASC_LOG_LEVEL_HARD, 918 "Hardware Error, invalid multiadapter configuration"}, 919 {0x04678100, IOASC_LOG_LEVEL_HARD, 920 "Hardware Error, incorrect connection between enclosures"}, 921 {0x04678200, IOASC_LOG_LEVEL_HARD, 922 "Hardware Error, connections exceed IOA design limits"}, 923 {0x04678300, IOASC_LOG_LEVEL_HARD, 924 "Hardware Error, incorrect multipath connection"}, 925 {0x04679000, IOASC_LOG_LEVEL_HARD, 926 "Hardware Error, command to LUN failed"}, 927 {0x064C8000, IOASC_LOG_LEVEL_HARD, 928 "Unit Attention, cache exists for missing/failed device"}, 929 {0x06670100, IOASC_LOG_LEVEL_HARD, 930 "Unit Attention, incompatible exposed mode device"}, 931 {0x06670600, IOASC_LOG_LEVEL_HARD, 932 "Unit Attention, attachment of logical unit failed"}, 933 {0x06678000, IOASC_LOG_LEVEL_HARD, 934 "Unit Attention, cables exceed connective design limit"}, 935 {0x06678300, IOASC_LOG_LEVEL_HARD, 936 "Unit Attention, incomplete multipath connection between" \ 937 "IOA and enclosure"}, 938 {0x06678400, IOASC_LOG_LEVEL_HARD, 939 "Unit Attention, incomplete multipath connection between" \ 940 "device and enclosure"}, 941 {0x06678500, IOASC_LOG_LEVEL_HARD, 942 "Unit Attention, incomplete multipath connection between" \ 943 "IOA and remote IOA"}, 944 {0x06678600, IOASC_LOG_LEVEL_HARD, 945 "Unit Attention, missing remote IOA"}, 946 {0x06679100, IOASC_LOG_LEVEL_HARD, 947 "Unit Attention, enclosure doesn't support required multipath" \ 948 "function"}, 949 {0x06698200, IOASC_LOG_LEVEL_HARD, 950 "Unit Attention, corrupt array parity detected on device"}, 951 {0x066B0200, IOASC_LOG_LEVEL_HARD, 952 "Unit Attention, array exposed"}, 953 {0x066B8200, IOASC_LOG_LEVEL_HARD, 954 "Unit Attention, exposed array is still protected"}, 955 {0x066B9200, IOASC_LOG_LEVEL_HARD, 956 "Unit Attention, Multipath redundancy level got worse"}, 957 {0x07270000, IOASC_LOG_LEVEL_HARD, 958 "Data Protect, device is read/write protected by IOA"}, 959 {0x07278000, IOASC_LOG_LEVEL_HARD, 960 "Data Protect, IOA doesn't support device attribute"}, 961 {0x07278100, IOASC_LOG_LEVEL_HARD, 962 "Data Protect, NVRAM mirroring prohibited"}, 963 {0x07278400, IOASC_LOG_LEVEL_HARD, 964 "Data Protect, array is short 2 or more devices"}, 965 {0x07278600, IOASC_LOG_LEVEL_HARD, 966 "Data Protect, exposed array is short a required device"}, 967 {0x07278700, IOASC_LOG_LEVEL_HARD, 968 "Data Protect, array members not at required addresses"}, 969 {0x07278800, IOASC_LOG_LEVEL_HARD, 970 "Data Protect, exposed mode device resource address conflict"}, 971 {0x07278900, IOASC_LOG_LEVEL_HARD, 972 "Data Protect, incorrect resource address of exposed mode device"}, 973 {0x07278A00, IOASC_LOG_LEVEL_HARD, 974 "Data Protect, Array is missing a device and parity is out of sync"}, 975 {0x07278B00, IOASC_LOG_LEVEL_HARD, 976 "Data Protect, maximum number of arrays already exist"}, 977 {0x07278C00, IOASC_LOG_LEVEL_HARD, 978 "Data Protect, cannot locate cache data for device"}, 979 {0x07278D00, IOASC_LOG_LEVEL_HARD, 980 "Data Protect, cache data exits for a changed device"}, 981 {0x07279100, IOASC_LOG_LEVEL_HARD, 982 "Data Protect, detection of a device requiring format"}, 983 {0x07279200, IOASC_LOG_LEVEL_HARD, 984 "Data Protect, IOA exceeds maximum number of devices"}, 985 {0x07279600, IOASC_LOG_LEVEL_HARD, 986 "Data Protect, missing array, volume set is not functional"}, 987 {0x07279700, IOASC_LOG_LEVEL_HARD, 988 "Data Protect, single device for a volume set"}, 989 {0x07279800, IOASC_LOG_LEVEL_HARD, 990 "Data Protect, missing multiple devices for a volume set"}, 991 {0x07279900, IOASC_LOG_LEVEL_HARD, 992 "Data Protect, maximum number of volument sets already exists"}, 993 {0x07279A00, IOASC_LOG_LEVEL_HARD, 994 "Data Protect, other volume set problem"}, 995}; 996 997/* macros to help in debugging */ 998#define pmcraid_err(...) \ 999 printk(KERN_ERR "MaxRAID: "__VA_ARGS__) 1000 1001#define pmcraid_info(...) \ 1002 if (pmcraid_debug_log) \ 1003 printk(KERN_INFO "MaxRAID: "__VA_ARGS__) 1004 1005/* check if given command is a SCSI READ or SCSI WRITE command */ 1006#define SCSI_READ_CMD 0x1 /* any of SCSI READ commands */ 1007#define SCSI_WRITE_CMD 0x2 /* any of SCSI WRITE commands */ 1008#define SCSI_CMD_TYPE(opcode) \ 1009({ u8 op = opcode; u8 __type = 0;\ 1010 if (op == READ_6 || op == READ_10 || op == READ_12 || op == READ_16)\ 1011 __type = SCSI_READ_CMD;\ 1012 else if (op == WRITE_6 || op == WRITE_10 || op == WRITE_12 || \ 1013 op == WRITE_16)\ 1014 __type = SCSI_WRITE_CMD;\ 1015 __type;\ 1016}) 1017 1018#define IS_SCSI_READ_WRITE(opcode) \ 1019({ u8 __type = SCSI_CMD_TYPE(opcode); \ 1020 (__type == SCSI_READ_CMD || __type == SCSI_WRITE_CMD) ? 1 : 0;\ 1021}) 1022 1023 1024/* 1025 * pmcraid_ioctl_header - definition of header structure that precedes all the 1026 * buffers given as ioctl arguments. 1027 * 1028 * .signature : always ASCII string, "PMCRAID" 1029 * .reserved : not used 1030 * .buffer_length : length of the buffer following the header 1031 */ 1032struct pmcraid_ioctl_header { 1033 u8 signature[8]; 1034 u32 reserved; 1035 u32 buffer_length; 1036}; 1037 1038#define PMCRAID_IOCTL_SIGNATURE "PMCRAID" 1039 1040/* 1041 * pmcraid_passthrough_ioctl_buffer - structure given as argument to 1042 * passthrough(or firmware handled) IOCTL commands. Note that ioarcb requires 1043 * 32-byte alignment so, it is necessary to pack this structure to avoid any 1044 * holes between ioctl_header and passthrough buffer 1045 * 1046 * .ioactl_header : ioctl header 1047 * .ioarcb : filled-up ioarcb buffer, driver always reads this buffer 1048 * .ioasa : buffer for ioasa, driver fills this with IOASA from firmware 1049 * .request_buffer: The I/O buffer (flat), driver reads/writes to this based on 1050 * the transfer directions passed in ioarcb.flags0. Contents 1051 * of this buffer are valid only when ioarcb.data_transfer_len 1052 * is not zero. 1053 */ 1054struct pmcraid_passthrough_ioctl_buffer { 1055 struct pmcraid_ioctl_header ioctl_header; 1056 struct pmcraid_ioarcb ioarcb; 1057 struct pmcraid_ioasa ioasa; 1058 u8 request_buffer[1]; 1059} __attribute__ ((packed)); 1060 1061/* 1062 * keys to differentiate between driver handled IOCTLs and passthrough 1063 * IOCTLs passed to IOA. driver determines the ioctl type using macro 1064 * _IOC_TYPE 1065 */ 1066#define PMCRAID_DRIVER_IOCTL 'D' 1067#define PMCRAID_PASSTHROUGH_IOCTL 'F' 1068 1069#define DRV_IOCTL(n, size) \ 1070 _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_DRIVER_IOCTL, (n), (size)) 1071 1072#define FMW_IOCTL(n, size) \ 1073 _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_PASSTHROUGH_IOCTL, (n), (size)) 1074 1075/* 1076 * _ARGSIZE: macro that gives size of the argument type passed to an IOCTL cmd. 1077 * This is to facilitate applications avoiding un-necessary memory allocations. 1078 * For example, most of driver handled ioctls do not require ioarcb, ioasa. 1079 */ 1080#define _ARGSIZE(arg) (sizeof(struct pmcraid_ioctl_header) + sizeof(arg)) 1081 1082/* Driver handled IOCTL command definitions */ 1083 1084#define PMCRAID_IOCTL_RESET_ADAPTER \ 1085 DRV_IOCTL(5, sizeof(struct pmcraid_ioctl_header)) 1086 1087/* passthrough/firmware handled commands */ 1088#define PMCRAID_IOCTL_PASSTHROUGH_COMMAND \ 1089 FMW_IOCTL(1, sizeof(struct pmcraid_passthrough_ioctl_buffer)) 1090 1091#define PMCRAID_IOCTL_DOWNLOAD_MICROCODE \ 1092 FMW_IOCTL(2, sizeof(struct pmcraid_passthrough_ioctl_buffer)) 1093 1094 1095#endif /* _PMCRAID_H */ 1096