1/* 2 * Driver for Atmel AT32 and AT91 SPI Controllers 3 * 4 * Copyright (C) 2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/clk.h> 13#include <linux/module.h> 14#include <linux/platform_device.h> 15#include <linux/delay.h> 16#include <linux/dma-mapping.h> 17#include <linux/dmaengine.h> 18#include <linux/err.h> 19#include <linux/interrupt.h> 20#include <linux/spi/spi.h> 21#include <linux/slab.h> 22#include <linux/platform_data/atmel.h> 23#include <linux/platform_data/dma-atmel.h> 24#include <linux/of.h> 25 26#include <linux/io.h> 27#include <linux/gpio.h> 28#include <linux/pinctrl/consumer.h> 29 30/* SPI register offsets */ 31#define SPI_CR 0x0000 32#define SPI_MR 0x0004 33#define SPI_RDR 0x0008 34#define SPI_TDR 0x000c 35#define SPI_SR 0x0010 36#define SPI_IER 0x0014 37#define SPI_IDR 0x0018 38#define SPI_IMR 0x001c 39#define SPI_CSR0 0x0030 40#define SPI_CSR1 0x0034 41#define SPI_CSR2 0x0038 42#define SPI_CSR3 0x003c 43#define SPI_VERSION 0x00fc 44#define SPI_RPR 0x0100 45#define SPI_RCR 0x0104 46#define SPI_TPR 0x0108 47#define SPI_TCR 0x010c 48#define SPI_RNPR 0x0110 49#define SPI_RNCR 0x0114 50#define SPI_TNPR 0x0118 51#define SPI_TNCR 0x011c 52#define SPI_PTCR 0x0120 53#define SPI_PTSR 0x0124 54 55/* Bitfields in CR */ 56#define SPI_SPIEN_OFFSET 0 57#define SPI_SPIEN_SIZE 1 58#define SPI_SPIDIS_OFFSET 1 59#define SPI_SPIDIS_SIZE 1 60#define SPI_SWRST_OFFSET 7 61#define SPI_SWRST_SIZE 1 62#define SPI_LASTXFER_OFFSET 24 63#define SPI_LASTXFER_SIZE 1 64 65/* Bitfields in MR */ 66#define SPI_MSTR_OFFSET 0 67#define SPI_MSTR_SIZE 1 68#define SPI_PS_OFFSET 1 69#define SPI_PS_SIZE 1 70#define SPI_PCSDEC_OFFSET 2 71#define SPI_PCSDEC_SIZE 1 72#define SPI_FDIV_OFFSET 3 73#define SPI_FDIV_SIZE 1 74#define SPI_MODFDIS_OFFSET 4 75#define SPI_MODFDIS_SIZE 1 76#define SPI_WDRBT_OFFSET 5 77#define SPI_WDRBT_SIZE 1 78#define SPI_LLB_OFFSET 7 79#define SPI_LLB_SIZE 1 80#define SPI_PCS_OFFSET 16 81#define SPI_PCS_SIZE 4 82#define SPI_DLYBCS_OFFSET 24 83#define SPI_DLYBCS_SIZE 8 84 85/* Bitfields in RDR */ 86#define SPI_RD_OFFSET 0 87#define SPI_RD_SIZE 16 88 89/* Bitfields in TDR */ 90#define SPI_TD_OFFSET 0 91#define SPI_TD_SIZE 16 92 93/* Bitfields in SR */ 94#define SPI_RDRF_OFFSET 0 95#define SPI_RDRF_SIZE 1 96#define SPI_TDRE_OFFSET 1 97#define SPI_TDRE_SIZE 1 98#define SPI_MODF_OFFSET 2 99#define SPI_MODF_SIZE 1 100#define SPI_OVRES_OFFSET 3 101#define SPI_OVRES_SIZE 1 102#define SPI_ENDRX_OFFSET 4 103#define SPI_ENDRX_SIZE 1 104#define SPI_ENDTX_OFFSET 5 105#define SPI_ENDTX_SIZE 1 106#define SPI_RXBUFF_OFFSET 6 107#define SPI_RXBUFF_SIZE 1 108#define SPI_TXBUFE_OFFSET 7 109#define SPI_TXBUFE_SIZE 1 110#define SPI_NSSR_OFFSET 8 111#define SPI_NSSR_SIZE 1 112#define SPI_TXEMPTY_OFFSET 9 113#define SPI_TXEMPTY_SIZE 1 114#define SPI_SPIENS_OFFSET 16 115#define SPI_SPIENS_SIZE 1 116 117/* Bitfields in CSR0 */ 118#define SPI_CPOL_OFFSET 0 119#define SPI_CPOL_SIZE 1 120#define SPI_NCPHA_OFFSET 1 121#define SPI_NCPHA_SIZE 1 122#define SPI_CSAAT_OFFSET 3 123#define SPI_CSAAT_SIZE 1 124#define SPI_BITS_OFFSET 4 125#define SPI_BITS_SIZE 4 126#define SPI_SCBR_OFFSET 8 127#define SPI_SCBR_SIZE 8 128#define SPI_DLYBS_OFFSET 16 129#define SPI_DLYBS_SIZE 8 130#define SPI_DLYBCT_OFFSET 24 131#define SPI_DLYBCT_SIZE 8 132 133/* Bitfields in RCR */ 134#define SPI_RXCTR_OFFSET 0 135#define SPI_RXCTR_SIZE 16 136 137/* Bitfields in TCR */ 138#define SPI_TXCTR_OFFSET 0 139#define SPI_TXCTR_SIZE 16 140 141/* Bitfields in RNCR */ 142#define SPI_RXNCR_OFFSET 0 143#define SPI_RXNCR_SIZE 16 144 145/* Bitfields in TNCR */ 146#define SPI_TXNCR_OFFSET 0 147#define SPI_TXNCR_SIZE 16 148 149/* Bitfields in PTCR */ 150#define SPI_RXTEN_OFFSET 0 151#define SPI_RXTEN_SIZE 1 152#define SPI_RXTDIS_OFFSET 1 153#define SPI_RXTDIS_SIZE 1 154#define SPI_TXTEN_OFFSET 8 155#define SPI_TXTEN_SIZE 1 156#define SPI_TXTDIS_OFFSET 9 157#define SPI_TXTDIS_SIZE 1 158 159/* Constants for BITS */ 160#define SPI_BITS_8_BPT 0 161#define SPI_BITS_9_BPT 1 162#define SPI_BITS_10_BPT 2 163#define SPI_BITS_11_BPT 3 164#define SPI_BITS_12_BPT 4 165#define SPI_BITS_13_BPT 5 166#define SPI_BITS_14_BPT 6 167#define SPI_BITS_15_BPT 7 168#define SPI_BITS_16_BPT 8 169 170/* Bit manipulation macros */ 171#define SPI_BIT(name) \ 172 (1 << SPI_##name##_OFFSET) 173#define SPI_BF(name, value) \ 174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 175#define SPI_BFEXT(name, value) \ 176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 177#define SPI_BFINS(name, value, old) \ 178 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 179 | SPI_BF(name, value)) 180 181/* Register access macros */ 182#define spi_readl(port, reg) \ 183 __raw_readl((port)->regs + SPI_##reg) 184#define spi_writel(port, reg, value) \ 185 __raw_writel((value), (port)->regs + SPI_##reg) 186 187/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 188 * cache operations; better heuristics consider wordsize and bitrate. 189 */ 190#define DMA_MIN_BYTES 16 191 192#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 193 194struct atmel_spi_dma { 195 struct dma_chan *chan_rx; 196 struct dma_chan *chan_tx; 197 struct scatterlist sgrx; 198 struct scatterlist sgtx; 199 struct dma_async_tx_descriptor *data_desc_rx; 200 struct dma_async_tx_descriptor *data_desc_tx; 201 202 struct at_dma_slave dma_slave; 203}; 204 205struct atmel_spi_caps { 206 bool is_spi2; 207 bool has_wdrbt; 208 bool has_dma_support; 209}; 210 211/* 212 * The core SPI transfer engine just talks to a register bank to set up 213 * DMA transfers; transfer queue progress is driven by IRQs. The clock 214 * framework provides the base clock, subdivided for each spi_device. 215 */ 216struct atmel_spi { 217 spinlock_t lock; 218 unsigned long flags; 219 220 phys_addr_t phybase; 221 void __iomem *regs; 222 int irq; 223 struct clk *clk; 224 struct platform_device *pdev; 225 226 struct spi_transfer *current_transfer; 227 int current_remaining_bytes; 228 int done_status; 229 230 struct completion xfer_completion; 231 232 /* scratch buffer */ 233 void *buffer; 234 dma_addr_t buffer_dma; 235 236 struct atmel_spi_caps caps; 237 238 bool use_dma; 239 bool use_pdc; 240 /* dmaengine data */ 241 struct atmel_spi_dma dma; 242 243 bool keep_cs; 244 bool cs_active; 245}; 246 247/* Controller-specific per-slave state */ 248struct atmel_spi_device { 249 unsigned int npcs_pin; 250 u32 csr; 251}; 252 253#define BUFFER_SIZE PAGE_SIZE 254#define INVALID_DMA_ADDRESS 0xffffffff 255 256/* 257 * Version 2 of the SPI controller has 258 * - CR.LASTXFER 259 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) 260 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) 261 * - SPI_CSRx.CSAAT 262 * - SPI_CSRx.SBCR allows faster clocking 263 */ 264static bool atmel_spi_is_v2(struct atmel_spi *as) 265{ 266 return as->caps.is_spi2; 267} 268 269/* 270 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby 271 * they assume that spi slave device state will not change on deselect, so 272 * that automagic deselection is OK. ("NPCSx rises if no data is to be 273 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer 274 * controllers have CSAAT and friends. 275 * 276 * Since the CSAAT functionality is a bit weird on newer controllers as 277 * well, we use GPIO to control nCSx pins on all controllers, updating 278 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us 279 * support active-high chipselects despite the controller's belief that 280 * only active-low devices/systems exists. 281 * 282 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work 283 * right when driven with GPIO. ("Mode Fault does not allow more than one 284 * Master on Chip Select 0.") No workaround exists for that ... so for 285 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, 286 * and (c) will trigger that first erratum in some cases. 287 */ 288 289static void cs_activate(struct atmel_spi *as, struct spi_device *spi) 290{ 291 struct atmel_spi_device *asd = spi->controller_state; 292 unsigned active = spi->mode & SPI_CS_HIGH; 293 u32 mr; 294 295 if (atmel_spi_is_v2(as)) { 296 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); 297 /* For the low SPI version, there is a issue that PDC transfer 298 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 299 */ 300 spi_writel(as, CSR0, asd->csr); 301 if (as->caps.has_wdrbt) { 302 spi_writel(as, MR, 303 SPI_BF(PCS, ~(0x01 << spi->chip_select)) 304 | SPI_BIT(WDRBT) 305 | SPI_BIT(MODFDIS) 306 | SPI_BIT(MSTR)); 307 } else { 308 spi_writel(as, MR, 309 SPI_BF(PCS, ~(0x01 << spi->chip_select)) 310 | SPI_BIT(MODFDIS) 311 | SPI_BIT(MSTR)); 312 } 313 314 mr = spi_readl(as, MR); 315 gpio_set_value(asd->npcs_pin, active); 316 } else { 317 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; 318 int i; 319 u32 csr; 320 321 /* Make sure clock polarity is correct */ 322 for (i = 0; i < spi->master->num_chipselect; i++) { 323 csr = spi_readl(as, CSR0 + 4 * i); 324 if ((csr ^ cpol) & SPI_BIT(CPOL)) 325 spi_writel(as, CSR0 + 4 * i, 326 csr ^ SPI_BIT(CPOL)); 327 } 328 329 mr = spi_readl(as, MR); 330 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); 331 if (spi->chip_select != 0) 332 gpio_set_value(asd->npcs_pin, active); 333 spi_writel(as, MR, mr); 334 } 335 336 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", 337 asd->npcs_pin, active ? " (high)" : "", 338 mr); 339} 340 341static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) 342{ 343 struct atmel_spi_device *asd = spi->controller_state; 344 unsigned active = spi->mode & SPI_CS_HIGH; 345 u32 mr; 346 347 /* only deactivate *this* device; sometimes transfers to 348 * another device may be active when this routine is called. 349 */ 350 mr = spi_readl(as, MR); 351 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { 352 mr = SPI_BFINS(PCS, 0xf, mr); 353 spi_writel(as, MR, mr); 354 } 355 356 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", 357 asd->npcs_pin, active ? " (low)" : "", 358 mr); 359 360 if (atmel_spi_is_v2(as) || spi->chip_select != 0) 361 gpio_set_value(asd->npcs_pin, !active); 362} 363 364static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) 365{ 366 spin_lock_irqsave(&as->lock, as->flags); 367} 368 369static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) 370{ 371 spin_unlock_irqrestore(&as->lock, as->flags); 372} 373 374static inline bool atmel_spi_use_dma(struct atmel_spi *as, 375 struct spi_transfer *xfer) 376{ 377 return as->use_dma && xfer->len >= DMA_MIN_BYTES; 378} 379 380static int atmel_spi_dma_slave_config(struct atmel_spi *as, 381 struct dma_slave_config *slave_config, 382 u8 bits_per_word) 383{ 384 int err = 0; 385 386 if (bits_per_word > 8) { 387 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 388 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 389 } else { 390 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 391 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 392 } 393 394 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; 395 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; 396 slave_config->src_maxburst = 1; 397 slave_config->dst_maxburst = 1; 398 slave_config->device_fc = false; 399 400 slave_config->direction = DMA_MEM_TO_DEV; 401 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) { 402 dev_err(&as->pdev->dev, 403 "failed to configure tx dma channel\n"); 404 err = -EINVAL; 405 } 406 407 slave_config->direction = DMA_DEV_TO_MEM; 408 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) { 409 dev_err(&as->pdev->dev, 410 "failed to configure rx dma channel\n"); 411 err = -EINVAL; 412 } 413 414 return err; 415} 416 417static bool filter(struct dma_chan *chan, void *pdata) 418{ 419 struct atmel_spi_dma *sl_pdata = pdata; 420 struct at_dma_slave *sl; 421 422 if (!sl_pdata) 423 return false; 424 425 sl = &sl_pdata->dma_slave; 426 if (sl->dma_dev == chan->device->dev) { 427 chan->private = sl; 428 return true; 429 } else { 430 return false; 431 } 432} 433 434static int atmel_spi_configure_dma(struct atmel_spi *as) 435{ 436 struct dma_slave_config slave_config; 437 struct device *dev = &as->pdev->dev; 438 int err; 439 440 dma_cap_mask_t mask; 441 dma_cap_zero(mask); 442 dma_cap_set(DMA_SLAVE, mask); 443 444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter, 445 &as->dma, 446 dev, "tx"); 447 if (!as->dma.chan_tx) { 448 dev_err(dev, 449 "DMA TX channel not available, SPI unable to use DMA\n"); 450 err = -EBUSY; 451 goto error; 452 } 453 454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter, 455 &as->dma, 456 dev, "rx"); 457 458 if (!as->dma.chan_rx) { 459 dev_err(dev, 460 "DMA RX channel not available, SPI unable to use DMA\n"); 461 err = -EBUSY; 462 goto error; 463 } 464 465 err = atmel_spi_dma_slave_config(as, &slave_config, 8); 466 if (err) 467 goto error; 468 469 dev_info(&as->pdev->dev, 470 "Using %s (tx) and %s (rx) for DMA transfers\n", 471 dma_chan_name(as->dma.chan_tx), 472 dma_chan_name(as->dma.chan_rx)); 473 return 0; 474error: 475 if (as->dma.chan_rx) 476 dma_release_channel(as->dma.chan_rx); 477 if (as->dma.chan_tx) 478 dma_release_channel(as->dma.chan_tx); 479 return err; 480} 481 482static void atmel_spi_stop_dma(struct atmel_spi *as) 483{ 484 if (as->dma.chan_rx) 485 as->dma.chan_rx->device->device_control(as->dma.chan_rx, 486 DMA_TERMINATE_ALL, 0); 487 if (as->dma.chan_tx) 488 as->dma.chan_tx->device->device_control(as->dma.chan_tx, 489 DMA_TERMINATE_ALL, 0); 490} 491 492static void atmel_spi_release_dma(struct atmel_spi *as) 493{ 494 if (as->dma.chan_rx) 495 dma_release_channel(as->dma.chan_rx); 496 if (as->dma.chan_tx) 497 dma_release_channel(as->dma.chan_tx); 498} 499 500/* This function is called by the DMA driver from tasklet context */ 501static void dma_callback(void *data) 502{ 503 struct spi_master *master = data; 504 struct atmel_spi *as = spi_master_get_devdata(master); 505 506 complete(&as->xfer_completion); 507} 508 509/* 510 * Next transfer using PIO. 511 */ 512static void atmel_spi_next_xfer_pio(struct spi_master *master, 513 struct spi_transfer *xfer) 514{ 515 struct atmel_spi *as = spi_master_get_devdata(master); 516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 517 518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); 519 520 /* Make sure data is not remaining in RDR */ 521 spi_readl(as, RDR); 522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 523 spi_readl(as, RDR); 524 cpu_relax(); 525 } 526 527 if (xfer->tx_buf) { 528 if (xfer->bits_per_word > 8) 529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); 530 else 531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); 532 } else { 533 spi_writel(as, TDR, 0); 534 } 535 536 dev_dbg(master->dev.parent, 537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 539 xfer->bits_per_word); 540 541 /* Enable relevant interrupts */ 542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); 543} 544 545/* 546 * Submit next transfer for DMA. 547 */ 548static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, 549 struct spi_transfer *xfer, 550 u32 *plen) 551{ 552 struct atmel_spi *as = spi_master_get_devdata(master); 553 struct dma_chan *rxchan = as->dma.chan_rx; 554 struct dma_chan *txchan = as->dma.chan_tx; 555 struct dma_async_tx_descriptor *rxdesc; 556 struct dma_async_tx_descriptor *txdesc; 557 struct dma_slave_config slave_config; 558 dma_cookie_t cookie; 559 u32 len = *plen; 560 561 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); 562 563 /* Check that the channels are available */ 564 if (!rxchan || !txchan) 565 return -ENODEV; 566 567 /* release lock for DMA operations */ 568 atmel_spi_unlock(as); 569 570 /* prepare the RX dma transfer */ 571 sg_init_table(&as->dma.sgrx, 1); 572 if (xfer->rx_buf) { 573 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen; 574 } else { 575 as->dma.sgrx.dma_address = as->buffer_dma; 576 if (len > BUFFER_SIZE) 577 len = BUFFER_SIZE; 578 } 579 580 /* prepare the TX dma transfer */ 581 sg_init_table(&as->dma.sgtx, 1); 582 if (xfer->tx_buf) { 583 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen; 584 } else { 585 as->dma.sgtx.dma_address = as->buffer_dma; 586 if (len > BUFFER_SIZE) 587 len = BUFFER_SIZE; 588 memset(as->buffer, 0, len); 589 } 590 591 sg_dma_len(&as->dma.sgtx) = len; 592 sg_dma_len(&as->dma.sgrx) = len; 593 594 *plen = len; 595 596 if (atmel_spi_dma_slave_config(as, &slave_config, 8)) 597 goto err_exit; 598 599 /* Send both scatterlists */ 600 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1, 601 DMA_FROM_DEVICE, 602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 603 if (!rxdesc) 604 goto err_dma; 605 606 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1, 607 DMA_TO_DEVICE, 608 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 609 if (!txdesc) 610 goto err_dma; 611 612 dev_dbg(master->dev.parent, 613 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 614 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, 615 xfer->rx_buf, (unsigned long long)xfer->rx_dma); 616 617 /* Enable relevant interrupts */ 618 spi_writel(as, IER, SPI_BIT(OVRES)); 619 620 /* Put the callback on the RX transfer only, that should finish last */ 621 rxdesc->callback = dma_callback; 622 rxdesc->callback_param = master; 623 624 /* Submit and fire RX and TX with TX last so we're ready to read! */ 625 cookie = rxdesc->tx_submit(rxdesc); 626 if (dma_submit_error(cookie)) 627 goto err_dma; 628 cookie = txdesc->tx_submit(txdesc); 629 if (dma_submit_error(cookie)) 630 goto err_dma; 631 rxchan->device->device_issue_pending(rxchan); 632 txchan->device->device_issue_pending(txchan); 633 634 /* take back lock */ 635 atmel_spi_lock(as); 636 return 0; 637 638err_dma: 639 spi_writel(as, IDR, SPI_BIT(OVRES)); 640 atmel_spi_stop_dma(as); 641err_exit: 642 atmel_spi_lock(as); 643 return -ENOMEM; 644} 645 646static void atmel_spi_next_xfer_data(struct spi_master *master, 647 struct spi_transfer *xfer, 648 dma_addr_t *tx_dma, 649 dma_addr_t *rx_dma, 650 u32 *plen) 651{ 652 struct atmel_spi *as = spi_master_get_devdata(master); 653 u32 len = *plen; 654 655 /* use scratch buffer only when rx or tx data is unspecified */ 656 if (xfer->rx_buf) 657 *rx_dma = xfer->rx_dma + xfer->len - *plen; 658 else { 659 *rx_dma = as->buffer_dma; 660 if (len > BUFFER_SIZE) 661 len = BUFFER_SIZE; 662 } 663 664 if (xfer->tx_buf) 665 *tx_dma = xfer->tx_dma + xfer->len - *plen; 666 else { 667 *tx_dma = as->buffer_dma; 668 if (len > BUFFER_SIZE) 669 len = BUFFER_SIZE; 670 memset(as->buffer, 0, len); 671 dma_sync_single_for_device(&as->pdev->dev, 672 as->buffer_dma, len, DMA_TO_DEVICE); 673 } 674 675 *plen = len; 676} 677 678static int atmel_spi_set_xfer_speed(struct atmel_spi *as, 679 struct spi_device *spi, 680 struct spi_transfer *xfer) 681{ 682 u32 scbr, csr; 683 unsigned long bus_hz; 684 685 /* v1 chips start out at half the peripheral bus speed. */ 686 bus_hz = clk_get_rate(as->clk); 687 if (!atmel_spi_is_v2(as)) 688 bus_hz /= 2; 689 690 /* 691 * Calculate the lowest divider that satisfies the 692 * constraint, assuming div32/fdiv/mbz == 0. 693 */ 694 if (xfer->speed_hz) 695 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); 696 else 697 /* 698 * This can happend if max_speed is null. 699 * In this case, we set the lowest possible speed 700 */ 701 scbr = 0xff; 702 703 /* 704 * If the resulting divider doesn't fit into the 705 * register bitfield, we can't satisfy the constraint. 706 */ 707 if (scbr >= (1 << SPI_SCBR_SIZE)) { 708 dev_err(&spi->dev, 709 "setup: %d Hz too slow, scbr %u; min %ld Hz\n", 710 xfer->speed_hz, scbr, bus_hz/255); 711 return -EINVAL; 712 } 713 if (scbr == 0) { 714 dev_err(&spi->dev, 715 "setup: %d Hz too high, scbr %u; max %ld Hz\n", 716 xfer->speed_hz, scbr, bus_hz); 717 return -EINVAL; 718 } 719 csr = spi_readl(as, CSR0 + 4 * spi->chip_select); 720 csr = SPI_BFINS(SCBR, scbr, csr); 721 spi_writel(as, CSR0 + 4 * spi->chip_select, csr); 722 723 return 0; 724} 725 726/* 727 * Submit next transfer for PDC. 728 * lock is held, spi irq is blocked 729 */ 730static void atmel_spi_pdc_next_xfer(struct spi_master *master, 731 struct spi_message *msg, 732 struct spi_transfer *xfer) 733{ 734 struct atmel_spi *as = spi_master_get_devdata(master); 735 u32 len; 736 dma_addr_t tx_dma, rx_dma; 737 738 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 739 740 len = as->current_remaining_bytes; 741 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 742 as->current_remaining_bytes -= len; 743 744 spi_writel(as, RPR, rx_dma); 745 spi_writel(as, TPR, tx_dma); 746 747 if (msg->spi->bits_per_word > 8) 748 len >>= 1; 749 spi_writel(as, RCR, len); 750 spi_writel(as, TCR, len); 751 752 dev_dbg(&msg->spi->dev, 753 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 754 xfer, xfer->len, xfer->tx_buf, 755 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 756 (unsigned long long)xfer->rx_dma); 757 758 if (as->current_remaining_bytes) { 759 len = as->current_remaining_bytes; 760 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 761 as->current_remaining_bytes -= len; 762 763 spi_writel(as, RNPR, rx_dma); 764 spi_writel(as, TNPR, tx_dma); 765 766 if (msg->spi->bits_per_word > 8) 767 len >>= 1; 768 spi_writel(as, RNCR, len); 769 spi_writel(as, TNCR, len); 770 771 dev_dbg(&msg->spi->dev, 772 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 773 xfer, xfer->len, xfer->tx_buf, 774 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 775 (unsigned long long)xfer->rx_dma); 776 } 777 778 /* REVISIT: We're waiting for ENDRX before we start the next 779 * transfer because we need to handle some difficult timing 780 * issues otherwise. If we wait for ENDTX in one transfer and 781 * then starts waiting for ENDRX in the next, it's difficult 782 * to tell the difference between the ENDRX interrupt we're 783 * actually waiting for and the ENDRX interrupt of the 784 * previous transfer. 785 * 786 * It should be doable, though. Just not now... 787 */ 788 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); 789 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 790} 791 792/* 793 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 794 * - The buffer is either valid for CPU access, else NULL 795 * - If the buffer is valid, so is its DMA address 796 * 797 * This driver manages the dma address unless message->is_dma_mapped. 798 */ 799static int 800atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) 801{ 802 struct device *dev = &as->pdev->dev; 803 804 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; 805 if (xfer->tx_buf) { 806 /* tx_buf is a const void* where we need a void * for the dma 807 * mapping */ 808 void *nonconst_tx = (void *)xfer->tx_buf; 809 810 xfer->tx_dma = dma_map_single(dev, 811 nonconst_tx, xfer->len, 812 DMA_TO_DEVICE); 813 if (dma_mapping_error(dev, xfer->tx_dma)) 814 return -ENOMEM; 815 } 816 if (xfer->rx_buf) { 817 xfer->rx_dma = dma_map_single(dev, 818 xfer->rx_buf, xfer->len, 819 DMA_FROM_DEVICE); 820 if (dma_mapping_error(dev, xfer->rx_dma)) { 821 if (xfer->tx_buf) 822 dma_unmap_single(dev, 823 xfer->tx_dma, xfer->len, 824 DMA_TO_DEVICE); 825 return -ENOMEM; 826 } 827 } 828 return 0; 829} 830 831static void atmel_spi_dma_unmap_xfer(struct spi_master *master, 832 struct spi_transfer *xfer) 833{ 834 if (xfer->tx_dma != INVALID_DMA_ADDRESS) 835 dma_unmap_single(master->dev.parent, xfer->tx_dma, 836 xfer->len, DMA_TO_DEVICE); 837 if (xfer->rx_dma != INVALID_DMA_ADDRESS) 838 dma_unmap_single(master->dev.parent, xfer->rx_dma, 839 xfer->len, DMA_FROM_DEVICE); 840} 841 842static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) 843{ 844 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 845} 846 847/* Called from IRQ 848 * 849 * Must update "current_remaining_bytes" to keep track of data 850 * to transfer. 851 */ 852static void 853atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 854{ 855 u8 *rxp; 856 u16 *rxp16; 857 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 858 859 if (xfer->rx_buf) { 860 if (xfer->bits_per_word > 8) { 861 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); 862 *rxp16 = spi_readl(as, RDR); 863 } else { 864 rxp = ((u8 *)xfer->rx_buf) + xfer_pos; 865 *rxp = spi_readl(as, RDR); 866 } 867 } else { 868 spi_readl(as, RDR); 869 } 870 if (xfer->bits_per_word > 8) { 871 if (as->current_remaining_bytes > 2) 872 as->current_remaining_bytes -= 2; 873 else 874 as->current_remaining_bytes = 0; 875 } else { 876 as->current_remaining_bytes--; 877 } 878} 879 880/* Interrupt 881 * 882 * No need for locking in this Interrupt handler: done_status is the 883 * only information modified. 884 */ 885static irqreturn_t 886atmel_spi_pio_interrupt(int irq, void *dev_id) 887{ 888 struct spi_master *master = dev_id; 889 struct atmel_spi *as = spi_master_get_devdata(master); 890 u32 status, pending, imr; 891 struct spi_transfer *xfer; 892 int ret = IRQ_NONE; 893 894 imr = spi_readl(as, IMR); 895 status = spi_readl(as, SR); 896 pending = status & imr; 897 898 if (pending & SPI_BIT(OVRES)) { 899 ret = IRQ_HANDLED; 900 spi_writel(as, IDR, SPI_BIT(OVRES)); 901 dev_warn(master->dev.parent, "overrun\n"); 902 903 /* 904 * When we get an overrun, we disregard the current 905 * transfer. Data will not be copied back from any 906 * bounce buffer and msg->actual_len will not be 907 * updated with the last xfer. 908 * 909 * We will also not process any remaning transfers in 910 * the message. 911 */ 912 as->done_status = -EIO; 913 smp_wmb(); 914 915 /* Clear any overrun happening while cleaning up */ 916 spi_readl(as, SR); 917 918 complete(&as->xfer_completion); 919 920 } else if (pending & SPI_BIT(RDRF)) { 921 atmel_spi_lock(as); 922 923 if (as->current_remaining_bytes) { 924 ret = IRQ_HANDLED; 925 xfer = as->current_transfer; 926 atmel_spi_pump_pio_data(as, xfer); 927 if (!as->current_remaining_bytes) 928 spi_writel(as, IDR, pending); 929 930 complete(&as->xfer_completion); 931 } 932 933 atmel_spi_unlock(as); 934 } else { 935 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); 936 ret = IRQ_HANDLED; 937 spi_writel(as, IDR, pending); 938 } 939 940 return ret; 941} 942 943static irqreturn_t 944atmel_spi_pdc_interrupt(int irq, void *dev_id) 945{ 946 struct spi_master *master = dev_id; 947 struct atmel_spi *as = spi_master_get_devdata(master); 948 u32 status, pending, imr; 949 int ret = IRQ_NONE; 950 951 imr = spi_readl(as, IMR); 952 status = spi_readl(as, SR); 953 pending = status & imr; 954 955 if (pending & SPI_BIT(OVRES)) { 956 957 ret = IRQ_HANDLED; 958 959 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 960 | SPI_BIT(OVRES))); 961 962 /* Clear any overrun happening while cleaning up */ 963 spi_readl(as, SR); 964 965 as->done_status = -EIO; 966 967 complete(&as->xfer_completion); 968 969 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 970 ret = IRQ_HANDLED; 971 972 spi_writel(as, IDR, pending); 973 974 complete(&as->xfer_completion); 975 } 976 977 return ret; 978} 979 980static int atmel_spi_setup(struct spi_device *spi) 981{ 982 struct atmel_spi *as; 983 struct atmel_spi_device *asd; 984 u32 csr; 985 unsigned int bits = spi->bits_per_word; 986 unsigned int npcs_pin; 987 int ret; 988 989 as = spi_master_get_devdata(spi->master); 990 991 /* see notes above re chipselect */ 992 if (!atmel_spi_is_v2(as) 993 && spi->chip_select == 0 994 && (spi->mode & SPI_CS_HIGH)) { 995 dev_dbg(&spi->dev, "setup: can't be active-high\n"); 996 return -EINVAL; 997 } 998 999 csr = SPI_BF(BITS, bits - 8); 1000 if (spi->mode & SPI_CPOL) 1001 csr |= SPI_BIT(CPOL); 1002 if (!(spi->mode & SPI_CPHA)) 1003 csr |= SPI_BIT(NCPHA); 1004 1005 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. 1006 * 1007 * DLYBCT would add delays between words, slowing down transfers. 1008 * It could potentially be useful to cope with DMA bottlenecks, but 1009 * in those cases it's probably best to just use a lower bitrate. 1010 */ 1011 csr |= SPI_BF(DLYBS, 0); 1012 csr |= SPI_BF(DLYBCT, 0); 1013 1014 /* chipselect must have been muxed as GPIO (e.g. in board setup) */ 1015 npcs_pin = (unsigned long)spi->controller_data; 1016 1017 if (gpio_is_valid(spi->cs_gpio)) 1018 npcs_pin = spi->cs_gpio; 1019 1020 asd = spi->controller_state; 1021 if (!asd) { 1022 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); 1023 if (!asd) 1024 return -ENOMEM; 1025 1026 ret = gpio_request(npcs_pin, dev_name(&spi->dev)); 1027 if (ret) { 1028 kfree(asd); 1029 return ret; 1030 } 1031 1032 asd->npcs_pin = npcs_pin; 1033 spi->controller_state = asd; 1034 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); 1035 } 1036 1037 asd->csr = csr; 1038 1039 dev_dbg(&spi->dev, 1040 "setup: bpw %u mode 0x%x -> csr%d %08x\n", 1041 bits, spi->mode, spi->chip_select, csr); 1042 1043 if (!atmel_spi_is_v2(as)) 1044 spi_writel(as, CSR0 + 4 * spi->chip_select, csr); 1045 1046 return 0; 1047} 1048 1049static int atmel_spi_one_transfer(struct spi_master *master, 1050 struct spi_message *msg, 1051 struct spi_transfer *xfer) 1052{ 1053 struct atmel_spi *as; 1054 struct spi_device *spi = msg->spi; 1055 u8 bits; 1056 u32 len; 1057 struct atmel_spi_device *asd; 1058 int timeout; 1059 int ret; 1060 1061 as = spi_master_get_devdata(master); 1062 1063 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { 1064 dev_dbg(&spi->dev, "missing rx or tx buf\n"); 1065 return -EINVAL; 1066 } 1067 1068 if (xfer->bits_per_word) { 1069 asd = spi->controller_state; 1070 bits = (asd->csr >> 4) & 0xf; 1071 if (bits != xfer->bits_per_word - 8) { 1072 dev_dbg(&spi->dev, 1073 "you can't yet change bits_per_word in transfers\n"); 1074 return -ENOPROTOOPT; 1075 } 1076 } 1077 1078 /* 1079 * DMA map early, for performance (empties dcache ASAP) and 1080 * better fault reporting. 1081 */ 1082 if ((!msg->is_dma_mapped) 1083 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) { 1084 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1085 return -ENOMEM; 1086 } 1087 1088 atmel_spi_set_xfer_speed(as, msg->spi, xfer); 1089 1090 as->done_status = 0; 1091 as->current_transfer = xfer; 1092 as->current_remaining_bytes = xfer->len; 1093 while (as->current_remaining_bytes) { 1094 reinit_completion(&as->xfer_completion); 1095 1096 if (as->use_pdc) { 1097 atmel_spi_pdc_next_xfer(master, msg, xfer); 1098 } else if (atmel_spi_use_dma(as, xfer)) { 1099 len = as->current_remaining_bytes; 1100 ret = atmel_spi_next_xfer_dma_submit(master, 1101 xfer, &len); 1102 if (ret) { 1103 dev_err(&spi->dev, 1104 "unable to use DMA, fallback to PIO\n"); 1105 atmel_spi_next_xfer_pio(master, xfer); 1106 } else { 1107 as->current_remaining_bytes -= len; 1108 if (as->current_remaining_bytes < 0) 1109 as->current_remaining_bytes = 0; 1110 } 1111 } else { 1112 atmel_spi_next_xfer_pio(master, xfer); 1113 } 1114 1115 /* interrupts are disabled, so free the lock for schedule */ 1116 atmel_spi_unlock(as); 1117 ret = wait_for_completion_timeout(&as->xfer_completion, 1118 SPI_DMA_TIMEOUT); 1119 atmel_spi_lock(as); 1120 if (WARN_ON(ret == 0)) { 1121 dev_err(&spi->dev, 1122 "spi trasfer timeout, err %d\n", ret); 1123 as->done_status = -EIO; 1124 } else { 1125 ret = 0; 1126 } 1127 1128 if (as->done_status) 1129 break; 1130 } 1131 1132 if (as->done_status) { 1133 if (as->use_pdc) { 1134 dev_warn(master->dev.parent, 1135 "overrun (%u/%u remaining)\n", 1136 spi_readl(as, TCR), spi_readl(as, RCR)); 1137 1138 /* 1139 * Clean up DMA registers and make sure the data 1140 * registers are empty. 1141 */ 1142 spi_writel(as, RNCR, 0); 1143 spi_writel(as, TNCR, 0); 1144 spi_writel(as, RCR, 0); 1145 spi_writel(as, TCR, 0); 1146 for (timeout = 1000; timeout; timeout--) 1147 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) 1148 break; 1149 if (!timeout) 1150 dev_warn(master->dev.parent, 1151 "timeout waiting for TXEMPTY"); 1152 while (spi_readl(as, SR) & SPI_BIT(RDRF)) 1153 spi_readl(as, RDR); 1154 1155 /* Clear any overrun happening while cleaning up */ 1156 spi_readl(as, SR); 1157 1158 } else if (atmel_spi_use_dma(as, xfer)) { 1159 atmel_spi_stop_dma(as); 1160 } 1161 1162 if (!msg->is_dma_mapped 1163 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) 1164 atmel_spi_dma_unmap_xfer(master, xfer); 1165 1166 return 0; 1167 1168 } else { 1169 /* only update length if no error */ 1170 msg->actual_length += xfer->len; 1171 } 1172 1173 if (!msg->is_dma_mapped 1174 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) 1175 atmel_spi_dma_unmap_xfer(master, xfer); 1176 1177 if (xfer->delay_usecs) 1178 udelay(xfer->delay_usecs); 1179 1180 if (xfer->cs_change) { 1181 if (list_is_last(&xfer->transfer_list, 1182 &msg->transfers)) { 1183 as->keep_cs = true; 1184 } else { 1185 as->cs_active = !as->cs_active; 1186 if (as->cs_active) 1187 cs_activate(as, msg->spi); 1188 else 1189 cs_deactivate(as, msg->spi); 1190 } 1191 } 1192 1193 return 0; 1194} 1195 1196static int atmel_spi_transfer_one_message(struct spi_master *master, 1197 struct spi_message *msg) 1198{ 1199 struct atmel_spi *as; 1200 struct spi_transfer *xfer; 1201 struct spi_device *spi = msg->spi; 1202 int ret = 0; 1203 1204 as = spi_master_get_devdata(master); 1205 1206 dev_dbg(&spi->dev, "new message %p submitted for %s\n", 1207 msg, dev_name(&spi->dev)); 1208 1209 atmel_spi_lock(as); 1210 cs_activate(as, spi); 1211 1212 as->cs_active = true; 1213 as->keep_cs = false; 1214 1215 msg->status = 0; 1216 msg->actual_length = 0; 1217 1218 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1219 ret = atmel_spi_one_transfer(master, msg, xfer); 1220 if (ret) 1221 goto msg_done; 1222 } 1223 1224 if (as->use_pdc) 1225 atmel_spi_disable_pdc_transfer(as); 1226 1227 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1228 dev_dbg(&spi->dev, 1229 " xfer %p: len %u tx %p/%pad rx %p/%pad\n", 1230 xfer, xfer->len, 1231 xfer->tx_buf, &xfer->tx_dma, 1232 xfer->rx_buf, &xfer->rx_dma); 1233 } 1234 1235msg_done: 1236 if (!as->keep_cs) 1237 cs_deactivate(as, msg->spi); 1238 1239 atmel_spi_unlock(as); 1240 1241 msg->status = as->done_status; 1242 spi_finalize_current_message(spi->master); 1243 1244 return ret; 1245} 1246 1247static void atmel_spi_cleanup(struct spi_device *spi) 1248{ 1249 struct atmel_spi_device *asd = spi->controller_state; 1250 unsigned gpio = (unsigned long) spi->controller_data; 1251 1252 if (!asd) 1253 return; 1254 1255 spi->controller_state = NULL; 1256 gpio_free(gpio); 1257 kfree(asd); 1258} 1259 1260static inline unsigned int atmel_get_version(struct atmel_spi *as) 1261{ 1262 return spi_readl(as, VERSION) & 0x00000fff; 1263} 1264 1265static void atmel_get_caps(struct atmel_spi *as) 1266{ 1267 unsigned int version; 1268 1269 version = atmel_get_version(as); 1270 dev_info(&as->pdev->dev, "version: 0x%x\n", version); 1271 1272 as->caps.is_spi2 = version > 0x121; 1273 as->caps.has_wdrbt = version >= 0x210; 1274 as->caps.has_dma_support = version >= 0x212; 1275} 1276 1277/*-------------------------------------------------------------------------*/ 1278 1279static int atmel_spi_probe(struct platform_device *pdev) 1280{ 1281 struct resource *regs; 1282 int irq; 1283 struct clk *clk; 1284 int ret; 1285 struct spi_master *master; 1286 struct atmel_spi *as; 1287 1288 /* Select default pin state */ 1289 pinctrl_pm_select_default_state(&pdev->dev); 1290 1291 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1292 if (!regs) 1293 return -ENXIO; 1294 1295 irq = platform_get_irq(pdev, 0); 1296 if (irq < 0) 1297 return irq; 1298 1299 clk = devm_clk_get(&pdev->dev, "spi_clk"); 1300 if (IS_ERR(clk)) 1301 return PTR_ERR(clk); 1302 1303 /* setup spi core then atmel-specific driver state */ 1304 ret = -ENOMEM; 1305 master = spi_alloc_master(&pdev->dev, sizeof(*as)); 1306 if (!master) 1307 goto out_free; 1308 1309 /* the spi->mode bits understood by this driver: */ 1310 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1311 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 1312 master->dev.of_node = pdev->dev.of_node; 1313 master->bus_num = pdev->id; 1314 master->num_chipselect = master->dev.of_node ? 0 : 4; 1315 master->setup = atmel_spi_setup; 1316 master->transfer_one_message = atmel_spi_transfer_one_message; 1317 master->cleanup = atmel_spi_cleanup; 1318 platform_set_drvdata(pdev, master); 1319 1320 as = spi_master_get_devdata(master); 1321 1322 /* 1323 * Scratch buffer is used for throwaway rx and tx data. 1324 * It's coherent to minimize dcache pollution. 1325 */ 1326 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, 1327 &as->buffer_dma, GFP_KERNEL); 1328 if (!as->buffer) 1329 goto out_free; 1330 1331 spin_lock_init(&as->lock); 1332 1333 as->pdev = pdev; 1334 as->regs = devm_ioremap_resource(&pdev->dev, regs); 1335 if (IS_ERR(as->regs)) { 1336 ret = PTR_ERR(as->regs); 1337 goto out_free_buffer; 1338 } 1339 as->phybase = regs->start; 1340 as->irq = irq; 1341 as->clk = clk; 1342 1343 init_completion(&as->xfer_completion); 1344 1345 atmel_get_caps(as); 1346 1347 as->use_dma = false; 1348 as->use_pdc = false; 1349 if (as->caps.has_dma_support) { 1350 if (atmel_spi_configure_dma(as) == 0) 1351 as->use_dma = true; 1352 } else { 1353 as->use_pdc = true; 1354 } 1355 1356 if (as->caps.has_dma_support && !as->use_dma) 1357 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1358 1359 if (as->use_pdc) { 1360 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, 1361 0, dev_name(&pdev->dev), master); 1362 } else { 1363 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, 1364 0, dev_name(&pdev->dev), master); 1365 } 1366 if (ret) 1367 goto out_unmap_regs; 1368 1369 /* Initialize the hardware */ 1370 ret = clk_prepare_enable(clk); 1371 if (ret) 1372 goto out_free_irq; 1373 spi_writel(as, CR, SPI_BIT(SWRST)); 1374 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1375 if (as->caps.has_wdrbt) { 1376 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1377 | SPI_BIT(MSTR)); 1378 } else { 1379 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1380 } 1381 1382 if (as->use_pdc) 1383 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1384 spi_writel(as, CR, SPI_BIT(SPIEN)); 1385 1386 /* go! */ 1387 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", 1388 (unsigned long)regs->start, irq); 1389 1390 ret = devm_spi_register_master(&pdev->dev, master); 1391 if (ret) 1392 goto out_free_dma; 1393 1394 return 0; 1395 1396out_free_dma: 1397 if (as->use_dma) 1398 atmel_spi_release_dma(as); 1399 1400 spi_writel(as, CR, SPI_BIT(SWRST)); 1401 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1402 clk_disable_unprepare(clk); 1403out_free_irq: 1404out_unmap_regs: 1405out_free_buffer: 1406 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, 1407 as->buffer_dma); 1408out_free: 1409 spi_master_put(master); 1410 return ret; 1411} 1412 1413static int atmel_spi_remove(struct platform_device *pdev) 1414{ 1415 struct spi_master *master = platform_get_drvdata(pdev); 1416 struct atmel_spi *as = spi_master_get_devdata(master); 1417 1418 /* reset the hardware and block queue progress */ 1419 spin_lock_irq(&as->lock); 1420 if (as->use_dma) { 1421 atmel_spi_stop_dma(as); 1422 atmel_spi_release_dma(as); 1423 } 1424 1425 spi_writel(as, CR, SPI_BIT(SWRST)); 1426 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1427 spi_readl(as, SR); 1428 spin_unlock_irq(&as->lock); 1429 1430 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, 1431 as->buffer_dma); 1432 1433 clk_disable_unprepare(as->clk); 1434 1435 return 0; 1436} 1437 1438#ifdef CONFIG_PM_SLEEP 1439static int atmel_spi_suspend(struct device *dev) 1440{ 1441 struct spi_master *master = dev_get_drvdata(dev); 1442 struct atmel_spi *as = spi_master_get_devdata(master); 1443 int ret; 1444 1445 /* Stop the queue running */ 1446 ret = spi_master_suspend(master); 1447 if (ret) { 1448 dev_warn(dev, "cannot suspend master\n"); 1449 return ret; 1450 } 1451 1452 clk_disable_unprepare(as->clk); 1453 1454 pinctrl_pm_select_sleep_state(dev); 1455 1456 return 0; 1457} 1458 1459static int atmel_spi_resume(struct device *dev) 1460{ 1461 struct spi_master *master = dev_get_drvdata(dev); 1462 struct atmel_spi *as = spi_master_get_devdata(master); 1463 int ret; 1464 1465 pinctrl_pm_select_default_state(dev); 1466 1467 clk_prepare_enable(as->clk); 1468 1469 /* Start the queue running */ 1470 ret = spi_master_resume(master); 1471 if (ret) 1472 dev_err(dev, "problem starting queue (%d)\n", ret); 1473 1474 return ret; 1475} 1476 1477static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume); 1478 1479#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) 1480#else 1481#define ATMEL_SPI_PM_OPS NULL 1482#endif 1483 1484#if defined(CONFIG_OF) 1485static const struct of_device_id atmel_spi_dt_ids[] = { 1486 { .compatible = "atmel,at91rm9200-spi" }, 1487 { /* sentinel */ } 1488}; 1489 1490MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); 1491#endif 1492 1493static struct platform_driver atmel_spi_driver = { 1494 .driver = { 1495 .name = "atmel_spi", 1496 .owner = THIS_MODULE, 1497 .pm = ATMEL_SPI_PM_OPS, 1498 .of_match_table = of_match_ptr(atmel_spi_dt_ids), 1499 }, 1500 .probe = atmel_spi_probe, 1501 .remove = atmel_spi_remove, 1502}; 1503module_platform_driver(atmel_spi_driver); 1504 1505MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); 1506MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1507MODULE_LICENSE("GPL"); 1508MODULE_ALIAS("platform:atmel_spi"); 1509