1/* 2 * Freescale eSPI controller driver. 3 * 4 * Copyright 2010 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11#include <linux/delay.h> 12#include <linux/err.h> 13#include <linux/fsl_devices.h> 14#include <linux/interrupt.h> 15#include <linux/irq.h> 16#include <linux/module.h> 17#include <linux/mm.h> 18#include <linux/of.h> 19#include <linux/of_address.h> 20#include <linux/of_irq.h> 21#include <linux/of_platform.h> 22#include <linux/platform_device.h> 23#include <linux/spi/spi.h> 24#include <sysdev/fsl_soc.h> 25 26#include "spi-fsl-lib.h" 27 28/* eSPI Controller registers */ 29struct fsl_espi_reg { 30 __be32 mode; /* 0x000 - eSPI mode register */ 31 __be32 event; /* 0x004 - eSPI event register */ 32 __be32 mask; /* 0x008 - eSPI mask register */ 33 __be32 command; /* 0x00c - eSPI command register */ 34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/ 35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/ 36 u8 res[8]; /* 0x018 - 0x01c reserved */ 37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */ 38}; 39 40struct fsl_espi_transfer { 41 const void *tx_buf; 42 void *rx_buf; 43 unsigned len; 44 unsigned n_tx; 45 unsigned n_rx; 46 unsigned actual_length; 47 int status; 48}; 49 50/* eSPI Controller mode register definitions */ 51#define SPMODE_ENABLE (1 << 31) 52#define SPMODE_LOOP (1 << 30) 53#define SPMODE_TXTHR(x) ((x) << 8) 54#define SPMODE_RXTHR(x) ((x) << 0) 55 56/* eSPI Controller CS mode register definitions */ 57#define CSMODE_CI_INACTIVEHIGH (1 << 31) 58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30) 59#define CSMODE_REV (1 << 29) 60#define CSMODE_DIV16 (1 << 28) 61#define CSMODE_PM(x) ((x) << 24) 62#define CSMODE_POL_1 (1 << 20) 63#define CSMODE_LEN(x) ((x) << 16) 64#define CSMODE_BEF(x) ((x) << 12) 65#define CSMODE_AFT(x) ((x) << 8) 66#define CSMODE_CG(x) ((x) << 3) 67 68/* Default mode/csmode for eSPI controller */ 69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) 70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ 71 | CSMODE_AFT(0) | CSMODE_CG(1)) 72 73/* SPIE register values */ 74#define SPIE_NE 0x00000200 /* Not empty */ 75#define SPIE_NF 0x00000100 /* Not full */ 76 77/* SPIM register values */ 78#define SPIM_NE 0x00000200 /* Not empty */ 79#define SPIM_NF 0x00000100 /* Not full */ 80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) 81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) 82 83/* SPCOM register values */ 84#define SPCOM_CS(x) ((x) << 30) 85#define SPCOM_TRANLEN(x) ((x) << 0) 86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */ 87 88static void fsl_espi_change_mode(struct spi_device *spi) 89{ 90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 91 struct spi_mpc8xxx_cs *cs = spi->controller_state; 92 struct fsl_espi_reg *reg_base = mspi->reg_base; 93 __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; 94 __be32 __iomem *espi_mode = ®_base->mode; 95 u32 tmp; 96 unsigned long flags; 97 98 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 99 local_irq_save(flags); 100 101 /* Turn off SPI unit prior changing mode */ 102 tmp = mpc8xxx_spi_read_reg(espi_mode); 103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE); 104 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 105 mpc8xxx_spi_write_reg(espi_mode, tmp); 106 107 local_irq_restore(flags); 108} 109 110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) 111{ 112 u32 data; 113 u16 data_h; 114 u16 data_l; 115 const u32 *tx = mpc8xxx_spi->tx; 116 117 if (!tx) 118 return 0; 119 120 data = *tx++ << mpc8xxx_spi->tx_shift; 121 data_l = data & 0xffff; 122 data_h = (data >> 16) & 0xffff; 123 swab16s(&data_l); 124 swab16s(&data_h); 125 data = data_h | data_l; 126 127 mpc8xxx_spi->tx = tx; 128 return data; 129} 130 131static int fsl_espi_setup_transfer(struct spi_device *spi, 132 struct spi_transfer *t) 133{ 134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 135 int bits_per_word = 0; 136 u8 pm; 137 u32 hz = 0; 138 struct spi_mpc8xxx_cs *cs = spi->controller_state; 139 140 if (t) { 141 bits_per_word = t->bits_per_word; 142 hz = t->speed_hz; 143 } 144 145 /* spi_transfer level calls that work per-word */ 146 if (!bits_per_word) 147 bits_per_word = spi->bits_per_word; 148 149 if (!hz) 150 hz = spi->max_speed_hz; 151 152 cs->rx_shift = 0; 153 cs->tx_shift = 0; 154 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 155 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 156 if (bits_per_word <= 8) { 157 cs->rx_shift = 8 - bits_per_word; 158 } else { 159 cs->rx_shift = 16 - bits_per_word; 160 if (spi->mode & SPI_LSB_FIRST) 161 cs->get_tx = fsl_espi_tx_buf_lsb; 162 } 163 164 mpc8xxx_spi->rx_shift = cs->rx_shift; 165 mpc8xxx_spi->tx_shift = cs->tx_shift; 166 mpc8xxx_spi->get_rx = cs->get_rx; 167 mpc8xxx_spi->get_tx = cs->get_tx; 168 169 bits_per_word = bits_per_word - 1; 170 171 /* mask out bits we are going to set */ 172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); 173 174 cs->hw_mode |= CSMODE_LEN(bits_per_word); 175 176 if ((mpc8xxx_spi->spibrg / hz) > 64) { 177 cs->hw_mode |= CSMODE_DIV16; 178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); 179 180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " 181 "Will use %d Hz instead.\n", dev_name(&spi->dev), 182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); 183 if (pm > 33) 184 pm = 33; 185 } else { 186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); 187 } 188 if (pm) 189 pm--; 190 if (pm < 2) 191 pm = 2; 192 193 cs->hw_mode |= CSMODE_PM(pm); 194 195 fsl_espi_change_mode(spi); 196 return 0; 197} 198 199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t, 200 unsigned int len) 201{ 202 u32 word; 203 struct fsl_espi_reg *reg_base = mspi->reg_base; 204 205 mspi->count = len; 206 207 /* enable rx ints */ 208 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 209 210 /* transmit word */ 211 word = mspi->get_tx(mspi); 212 mpc8xxx_spi_write_reg(®_base->transmit, word); 213 214 return 0; 215} 216 217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) 218{ 219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; 221 unsigned int len = t->len; 222 int ret; 223 224 mpc8xxx_spi->len = t->len; 225 len = roundup(len, 4) / 4; 226 227 mpc8xxx_spi->tx = t->tx_buf; 228 mpc8xxx_spi->rx = t->rx_buf; 229 230 reinit_completion(&mpc8xxx_spi->done); 231 232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ 233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) { 234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)" 235 " beyond the SPCOM[TRANLEN] field\n", t->len); 236 return -EINVAL; 237 } 238 mpc8xxx_spi_write_reg(®_base->command, 239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); 240 241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len); 242 if (ret) 243 return ret; 244 245 wait_for_completion(&mpc8xxx_spi->done); 246 247 /* disable rx ints */ 248 mpc8xxx_spi_write_reg(®_base->mask, 0); 249 250 return mpc8xxx_spi->count; 251} 252 253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd) 254{ 255 if (cmd) { 256 cmd[1] = (u8)(addr >> 16); 257 cmd[2] = (u8)(addr >> 8); 258 cmd[3] = (u8)(addr >> 0); 259 } 260} 261 262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd) 263{ 264 if (cmd) 265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0; 266 267 return 0; 268} 269 270static void fsl_espi_do_trans(struct spi_message *m, 271 struct fsl_espi_transfer *tr) 272{ 273 struct spi_device *spi = m->spi; 274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 275 struct fsl_espi_transfer *espi_trans = tr; 276 struct spi_message message; 277 struct spi_transfer *t, *first, trans; 278 int status = 0; 279 280 spi_message_init(&message); 281 memset(&trans, 0, sizeof(trans)); 282 283 first = list_first_entry(&m->transfers, struct spi_transfer, 284 transfer_list); 285 list_for_each_entry(t, &m->transfers, transfer_list) { 286 if ((first->bits_per_word != t->bits_per_word) || 287 (first->speed_hz != t->speed_hz)) { 288 espi_trans->status = -EINVAL; 289 dev_err(mspi->dev, 290 "bits_per_word/speed_hz should be same for the same SPI transfer\n"); 291 return; 292 } 293 294 trans.speed_hz = t->speed_hz; 295 trans.bits_per_word = t->bits_per_word; 296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs); 297 } 298 299 trans.len = espi_trans->len; 300 trans.tx_buf = espi_trans->tx_buf; 301 trans.rx_buf = espi_trans->rx_buf; 302 spi_message_add_tail(&trans, &message); 303 304 list_for_each_entry(t, &message.transfers, transfer_list) { 305 if (t->bits_per_word || t->speed_hz) { 306 status = -EINVAL; 307 308 status = fsl_espi_setup_transfer(spi, t); 309 if (status < 0) 310 break; 311 } 312 313 if (t->len) 314 status = fsl_espi_bufs(spi, t); 315 316 if (status) { 317 status = -EMSGSIZE; 318 break; 319 } 320 321 if (t->delay_usecs) 322 udelay(t->delay_usecs); 323 } 324 325 espi_trans->status = status; 326 fsl_espi_setup_transfer(spi, NULL); 327} 328 329static void fsl_espi_cmd_trans(struct spi_message *m, 330 struct fsl_espi_transfer *trans, u8 *rx_buff) 331{ 332 struct spi_transfer *t; 333 u8 *local_buf; 334 int i = 0; 335 struct fsl_espi_transfer *espi_trans = trans; 336 337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 338 if (!local_buf) { 339 espi_trans->status = -ENOMEM; 340 return; 341 } 342 343 list_for_each_entry(t, &m->transfers, transfer_list) { 344 if (t->tx_buf) { 345 memcpy(local_buf + i, t->tx_buf, t->len); 346 i += t->len; 347 } 348 } 349 350 espi_trans->tx_buf = local_buf; 351 espi_trans->rx_buf = local_buf; 352 fsl_espi_do_trans(m, espi_trans); 353 354 espi_trans->actual_length = espi_trans->len; 355 kfree(local_buf); 356} 357 358static void fsl_espi_rw_trans(struct spi_message *m, 359 struct fsl_espi_transfer *trans, u8 *rx_buff) 360{ 361 struct fsl_espi_transfer *espi_trans = trans; 362 unsigned int n_tx = espi_trans->n_tx; 363 unsigned int n_rx = espi_trans->n_rx; 364 struct spi_transfer *t; 365 u8 *local_buf; 366 u8 *rx_buf = rx_buff; 367 unsigned int trans_len; 368 unsigned int addr; 369 int i, pos, loop; 370 371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 372 if (!local_buf) { 373 espi_trans->status = -ENOMEM; 374 return; 375 } 376 377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) { 378 trans_len = n_rx - pos; 379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx) 380 trans_len = SPCOM_TRANLEN_MAX - n_tx; 381 382 i = 0; 383 list_for_each_entry(t, &m->transfers, transfer_list) { 384 if (t->tx_buf) { 385 memcpy(local_buf + i, t->tx_buf, t->len); 386 i += t->len; 387 } 388 } 389 390 if (pos > 0) { 391 addr = fsl_espi_cmd2addr(local_buf); 392 addr += pos; 393 fsl_espi_addr2cmd(addr, local_buf); 394 } 395 396 espi_trans->n_tx = n_tx; 397 espi_trans->n_rx = trans_len; 398 espi_trans->len = trans_len + n_tx; 399 espi_trans->tx_buf = local_buf; 400 espi_trans->rx_buf = local_buf; 401 fsl_espi_do_trans(m, espi_trans); 402 403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len); 404 405 if (loop > 0) 406 espi_trans->actual_length += espi_trans->len - n_tx; 407 else 408 espi_trans->actual_length += espi_trans->len; 409 } 410 411 kfree(local_buf); 412} 413 414static void fsl_espi_do_one_msg(struct spi_message *m) 415{ 416 struct spi_transfer *t; 417 u8 *rx_buf = NULL; 418 unsigned int n_tx = 0; 419 unsigned int n_rx = 0; 420 struct fsl_espi_transfer espi_trans; 421 422 list_for_each_entry(t, &m->transfers, transfer_list) { 423 if (t->tx_buf) 424 n_tx += t->len; 425 if (t->rx_buf) { 426 n_rx += t->len; 427 rx_buf = t->rx_buf; 428 } 429 } 430 431 espi_trans.n_tx = n_tx; 432 espi_trans.n_rx = n_rx; 433 espi_trans.len = n_tx + n_rx; 434 espi_trans.actual_length = 0; 435 espi_trans.status = 0; 436 437 if (!rx_buf) 438 fsl_espi_cmd_trans(m, &espi_trans, NULL); 439 else 440 fsl_espi_rw_trans(m, &espi_trans, rx_buf); 441 442 m->actual_length = espi_trans.actual_length; 443 m->status = espi_trans.status; 444 if (m->complete) 445 m->complete(m->context); 446} 447 448static int fsl_espi_setup(struct spi_device *spi) 449{ 450 struct mpc8xxx_spi *mpc8xxx_spi; 451 struct fsl_espi_reg *reg_base; 452 int retval; 453 u32 hw_mode; 454 u32 loop_mode; 455 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 456 457 if (!spi->max_speed_hz) 458 return -EINVAL; 459 460 if (!cs) { 461 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 462 if (!cs) 463 return -ENOMEM; 464 spi_set_ctldata(spi, cs); 465 } 466 467 mpc8xxx_spi = spi_master_get_devdata(spi->master); 468 reg_base = mpc8xxx_spi->reg_base; 469 470 hw_mode = cs->hw_mode; /* Save original settings */ 471 cs->hw_mode = mpc8xxx_spi_read_reg( 472 ®_base->csmode[spi->chip_select]); 473 /* mask out bits we are going to set */ 474 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH 475 | CSMODE_REV); 476 477 if (spi->mode & SPI_CPHA) 478 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; 479 if (spi->mode & SPI_CPOL) 480 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; 481 if (!(spi->mode & SPI_LSB_FIRST)) 482 cs->hw_mode |= CSMODE_REV; 483 484 /* Handle the loop mode */ 485 loop_mode = mpc8xxx_spi_read_reg(®_base->mode); 486 loop_mode &= ~SPMODE_LOOP; 487 if (spi->mode & SPI_LOOP) 488 loop_mode |= SPMODE_LOOP; 489 mpc8xxx_spi_write_reg(®_base->mode, loop_mode); 490 491 retval = fsl_espi_setup_transfer(spi, NULL); 492 if (retval < 0) { 493 cs->hw_mode = hw_mode; /* Restore settings */ 494 return retval; 495 } 496 return 0; 497} 498 499static void fsl_espi_cleanup(struct spi_device *spi) 500{ 501 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 502 503 kfree(cs); 504 spi_set_ctldata(spi, NULL); 505} 506 507void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 508{ 509 struct fsl_espi_reg *reg_base = mspi->reg_base; 510 511 /* We need handle RX first */ 512 if (events & SPIE_NE) { 513 u32 rx_data, tmp; 514 u8 rx_data_8; 515 516 /* Spin until RX is done */ 517 while (SPIE_RXCNT(events) < min(4, mspi->len)) { 518 cpu_relax(); 519 events = mpc8xxx_spi_read_reg(®_base->event); 520 } 521 522 if (mspi->len >= 4) { 523 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 524 } else { 525 tmp = mspi->len; 526 rx_data = 0; 527 while (tmp--) { 528 rx_data_8 = in_8((u8 *)®_base->receive); 529 rx_data |= (rx_data_8 << (tmp * 8)); 530 } 531 532 rx_data <<= (4 - mspi->len) * 8; 533 } 534 535 mspi->len -= 4; 536 537 if (mspi->rx) 538 mspi->get_rx(rx_data, mspi); 539 } 540 541 if (!(events & SPIE_NF)) { 542 int ret; 543 544 /* spin until TX is done */ 545 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg( 546 ®_base->event)) & SPIE_NF) == 0, 1000, 0); 547 if (!ret) { 548 dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); 549 return; 550 } 551 } 552 553 /* Clear the events */ 554 mpc8xxx_spi_write_reg(®_base->event, events); 555 556 mspi->count -= 1; 557 if (mspi->count) { 558 u32 word = mspi->get_tx(mspi); 559 560 mpc8xxx_spi_write_reg(®_base->transmit, word); 561 } else { 562 complete(&mspi->done); 563 } 564} 565 566static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) 567{ 568 struct mpc8xxx_spi *mspi = context_data; 569 struct fsl_espi_reg *reg_base = mspi->reg_base; 570 irqreturn_t ret = IRQ_NONE; 571 u32 events; 572 573 /* Get interrupt events(tx/rx) */ 574 events = mpc8xxx_spi_read_reg(®_base->event); 575 if (events) 576 ret = IRQ_HANDLED; 577 578 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); 579 580 fsl_espi_cpu_irq(mspi, events); 581 582 return ret; 583} 584 585static void fsl_espi_remove(struct mpc8xxx_spi *mspi) 586{ 587 iounmap(mspi->reg_base); 588} 589 590static struct spi_master * fsl_espi_probe(struct device *dev, 591 struct resource *mem, unsigned int irq) 592{ 593 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 594 struct spi_master *master; 595 struct mpc8xxx_spi *mpc8xxx_spi; 596 struct fsl_espi_reg *reg_base; 597 struct device_node *nc; 598 const __be32 *prop; 599 u32 regval, csmode; 600 int i, len, ret = 0; 601 602 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 603 if (!master) { 604 ret = -ENOMEM; 605 goto err; 606 } 607 608 dev_set_drvdata(dev, master); 609 610 ret = mpc8xxx_spi_probe(dev, mem, irq); 611 if (ret) 612 goto err_probe; 613 614 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 615 master->setup = fsl_espi_setup; 616 master->cleanup = fsl_espi_cleanup; 617 618 mpc8xxx_spi = spi_master_get_devdata(master); 619 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg; 620 mpc8xxx_spi->spi_remove = fsl_espi_remove; 621 622 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 623 if (!mpc8xxx_spi->reg_base) { 624 ret = -ENOMEM; 625 goto err_probe; 626 } 627 628 reg_base = mpc8xxx_spi->reg_base; 629 630 /* Register for SPI Interrupt */ 631 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq, 632 0, "fsl_espi", mpc8xxx_spi); 633 if (ret) 634 goto free_irq; 635 636 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { 637 mpc8xxx_spi->rx_shift = 16; 638 mpc8xxx_spi->tx_shift = 24; 639 } 640 641 /* SPI controller initializations */ 642 mpc8xxx_spi_write_reg(®_base->mode, 0); 643 mpc8xxx_spi_write_reg(®_base->mask, 0); 644 mpc8xxx_spi_write_reg(®_base->command, 0); 645 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 646 647 /* Init eSPI CS mode register */ 648 for_each_available_child_of_node(master->dev.of_node, nc) { 649 /* get chip select */ 650 prop = of_get_property(nc, "reg", &len); 651 if (!prop || len < sizeof(*prop)) 652 continue; 653 i = be32_to_cpup(prop); 654 if (i < 0 || i >= pdata->max_chipselect) 655 continue; 656 657 csmode = CSMODE_INIT_VAL; 658 /* check if CSBEF is set in device tree */ 659 prop = of_get_property(nc, "fsl,csbef", &len); 660 if (prop && len >= sizeof(*prop)) { 661 csmode &= ~(CSMODE_BEF(0xf)); 662 csmode |= CSMODE_BEF(be32_to_cpup(prop)); 663 } 664 /* check if CSAFT is set in device tree */ 665 prop = of_get_property(nc, "fsl,csaft", &len); 666 if (prop && len >= sizeof(*prop)) { 667 csmode &= ~(CSMODE_AFT(0xf)); 668 csmode |= CSMODE_AFT(be32_to_cpup(prop)); 669 } 670 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode); 671 672 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); 673 } 674 675 /* Enable SPI interface */ 676 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 677 678 mpc8xxx_spi_write_reg(®_base->mode, regval); 679 680 ret = spi_register_master(master); 681 if (ret < 0) 682 goto unreg_master; 683 684 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq); 685 686 return master; 687 688unreg_master: 689 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 690free_irq: 691 iounmap(mpc8xxx_spi->reg_base); 692err_probe: 693 spi_master_put(master); 694err: 695 return ERR_PTR(ret); 696} 697 698static int of_fsl_espi_get_chipselects(struct device *dev) 699{ 700 struct device_node *np = dev->of_node; 701 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 702 const u32 *prop; 703 int len; 704 705 prop = of_get_property(np, "fsl,espi-num-chipselects", &len); 706 if (!prop || len < sizeof(*prop)) { 707 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); 708 return -EINVAL; 709 } 710 711 pdata->max_chipselect = *prop; 712 pdata->cs_control = NULL; 713 714 return 0; 715} 716 717static int of_fsl_espi_probe(struct platform_device *ofdev) 718{ 719 struct device *dev = &ofdev->dev; 720 struct device_node *np = ofdev->dev.of_node; 721 struct spi_master *master; 722 struct resource mem; 723 unsigned int irq; 724 int ret = -ENOMEM; 725 726 ret = of_mpc8xxx_spi_probe(ofdev); 727 if (ret) 728 return ret; 729 730 ret = of_fsl_espi_get_chipselects(dev); 731 if (ret) 732 goto err; 733 734 ret = of_address_to_resource(np, 0, &mem); 735 if (ret) 736 goto err; 737 738 irq = irq_of_parse_and_map(np, 0); 739 if (!irq) { 740 ret = -EINVAL; 741 goto err; 742 } 743 744 master = fsl_espi_probe(dev, &mem, irq); 745 if (IS_ERR(master)) { 746 ret = PTR_ERR(master); 747 goto err; 748 } 749 750 return 0; 751 752err: 753 return ret; 754} 755 756static int of_fsl_espi_remove(struct platform_device *dev) 757{ 758 return mpc8xxx_spi_remove(&dev->dev); 759} 760 761#ifdef CONFIG_PM_SLEEP 762static int of_fsl_espi_suspend(struct device *dev) 763{ 764 struct spi_master *master = dev_get_drvdata(dev); 765 struct mpc8xxx_spi *mpc8xxx_spi; 766 struct fsl_espi_reg *reg_base; 767 u32 regval; 768 int ret; 769 770 mpc8xxx_spi = spi_master_get_devdata(master); 771 reg_base = mpc8xxx_spi->reg_base; 772 773 ret = spi_master_suspend(master); 774 if (ret) { 775 dev_warn(dev, "cannot suspend master\n"); 776 return ret; 777 } 778 779 regval = mpc8xxx_spi_read_reg(®_base->mode); 780 regval &= ~SPMODE_ENABLE; 781 mpc8xxx_spi_write_reg(®_base->mode, regval); 782 783 return 0; 784} 785 786static int of_fsl_espi_resume(struct device *dev) 787{ 788 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 789 struct spi_master *master = dev_get_drvdata(dev); 790 struct mpc8xxx_spi *mpc8xxx_spi; 791 struct fsl_espi_reg *reg_base; 792 u32 regval; 793 int i; 794 795 mpc8xxx_spi = spi_master_get_devdata(master); 796 reg_base = mpc8xxx_spi->reg_base; 797 798 /* SPI controller initializations */ 799 mpc8xxx_spi_write_reg(®_base->mode, 0); 800 mpc8xxx_spi_write_reg(®_base->mask, 0); 801 mpc8xxx_spi_write_reg(®_base->command, 0); 802 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 803 804 /* Init eSPI CS mode register */ 805 for (i = 0; i < pdata->max_chipselect; i++) 806 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL); 807 808 /* Enable SPI interface */ 809 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 810 811 mpc8xxx_spi_write_reg(®_base->mode, regval); 812 813 return spi_master_resume(master); 814} 815#endif /* CONFIG_PM_SLEEP */ 816 817static const struct dev_pm_ops espi_pm = { 818 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) 819}; 820 821static const struct of_device_id of_fsl_espi_match[] = { 822 { .compatible = "fsl,mpc8536-espi" }, 823 {} 824}; 825MODULE_DEVICE_TABLE(of, of_fsl_espi_match); 826 827static struct platform_driver fsl_espi_driver = { 828 .driver = { 829 .name = "fsl_espi", 830 .owner = THIS_MODULE, 831 .of_match_table = of_fsl_espi_match, 832 .pm = &espi_pm, 833 }, 834 .probe = of_fsl_espi_probe, 835 .remove = of_fsl_espi_remove, 836}; 837module_platform_driver(fsl_espi_driver); 838 839MODULE_AUTHOR("Mingkai Hu"); 840MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); 841MODULE_LICENSE("GPL"); 842