ad7280a.c revision c8a9f8056f40f6201b84fdddb49a1c62630902c5
1/* 2 * AD7280A Lithium Ion Battery Monitoring System 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/device.h> 10#include <linux/kernel.h> 11#include <linux/slab.h> 12#include <linux/sysfs.h> 13#include <linux/spi/spi.h> 14#include <linux/err.h> 15#include <linux/delay.h> 16#include <linux/interrupt.h> 17#include <linux/module.h> 18 19#include "../iio.h" 20#include "../sysfs.h" 21#include "../events.h" 22 23#include "ad7280a.h" 24 25/* Registers */ 26#define AD7280A_CELL_VOLTAGE_1 0x0 /* D11 to D0, Read only */ 27#define AD7280A_CELL_VOLTAGE_2 0x1 /* D11 to D0, Read only */ 28#define AD7280A_CELL_VOLTAGE_3 0x2 /* D11 to D0, Read only */ 29#define AD7280A_CELL_VOLTAGE_4 0x3 /* D11 to D0, Read only */ 30#define AD7280A_CELL_VOLTAGE_5 0x4 /* D11 to D0, Read only */ 31#define AD7280A_CELL_VOLTAGE_6 0x5 /* D11 to D0, Read only */ 32#define AD7280A_AUX_ADC_1 0x6 /* D11 to D0, Read only */ 33#define AD7280A_AUX_ADC_2 0x7 /* D11 to D0, Read only */ 34#define AD7280A_AUX_ADC_3 0x8 /* D11 to D0, Read only */ 35#define AD7280A_AUX_ADC_4 0x9 /* D11 to D0, Read only */ 36#define AD7280A_AUX_ADC_5 0xA /* D11 to D0, Read only */ 37#define AD7280A_AUX_ADC_6 0xB /* D11 to D0, Read only */ 38#define AD7280A_SELF_TEST 0xC /* D11 to D0, Read only */ 39#define AD7280A_CONTROL_HB 0xD /* D15 to D8, Read/write */ 40#define AD7280A_CONTROL_LB 0xE /* D7 to D0, Read/write */ 41#define AD7280A_CELL_OVERVOLTAGE 0xF /* D7 to D0, Read/write */ 42#define AD7280A_CELL_UNDERVOLTAGE 0x10 /* D7 to D0, Read/write */ 43#define AD7280A_AUX_ADC_OVERVOLTAGE 0x11 /* D7 to D0, Read/write */ 44#define AD7280A_AUX_ADC_UNDERVOLTAGE 0x12 /* D7 to D0, Read/write */ 45#define AD7280A_ALERT 0x13 /* D7 to D0, Read/write */ 46#define AD7280A_CELL_BALANCE 0x14 /* D7 to D0, Read/write */ 47#define AD7280A_CB1_TIMER 0x15 /* D7 to D0, Read/write */ 48#define AD7280A_CB2_TIMER 0x16 /* D7 to D0, Read/write */ 49#define AD7280A_CB3_TIMER 0x17 /* D7 to D0, Read/write */ 50#define AD7280A_CB4_TIMER 0x18 /* D7 to D0, Read/write */ 51#define AD7280A_CB5_TIMER 0x19 /* D7 to D0, Read/write */ 52#define AD7280A_CB6_TIMER 0x1A /* D7 to D0, Read/write */ 53#define AD7280A_PD_TIMER 0x1B /* D7 to D0, Read/write */ 54#define AD7280A_READ 0x1C /* D7 to D0, Read/write */ 55#define AD7280A_CNVST_CONTROL 0x1D /* D7 to D0, Read/write */ 56 57/* Bits and Masks */ 58#define AD7280A_CTRL_HB_CONV_INPUT_ALL (0 << 6) 59#define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 (1 << 6) 60#define AD7280A_CTRL_HB_CONV_INPUT_6CELL (2 << 6) 61#define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (3 << 6) 62#define AD7280A_CTRL_HB_CONV_RES_READ_ALL (0 << 4) 63#define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 (1 << 4) 64#define AD7280A_CTRL_HB_CONV_RES_READ_6CELL (2 << 4) 65#define AD7280A_CTRL_HB_CONV_RES_READ_NO (3 << 4) 66#define AD7280A_CTRL_HB_CONV_START_CNVST (0 << 3) 67#define AD7280A_CTRL_HB_CONV_START_CS (1 << 3) 68#define AD7280A_CTRL_HB_CONV_AVG_DIS (0 << 1) 69#define AD7280A_CTRL_HB_CONV_AVG_2 (1 << 1) 70#define AD7280A_CTRL_HB_CONV_AVG_4 (2 << 1) 71#define AD7280A_CTRL_HB_CONV_AVG_8 (3 << 1) 72#define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1) 73#define AD7280A_CTRL_HB_PWRDN_SW (1 << 0) 74 75#define AD7280A_CTRL_LB_SWRST (1 << 7) 76#define AD7280A_CTRL_LB_ACQ_TIME_400ns (0 << 5) 77#define AD7280A_CTRL_LB_ACQ_TIME_800ns (1 << 5) 78#define AD7280A_CTRL_LB_ACQ_TIME_1200ns (2 << 5) 79#define AD7280A_CTRL_LB_ACQ_TIME_1600ns (3 << 5) 80#define AD7280A_CTRL_LB_ACQ_TIME(x) ((x) << 5) 81#define AD7280A_CTRL_LB_MUST_SET (1 << 4) 82#define AD7280A_CTRL_LB_THERMISTOR_EN (1 << 3) 83#define AD7280A_CTRL_LB_LOCK_DEV_ADDR (1 << 2) 84#define AD7280A_CTRL_LB_INC_DEV_ADDR (1 << 1) 85#define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN (1 << 0) 86 87#define AD7280A_ALERT_GEN_STATIC_HIGH (1 << 6) 88#define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (3 << 6) 89 90#define AD7280A_ALL_CELLS (0xAD << 16) 91 92#define AD7280A_MAX_SPI_CLK_Hz 700000 /* < 1MHz */ 93#define AD7280A_MAX_CHAIN 8 94#define AD7280A_CELLS_PER_DEV 6 95#define AD7280A_BITS 12 96#define AD7280A_NUM_CH (AD7280A_AUX_ADC_6 - \ 97 AD7280A_CELL_VOLTAGE_1 + 1) 98 99#define AD7280A_DEVADDR_MASTER 0 100#define AD7280A_DEVADDR_ALL 0x1F 101/* 5-bit device address is sent LSB first */ 102#define AD7280A_DEVADDR(addr) (((addr & 0x1) << 4) | ((addr & 0x2) << 3) | \ 103 (addr & 0x4) | ((addr & 0x8) >> 3) | \ 104 ((addr & 0x10) >> 4)) 105 106/* During a read a valid write is mandatory. 107 * So writing to the highest available address (Address 0x1F) 108 * and setting the address all parts bit to 0 is recommended 109 * So the TXVAL is AD7280A_DEVADDR_ALL + CRC 110 */ 111#define AD7280A_READ_TXVAL 0xF800030A 112 113/* 114 * AD7280 CRC 115 * 116 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F 117 */ 118#define POLYNOM 0x2F 119#define POLYNOM_ORDER 8 120#define HIGHBIT 1 << (POLYNOM_ORDER - 1); 121 122struct ad7280_state { 123 struct spi_device *spi; 124 struct iio_chan_spec *channels; 125 struct iio_dev_attr *iio_attr; 126 int slave_num; 127 int scan_cnt; 128 int readback_delay_us; 129 unsigned char crc_tab[256]; 130 unsigned char ctrl_hb; 131 unsigned char ctrl_lb; 132 unsigned char cell_threshhigh; 133 unsigned char cell_threshlow; 134 unsigned char aux_threshhigh; 135 unsigned char aux_threshlow; 136 unsigned char cb_mask[AD7280A_MAX_CHAIN]; 137}; 138 139static void ad7280_crc8_build_table(unsigned char *crc_tab) 140{ 141 unsigned char bit, crc; 142 int cnt, i; 143 144 for (cnt = 0; cnt < 256; cnt++) { 145 crc = cnt; 146 for (i = 0; i < 8; i++) { 147 bit = crc & HIGHBIT; 148 crc <<= 1; 149 if (bit) 150 crc ^= POLYNOM; 151 } 152 crc_tab[cnt] = crc; 153 } 154} 155 156static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned val) 157{ 158 unsigned char crc; 159 160 crc = crc_tab[val >> 16 & 0xFF]; 161 crc = crc_tab[crc ^ (val >> 8 & 0xFF)]; 162 163 return crc ^ (val & 0xFF); 164} 165 166static int ad7280_check_crc(struct ad7280_state *st, unsigned val) 167{ 168 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10); 169 170 if (crc != ((val >> 2) & 0xFF)) 171 return -EIO; 172 173 return 0; 174} 175 176/* After initiating a conversion sequence we need to wait until the 177 * conversion is done. The delay is typically in the range of 15..30 us 178 * however depending an the number of devices in the daisy chain and the 179 * number of averages taken, conversion delays and acquisition time options 180 * it may take up to 250us, in this case we better sleep instead of busy 181 * wait. 182 */ 183 184static void ad7280_delay(struct ad7280_state *st) 185{ 186 if (st->readback_delay_us < 50) 187 udelay(st->readback_delay_us); 188 else 189 msleep(1); 190} 191 192static int __ad7280_read32(struct spi_device *spi, unsigned *val) 193{ 194 unsigned rx_buf, tx_buf = cpu_to_be32(AD7280A_READ_TXVAL); 195 int ret; 196 197 struct spi_transfer t = { 198 .tx_buf = &tx_buf, 199 .rx_buf = &rx_buf, 200 .len = 4, 201 }; 202 struct spi_message m; 203 204 spi_message_init(&m); 205 spi_message_add_tail(&t, &m); 206 207 ret = spi_sync(spi, &m); 208 if (ret) 209 return ret; 210 211 *val = be32_to_cpu(rx_buf); 212 213 return 0; 214} 215 216static int ad7280_write(struct ad7280_state *st, unsigned devaddr, 217 unsigned addr, bool all, unsigned val) 218{ 219 unsigned reg = (devaddr << 27 | addr << 21 | 220 (val & 0xFF) << 13 | all << 12); 221 222 reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2; 223 reg = cpu_to_be32(reg); 224 225 return spi_write(st->spi, ®, 4); 226} 227 228static int ad7280_read(struct ad7280_state *st, unsigned devaddr, 229 unsigned addr) 230{ 231 int ret; 232 unsigned tmp; 233 234 /* turns off the read operation on all parts */ 235 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 236 AD7280A_CTRL_HB_CONV_INPUT_ALL | 237 AD7280A_CTRL_HB_CONV_RES_READ_NO | 238 st->ctrl_hb); 239 if (ret) 240 return ret; 241 242 /* turns on the read operation on the addressed part */ 243 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0, 244 AD7280A_CTRL_HB_CONV_INPUT_ALL | 245 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 246 st->ctrl_hb); 247 if (ret) 248 return ret; 249 250 /* Set register address on the part to be read from */ 251 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2); 252 if (ret) 253 return ret; 254 255 __ad7280_read32(st->spi, &tmp); 256 257 if (ad7280_check_crc(st, tmp)) 258 return -EIO; 259 260 if (((tmp >> 27) != devaddr) || (((tmp >> 21) & 0x3F) != addr)) 261 return -EFAULT; 262 263 return (tmp >> 13) & 0xFF; 264} 265 266static int ad7280_read_channel(struct ad7280_state *st, unsigned devaddr, 267 unsigned addr) 268{ 269 int ret; 270 unsigned tmp; 271 272 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2); 273 if (ret) 274 return ret; 275 276 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 277 AD7280A_CTRL_HB_CONV_INPUT_ALL | 278 AD7280A_CTRL_HB_CONV_RES_READ_NO | 279 st->ctrl_hb); 280 if (ret) 281 return ret; 282 283 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0, 284 AD7280A_CTRL_HB_CONV_INPUT_ALL | 285 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 286 AD7280A_CTRL_HB_CONV_START_CS | 287 st->ctrl_hb); 288 if (ret) 289 return ret; 290 291 ad7280_delay(st); 292 293 __ad7280_read32(st->spi, &tmp); 294 295 if (ad7280_check_crc(st, tmp)) 296 return -EIO; 297 298 if (((tmp >> 27) != devaddr) || (((tmp >> 23) & 0xF) != addr)) 299 return -EFAULT; 300 301 return (tmp >> 11) & 0xFFF; 302} 303 304static int ad7280_read_all_channels(struct ad7280_state *st, unsigned cnt, 305 unsigned *array) 306{ 307 int i, ret; 308 unsigned tmp, sum = 0; 309 310 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1, 311 AD7280A_CELL_VOLTAGE_1 << 2); 312 if (ret) 313 return ret; 314 315 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 316 AD7280A_CTRL_HB_CONV_INPUT_ALL | 317 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 318 AD7280A_CTRL_HB_CONV_START_CS | 319 st->ctrl_hb); 320 if (ret) 321 return ret; 322 323 ad7280_delay(st); 324 325 for (i = 0; i < cnt; i++) { 326 __ad7280_read32(st->spi, &tmp); 327 328 if (ad7280_check_crc(st, tmp)) 329 return -EIO; 330 331 if (array) 332 array[i] = tmp; 333 /* only sum cell voltages */ 334 if (((tmp >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) 335 sum += ((tmp >> 11) & 0xFFF); 336 } 337 338 return sum; 339} 340 341static int ad7280_chain_setup(struct ad7280_state *st) 342{ 343 unsigned val, n; 344 int ret; 345 346 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1, 347 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN | 348 AD7280A_CTRL_LB_LOCK_DEV_ADDR | 349 AD7280A_CTRL_LB_MUST_SET | 350 AD7280A_CTRL_LB_SWRST | 351 st->ctrl_lb); 352 if (ret) 353 return ret; 354 355 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1, 356 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN | 357 AD7280A_CTRL_LB_LOCK_DEV_ADDR | 358 AD7280A_CTRL_LB_MUST_SET | 359 st->ctrl_lb); 360 if (ret) 361 return ret; 362 363 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1, 364 AD7280A_CONTROL_LB << 2); 365 if (ret) 366 return ret; 367 368 for (n = 0; n <= AD7280A_MAX_CHAIN; n++) { 369 __ad7280_read32(st->spi, &val); 370 if (val == 0) 371 return n - 1; 372 373 if (ad7280_check_crc(st, val)) 374 return -EIO; 375 376 if (n != AD7280A_DEVADDR(val >> 27)) 377 return -EIO; 378 } 379 380 return -EFAULT; 381} 382 383static ssize_t ad7280_show_balance_sw(struct device *dev, 384 struct device_attribute *attr, 385 char *buf) 386{ 387 struct iio_dev *indio_dev = dev_get_drvdata(dev); 388 struct ad7280_state *st = iio_priv(indio_dev); 389 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 390 391 return sprintf(buf, "%d\n", 392 !!(st->cb_mask[this_attr->address >> 8] & 393 (1 << ((this_attr->address & 0xFF) + 2)))); 394} 395 396static ssize_t ad7280_store_balance_sw(struct device *dev, 397 struct device_attribute *attr, 398 const char *buf, 399 size_t len) 400{ 401 struct iio_dev *indio_dev = dev_get_drvdata(dev); 402 struct ad7280_state *st = iio_priv(indio_dev); 403 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 404 bool readin; 405 int ret; 406 unsigned devaddr, ch; 407 408 ret = strtobool(buf, &readin); 409 if (ret) 410 return ret; 411 412 devaddr = this_attr->address >> 8; 413 ch = this_attr->address & 0xFF; 414 415 mutex_lock(&indio_dev->mlock); 416 if (readin) 417 st->cb_mask[devaddr] |= 1 << (ch + 2); 418 else 419 st->cb_mask[devaddr] &= ~(1 << (ch + 2)); 420 421 ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE, 422 0, st->cb_mask[devaddr]); 423 mutex_unlock(&indio_dev->mlock); 424 425 return ret ? ret : len; 426} 427 428static ssize_t ad7280_show_balance_timer(struct device *dev, 429 struct device_attribute *attr, 430 char *buf) 431{ 432 struct iio_dev *indio_dev = dev_get_drvdata(dev); 433 struct ad7280_state *st = iio_priv(indio_dev); 434 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 435 int ret; 436 unsigned msecs; 437 438 mutex_lock(&indio_dev->mlock); 439 ret = ad7280_read(st, this_attr->address >> 8, 440 this_attr->address & 0xFF); 441 mutex_unlock(&indio_dev->mlock); 442 443 if (ret < 0) 444 return ret; 445 446 msecs = (ret >> 3) * 71500; 447 448 return sprintf(buf, "%d\n", msecs); 449} 450 451static ssize_t ad7280_store_balance_timer(struct device *dev, 452 struct device_attribute *attr, 453 const char *buf, 454 size_t len) 455{ 456 struct iio_dev *indio_dev = dev_get_drvdata(dev); 457 struct ad7280_state *st = iio_priv(indio_dev); 458 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 459 long val; 460 int ret; 461 462 ret = strict_strtoul(buf, 10, &val); 463 if (ret) 464 return ret; 465 466 val /= 71500; 467 468 if (val > 31) 469 return -EINVAL; 470 471 mutex_lock(&indio_dev->mlock); 472 ret = ad7280_write(st, this_attr->address >> 8, 473 this_attr->address & 0xFF, 474 0, (val & 0x1F) << 3); 475 mutex_unlock(&indio_dev->mlock); 476 477 return ret ? ret : len; 478} 479 480static struct attribute *ad7280_attributes[AD7280A_MAX_CHAIN * 481 AD7280A_CELLS_PER_DEV * 2 + 1]; 482 483static struct attribute_group ad7280_attrs_group = { 484 .attrs = ad7280_attributes, 485}; 486 487static int ad7280_channel_init(struct ad7280_state *st) 488{ 489 int dev, ch, cnt; 490 491 st->channels = kzalloc(sizeof(*st->channels) * 492 ((st->slave_num + 1) * 12 + 2), GFP_KERNEL); 493 if (st->channels == NULL) 494 return -ENOMEM; 495 496 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++) 497 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_AUX_ADC_6; ch++, 498 cnt++) { 499 if (ch < AD7280A_AUX_ADC_1) { 500 st->channels[cnt].type = IIO_VOLTAGE; 501 st->channels[cnt].differential = 1; 502 st->channels[cnt].channel = (dev * 6) + ch; 503 st->channels[cnt].channel2 = 504 st->channels[cnt].channel + 1; 505 } else { 506 st->channels[cnt].type = IIO_TEMP; 507 st->channels[cnt].channel = (dev * 6) + ch - 6; 508 } 509 st->channels[cnt].indexed = 1; 510 st->channels[cnt].info_mask = 511 IIO_CHAN_INFO_SCALE_SHARED_BIT; 512 st->channels[cnt].address = 513 AD7280A_DEVADDR(dev) << 8 | ch; 514 st->channels[cnt].scan_index = cnt; 515 st->channels[cnt].scan_type.sign = 'u'; 516 st->channels[cnt].scan_type.realbits = 12; 517 st->channels[cnt].scan_type.storagebits = 32; 518 st->channels[cnt].scan_type.shift = 0; 519 } 520 521 st->channels[cnt].type = IIO_VOLTAGE; 522 st->channels[cnt].differential = 1; 523 st->channels[cnt].channel = 0; 524 st->channels[cnt].channel2 = dev * 6; 525 st->channels[cnt].address = AD7280A_ALL_CELLS; 526 st->channels[cnt].indexed = 1; 527 st->channels[cnt].info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT; 528 st->channels[cnt].scan_index = cnt; 529 st->channels[cnt].scan_type.sign = 'u'; 530 st->channels[cnt].scan_type.realbits = 32; 531 st->channels[cnt].scan_type.storagebits = 32; 532 st->channels[cnt].scan_type.shift = 0; 533 cnt++; 534 st->channels[cnt].type = IIO_TIMESTAMP; 535 st->channels[cnt].channel = -1; 536 st->channels[cnt].scan_index = cnt; 537 st->channels[cnt].scan_type.sign = 's'; 538 st->channels[cnt].scan_type.realbits = 64; 539 st->channels[cnt].scan_type.storagebits = 64; 540 st->channels[cnt].scan_type.shift = 0; 541 542 return cnt + 1; 543} 544 545static int ad7280_attr_init(struct ad7280_state *st) 546{ 547 int dev, ch, cnt; 548 549 st->iio_attr = kzalloc(sizeof(*st->iio_attr) * (st->slave_num + 1) * 550 AD7280A_CELLS_PER_DEV * 2, GFP_KERNEL); 551 if (st->iio_attr == NULL) 552 return -ENOMEM; 553 554 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++) 555 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_CELL_VOLTAGE_6; 556 ch++, cnt++) { 557 st->iio_attr[cnt].address = 558 AD7280A_DEVADDR(dev) << 8 | ch; 559 st->iio_attr[cnt].dev_attr.attr.mode = 560 S_IWUSR | S_IRUGO; 561 st->iio_attr[cnt].dev_attr.show = 562 ad7280_show_balance_sw; 563 st->iio_attr[cnt].dev_attr.store = 564 ad7280_store_balance_sw; 565 st->iio_attr[cnt].dev_attr.attr.name = 566 kasprintf(GFP_KERNEL, 567 "in%d-in%d_balance_switch_en", 568 (dev * AD7280A_CELLS_PER_DEV) + ch, 569 (dev * AD7280A_CELLS_PER_DEV) + ch + 1); 570 ad7280_attributes[cnt] = 571 &st->iio_attr[cnt].dev_attr.attr; 572 cnt++; 573 st->iio_attr[cnt].address = 574 AD7280A_DEVADDR(dev) << 8 | 575 (AD7280A_CB1_TIMER + ch); 576 st->iio_attr[cnt].dev_attr.attr.mode = 577 S_IWUSR | S_IRUGO; 578 st->iio_attr[cnt].dev_attr.show = 579 ad7280_show_balance_timer; 580 st->iio_attr[cnt].dev_attr.store = 581 ad7280_store_balance_timer; 582 st->iio_attr[cnt].dev_attr.attr.name = 583 kasprintf(GFP_KERNEL, "in%d-in%d_balance_timer", 584 (dev * AD7280A_CELLS_PER_DEV) + ch, 585 (dev * AD7280A_CELLS_PER_DEV) + ch + 1); 586 ad7280_attributes[cnt] = 587 &st->iio_attr[cnt].dev_attr.attr; 588 } 589 590 ad7280_attributes[cnt] = NULL; 591 592 return 0; 593} 594 595static ssize_t ad7280_read_channel_config(struct device *dev, 596 struct device_attribute *attr, 597 char *buf) 598{ 599 struct iio_dev *indio_dev = dev_get_drvdata(dev); 600 struct ad7280_state *st = iio_priv(indio_dev); 601 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 602 unsigned val; 603 604 switch ((u32) this_attr->address) { 605 case AD7280A_CELL_OVERVOLTAGE: 606 val = 1000 + (st->cell_threshhigh * 1568) / 100; 607 break; 608 case AD7280A_CELL_UNDERVOLTAGE: 609 val = 1000 + (st->cell_threshlow * 1568) / 100; 610 break; 611 case AD7280A_AUX_ADC_OVERVOLTAGE: 612 val = (st->aux_threshhigh * 196) / 10; 613 break; 614 case AD7280A_AUX_ADC_UNDERVOLTAGE: 615 val = (st->aux_threshlow * 196) / 10; 616 break; 617 default: 618 return -EINVAL; 619 } 620 621 return sprintf(buf, "%d\n", val); 622} 623 624static ssize_t ad7280_write_channel_config(struct device *dev, 625 struct device_attribute *attr, 626 const char *buf, 627 size_t len) 628{ 629 struct iio_dev *indio_dev = dev_get_drvdata(dev); 630 struct ad7280_state *st = iio_priv(indio_dev); 631 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 632 633 long val; 634 int ret; 635 636 ret = strict_strtol(buf, 10, &val); 637 if (ret) 638 return ret; 639 640 switch ((u32) this_attr->address) { 641 case AD7280A_CELL_OVERVOLTAGE: 642 case AD7280A_CELL_UNDERVOLTAGE: 643 val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */ 644 break; 645 case AD7280A_AUX_ADC_OVERVOLTAGE: 646 case AD7280A_AUX_ADC_UNDERVOLTAGE: 647 val = (val * 10) / 196; /* LSB 19.6mV */ 648 break; 649 default: 650 return -EFAULT; 651 } 652 653 val = clamp(val, 0L, 0xFFL); 654 655 mutex_lock(&indio_dev->mlock); 656 switch ((u32) this_attr->address) { 657 case AD7280A_CELL_OVERVOLTAGE: 658 st->cell_threshhigh = val; 659 break; 660 case AD7280A_CELL_UNDERVOLTAGE: 661 st->cell_threshlow = val; 662 break; 663 case AD7280A_AUX_ADC_OVERVOLTAGE: 664 st->aux_threshhigh = val; 665 break; 666 case AD7280A_AUX_ADC_UNDERVOLTAGE: 667 st->aux_threshlow = val; 668 break; 669 } 670 671 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, 672 this_attr->address, 1, val); 673 674 mutex_unlock(&indio_dev->mlock); 675 676 return ret ? ret : len; 677} 678 679static irqreturn_t ad7280_event_handler(int irq, void *private) 680{ 681 struct iio_dev *indio_dev = private; 682 struct ad7280_state *st = iio_priv(indio_dev); 683 unsigned *channels; 684 int i, ret; 685 686 channels = kzalloc(sizeof(*channels) * st->scan_cnt, GFP_KERNEL); 687 if (channels == NULL) 688 return IRQ_HANDLED; 689 690 ret = ad7280_read_all_channels(st, st->scan_cnt, channels); 691 if (ret < 0) 692 goto out; 693 694 for (i = 0; i < st->scan_cnt; i++) { 695 if (((channels[i] >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) { 696 if (((channels[i] >> 11) & 0xFFF) >= 697 st->cell_threshhigh) 698 iio_push_event(indio_dev, 699 IIO_EVENT_CODE(IIO_VOLTAGE, 700 1, 701 0, 702 IIO_EV_DIR_RISING, 703 IIO_EV_TYPE_THRESH, 704 0, 0, 0), 705 iio_get_time_ns()); 706 else if (((channels[i] >> 11) & 0xFFF) <= 707 st->cell_threshlow) 708 iio_push_event(indio_dev, 709 IIO_EVENT_CODE(IIO_VOLTAGE, 710 1, 711 0, 712 IIO_EV_DIR_FALLING, 713 IIO_EV_TYPE_THRESH, 714 0, 0, 0), 715 iio_get_time_ns()); 716 } else { 717 if (((channels[i] >> 11) & 0xFFF) >= st->aux_threshhigh) 718 iio_push_event(indio_dev, 719 IIO_UNMOD_EVENT_CODE(IIO_TEMP, 720 0, 721 IIO_EV_TYPE_THRESH, 722 IIO_EV_DIR_RISING), 723 iio_get_time_ns()); 724 else if (((channels[i] >> 11) & 0xFFF) <= 725 st->aux_threshlow) 726 iio_push_event(indio_dev, 727 IIO_UNMOD_EVENT_CODE(IIO_TEMP, 728 0, 729 IIO_EV_TYPE_THRESH, 730 IIO_EV_DIR_FALLING), 731 iio_get_time_ns()); 732 } 733 } 734 735out: 736 kfree(channels); 737 738 return IRQ_HANDLED; 739} 740 741static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value, 742 in_voltage-voltage_thresh_low_value, 743 S_IRUGO | S_IWUSR, 744 ad7280_read_channel_config, 745 ad7280_write_channel_config, 746 AD7280A_CELL_UNDERVOLTAGE); 747 748static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value, 749 in_voltage-voltage_thresh_high_value, 750 S_IRUGO | S_IWUSR, 751 ad7280_read_channel_config, 752 ad7280_write_channel_config, 753 AD7280A_CELL_OVERVOLTAGE); 754 755static IIO_DEVICE_ATTR(in_temp_thresh_low_value, 756 S_IRUGO | S_IWUSR, 757 ad7280_read_channel_config, 758 ad7280_write_channel_config, 759 AD7280A_AUX_ADC_UNDERVOLTAGE); 760 761static IIO_DEVICE_ATTR(in_temp_thresh_high_value, 762 S_IRUGO | S_IWUSR, 763 ad7280_read_channel_config, 764 ad7280_write_channel_config, 765 AD7280A_AUX_ADC_OVERVOLTAGE); 766 767 768static struct attribute *ad7280_event_attributes[] = { 769 &iio_dev_attr_in_thresh_low_value.dev_attr.attr, 770 &iio_dev_attr_in_thresh_high_value.dev_attr.attr, 771 &iio_dev_attr_in_temp_thresh_low_value.dev_attr.attr, 772 &iio_dev_attr_in_temp_thresh_high_value.dev_attr.attr, 773 NULL, 774}; 775 776static struct attribute_group ad7280_event_attrs_group = { 777 .attrs = ad7280_event_attributes, 778}; 779 780static int ad7280_read_raw(struct iio_dev *indio_dev, 781 struct iio_chan_spec const *chan, 782 int *val, 783 int *val2, 784 long m) 785{ 786 struct ad7280_state *st = iio_priv(indio_dev); 787 unsigned int scale_uv; 788 int ret; 789 790 switch (m) { 791 case 0: 792 mutex_lock(&indio_dev->mlock); 793 if (chan->address == AD7280A_ALL_CELLS) 794 ret = ad7280_read_all_channels(st, st->scan_cnt, NULL); 795 else 796 ret = ad7280_read_channel(st, chan->address >> 8, 797 chan->address & 0xFF); 798 mutex_unlock(&indio_dev->mlock); 799 800 if (ret < 0) 801 return ret; 802 803 *val = ret; 804 805 return IIO_VAL_INT; 806 case IIO_CHAN_INFO_SCALE: 807 if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6) 808 scale_uv = (4000 * 1000) >> AD7280A_BITS; 809 else 810 scale_uv = (5000 * 1000) >> AD7280A_BITS; 811 812 *val = scale_uv / 1000; 813 *val2 = (scale_uv % 1000) * 1000; 814 return IIO_VAL_INT_PLUS_MICRO; 815 } 816 return -EINVAL; 817} 818 819static const struct iio_info ad7280_info = { 820 .read_raw = &ad7280_read_raw, 821 .event_attrs = &ad7280_event_attrs_group, 822 .attrs = &ad7280_attrs_group, 823 .driver_module = THIS_MODULE, 824}; 825 826static const struct ad7280_platform_data ad7793_default_pdata = { 827 .acquisition_time = AD7280A_ACQ_TIME_400ns, 828 .conversion_averaging = AD7280A_CONV_AVG_DIS, 829 .thermistor_term_en = true, 830}; 831 832static int __devinit ad7280_probe(struct spi_device *spi) 833{ 834 const struct ad7280_platform_data *pdata = spi->dev.platform_data; 835 struct ad7280_state *st; 836 int ret; 837 const unsigned short tACQ_ns[4] = {465, 1010, 1460, 1890}; 838 const unsigned short nAVG[4] = {1, 2, 4, 8}; 839 struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st)); 840 841 if (indio_dev == NULL) 842 return -ENOMEM; 843 844 st = iio_priv(indio_dev); 845 spi_set_drvdata(spi, indio_dev); 846 st->spi = spi; 847 848 if (!pdata) 849 pdata = &ad7793_default_pdata; 850 851 ad7280_crc8_build_table(st->crc_tab); 852 853 st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_Hz; 854 st->spi->mode = SPI_MODE_1; 855 spi_setup(st->spi); 856 857 st->ctrl_lb = AD7280A_CTRL_LB_ACQ_TIME(pdata->acquisition_time & 0x3); 858 st->ctrl_hb = AD7280A_CTRL_HB_CONV_AVG(pdata->conversion_averaging 859 & 0x3) | (pdata->thermistor_term_en ? 860 AD7280A_CTRL_LB_THERMISTOR_EN : 0); 861 862 ret = ad7280_chain_setup(st); 863 if (ret < 0) 864 goto error_free_device; 865 866 st->slave_num = ret; 867 st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH; 868 st->cell_threshhigh = 0xFF; 869 st->aux_threshhigh = 0xFF; 870 871 /* 872 * Total Conversion Time = ((tACQ + tCONV) * 873 * (Number of Conversions per Part)) − 874 * tACQ + ((N - 1) * tDELAY) 875 * 876 * Readback Delay = Total Conversion Time + tWAIT 877 */ 878 879 st->readback_delay_us = 880 ((tACQ_ns[pdata->acquisition_time & 0x3] + 695) * 881 (AD7280A_NUM_CH * nAVG[pdata->conversion_averaging & 0x3])) 882 - tACQ_ns[pdata->acquisition_time & 0x3] + 883 st->slave_num * 250; 884 885 /* Convert to usecs */ 886 st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000); 887 st->readback_delay_us += 5; /* Add tWAIT */ 888 889 indio_dev->name = spi_get_device_id(spi)->name; 890 indio_dev->dev.parent = &spi->dev; 891 indio_dev->modes = INDIO_DIRECT_MODE; 892 893 ret = ad7280_channel_init(st); 894 if (ret < 0) 895 goto error_free_device; 896 897 indio_dev->num_channels = ret; 898 indio_dev->channels = st->channels; 899 indio_dev->info = &ad7280_info; 900 901 ret = ad7280_attr_init(st); 902 if (ret < 0) 903 goto error_free_channels; 904 905 ret = iio_device_register(indio_dev); 906 if (ret) 907 goto error_free_attr; 908 909 if (spi->irq > 0) { 910 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, 911 AD7280A_ALERT, 1, 912 AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN); 913 if (ret) 914 goto error_unregister; 915 916 ret = ad7280_write(st, AD7280A_DEVADDR(st->slave_num), 917 AD7280A_ALERT, 0, 918 AD7280A_ALERT_GEN_STATIC_HIGH | 919 (pdata->chain_last_alert_ignore & 0xF)); 920 if (ret) 921 goto error_unregister; 922 923 ret = request_threaded_irq(spi->irq, 924 NULL, 925 ad7280_event_handler, 926 IRQF_TRIGGER_FALLING | 927 IRQF_ONESHOT, 928 indio_dev->name, 929 indio_dev); 930 if (ret) 931 goto error_unregister; 932 } 933 934 return 0; 935error_unregister: 936 iio_device_unregister(indio_dev); 937 938error_free_attr: 939 kfree(st->iio_attr); 940 941error_free_channels: 942 kfree(st->channels); 943 944error_free_device: 945 iio_free_device(indio_dev); 946 947 return ret; 948} 949 950static int __devexit ad7280_remove(struct spi_device *spi) 951{ 952 struct iio_dev *indio_dev = spi_get_drvdata(spi); 953 struct ad7280_state *st = iio_priv(indio_dev); 954 955 if (spi->irq > 0) 956 free_irq(spi->irq, indio_dev); 957 iio_device_unregister(indio_dev); 958 959 ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 960 AD7280A_CTRL_HB_PWRDN_SW | st->ctrl_hb); 961 962 kfree(st->channels); 963 kfree(st->iio_attr); 964 iio_free_device(indio_dev); 965 966 return 0; 967} 968 969static const struct spi_device_id ad7280_id[] = { 970 {"ad7280a", 0}, 971 {} 972}; 973 974static struct spi_driver ad7280_driver = { 975 .driver = { 976 .name = "ad7280", 977 .bus = &spi_bus_type, 978 .owner = THIS_MODULE, 979 }, 980 .probe = ad7280_probe, 981 .remove = __devexit_p(ad7280_remove), 982 .id_table = ad7280_id, 983}; 984 985static int __init ad7280_init(void) 986{ 987 return spi_register_driver(&ad7280_driver); 988} 989module_init(ad7280_init); 990 991static void __exit ad7280_exit(void) 992{ 993 spi_unregister_driver(&ad7280_driver); 994} 995module_exit(ad7280_exit); 996 997MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 998MODULE_DESCRIPTION("Analog Devices AD7280A"); 999MODULE_LICENSE("GPL v2"); 1000