1/* 2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9#include <linux/kernel.h> 10#include <linux/pci.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/gpio.h> 14#include <linux/module.h> 15#include <linux/mbus.h> 16#include <linux/msi.h> 17#include <linux/slab.h> 18#include <linux/platform_device.h> 19#include <linux/of_address.h> 20#include <linux/of_irq.h> 21#include <linux/of_gpio.h> 22#include <linux/of_pci.h> 23#include <linux/of_platform.h> 24 25/* 26 * PCIe unit register offsets. 27 */ 28#define PCIE_DEV_ID_OFF 0x0000 29#define PCIE_CMD_OFF 0x0004 30#define PCIE_DEV_REV_OFF 0x0008 31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 33#define PCIE_HEADER_LOG_4_OFF 0x0128 34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 38#define PCIE_WIN5_CTRL_OFF 0x1880 39#define PCIE_WIN5_BASE_OFF 0x1884 40#define PCIE_WIN5_REMAP_OFF 0x188c 41#define PCIE_CONF_ADDR_OFF 0x18f8 42#define PCIE_CONF_ADDR_EN 0x80000000 43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 47#define PCIE_CONF_ADDR(bus, devfn, where) \ 48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 50 PCIE_CONF_ADDR_EN) 51#define PCIE_CONF_DATA_OFF 0x18fc 52#define PCIE_MASK_OFF 0x1910 53#define PCIE_MASK_ENABLE_INTS 0x0f000000 54#define PCIE_CTRL_OFF 0x1a00 55#define PCIE_CTRL_X1_MODE 0x0001 56#define PCIE_STAT_OFF 0x1a04 57#define PCIE_STAT_BUS 0xff00 58#define PCIE_STAT_DEV 0x1f0000 59#define PCIE_STAT_LINK_DOWN BIT(0) 60#define PCIE_DEBUG_CTRL 0x1a60 61#define PCIE_DEBUG_SOFT_RESET BIT(20) 62 63/* PCI configuration space of a PCI-to-PCI bridge */ 64struct mvebu_sw_pci_bridge { 65 u16 vendor; 66 u16 device; 67 u16 command; 68 u16 class; 69 u8 interface; 70 u8 revision; 71 u8 bist; 72 u8 header_type; 73 u8 latency_timer; 74 u8 cache_line_size; 75 u32 bar[2]; 76 u8 primary_bus; 77 u8 secondary_bus; 78 u8 subordinate_bus; 79 u8 secondary_latency_timer; 80 u8 iobase; 81 u8 iolimit; 82 u16 secondary_status; 83 u16 membase; 84 u16 memlimit; 85 u16 iobaseupper; 86 u16 iolimitupper; 87 u8 cappointer; 88 u8 reserved1; 89 u16 reserved2; 90 u32 romaddr; 91 u8 intline; 92 u8 intpin; 93 u16 bridgectrl; 94}; 95 96struct mvebu_pcie_port; 97 98/* Structure representing all PCIe interfaces */ 99struct mvebu_pcie { 100 struct platform_device *pdev; 101 struct mvebu_pcie_port *ports; 102 struct msi_chip *msi; 103 struct resource io; 104 char io_name[30]; 105 struct resource realio; 106 char mem_name[30]; 107 struct resource mem; 108 struct resource busn; 109 int nports; 110}; 111 112/* Structure representing one PCIe interface */ 113struct mvebu_pcie_port { 114 char *name; 115 void __iomem *base; 116 u32 port; 117 u32 lane; 118 int devfn; 119 unsigned int mem_target; 120 unsigned int mem_attr; 121 unsigned int io_target; 122 unsigned int io_attr; 123 struct clk *clk; 124 int reset_gpio; 125 int reset_active_low; 126 char *reset_name; 127 struct mvebu_sw_pci_bridge bridge; 128 struct device_node *dn; 129 struct mvebu_pcie *pcie; 130 phys_addr_t memwin_base; 131 size_t memwin_size; 132 phys_addr_t iowin_base; 133 size_t iowin_size; 134}; 135 136static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 137{ 138 writel(val, port->base + reg); 139} 140 141static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 142{ 143 return readl(port->base + reg); 144} 145 146static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 147{ 148 return port->io_target != -1 && port->io_attr != -1; 149} 150 151static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 152{ 153 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 154} 155 156static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 157{ 158 u32 stat; 159 160 stat = mvebu_readl(port, PCIE_STAT_OFF); 161 stat &= ~PCIE_STAT_BUS; 162 stat |= nr << 8; 163 mvebu_writel(port, stat, PCIE_STAT_OFF); 164} 165 166static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 167{ 168 u32 stat; 169 170 stat = mvebu_readl(port, PCIE_STAT_OFF); 171 stat &= ~PCIE_STAT_DEV; 172 stat |= nr << 16; 173 mvebu_writel(port, stat, PCIE_STAT_OFF); 174} 175 176/* 177 * Setup PCIE BARs and Address Decode Wins: 178 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 179 * WIN[0-3] -> DRAM bank[0-3] 180 */ 181static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 182{ 183 const struct mbus_dram_target_info *dram; 184 u32 size; 185 int i; 186 187 dram = mv_mbus_dram_info(); 188 189 /* First, disable and clear BARs and windows. */ 190 for (i = 1; i < 3; i++) { 191 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 192 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 193 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 194 } 195 196 for (i = 0; i < 5; i++) { 197 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 198 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 199 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 200 } 201 202 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 203 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 204 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 205 206 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 207 size = 0; 208 for (i = 0; i < dram->num_cs; i++) { 209 const struct mbus_dram_window *cs = dram->cs + i; 210 211 mvebu_writel(port, cs->base & 0xffff0000, 212 PCIE_WIN04_BASE_OFF(i)); 213 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 214 mvebu_writel(port, 215 ((cs->size - 1) & 0xffff0000) | 216 (cs->mbus_attr << 8) | 217 (dram->mbus_dram_target_id << 4) | 1, 218 PCIE_WIN04_CTRL_OFF(i)); 219 220 size += cs->size; 221 } 222 223 /* Round up 'size' to the nearest power of two. */ 224 if ((size & (size - 1)) != 0) 225 size = 1 << fls(size); 226 227 /* Setup BAR[1] to all DRAM banks. */ 228 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 229 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 230 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 231 PCIE_BAR_CTRL_OFF(1)); 232} 233 234static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 235{ 236 u32 cmd, mask; 237 238 /* Point PCIe unit MBUS decode windows to DRAM space. */ 239 mvebu_pcie_setup_wins(port); 240 241 /* Master + slave enable. */ 242 cmd = mvebu_readl(port, PCIE_CMD_OFF); 243 cmd |= PCI_COMMAND_IO; 244 cmd |= PCI_COMMAND_MEMORY; 245 cmd |= PCI_COMMAND_MASTER; 246 mvebu_writel(port, cmd, PCIE_CMD_OFF); 247 248 /* Enable interrupt lines A-D. */ 249 mask = mvebu_readl(port, PCIE_MASK_OFF); 250 mask |= PCIE_MASK_ENABLE_INTS; 251 mvebu_writel(port, mask, PCIE_MASK_OFF); 252} 253 254static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, 255 struct pci_bus *bus, 256 u32 devfn, int where, int size, u32 *val) 257{ 258 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 259 PCIE_CONF_ADDR_OFF); 260 261 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF); 262 263 if (size == 1) 264 *val = (*val >> (8 * (where & 3))) & 0xff; 265 else if (size == 2) 266 *val = (*val >> (8 * (where & 3))) & 0xffff; 267 268 return PCIBIOS_SUCCESSFUL; 269} 270 271static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, 272 struct pci_bus *bus, 273 u32 devfn, int where, int size, u32 val) 274{ 275 u32 _val, shift = 8 * (where & 3); 276 277 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 278 PCIE_CONF_ADDR_OFF); 279 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF); 280 281 if (size == 4) 282 _val = val; 283 else if (size == 2) 284 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift); 285 else if (size == 1) 286 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift); 287 else 288 return PCIBIOS_BAD_REGISTER_NUMBER; 289 290 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF); 291 292 return PCIBIOS_SUCCESSFUL; 293} 294 295/* 296 * Remove windows, starting from the largest ones to the smallest 297 * ones. 298 */ 299static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, 300 phys_addr_t base, size_t size) 301{ 302 while (size) { 303 size_t sz = 1 << (fls(size) - 1); 304 305 mvebu_mbus_del_window(base, sz); 306 base += sz; 307 size -= sz; 308 } 309} 310 311/* 312 * MBus windows can only have a power of two size, but PCI BARs do not 313 * have this constraint. Therefore, we have to split the PCI BAR into 314 * areas each having a power of two size. We start from the largest 315 * one (i.e highest order bit set in the size). 316 */ 317static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, 318 unsigned int target, unsigned int attribute, 319 phys_addr_t base, size_t size, 320 phys_addr_t remap) 321{ 322 size_t size_mapped = 0; 323 324 while (size) { 325 size_t sz = 1 << (fls(size) - 1); 326 int ret; 327 328 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, 329 sz, remap); 330 if (ret) { 331 phys_addr_t end = base + sz - 1; 332 333 dev_err(&port->pcie->pdev->dev, 334 "Could not create MBus window at [mem %pa-%pa]: %d\n", 335 &base, &end, ret); 336 mvebu_pcie_del_windows(port, base - size_mapped, 337 size_mapped); 338 return; 339 } 340 341 size -= sz; 342 size_mapped += sz; 343 base += sz; 344 if (remap != MVEBU_MBUS_NO_REMAP) 345 remap += sz; 346 } 347} 348 349static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 350{ 351 phys_addr_t iobase; 352 353 /* Are the new iobase/iolimit values invalid? */ 354 if (port->bridge.iolimit < port->bridge.iobase || 355 port->bridge.iolimitupper < port->bridge.iobaseupper || 356 !(port->bridge.command & PCI_COMMAND_IO)) { 357 358 /* If a window was configured, remove it */ 359 if (port->iowin_base) { 360 mvebu_pcie_del_windows(port, port->iowin_base, 361 port->iowin_size); 362 port->iowin_base = 0; 363 port->iowin_size = 0; 364 } 365 366 return; 367 } 368 369 if (!mvebu_has_ioport(port)) { 370 dev_WARN(&port->pcie->pdev->dev, 371 "Attempt to set IO when IO is disabled\n"); 372 return; 373 } 374 375 /* 376 * We read the PCI-to-PCI bridge emulated registers, and 377 * calculate the base address and size of the address decoding 378 * window to setup, according to the PCI-to-PCI bridge 379 * specifications. iobase is the bus address, port->iowin_base 380 * is the CPU address. 381 */ 382 iobase = ((port->bridge.iobase & 0xF0) << 8) | 383 (port->bridge.iobaseupper << 16); 384 port->iowin_base = port->pcie->io.start + iobase; 385 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 386 (port->bridge.iolimitupper << 16)) - 387 iobase) + 1; 388 389 mvebu_pcie_add_windows(port, port->io_target, port->io_attr, 390 port->iowin_base, port->iowin_size, 391 iobase); 392} 393 394static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 395{ 396 /* Are the new membase/memlimit values invalid? */ 397 if (port->bridge.memlimit < port->bridge.membase || 398 !(port->bridge.command & PCI_COMMAND_MEMORY)) { 399 400 /* If a window was configured, remove it */ 401 if (port->memwin_base) { 402 mvebu_pcie_del_windows(port, port->memwin_base, 403 port->memwin_size); 404 port->memwin_base = 0; 405 port->memwin_size = 0; 406 } 407 408 return; 409 } 410 411 /* 412 * We read the PCI-to-PCI bridge emulated registers, and 413 * calculate the base address and size of the address decoding 414 * window to setup, according to the PCI-to-PCI bridge 415 * specifications. 416 */ 417 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); 418 port->memwin_size = 419 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 420 port->memwin_base + 1; 421 422 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr, 423 port->memwin_base, port->memwin_size, 424 MVEBU_MBUS_NO_REMAP); 425} 426 427/* 428 * Initialize the configuration space of the PCI-to-PCI bridge 429 * associated with the given PCIe interface. 430 */ 431static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) 432{ 433 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 434 435 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); 436 437 bridge->class = PCI_CLASS_BRIDGE_PCI; 438 bridge->vendor = PCI_VENDOR_ID_MARVELL; 439 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; 440 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; 441 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; 442 bridge->cache_line_size = 0x10; 443 444 /* We support 32 bits I/O addressing */ 445 bridge->iobase = PCI_IO_RANGE_TYPE_32; 446 bridge->iolimit = PCI_IO_RANGE_TYPE_32; 447} 448 449/* 450 * Read the configuration space of the PCI-to-PCI bridge associated to 451 * the given PCIe interface. 452 */ 453static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, 454 unsigned int where, int size, u32 *value) 455{ 456 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 457 458 switch (where & ~3) { 459 case PCI_VENDOR_ID: 460 *value = bridge->device << 16 | bridge->vendor; 461 break; 462 463 case PCI_COMMAND: 464 *value = bridge->command; 465 break; 466 467 case PCI_CLASS_REVISION: 468 *value = bridge->class << 16 | bridge->interface << 8 | 469 bridge->revision; 470 break; 471 472 case PCI_CACHE_LINE_SIZE: 473 *value = bridge->bist << 24 | bridge->header_type << 16 | 474 bridge->latency_timer << 8 | bridge->cache_line_size; 475 break; 476 477 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 478 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; 479 break; 480 481 case PCI_PRIMARY_BUS: 482 *value = (bridge->secondary_latency_timer << 24 | 483 bridge->subordinate_bus << 16 | 484 bridge->secondary_bus << 8 | 485 bridge->primary_bus); 486 break; 487 488 case PCI_IO_BASE: 489 if (!mvebu_has_ioport(port)) 490 *value = bridge->secondary_status << 16; 491 else 492 *value = (bridge->secondary_status << 16 | 493 bridge->iolimit << 8 | 494 bridge->iobase); 495 break; 496 497 case PCI_MEMORY_BASE: 498 *value = (bridge->memlimit << 16 | bridge->membase); 499 break; 500 501 case PCI_PREF_MEMORY_BASE: 502 *value = 0; 503 break; 504 505 case PCI_IO_BASE_UPPER16: 506 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); 507 break; 508 509 case PCI_ROM_ADDRESS1: 510 *value = 0; 511 break; 512 513 case PCI_INTERRUPT_LINE: 514 /* LINE PIN MIN_GNT MAX_LAT */ 515 *value = 0; 516 break; 517 518 default: 519 *value = 0xffffffff; 520 return PCIBIOS_BAD_REGISTER_NUMBER; 521 } 522 523 if (size == 2) 524 *value = (*value >> (8 * (where & 3))) & 0xffff; 525 else if (size == 1) 526 *value = (*value >> (8 * (where & 3))) & 0xff; 527 528 return PCIBIOS_SUCCESSFUL; 529} 530 531/* Write to the PCI-to-PCI bridge configuration space */ 532static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, 533 unsigned int where, int size, u32 value) 534{ 535 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 536 u32 mask, reg; 537 int err; 538 539 if (size == 4) 540 mask = 0x0; 541 else if (size == 2) 542 mask = ~(0xffff << ((where & 3) * 8)); 543 else if (size == 1) 544 mask = ~(0xff << ((where & 3) * 8)); 545 else 546 return PCIBIOS_BAD_REGISTER_NUMBER; 547 548 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); 549 if (err) 550 return err; 551 552 value = (reg & mask) | value << ((where & 3) * 8); 553 554 switch (where & ~3) { 555 case PCI_COMMAND: 556 { 557 u32 old = bridge->command; 558 559 if (!mvebu_has_ioport(port)) 560 value &= ~PCI_COMMAND_IO; 561 562 bridge->command = value & 0xffff; 563 if ((old ^ bridge->command) & PCI_COMMAND_IO) 564 mvebu_pcie_handle_iobase_change(port); 565 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) 566 mvebu_pcie_handle_membase_change(port); 567 break; 568 } 569 570 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: 571 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; 572 break; 573 574 case PCI_IO_BASE: 575 /* 576 * We also keep bit 1 set, it is a read-only bit that 577 * indicates we support 32 bits addressing for the 578 * I/O 579 */ 580 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; 581 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; 582 mvebu_pcie_handle_iobase_change(port); 583 break; 584 585 case PCI_MEMORY_BASE: 586 bridge->membase = value & 0xffff; 587 bridge->memlimit = value >> 16; 588 mvebu_pcie_handle_membase_change(port); 589 break; 590 591 case PCI_IO_BASE_UPPER16: 592 bridge->iobaseupper = value & 0xffff; 593 bridge->iolimitupper = value >> 16; 594 mvebu_pcie_handle_iobase_change(port); 595 break; 596 597 case PCI_PRIMARY_BUS: 598 bridge->primary_bus = value & 0xff; 599 bridge->secondary_bus = (value >> 8) & 0xff; 600 bridge->subordinate_bus = (value >> 16) & 0xff; 601 bridge->secondary_latency_timer = (value >> 24) & 0xff; 602 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); 603 break; 604 605 default: 606 break; 607 } 608 609 return PCIBIOS_SUCCESSFUL; 610} 611 612static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 613{ 614 return sys->private_data; 615} 616 617static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 618 struct pci_bus *bus, 619 int devfn) 620{ 621 int i; 622 623 for (i = 0; i < pcie->nports; i++) { 624 struct mvebu_pcie_port *port = &pcie->ports[i]; 625 if (bus->number == 0 && port->devfn == devfn) 626 return port; 627 if (bus->number != 0 && 628 bus->number >= port->bridge.secondary_bus && 629 bus->number <= port->bridge.subordinate_bus) 630 return port; 631 } 632 633 return NULL; 634} 635 636/* PCI configuration space write function */ 637static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 638 int where, int size, u32 val) 639{ 640 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 641 struct mvebu_pcie_port *port; 642 int ret; 643 644 port = mvebu_pcie_find_port(pcie, bus, devfn); 645 if (!port) 646 return PCIBIOS_DEVICE_NOT_FOUND; 647 648 /* Access the emulated PCI-to-PCI bridge */ 649 if (bus->number == 0) 650 return mvebu_sw_pci_bridge_write(port, where, size, val); 651 652 if (!mvebu_pcie_link_up(port)) 653 return PCIBIOS_DEVICE_NOT_FOUND; 654 655 /* 656 * On the secondary bus, we don't want to expose any other 657 * device than the device physically connected in the PCIe 658 * slot, visible in slot 0. In slot 1, there's a special 659 * Marvell device that only makes sense when the Armada is 660 * used as a PCIe endpoint. 661 */ 662 if (bus->number == port->bridge.secondary_bus && 663 PCI_SLOT(devfn) != 0) 664 return PCIBIOS_DEVICE_NOT_FOUND; 665 666 /* Access the real PCIe interface */ 667 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 668 where, size, val); 669 670 return ret; 671} 672 673/* PCI configuration space read function */ 674static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 675 int size, u32 *val) 676{ 677 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 678 struct mvebu_pcie_port *port; 679 int ret; 680 681 port = mvebu_pcie_find_port(pcie, bus, devfn); 682 if (!port) { 683 *val = 0xffffffff; 684 return PCIBIOS_DEVICE_NOT_FOUND; 685 } 686 687 /* Access the emulated PCI-to-PCI bridge */ 688 if (bus->number == 0) 689 return mvebu_sw_pci_bridge_read(port, where, size, val); 690 691 if (!mvebu_pcie_link_up(port)) { 692 *val = 0xffffffff; 693 return PCIBIOS_DEVICE_NOT_FOUND; 694 } 695 696 /* 697 * On the secondary bus, we don't want to expose any other 698 * device than the device physically connected in the PCIe 699 * slot, visible in slot 0. In slot 1, there's a special 700 * Marvell device that only makes sense when the Armada is 701 * used as a PCIe endpoint. 702 */ 703 if (bus->number == port->bridge.secondary_bus && 704 PCI_SLOT(devfn) != 0) { 705 *val = 0xffffffff; 706 return PCIBIOS_DEVICE_NOT_FOUND; 707 } 708 709 /* Access the real PCIe interface */ 710 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 711 where, size, val); 712 713 return ret; 714} 715 716static struct pci_ops mvebu_pcie_ops = { 717 .read = mvebu_pcie_rd_conf, 718 .write = mvebu_pcie_wr_conf, 719}; 720 721static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) 722{ 723 struct mvebu_pcie *pcie = sys_to_pcie(sys); 724 int i; 725 int domain = 0; 726 727#ifdef CONFIG_PCI_DOMAINS 728 domain = sys->domain; 729#endif 730 731 snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x", 732 domain); 733 pcie->mem.name = pcie->mem_name; 734 735 snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain); 736 pcie->realio.name = pcie->io_name; 737 738 if (request_resource(&iomem_resource, &pcie->mem)) 739 return 0; 740 741 if (resource_size(&pcie->realio) != 0) { 742 if (request_resource(&ioport_resource, &pcie->realio)) { 743 release_resource(&pcie->mem); 744 return 0; 745 } 746 pci_add_resource_offset(&sys->resources, &pcie->realio, 747 sys->io_offset); 748 } 749 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); 750 pci_add_resource(&sys->resources, &pcie->busn); 751 752 for (i = 0; i < pcie->nports; i++) { 753 struct mvebu_pcie_port *port = &pcie->ports[i]; 754 if (!port->base) 755 continue; 756 mvebu_pcie_setup_hw(port); 757 } 758 759 return 1; 760} 761 762static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys) 763{ 764 struct mvebu_pcie *pcie = sys_to_pcie(sys); 765 struct pci_bus *bus; 766 767 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, 768 &mvebu_pcie_ops, sys, &sys->resources); 769 if (!bus) 770 return NULL; 771 772 pci_scan_child_bus(bus); 773 774 return bus; 775} 776 777static void mvebu_pcie_add_bus(struct pci_bus *bus) 778{ 779 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 780 bus->msi = pcie->msi; 781} 782 783static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 784 const struct resource *res, 785 resource_size_t start, 786 resource_size_t size, 787 resource_size_t align) 788{ 789 if (dev->bus->number != 0) 790 return start; 791 792 /* 793 * On the PCI-to-PCI bridge side, the I/O windows must have at 794 * least a 64 KB size and the memory windows must have at 795 * least a 1 MB size. Moreover, MBus windows need to have a 796 * base address aligned on their size, and their size must be 797 * a power of two. This means that if the BAR doesn't have a 798 * power of two size, several MBus windows will actually be 799 * created. We need to ensure that the biggest MBus window 800 * (which will be the first one) is aligned on its size, which 801 * explains the rounddown_pow_of_two() being done here. 802 */ 803 if (res->flags & IORESOURCE_IO) 804 return round_up(start, max_t(resource_size_t, SZ_64K, 805 rounddown_pow_of_two(size))); 806 else if (res->flags & IORESOURCE_MEM) 807 return round_up(start, max_t(resource_size_t, SZ_1M, 808 rounddown_pow_of_two(size))); 809 else 810 return start; 811} 812 813static void mvebu_pcie_enable(struct mvebu_pcie *pcie) 814{ 815 struct hw_pci hw; 816 817 memset(&hw, 0, sizeof(hw)); 818 819 hw.nr_controllers = 1; 820 hw.private_data = (void **)&pcie; 821 hw.setup = mvebu_pcie_setup; 822 hw.scan = mvebu_pcie_scan_bus; 823 hw.map_irq = of_irq_parse_and_map_pci; 824 hw.ops = &mvebu_pcie_ops; 825 hw.align_resource = mvebu_pcie_align_resource; 826 hw.add_bus = mvebu_pcie_add_bus; 827 828 pci_common_init(&hw); 829} 830 831/* 832 * Looks up the list of register addresses encoded into the reg = 833 * <...> property for one that matches the given port/lane. Once 834 * found, maps it. 835 */ 836static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 837 struct device_node *np, 838 struct mvebu_pcie_port *port) 839{ 840 struct resource regs; 841 int ret = 0; 842 843 ret = of_address_to_resource(np, 0, ®s); 844 if (ret) 845 return ERR_PTR(ret); 846 847 return devm_ioremap_resource(&pdev->dev, ®s); 848} 849 850#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 851#define DT_TYPE_IO 0x1 852#define DT_TYPE_MEM32 0x2 853#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 854#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 855 856static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 857 unsigned long type, 858 unsigned int *tgt, 859 unsigned int *attr) 860{ 861 const int na = 3, ns = 2; 862 const __be32 *range; 863 int rlen, nranges, rangesz, pna, i; 864 865 *tgt = -1; 866 *attr = -1; 867 868 range = of_get_property(np, "ranges", &rlen); 869 if (!range) 870 return -EINVAL; 871 872 pna = of_n_addr_cells(np); 873 rangesz = pna + na + ns; 874 nranges = rlen / sizeof(__be32) / rangesz; 875 876 for (i = 0; i < nranges; i++, range += rangesz) { 877 u32 flags = of_read_number(range, 1); 878 u32 slot = of_read_number(range + 1, 1); 879 u64 cpuaddr = of_read_number(range + na, pna); 880 unsigned long rtype; 881 882 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 883 rtype = IORESOURCE_IO; 884 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 885 rtype = IORESOURCE_MEM; 886 else 887 continue; 888 889 if (slot == PCI_SLOT(devfn) && type == rtype) { 890 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 891 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 892 return 0; 893 } 894 } 895 896 return -ENOENT; 897} 898 899static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie) 900{ 901 struct device_node *msi_node; 902 903 msi_node = of_parse_phandle(pcie->pdev->dev.of_node, 904 "msi-parent", 0); 905 if (!msi_node) 906 return; 907 908 pcie->msi = of_pci_find_msi_chip_by_node(msi_node); 909 910 if (pcie->msi) 911 pcie->msi->dev = &pcie->pdev->dev; 912} 913 914static int mvebu_pcie_probe(struct platform_device *pdev) 915{ 916 struct mvebu_pcie *pcie; 917 struct device_node *np = pdev->dev.of_node; 918 struct device_node *child; 919 int i, ret; 920 921 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), 922 GFP_KERNEL); 923 if (!pcie) 924 return -ENOMEM; 925 926 pcie->pdev = pdev; 927 platform_set_drvdata(pdev, pcie); 928 929 /* Get the PCIe memory and I/O aperture */ 930 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 931 if (resource_size(&pcie->mem) == 0) { 932 dev_err(&pdev->dev, "invalid memory aperture size\n"); 933 return -EINVAL; 934 } 935 936 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 937 938 if (resource_size(&pcie->io) != 0) { 939 pcie->realio.flags = pcie->io.flags; 940 pcie->realio.start = PCIBIOS_MIN_IO; 941 pcie->realio.end = min_t(resource_size_t, 942 IO_SPACE_LIMIT, 943 resource_size(&pcie->io)); 944 } else 945 pcie->realio = pcie->io; 946 947 /* Get the bus range */ 948 ret = of_pci_parse_bus_range(np, &pcie->busn); 949 if (ret) { 950 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", 951 ret); 952 return ret; 953 } 954 955 i = 0; 956 for_each_child_of_node(pdev->dev.of_node, child) { 957 if (!of_device_is_available(child)) 958 continue; 959 i++; 960 } 961 962 pcie->ports = devm_kzalloc(&pdev->dev, i * 963 sizeof(struct mvebu_pcie_port), 964 GFP_KERNEL); 965 if (!pcie->ports) 966 return -ENOMEM; 967 968 i = 0; 969 for_each_child_of_node(pdev->dev.of_node, child) { 970 struct mvebu_pcie_port *port = &pcie->ports[i]; 971 enum of_gpio_flags flags; 972 973 if (!of_device_is_available(child)) 974 continue; 975 976 port->pcie = pcie; 977 978 if (of_property_read_u32(child, "marvell,pcie-port", 979 &port->port)) { 980 dev_warn(&pdev->dev, 981 "ignoring PCIe DT node, missing pcie-port property\n"); 982 continue; 983 } 984 985 if (of_property_read_u32(child, "marvell,pcie-lane", 986 &port->lane)) 987 port->lane = 0; 988 989 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", 990 port->port, port->lane); 991 992 port->devfn = of_pci_get_devfn(child); 993 if (port->devfn < 0) 994 continue; 995 996 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM, 997 &port->mem_target, &port->mem_attr); 998 if (ret < 0) { 999 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n", 1000 port->port, port->lane); 1001 continue; 1002 } 1003 1004 if (resource_size(&pcie->io) != 0) 1005 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO, 1006 &port->io_target, &port->io_attr); 1007 else { 1008 port->io_target = -1; 1009 port->io_attr = -1; 1010 } 1011 1012 port->reset_gpio = of_get_named_gpio_flags(child, 1013 "reset-gpios", 0, &flags); 1014 if (gpio_is_valid(port->reset_gpio)) { 1015 u32 reset_udelay = 20000; 1016 1017 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW; 1018 port->reset_name = kasprintf(GFP_KERNEL, 1019 "pcie%d.%d-reset", port->port, port->lane); 1020 of_property_read_u32(child, "reset-delay-us", 1021 &reset_udelay); 1022 1023 ret = devm_gpio_request_one(&pdev->dev, 1024 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name); 1025 if (ret) { 1026 if (ret == -EPROBE_DEFER) 1027 return ret; 1028 continue; 1029 } 1030 1031 gpio_set_value(port->reset_gpio, 1032 (port->reset_active_low) ? 1 : 0); 1033 msleep(reset_udelay/1000); 1034 } 1035 1036 port->clk = of_clk_get_by_name(child, NULL); 1037 if (IS_ERR(port->clk)) { 1038 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", 1039 port->port, port->lane); 1040 continue; 1041 } 1042 1043 ret = clk_prepare_enable(port->clk); 1044 if (ret) 1045 continue; 1046 1047 port->base = mvebu_pcie_map_registers(pdev, child, port); 1048 if (IS_ERR(port->base)) { 1049 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", 1050 port->port, port->lane); 1051 port->base = NULL; 1052 clk_disable_unprepare(port->clk); 1053 continue; 1054 } 1055 1056 mvebu_pcie_set_local_dev_nr(port, 1); 1057 1058 port->dn = child; 1059 mvebu_sw_pci_bridge_init(port); 1060 i++; 1061 } 1062 1063 pcie->nports = i; 1064 1065 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K) 1066 pci_ioremap_io(i, pcie->io.start + i); 1067 1068 mvebu_pcie_msi_enable(pcie); 1069 mvebu_pcie_enable(pcie); 1070 1071 return 0; 1072} 1073 1074static const struct of_device_id mvebu_pcie_of_match_table[] = { 1075 { .compatible = "marvell,armada-xp-pcie", }, 1076 { .compatible = "marvell,armada-370-pcie", }, 1077 { .compatible = "marvell,dove-pcie", }, 1078 { .compatible = "marvell,kirkwood-pcie", }, 1079 {}, 1080}; 1081MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); 1082 1083static struct platform_driver mvebu_pcie_driver = { 1084 .driver = { 1085 .owner = THIS_MODULE, 1086 .name = "mvebu-pcie", 1087 .of_match_table = mvebu_pcie_of_match_table, 1088 /* driver unloading/unbinding currently not supported */ 1089 .suppress_bind_attrs = true, 1090 }, 1091 .probe = mvebu_pcie_probe, 1092}; 1093module_platform_driver(mvebu_pcie_driver); 1094 1095MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 1096MODULE_DESCRIPTION("Marvell EBU PCIe driver"); 1097MODULE_LICENSE("GPL v2"); 1098