shpchp.h revision a4534560815ffc525bfbe465a290ce048aab4c01
1/* 2 * Standard Hot Plug Controller Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29#ifndef _SHPCHP_H 30#define _SHPCHP_H 31 32#include <linux/types.h> 33#include <linux/pci.h> 34#include <linux/delay.h> 35#include <linux/sched.h> /* signal_pending(), struct timer_list */ 36#include <linux/mutex.h> 37 38#include "pci_hotplug.h" 39 40#if !defined(MODULE) 41 #define MY_NAME "shpchp" 42#else 43 #define MY_NAME THIS_MODULE->name 44#endif 45 46extern int shpchp_poll_mode; 47extern int shpchp_poll_time; 48extern int shpchp_debug; 49 50/*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/ 51#define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0) 52#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg) 53#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) 54#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) 55 56#define SLOT_MAGIC 0x67267321 57struct slot { 58 u32 magic; 59 u8 bus; 60 u8 device; 61 u16 status; 62 u32 number; 63 u8 is_a_board; 64 u8 state; 65 u8 presence_save; 66 u8 pwr_save; 67 struct timer_list task_event; 68 u8 hp_slot; 69 struct controller *ctrl; 70 struct hpc_ops *hpc_ops; 71 struct hotplug_slot *hotplug_slot; 72 struct list_head slot_list; 73}; 74 75struct event_info { 76 u32 event_type; 77 u8 hp_slot; 78}; 79 80struct controller { 81 struct list_head ctrl_list; 82 struct mutex crit_sect; /* critical section mutex */ 83 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */ 84 int num_slots; /* Number of slots on ctlr */ 85 int slot_num_inc; /* 1 or -1 */ 86 struct pci_dev *pci_dev; 87 struct pci_bus *pci_bus; 88 struct event_info event_queue[10]; 89 struct list_head slot_list; 90 struct hpc_ops *hpc_ops; 91 wait_queue_head_t queue; /* sleep & wake process */ 92 u8 next_event; 93 u8 bus; 94 u8 device; 95 u8 function; 96 u8 slot_device_offset; 97 u8 add_support; 98 u32 pcix_misc2_reg; /* for amd pogo errata */ 99 enum pci_bus_speed speed; 100 u32 first_slot; /* First physical slot number */ 101 u8 slot_bus; /* Bus where the slots handled by this controller sit */ 102 u32 cap_offset; 103 unsigned long mmio_base; 104 unsigned long mmio_size; 105 volatile int cmd_busy; 106}; 107 108struct hotplug_params { 109 u8 cache_line_size; 110 u8 latency_timer; 111 u8 enable_serr; 112 u8 enable_perr; 113}; 114 115/* Define AMD SHPC ID */ 116#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 117#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 118 119/* AMD PCIX bridge registers */ 120 121#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C 122#define PCIX_MISCII_OFFSET 0x48 123#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 124 125/* AMD PCIX_MISCII masks and offsets */ 126#define PERRNONFATALENABLE_MASK 0x00040000 127#define PERRFATALENABLE_MASK 0x00080000 128#define PERRFLOODENABLE_MASK 0x00100000 129#define SERRNONFATALENABLE_MASK 0x00200000 130#define SERRFATALENABLE_MASK 0x00400000 131 132/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */ 133#define PERR_OBSERVED_MASK 0x00000001 134 135/* AMD PCIX_MEM_BASE_LIMIT masks */ 136#define RSE_MASK 0x40000000 137 138#define INT_BUTTON_IGNORE 0 139#define INT_PRESENCE_ON 1 140#define INT_PRESENCE_OFF 2 141#define INT_SWITCH_CLOSE 3 142#define INT_SWITCH_OPEN 4 143#define INT_POWER_FAULT 5 144#define INT_POWER_FAULT_CLEAR 6 145#define INT_BUTTON_PRESS 7 146#define INT_BUTTON_RELEASE 8 147#define INT_BUTTON_CANCEL 9 148 149#define STATIC_STATE 0 150#define BLINKINGON_STATE 1 151#define BLINKINGOFF_STATE 2 152#define POWERON_STATE 3 153#define POWEROFF_STATE 4 154 155#define PCI_TO_PCI_BRIDGE_CLASS 0x00060400 156 157/* Error messages */ 158#define INTERLOCK_OPEN 0x00000002 159#define ADD_NOT_SUPPORTED 0x00000003 160#define CARD_FUNCTIONING 0x00000005 161#define ADAPTER_NOT_SAME 0x00000006 162#define NO_ADAPTER_PRESENT 0x00000009 163#define NOT_ENOUGH_RESOURCES 0x0000000B 164#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C 165#define WRONG_BUS_FREQUENCY 0x0000000D 166#define POWER_FAILURE 0x0000000E 167 168#define REMOVE_NOT_SUPPORTED 0x00000003 169 170#define DISABLE_CARD 1 171 172/* 173 * error Messages 174 */ 175#define msg_initialization_err "Initialization failure, error=%d\n" 176#define msg_button_on "PCI slot #%d - powering on due to button press.\n" 177#define msg_button_off "PCI slot #%d - powering off due to button press.\n" 178#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n" 179 180/* sysfs functions for the hotplug controller info */ 181extern void shpchp_create_ctrl_files (struct controller *ctrl); 182 183/* controller functions */ 184extern int shpchp_event_start_thread(void); 185extern void shpchp_event_stop_thread(void); 186extern int shpchp_enable_slot(struct slot *slot); 187extern int shpchp_disable_slot(struct slot *slot); 188 189extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id); 190extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id); 191extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id); 192extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id); 193 194/* pci functions */ 195extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num); 196extern int shpchp_configure_device(struct slot *p_slot); 197extern int shpchp_unconfigure_device(struct slot *p_slot); 198extern void get_hp_hw_control_from_firmware(struct pci_dev *dev); 199extern void get_hp_params_from_firmware(struct pci_dev *dev, 200 struct hotplug_params *hpp); 201extern int shpchprm_get_physical_slot_number(struct controller *ctrl, 202 u32 *sun, u8 busnum, u8 devnum); 203extern void shpchp_remove_ctrl_files(struct controller *ctrl); 204 205 206/* Global variables */ 207extern struct list_head shpchp_ctrl_list; 208 209struct ctrl_reg { 210 volatile u32 base_offset; 211 volatile u32 slot_avail1; 212 volatile u32 slot_avail2; 213 volatile u32 slot_config; 214 volatile u16 sec_bus_config; 215 volatile u8 msi_ctrl; 216 volatile u8 prog_interface; 217 volatile u16 cmd; 218 volatile u16 cmd_status; 219 volatile u32 intr_loc; 220 volatile u32 serr_loc; 221 volatile u32 serr_intr_enable; 222 volatile u32 slot1; 223 volatile u32 slot2; 224 volatile u32 slot3; 225 volatile u32 slot4; 226 volatile u32 slot5; 227 volatile u32 slot6; 228 volatile u32 slot7; 229 volatile u32 slot8; 230 volatile u32 slot9; 231 volatile u32 slot10; 232 volatile u32 slot11; 233 volatile u32 slot12; 234} __attribute__ ((packed)); 235 236/* offsets to the controller registers based on the above structure layout */ 237enum ctrl_offsets { 238 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 239 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 240 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), 241 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 242 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), 243 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), 244 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 245 CMD = offsetof(struct ctrl_reg, cmd), 246 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), 247 INTR_LOC = offsetof(struct ctrl_reg, intr_loc), 248 SERR_LOC = offsetof(struct ctrl_reg, serr_loc), 249 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable), 250 SLOT1 = offsetof(struct ctrl_reg, slot1), 251 SLOT2 = offsetof(struct ctrl_reg, slot2), 252 SLOT3 = offsetof(struct ctrl_reg, slot3), 253 SLOT4 = offsetof(struct ctrl_reg, slot4), 254 SLOT5 = offsetof(struct ctrl_reg, slot5), 255 SLOT6 = offsetof(struct ctrl_reg, slot6), 256 SLOT7 = offsetof(struct ctrl_reg, slot7), 257 SLOT8 = offsetof(struct ctrl_reg, slot8), 258 SLOT9 = offsetof(struct ctrl_reg, slot9), 259 SLOT10 = offsetof(struct ctrl_reg, slot10), 260 SLOT11 = offsetof(struct ctrl_reg, slot11), 261 SLOT12 = offsetof(struct ctrl_reg, slot12), 262}; 263typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id); 264struct php_ctlr_state_s { 265 struct php_ctlr_state_s *pnext; 266 struct pci_dev *pci_dev; 267 unsigned int irq; 268 unsigned long flags; /* spinlock's */ 269 u32 slot_device_offset; 270 u32 num_slots; 271 struct timer_list int_poll_timer; /* Added for poll event */ 272 php_intr_callback_t attention_button_callback; 273 php_intr_callback_t switch_change_callback; 274 php_intr_callback_t presence_change_callback; 275 php_intr_callback_t power_fault_callback; 276 void *callback_instance_id; 277 void __iomem *creg; /* Ptr to controller register space */ 278}; 279/* Inline functions */ 280 281 282/* Inline functions to check the sanity of a pointer that is passed to us */ 283static inline int slot_paranoia_check (struct slot *slot, const char *function) 284{ 285 if (!slot) { 286 dbg("%s - slot == NULL", function); 287 return -1; 288 } 289 if (slot->magic != SLOT_MAGIC) { 290 dbg("%s - bad magic number for slot", function); 291 return -1; 292 } 293 if (!slot->hotplug_slot) { 294 dbg("%s - slot->hotplug_slot == NULL!", function); 295 return -1; 296 } 297 return 0; 298} 299 300static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function) 301{ 302 struct slot *slot; 303 304 if (!hotplug_slot) { 305 dbg("%s - hotplug_slot == NULL\n", function); 306 return NULL; 307 } 308 309 slot = (struct slot *)hotplug_slot->private; 310 if (slot_paranoia_check (slot, function)) 311 return NULL; 312 return slot; 313} 314 315static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device) 316{ 317 struct slot *slot; 318 319 if (!ctrl) 320 return NULL; 321 322 list_for_each_entry(slot, &ctrl->slot_list, slot_list) { 323 if (slot->device == device) 324 return slot; 325 } 326 327 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device); 328 329 return NULL; 330} 331 332static inline int wait_for_ctrl_irq (struct controller *ctrl) 333{ 334 DECLARE_WAITQUEUE(wait, current); 335 int retval = 0; 336 337 add_wait_queue(&ctrl->queue, &wait); 338 339 if (!shpchp_poll_mode) { 340 /* Sleep for up to 1 second */ 341 msleep_interruptible(1000); 342 } else { 343 /* Sleep for up to 2 seconds */ 344 msleep_interruptible(2000); 345 } 346 remove_wait_queue(&ctrl->queue, &wait); 347 if (signal_pending(current)) 348 retval = -EINTR; 349 350 return retval; 351} 352 353static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot) 354{ 355 u32 pcix_misc2_temp; 356 357 /* save MiscII register */ 358 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 359 360 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; 361 362 /* clear SERR/PERR enable bits */ 363 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 364 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 365 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 366 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 367 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 368 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 369} 370 371static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) 372{ 373 u32 pcix_misc2_temp; 374 u32 pcix_bridge_errors_reg; 375 u32 pcix_mem_base_reg; 376 u8 perr_set; 377 u8 rse_set; 378 379 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */ 380 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 381 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 382 if (perr_set) { 383 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set); 384 385 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 386 } 387 388 /* write-one-to-clear Memory_Base_Limit[ RSE ] */ 389 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 390 rse_set = pcix_mem_base_reg & RSE_MASK; 391 if (rse_set) { 392 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ ); 393 394 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 395 } 396 /* restore MiscII register */ 397 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp ); 398 399 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) 400 pcix_misc2_temp |= SERRFATALENABLE_MASK; 401 else 402 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 403 404 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) 405 pcix_misc2_temp |= SERRNONFATALENABLE_MASK; 406 else 407 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 408 409 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) 410 pcix_misc2_temp |= PERRFLOODENABLE_MASK; 411 else 412 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 413 414 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) 415 pcix_misc2_temp |= PERRFATALENABLE_MASK; 416 else 417 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 418 419 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) 420 pcix_misc2_temp |= PERRNONFATALENABLE_MASK; 421 else 422 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 423 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 424} 425 426enum php_ctlr_type { 427 PCI, 428 ISA, 429 ACPI 430}; 431 432int shpc_init( struct controller *ctrl, struct pci_dev *pdev); 433 434int shpc_get_ctlr_slot_config( struct controller *ctrl, 435 int *num_ctlr_slots, 436 int *first_device_num, 437 int *physical_slot_num, 438 int *updown, 439 int *flags); 440 441struct hpc_ops { 442 int (*power_on_slot ) (struct slot *slot); 443 int (*slot_enable ) (struct slot *slot); 444 int (*slot_disable ) (struct slot *slot); 445 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed); 446 int (*get_power_status) (struct slot *slot, u8 *status); 447 int (*get_attention_status) (struct slot *slot, u8 *status); 448 int (*set_attention_status) (struct slot *slot, u8 status); 449 int (*get_latch_status) (struct slot *slot, u8 *status); 450 int (*get_adapter_status) (struct slot *slot, u8 *status); 451 452 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed); 453 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed); 454 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed); 455 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode); 456 int (*get_prog_int) (struct slot *slot, u8 *prog_int); 457 458 int (*query_power_fault) (struct slot *slot); 459 void (*green_led_on) (struct slot *slot); 460 void (*green_led_off) (struct slot *slot); 461 void (*green_led_blink) (struct slot *slot); 462 void (*release_ctlr) (struct controller *ctrl); 463 int (*check_cmd_status) (struct controller *ctrl); 464}; 465 466#endif /* _SHPCHP_H */ 467