1/* 2 * at91 pinctrl driver based on at91 pinmux core 3 * 4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Under GPLv2 only 7 */ 8 9#include <linux/clk.h> 10#include <linux/err.h> 11#include <linux/init.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/of_device.h> 15#include <linux/of_address.h> 16#include <linux/of_irq.h> 17#include <linux/slab.h> 18#include <linux/interrupt.h> 19#include <linux/io.h> 20#include <linux/gpio.h> 21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25/* Since we request GPIOs from ourself */ 26#include <linux/pinctrl/consumer.h> 27 28#include <mach/hardware.h> 29#include <mach/at91_pio.h> 30 31#include "core.h" 32 33#define MAX_GPIO_BANKS 5 34#define MAX_NB_GPIO_PER_BANK 32 35 36struct at91_pinctrl_mux_ops; 37 38struct at91_gpio_chip { 39 struct gpio_chip chip; 40 struct pinctrl_gpio_range range; 41 struct at91_gpio_chip *next; /* Bank sharing same clock */ 42 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 43 int pioc_virq; /* PIO bank Linux virtual interrupt */ 44 int pioc_idx; /* PIO bank index */ 45 void __iomem *regbase; /* PIO bank virtual address */ 46 struct clk *clock; /* associated clock */ 47 struct at91_pinctrl_mux_ops *ops; /* ops */ 48}; 49 50#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 51 52static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 53 54static int gpio_banks; 55 56#define PULL_UP (1 << 0) 57#define MULTI_DRIVE (1 << 1) 58#define DEGLITCH (1 << 2) 59#define PULL_DOWN (1 << 3) 60#define DIS_SCHMIT (1 << 4) 61#define DRIVE_STRENGTH_SHIFT 5 62#define DRIVE_STRENGTH_MASK 0x3 63#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) 64#define DEBOUNCE (1 << 16) 65#define DEBOUNCE_VAL_SHIFT 17 66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 67 68/** 69 * These defines will translated the dt binding settings to our internal 70 * settings. They are not necessarily the same value as the register setting. 71 * The actual drive strength current of low, medium and high must be looked up 72 * from the corresponding device datasheet. This value is different for pins 73 * that are even in the same banks. It is also dependent on VCC. 74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive 75 * strength when there is no dt config for it. 76 */ 77#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) 78#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) 79#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) 80#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) 81 82/** 83 * struct at91_pmx_func - describes AT91 pinmux functions 84 * @name: the name of this specific function 85 * @groups: corresponding pin groups 86 * @ngroups: the number of groups 87 */ 88struct at91_pmx_func { 89 const char *name; 90 const char **groups; 91 unsigned ngroups; 92}; 93 94enum at91_mux { 95 AT91_MUX_GPIO = 0, 96 AT91_MUX_PERIPH_A = 1, 97 AT91_MUX_PERIPH_B = 2, 98 AT91_MUX_PERIPH_C = 3, 99 AT91_MUX_PERIPH_D = 4, 100}; 101 102/** 103 * struct at91_pmx_pin - describes an At91 pin mux 104 * @bank: the bank of the pin 105 * @pin: the pin number in the @bank 106 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 107 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 108 */ 109struct at91_pmx_pin { 110 uint32_t bank; 111 uint32_t pin; 112 enum at91_mux mux; 113 unsigned long conf; 114}; 115 116/** 117 * struct at91_pin_group - describes an At91 pin group 118 * @name: the name of this specific pin group 119 * @pins_conf: the mux mode for each pin in this group. The size of this 120 * array is the same as pins. 121 * @pins: an array of discrete physical pins used in this group, taken 122 * from the driver-local pin enumeration space 123 * @npins: the number of pins in this group array, i.e. the number of 124 * elements in .pins so we can iterate over that array 125 */ 126struct at91_pin_group { 127 const char *name; 128 struct at91_pmx_pin *pins_conf; 129 unsigned int *pins; 130 unsigned npins; 131}; 132 133/** 134 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 135 * on new IP with support for periph C and D the way to mux in 136 * periph A and B has changed 137 * So provide the right call back 138 * if not present means the IP does not support it 139 * @get_periph: return the periph mode configured 140 * @mux_A_periph: mux as periph A 141 * @mux_B_periph: mux as periph B 142 * @mux_C_periph: mux as periph C 143 * @mux_D_periph: mux as periph D 144 * @get_deglitch: get deglitch status 145 * @set_deglitch: enable/disable deglitch 146 * @get_debounce: get debounce status 147 * @set_debounce: enable/disable debounce 148 * @get_pulldown: get pulldown status 149 * @set_pulldown: enable/disable pulldown 150 * @get_schmitt_trig: get schmitt trigger status 151 * @disable_schmitt_trig: disable schmitt trigger 152 * @irq_type: return irq type 153 */ 154struct at91_pinctrl_mux_ops { 155 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 156 void (*mux_A_periph)(void __iomem *pio, unsigned mask); 157 void (*mux_B_periph)(void __iomem *pio, unsigned mask); 158 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 159 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 160 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 161 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); 162 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 163 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 164 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 165 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 166 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 167 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 168 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); 169 void (*set_drivestrength)(void __iomem *pio, unsigned pin, 170 u32 strength); 171 /* irq */ 172 int (*irq_type)(struct irq_data *d, unsigned type); 173}; 174 175static int gpio_irq_type(struct irq_data *d, unsigned type); 176static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 177 178struct at91_pinctrl { 179 struct device *dev; 180 struct pinctrl_dev *pctl; 181 182 int nbanks; 183 184 uint32_t *mux_mask; 185 int nmux; 186 187 struct at91_pmx_func *functions; 188 int nfunctions; 189 190 struct at91_pin_group *groups; 191 int ngroups; 192 193 struct at91_pinctrl_mux_ops *ops; 194}; 195 196static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 197 const struct at91_pinctrl *info, 198 const char *name) 199{ 200 const struct at91_pin_group *grp = NULL; 201 int i; 202 203 for (i = 0; i < info->ngroups; i++) { 204 if (strcmp(info->groups[i].name, name)) 205 continue; 206 207 grp = &info->groups[i]; 208 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 209 break; 210 } 211 212 return grp; 213} 214 215static int at91_get_groups_count(struct pinctrl_dev *pctldev) 216{ 217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 218 219 return info->ngroups; 220} 221 222static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 223 unsigned selector) 224{ 225 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 226 227 return info->groups[selector].name; 228} 229 230static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 231 const unsigned **pins, 232 unsigned *npins) 233{ 234 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 235 236 if (selector >= info->ngroups) 237 return -EINVAL; 238 239 *pins = info->groups[selector].pins; 240 *npins = info->groups[selector].npins; 241 242 return 0; 243} 244 245static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 246 unsigned offset) 247{ 248 seq_printf(s, "%s", dev_name(pctldev->dev)); 249} 250 251static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 252 struct device_node *np, 253 struct pinctrl_map **map, unsigned *num_maps) 254{ 255 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 256 const struct at91_pin_group *grp; 257 struct pinctrl_map *new_map; 258 struct device_node *parent; 259 int map_num = 1; 260 int i; 261 262 /* 263 * first find the group of this node and check if we need to create 264 * config maps for pins 265 */ 266 grp = at91_pinctrl_find_group_by_name(info, np->name); 267 if (!grp) { 268 dev_err(info->dev, "unable to find group for node %s\n", 269 np->name); 270 return -EINVAL; 271 } 272 273 map_num += grp->npins; 274 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 275 if (!new_map) 276 return -ENOMEM; 277 278 *map = new_map; 279 *num_maps = map_num; 280 281 /* create mux map */ 282 parent = of_get_parent(np); 283 if (!parent) { 284 devm_kfree(pctldev->dev, new_map); 285 return -EINVAL; 286 } 287 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 288 new_map[0].data.mux.function = parent->name; 289 new_map[0].data.mux.group = np->name; 290 of_node_put(parent); 291 292 /* create config map */ 293 new_map++; 294 for (i = 0; i < grp->npins; i++) { 295 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 296 new_map[i].data.configs.group_or_pin = 297 pin_get_name(pctldev, grp->pins[i]); 298 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 299 new_map[i].data.configs.num_configs = 1; 300 } 301 302 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 303 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 304 305 return 0; 306} 307 308static void at91_dt_free_map(struct pinctrl_dev *pctldev, 309 struct pinctrl_map *map, unsigned num_maps) 310{ 311} 312 313static const struct pinctrl_ops at91_pctrl_ops = { 314 .get_groups_count = at91_get_groups_count, 315 .get_group_name = at91_get_group_name, 316 .get_group_pins = at91_get_group_pins, 317 .pin_dbg_show = at91_pin_dbg_show, 318 .dt_node_to_map = at91_dt_node_to_map, 319 .dt_free_map = at91_dt_free_map, 320}; 321 322static void __iomem *pin_to_controller(struct at91_pinctrl *info, 323 unsigned int bank) 324{ 325 return gpio_chips[bank]->regbase; 326} 327 328static inline int pin_to_bank(unsigned pin) 329{ 330 return pin /= MAX_NB_GPIO_PER_BANK; 331} 332 333static unsigned pin_to_mask(unsigned int pin) 334{ 335 return 1 << pin; 336} 337 338static unsigned two_bit_pin_value_shift_amount(unsigned int pin) 339{ 340 /* return the shift value for a pin for "two bit" per pin registers, 341 * i.e. drive strength */ 342 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) 343 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); 344} 345 346static unsigned sama5d3_get_drive_register(unsigned int pin) 347{ 348 /* drive strength is split between two registers 349 * with two bits per pin */ 350 return (pin >= MAX_NB_GPIO_PER_BANK/2) 351 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; 352} 353 354static unsigned at91sam9x5_get_drive_register(unsigned int pin) 355{ 356 /* drive strength is split between two registers 357 * with two bits per pin */ 358 return (pin >= MAX_NB_GPIO_PER_BANK/2) 359 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; 360} 361 362static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 363{ 364 writel_relaxed(mask, pio + PIO_IDR); 365} 366 367static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 368{ 369 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 370} 371 372static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 373{ 374 if (on) 375 writel_relaxed(mask, pio + PIO_PPDDR); 376 377 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 378} 379 380static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 381{ 382 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 383} 384 385static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 386{ 387 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 388} 389 390static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 391{ 392 writel_relaxed(mask, pio + PIO_ASR); 393} 394 395static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 396{ 397 writel_relaxed(mask, pio + PIO_BSR); 398} 399 400static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 401{ 402 403 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 404 pio + PIO_ABCDSR1); 405 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 406 pio + PIO_ABCDSR2); 407} 408 409static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 410{ 411 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 412 pio + PIO_ABCDSR1); 413 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 414 pio + PIO_ABCDSR2); 415} 416 417static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 418{ 419 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 420 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 421} 422 423static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 424{ 425 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 426 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 427} 428 429static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 430{ 431 unsigned select; 432 433 if (readl_relaxed(pio + PIO_PSR) & mask) 434 return AT91_MUX_GPIO; 435 436 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 437 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 438 439 return select + 1; 440} 441 442static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 443{ 444 unsigned select; 445 446 if (readl_relaxed(pio + PIO_PSR) & mask) 447 return AT91_MUX_GPIO; 448 449 select = readl_relaxed(pio + PIO_ABSR) & mask; 450 451 return select + 1; 452} 453 454static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 455{ 456 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 457} 458 459static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 460{ 461 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 462} 463 464static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 465{ 466 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) 467 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 468 469 return false; 470} 471 472static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 473{ 474 if (is_on) 475 __raw_writel(mask, pio + PIO_IFSCDR); 476 at91_mux_set_deglitch(pio, mask, is_on); 477} 478 479static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 480{ 481 *div = __raw_readl(pio + PIO_SCDR); 482 483 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && 484 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 485} 486 487static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 488 bool is_on, u32 div) 489{ 490 if (is_on) { 491 __raw_writel(mask, pio + PIO_IFSCER); 492 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 493 __raw_writel(mask, pio + PIO_IFER); 494 } else 495 __raw_writel(mask, pio + PIO_IFSCDR); 496} 497 498static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 499{ 500 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); 501} 502 503static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 504{ 505 if (is_on) 506 __raw_writel(mask, pio + PIO_PUDR); 507 508 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 509} 510 511static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 512{ 513 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 514} 515 516static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 517{ 518 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 519} 520 521static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 522{ 523 unsigned tmp = __raw_readl(reg); 524 525 tmp = tmp >> two_bit_pin_value_shift_amount(pin); 526 527 return tmp & DRIVE_STRENGTH_MASK; 528} 529 530static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, 531 unsigned pin) 532{ 533 unsigned tmp = read_drive_strength(pio + 534 sama5d3_get_drive_register(pin), pin); 535 536 /* SAMA5 strength is 1:1 with our defines, 537 * except 0 is equivalent to low per datasheet */ 538 if (!tmp) 539 tmp = DRIVE_STRENGTH_LOW; 540 541 return tmp; 542} 543 544static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, 545 unsigned pin) 546{ 547 unsigned tmp = read_drive_strength(pio + 548 at91sam9x5_get_drive_register(pin), pin); 549 550 /* strength is inverse in SAM9x5s hardware with the pinctrl defines 551 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 552 tmp = DRIVE_STRENGTH_HI - tmp; 553 554 return tmp; 555} 556 557static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 558{ 559 unsigned tmp = __raw_readl(reg); 560 unsigned shift = two_bit_pin_value_shift_amount(pin); 561 562 tmp &= ~(DRIVE_STRENGTH_MASK << shift); 563 tmp |= strength << shift; 564 565 __raw_writel(tmp, reg); 566} 567 568static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 569 u32 setting) 570{ 571 /* do nothing if setting is zero */ 572 if (!setting) 573 return; 574 575 /* strength is 1 to 1 with setting for SAMA5 */ 576 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); 577} 578 579static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, 580 u32 setting) 581{ 582 /* do nothing if setting is zero */ 583 if (!setting) 584 return; 585 586 /* strength is inverse on SAM9x5s with our defines 587 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 588 setting = DRIVE_STRENGTH_HI - setting; 589 590 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, 591 setting); 592} 593 594static struct at91_pinctrl_mux_ops at91rm9200_ops = { 595 .get_periph = at91_mux_get_periph, 596 .mux_A_periph = at91_mux_set_A_periph, 597 .mux_B_periph = at91_mux_set_B_periph, 598 .get_deglitch = at91_mux_get_deglitch, 599 .set_deglitch = at91_mux_set_deglitch, 600 .irq_type = gpio_irq_type, 601}; 602 603static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 604 .get_periph = at91_mux_pio3_get_periph, 605 .mux_A_periph = at91_mux_pio3_set_A_periph, 606 .mux_B_periph = at91_mux_pio3_set_B_periph, 607 .mux_C_periph = at91_mux_pio3_set_C_periph, 608 .mux_D_periph = at91_mux_pio3_set_D_periph, 609 .get_deglitch = at91_mux_pio3_get_deglitch, 610 .set_deglitch = at91_mux_pio3_set_deglitch, 611 .get_debounce = at91_mux_pio3_get_debounce, 612 .set_debounce = at91_mux_pio3_set_debounce, 613 .get_pulldown = at91_mux_pio3_get_pulldown, 614 .set_pulldown = at91_mux_pio3_set_pulldown, 615 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 616 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 617 .get_drivestrength = at91_mux_sam9x5_get_drivestrength, 618 .set_drivestrength = at91_mux_sam9x5_set_drivestrength, 619 .irq_type = alt_gpio_irq_type, 620}; 621 622static struct at91_pinctrl_mux_ops sama5d3_ops = { 623 .get_periph = at91_mux_pio3_get_periph, 624 .mux_A_periph = at91_mux_pio3_set_A_periph, 625 .mux_B_periph = at91_mux_pio3_set_B_periph, 626 .mux_C_periph = at91_mux_pio3_set_C_periph, 627 .mux_D_periph = at91_mux_pio3_set_D_periph, 628 .get_deglitch = at91_mux_pio3_get_deglitch, 629 .set_deglitch = at91_mux_pio3_set_deglitch, 630 .get_debounce = at91_mux_pio3_get_debounce, 631 .set_debounce = at91_mux_pio3_set_debounce, 632 .get_pulldown = at91_mux_pio3_get_pulldown, 633 .set_pulldown = at91_mux_pio3_set_pulldown, 634 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 635 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 636 .get_drivestrength = at91_mux_sama5d3_get_drivestrength, 637 .set_drivestrength = at91_mux_sama5d3_set_drivestrength, 638 .irq_type = alt_gpio_irq_type, 639}; 640 641static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 642{ 643 if (pin->mux) { 644 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", 645 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 646 } else { 647 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", 648 pin->bank + 'A', pin->pin, pin->conf); 649 } 650} 651 652static int pin_check_config(struct at91_pinctrl *info, const char *name, 653 int index, const struct at91_pmx_pin *pin) 654{ 655 int mux; 656 657 /* check if it's a valid config */ 658 if (pin->bank >= info->nbanks) { 659 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 660 name, index, pin->bank, info->nbanks); 661 return -EINVAL; 662 } 663 664 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 665 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 666 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 667 return -EINVAL; 668 } 669 670 if (!pin->mux) 671 return 0; 672 673 mux = pin->mux - 1; 674 675 if (mux >= info->nmux) { 676 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 677 name, index, mux, info->nmux); 678 return -EINVAL; 679 } 680 681 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 682 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 683 name, index, mux, pin->bank + 'A', pin->pin); 684 return -EINVAL; 685 } 686 687 return 0; 688} 689 690static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 691{ 692 writel_relaxed(mask, pio + PIO_PDR); 693} 694 695static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 696{ 697 writel_relaxed(mask, pio + PIO_PER); 698 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 699} 700 701static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 702 unsigned group) 703{ 704 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 705 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 706 const struct at91_pmx_pin *pin; 707 uint32_t npins = info->groups[group].npins; 708 int i, ret; 709 unsigned mask; 710 void __iomem *pio; 711 712 dev_dbg(info->dev, "enable function %s group %s\n", 713 info->functions[selector].name, info->groups[group].name); 714 715 /* first check that all the pins of the group are valid with a valid 716 * parameter */ 717 for (i = 0; i < npins; i++) { 718 pin = &pins_conf[i]; 719 ret = pin_check_config(info, info->groups[group].name, i, pin); 720 if (ret) 721 return ret; 722 } 723 724 for (i = 0; i < npins; i++) { 725 pin = &pins_conf[i]; 726 at91_pin_dbg(info->dev, pin); 727 pio = pin_to_controller(info, pin->bank); 728 mask = pin_to_mask(pin->pin); 729 at91_mux_disable_interrupt(pio, mask); 730 switch (pin->mux) { 731 case AT91_MUX_GPIO: 732 at91_mux_gpio_enable(pio, mask, 1); 733 break; 734 case AT91_MUX_PERIPH_A: 735 info->ops->mux_A_periph(pio, mask); 736 break; 737 case AT91_MUX_PERIPH_B: 738 info->ops->mux_B_periph(pio, mask); 739 break; 740 case AT91_MUX_PERIPH_C: 741 if (!info->ops->mux_C_periph) 742 return -EINVAL; 743 info->ops->mux_C_periph(pio, mask); 744 break; 745 case AT91_MUX_PERIPH_D: 746 if (!info->ops->mux_D_periph) 747 return -EINVAL; 748 info->ops->mux_D_periph(pio, mask); 749 break; 750 } 751 if (pin->mux) 752 at91_mux_gpio_disable(pio, mask); 753 } 754 755 return 0; 756} 757 758static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 759{ 760 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 761 762 return info->nfunctions; 763} 764 765static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 766 unsigned selector) 767{ 768 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 769 770 return info->functions[selector].name; 771} 772 773static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 774 const char * const **groups, 775 unsigned * const num_groups) 776{ 777 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 778 779 *groups = info->functions[selector].groups; 780 *num_groups = info->functions[selector].ngroups; 781 782 return 0; 783} 784 785static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 786 struct pinctrl_gpio_range *range, 787 unsigned offset) 788{ 789 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 790 struct at91_gpio_chip *at91_chip; 791 struct gpio_chip *chip; 792 unsigned mask; 793 794 if (!range) { 795 dev_err(npct->dev, "invalid range\n"); 796 return -EINVAL; 797 } 798 if (!range->gc) { 799 dev_err(npct->dev, "missing GPIO chip in range\n"); 800 return -EINVAL; 801 } 802 chip = range->gc; 803 at91_chip = container_of(chip, struct at91_gpio_chip, chip); 804 805 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 806 807 mask = 1 << (offset - chip->base); 808 809 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 810 offset, 'A' + range->id, offset - chip->base, mask); 811 812 writel_relaxed(mask, at91_chip->regbase + PIO_PER); 813 814 return 0; 815} 816 817static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 818 struct pinctrl_gpio_range *range, 819 unsigned offset) 820{ 821 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 822 823 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 824 /* Set the pin to some default state, GPIO is usually default */ 825} 826 827static const struct pinmux_ops at91_pmx_ops = { 828 .get_functions_count = at91_pmx_get_funcs_count, 829 .get_function_name = at91_pmx_get_func_name, 830 .get_function_groups = at91_pmx_get_groups, 831 .set_mux = at91_pmx_set, 832 .gpio_request_enable = at91_gpio_request_enable, 833 .gpio_disable_free = at91_gpio_disable_free, 834}; 835 836static int at91_pinconf_get(struct pinctrl_dev *pctldev, 837 unsigned pin_id, unsigned long *config) 838{ 839 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 840 void __iomem *pio; 841 unsigned pin; 842 int div; 843 844 *config = 0; 845 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 846 pio = pin_to_controller(info, pin_to_bank(pin_id)); 847 pin = pin_id % MAX_NB_GPIO_PER_BANK; 848 849 if (at91_mux_get_multidrive(pio, pin)) 850 *config |= MULTI_DRIVE; 851 852 if (at91_mux_get_pullup(pio, pin)) 853 *config |= PULL_UP; 854 855 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 856 *config |= DEGLITCH; 857 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 858 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 859 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 860 *config |= PULL_DOWN; 861 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 862 *config |= DIS_SCHMIT; 863 if (info->ops->get_drivestrength) 864 *config |= (info->ops->get_drivestrength(pio, pin) 865 << DRIVE_STRENGTH_SHIFT); 866 867 return 0; 868} 869 870static int at91_pinconf_set(struct pinctrl_dev *pctldev, 871 unsigned pin_id, unsigned long *configs, 872 unsigned num_configs) 873{ 874 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 875 unsigned mask; 876 void __iomem *pio; 877 int i; 878 unsigned long config; 879 unsigned pin; 880 881 for (i = 0; i < num_configs; i++) { 882 config = configs[i]; 883 884 dev_dbg(info->dev, 885 "%s:%d, pin_id=%d, config=0x%lx", 886 __func__, __LINE__, pin_id, config); 887 pio = pin_to_controller(info, pin_to_bank(pin_id)); 888 pin = pin_id % MAX_NB_GPIO_PER_BANK; 889 mask = pin_to_mask(pin); 890 891 if (config & PULL_UP && config & PULL_DOWN) 892 return -EINVAL; 893 894 at91_mux_set_pullup(pio, mask, config & PULL_UP); 895 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 896 if (info->ops->set_deglitch) 897 info->ops->set_deglitch(pio, mask, config & DEGLITCH); 898 if (info->ops->set_debounce) 899 info->ops->set_debounce(pio, mask, config & DEBOUNCE, 900 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 901 if (info->ops->set_pulldown) 902 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 903 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 904 info->ops->disable_schmitt_trig(pio, mask); 905 if (info->ops->set_drivestrength) 906 info->ops->set_drivestrength(pio, pin, 907 (config & DRIVE_STRENGTH) 908 >> DRIVE_STRENGTH_SHIFT); 909 910 } /* for each config */ 911 912 return 0; 913} 914 915#define DBG_SHOW_FLAG(flag) do { \ 916 if (config & flag) { \ 917 if (num_conf) \ 918 seq_puts(s, "|"); \ 919 seq_puts(s, #flag); \ 920 num_conf++; \ 921 } \ 922} while (0) 923 924#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \ 925 if ((config & mask) == flag) { \ 926 if (num_conf) \ 927 seq_puts(s, "|"); \ 928 seq_puts(s, #flag); \ 929 num_conf++; \ 930 } \ 931} while (0) 932 933static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 934 struct seq_file *s, unsigned pin_id) 935{ 936 unsigned long config; 937 int val, num_conf = 0; 938 939 at91_pinconf_get(pctldev, pin_id, &config); 940 941 DBG_SHOW_FLAG(MULTI_DRIVE); 942 DBG_SHOW_FLAG(PULL_UP); 943 DBG_SHOW_FLAG(PULL_DOWN); 944 DBG_SHOW_FLAG(DIS_SCHMIT); 945 DBG_SHOW_FLAG(DEGLITCH); 946 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW); 947 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED); 948 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI); 949 DBG_SHOW_FLAG(DEBOUNCE); 950 if (config & DEBOUNCE) { 951 val = config >> DEBOUNCE_VAL_SHIFT; 952 seq_printf(s, "(%d)", val); 953 } 954 955 return; 956} 957 958static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 959 struct seq_file *s, unsigned group) 960{ 961} 962 963static const struct pinconf_ops at91_pinconf_ops = { 964 .pin_config_get = at91_pinconf_get, 965 .pin_config_set = at91_pinconf_set, 966 .pin_config_dbg_show = at91_pinconf_dbg_show, 967 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 968}; 969 970static struct pinctrl_desc at91_pinctrl_desc = { 971 .pctlops = &at91_pctrl_ops, 972 .pmxops = &at91_pmx_ops, 973 .confops = &at91_pinconf_ops, 974 .owner = THIS_MODULE, 975}; 976 977static const char *gpio_compat = "atmel,at91rm9200-gpio"; 978 979static void at91_pinctrl_child_count(struct at91_pinctrl *info, 980 struct device_node *np) 981{ 982 struct device_node *child; 983 984 for_each_child_of_node(np, child) { 985 if (of_device_is_compatible(child, gpio_compat)) { 986 info->nbanks++; 987 } else { 988 info->nfunctions++; 989 info->ngroups += of_get_child_count(child); 990 } 991 } 992} 993 994static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 995 struct device_node *np) 996{ 997 int ret = 0; 998 int size; 999 const __be32 *list; 1000 1001 list = of_get_property(np, "atmel,mux-mask", &size); 1002 if (!list) { 1003 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1004 return -EINVAL; 1005 } 1006 1007 size /= sizeof(*list); 1008 if (!size || size % info->nbanks) { 1009 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 1010 return -EINVAL; 1011 } 1012 info->nmux = size / info->nbanks; 1013 1014 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 1015 if (!info->mux_mask) { 1016 dev_err(info->dev, "could not alloc mux_mask\n"); 1017 return -ENOMEM; 1018 } 1019 1020 ret = of_property_read_u32_array(np, "atmel,mux-mask", 1021 info->mux_mask, size); 1022 if (ret) 1023 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1024 return ret; 1025} 1026 1027static int at91_pinctrl_parse_groups(struct device_node *np, 1028 struct at91_pin_group *grp, 1029 struct at91_pinctrl *info, u32 index) 1030{ 1031 struct at91_pmx_pin *pin; 1032 int size; 1033 const __be32 *list; 1034 int i, j; 1035 1036 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1037 1038 /* Initialise group */ 1039 grp->name = np->name; 1040 1041 /* 1042 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 1043 * do sanity check and calculate pins number 1044 */ 1045 list = of_get_property(np, "atmel,pins", &size); 1046 /* we do not check return since it's safe node passed down */ 1047 size /= sizeof(*list); 1048 if (!size || size % 4) { 1049 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1050 return -EINVAL; 1051 } 1052 1053 grp->npins = size / 4; 1054 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 1055 GFP_KERNEL); 1056 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1057 GFP_KERNEL); 1058 if (!grp->pins_conf || !grp->pins) 1059 return -ENOMEM; 1060 1061 for (i = 0, j = 0; i < size; i += 4, j++) { 1062 pin->bank = be32_to_cpu(*list++); 1063 pin->pin = be32_to_cpu(*list++); 1064 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 1065 pin->mux = be32_to_cpu(*list++); 1066 pin->conf = be32_to_cpu(*list++); 1067 1068 at91_pin_dbg(info->dev, pin); 1069 pin++; 1070 } 1071 1072 return 0; 1073} 1074 1075static int at91_pinctrl_parse_functions(struct device_node *np, 1076 struct at91_pinctrl *info, u32 index) 1077{ 1078 struct device_node *child; 1079 struct at91_pmx_func *func; 1080 struct at91_pin_group *grp; 1081 int ret; 1082 static u32 grp_index; 1083 u32 i = 0; 1084 1085 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1086 1087 func = &info->functions[index]; 1088 1089 /* Initialise function */ 1090 func->name = np->name; 1091 func->ngroups = of_get_child_count(np); 1092 if (func->ngroups == 0) { 1093 dev_err(info->dev, "no groups defined\n"); 1094 return -EINVAL; 1095 } 1096 func->groups = devm_kzalloc(info->dev, 1097 func->ngroups * sizeof(char *), GFP_KERNEL); 1098 if (!func->groups) 1099 return -ENOMEM; 1100 1101 for_each_child_of_node(np, child) { 1102 func->groups[i] = child->name; 1103 grp = &info->groups[grp_index++]; 1104 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 1105 if (ret) 1106 return ret; 1107 } 1108 1109 return 0; 1110} 1111 1112static struct of_device_id at91_pinctrl_of_match[] = { 1113 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 1114 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1115 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1116 { /* sentinel */ } 1117}; 1118 1119static int at91_pinctrl_probe_dt(struct platform_device *pdev, 1120 struct at91_pinctrl *info) 1121{ 1122 int ret = 0; 1123 int i, j; 1124 uint32_t *tmp; 1125 struct device_node *np = pdev->dev.of_node; 1126 struct device_node *child; 1127 1128 if (!np) 1129 return -ENODEV; 1130 1131 info->dev = &pdev->dev; 1132 info->ops = (struct at91_pinctrl_mux_ops *) 1133 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 1134 at91_pinctrl_child_count(info, np); 1135 1136 if (info->nbanks < 1) { 1137 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); 1138 return -EINVAL; 1139 } 1140 1141 ret = at91_pinctrl_mux_mask(info, np); 1142 if (ret) 1143 return ret; 1144 1145 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 1146 1147 dev_dbg(&pdev->dev, "mux-mask\n"); 1148 tmp = info->mux_mask; 1149 for (i = 0; i < info->nbanks; i++) { 1150 for (j = 0; j < info->nmux; j++, tmp++) { 1151 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 1152 } 1153 } 1154 1155 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1156 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1157 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 1158 GFP_KERNEL); 1159 if (!info->functions) 1160 return -ENOMEM; 1161 1162 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 1163 GFP_KERNEL); 1164 if (!info->groups) 1165 return -ENOMEM; 1166 1167 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 1168 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1169 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1170 1171 i = 0; 1172 1173 for_each_child_of_node(np, child) { 1174 if (of_device_is_compatible(child, gpio_compat)) 1175 continue; 1176 ret = at91_pinctrl_parse_functions(child, info, i++); 1177 if (ret) { 1178 dev_err(&pdev->dev, "failed to parse function\n"); 1179 return ret; 1180 } 1181 } 1182 1183 return 0; 1184} 1185 1186static int at91_pinctrl_probe(struct platform_device *pdev) 1187{ 1188 struct at91_pinctrl *info; 1189 struct pinctrl_pin_desc *pdesc; 1190 int ret, i, j, k; 1191 1192 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1193 if (!info) 1194 return -ENOMEM; 1195 1196 ret = at91_pinctrl_probe_dt(pdev, info); 1197 if (ret) 1198 return ret; 1199 1200 /* 1201 * We need all the GPIO drivers to probe FIRST, or we will not be able 1202 * to obtain references to the struct gpio_chip * for them, and we 1203 * need this to proceed. 1204 */ 1205 for (i = 0; i < info->nbanks; i++) { 1206 if (!gpio_chips[i]) { 1207 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1208 devm_kfree(&pdev->dev, info); 1209 return -EPROBE_DEFER; 1210 } 1211 } 1212 1213 at91_pinctrl_desc.name = dev_name(&pdev->dev); 1214 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 1215 at91_pinctrl_desc.pins = pdesc = 1216 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 1217 1218 if (!at91_pinctrl_desc.pins) 1219 return -ENOMEM; 1220 1221 for (i = 0 , k = 0; i < info->nbanks; i++) { 1222 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 1223 pdesc->number = k; 1224 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 1225 pdesc++; 1226 } 1227 } 1228 1229 platform_set_drvdata(pdev, info); 1230 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 1231 1232 if (!info->pctl) { 1233 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1234 ret = -EINVAL; 1235 goto err; 1236 } 1237 1238 /* We will handle a range of GPIO pins */ 1239 for (i = 0; i < info->nbanks; i++) 1240 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1241 1242 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1243 1244 return 0; 1245 1246err: 1247 return ret; 1248} 1249 1250static int at91_pinctrl_remove(struct platform_device *pdev) 1251{ 1252 struct at91_pinctrl *info = platform_get_drvdata(pdev); 1253 1254 pinctrl_unregister(info->pctl); 1255 1256 return 0; 1257} 1258 1259static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 1260{ 1261 /* 1262 * Map back to global GPIO space and request muxing, the direction 1263 * parameter does not matter for this controller. 1264 */ 1265 int gpio = chip->base + offset; 1266 int bank = chip->base / chip->ngpio; 1267 1268 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 1269 'A' + bank, offset, gpio); 1270 1271 return pinctrl_request_gpio(gpio); 1272} 1273 1274static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 1275{ 1276 int gpio = chip->base + offset; 1277 1278 pinctrl_free_gpio(gpio); 1279} 1280 1281static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1282{ 1283 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1284 void __iomem *pio = at91_gpio->regbase; 1285 unsigned mask = 1 << offset; 1286 u32 osr; 1287 1288 osr = readl_relaxed(pio + PIO_OSR); 1289 return !(osr & mask); 1290} 1291 1292static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1293{ 1294 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1295 void __iomem *pio = at91_gpio->regbase; 1296 unsigned mask = 1 << offset; 1297 1298 writel_relaxed(mask, pio + PIO_ODR); 1299 return 0; 1300} 1301 1302static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 1303{ 1304 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1305 void __iomem *pio = at91_gpio->regbase; 1306 unsigned mask = 1 << offset; 1307 u32 pdsr; 1308 1309 pdsr = readl_relaxed(pio + PIO_PDSR); 1310 return (pdsr & mask) != 0; 1311} 1312 1313static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 1314 int val) 1315{ 1316 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1317 void __iomem *pio = at91_gpio->regbase; 1318 unsigned mask = 1 << offset; 1319 1320 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1321} 1322 1323static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1324 int val) 1325{ 1326 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1327 void __iomem *pio = at91_gpio->regbase; 1328 unsigned mask = 1 << offset; 1329 1330 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1331 writel_relaxed(mask, pio + PIO_OER); 1332 1333 return 0; 1334} 1335 1336#ifdef CONFIG_DEBUG_FS 1337static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1338{ 1339 enum at91_mux mode; 1340 int i; 1341 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1342 void __iomem *pio = at91_gpio->regbase; 1343 1344 for (i = 0; i < chip->ngpio; i++) { 1345 unsigned mask = pin_to_mask(i); 1346 const char *gpio_label; 1347 u32 pdsr; 1348 1349 gpio_label = gpiochip_is_requested(chip, i); 1350 if (!gpio_label) 1351 continue; 1352 mode = at91_gpio->ops->get_periph(pio, mask); 1353 seq_printf(s, "[%s] GPIO%s%d: ", 1354 gpio_label, chip->label, i); 1355 if (mode == AT91_MUX_GPIO) { 1356 pdsr = readl_relaxed(pio + PIO_PDSR); 1357 1358 seq_printf(s, "[gpio] %s\n", 1359 pdsr & mask ? 1360 "set" : "clear"); 1361 } else { 1362 seq_printf(s, "[periph %c]\n", 1363 mode + 'A' - 1); 1364 } 1365 } 1366} 1367#else 1368#define at91_gpio_dbg_show NULL 1369#endif 1370 1371/* Several AIC controller irqs are dispatched through this GPIO handler. 1372 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1373 * at91_set_gpio_input() then maybe enable its glitch filter. 1374 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1375 * handler. 1376 * First implementation always triggers on rising and falling edges 1377 * whereas the newer PIO3 can be additionally configured to trigger on 1378 * level, edge with any polarity. 1379 * 1380 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 1381 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 1382 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 1383 */ 1384 1385static void gpio_irq_mask(struct irq_data *d) 1386{ 1387 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1388 void __iomem *pio = at91_gpio->regbase; 1389 unsigned mask = 1 << d->hwirq; 1390 1391 if (pio) 1392 writel_relaxed(mask, pio + PIO_IDR); 1393} 1394 1395static void gpio_irq_unmask(struct irq_data *d) 1396{ 1397 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1398 void __iomem *pio = at91_gpio->regbase; 1399 unsigned mask = 1 << d->hwirq; 1400 1401 if (pio) 1402 writel_relaxed(mask, pio + PIO_IER); 1403} 1404 1405static int gpio_irq_type(struct irq_data *d, unsigned type) 1406{ 1407 switch (type) { 1408 case IRQ_TYPE_NONE: 1409 case IRQ_TYPE_EDGE_BOTH: 1410 return 0; 1411 default: 1412 return -EINVAL; 1413 } 1414} 1415 1416/* Alternate irq type for PIO3 support */ 1417static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 1418{ 1419 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1420 void __iomem *pio = at91_gpio->regbase; 1421 unsigned mask = 1 << d->hwirq; 1422 1423 switch (type) { 1424 case IRQ_TYPE_EDGE_RISING: 1425 __irq_set_handler_locked(d->irq, handle_simple_irq); 1426 writel_relaxed(mask, pio + PIO_ESR); 1427 writel_relaxed(mask, pio + PIO_REHLSR); 1428 break; 1429 case IRQ_TYPE_EDGE_FALLING: 1430 __irq_set_handler_locked(d->irq, handle_simple_irq); 1431 writel_relaxed(mask, pio + PIO_ESR); 1432 writel_relaxed(mask, pio + PIO_FELLSR); 1433 break; 1434 case IRQ_TYPE_LEVEL_LOW: 1435 __irq_set_handler_locked(d->irq, handle_level_irq); 1436 writel_relaxed(mask, pio + PIO_LSR); 1437 writel_relaxed(mask, pio + PIO_FELLSR); 1438 break; 1439 case IRQ_TYPE_LEVEL_HIGH: 1440 __irq_set_handler_locked(d->irq, handle_level_irq); 1441 writel_relaxed(mask, pio + PIO_LSR); 1442 writel_relaxed(mask, pio + PIO_REHLSR); 1443 break; 1444 case IRQ_TYPE_EDGE_BOTH: 1445 /* 1446 * disable additional interrupt modes: 1447 * fall back to default behavior 1448 */ 1449 __irq_set_handler_locked(d->irq, handle_simple_irq); 1450 writel_relaxed(mask, pio + PIO_AIMDR); 1451 return 0; 1452 case IRQ_TYPE_NONE: 1453 default: 1454 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 1455 return -EINVAL; 1456 } 1457 1458 /* enable additional interrupt modes */ 1459 writel_relaxed(mask, pio + PIO_AIMER); 1460 1461 return 0; 1462} 1463 1464static void gpio_irq_ack(struct irq_data *d) 1465{ 1466 /* the interrupt is already cleared before by reading ISR */ 1467} 1468 1469static unsigned int gpio_irq_startup(struct irq_data *d) 1470{ 1471 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1472 unsigned pin = d->hwirq; 1473 int ret; 1474 1475 ret = gpio_lock_as_irq(&at91_gpio->chip, pin); 1476 if (ret) { 1477 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", 1478 d->hwirq); 1479 return ret; 1480 } 1481 gpio_irq_unmask(d); 1482 return 0; 1483} 1484 1485static void gpio_irq_shutdown(struct irq_data *d) 1486{ 1487 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1488 unsigned pin = d->hwirq; 1489 1490 gpio_irq_mask(d); 1491 gpio_unlock_as_irq(&at91_gpio->chip, pin); 1492} 1493 1494#ifdef CONFIG_PM 1495 1496static u32 wakeups[MAX_GPIO_BANKS]; 1497static u32 backups[MAX_GPIO_BANKS]; 1498 1499static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 1500{ 1501 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1502 unsigned bank = at91_gpio->pioc_idx; 1503 unsigned mask = 1 << d->hwirq; 1504 1505 if (unlikely(bank >= MAX_GPIO_BANKS)) 1506 return -EINVAL; 1507 1508 if (state) 1509 wakeups[bank] |= mask; 1510 else 1511 wakeups[bank] &= ~mask; 1512 1513 irq_set_irq_wake(at91_gpio->pioc_virq, state); 1514 1515 return 0; 1516} 1517 1518void at91_pinctrl_gpio_suspend(void) 1519{ 1520 int i; 1521 1522 for (i = 0; i < gpio_banks; i++) { 1523 void __iomem *pio; 1524 1525 if (!gpio_chips[i]) 1526 continue; 1527 1528 pio = gpio_chips[i]->regbase; 1529 1530 backups[i] = __raw_readl(pio + PIO_IMR); 1531 __raw_writel(backups[i], pio + PIO_IDR); 1532 __raw_writel(wakeups[i], pio + PIO_IER); 1533 1534 if (!wakeups[i]) 1535 clk_disable_unprepare(gpio_chips[i]->clock); 1536 else 1537 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1538 'A'+i, wakeups[i]); 1539 } 1540} 1541 1542void at91_pinctrl_gpio_resume(void) 1543{ 1544 int i; 1545 1546 for (i = 0; i < gpio_banks; i++) { 1547 void __iomem *pio; 1548 1549 if (!gpio_chips[i]) 1550 continue; 1551 1552 pio = gpio_chips[i]->regbase; 1553 1554 if (!wakeups[i]) 1555 clk_prepare_enable(gpio_chips[i]->clock); 1556 1557 __raw_writel(wakeups[i], pio + PIO_IDR); 1558 __raw_writel(backups[i], pio + PIO_IER); 1559 } 1560} 1561 1562#else 1563#define gpio_irq_set_wake NULL 1564#endif /* CONFIG_PM */ 1565 1566static struct irq_chip gpio_irqchip = { 1567 .name = "GPIO", 1568 .irq_ack = gpio_irq_ack, 1569 .irq_startup = gpio_irq_startup, 1570 .irq_shutdown = gpio_irq_shutdown, 1571 .irq_disable = gpio_irq_mask, 1572 .irq_mask = gpio_irq_mask, 1573 .irq_unmask = gpio_irq_unmask, 1574 /* .irq_set_type is set dynamically */ 1575 .irq_set_wake = gpio_irq_set_wake, 1576}; 1577 1578static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1579{ 1580 struct irq_chip *chip = irq_get_chip(irq); 1581 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 1582 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, 1583 struct at91_gpio_chip, chip); 1584 1585 void __iomem *pio = at91_gpio->regbase; 1586 unsigned long isr; 1587 int n; 1588 1589 chained_irq_enter(chip, desc); 1590 for (;;) { 1591 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1592 * When there are none pending, we're finished unless we need 1593 * to process multiple banks (like ID_PIOCDE on sam9263). 1594 */ 1595 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1596 if (!isr) { 1597 if (!at91_gpio->next) 1598 break; 1599 at91_gpio = at91_gpio->next; 1600 pio = at91_gpio->regbase; 1601 gpio_chip = &at91_gpio->chip; 1602 continue; 1603 } 1604 1605 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1606 generic_handle_irq(irq_find_mapping( 1607 gpio_chip->irqdomain, n)); 1608 } 1609 } 1610 chained_irq_exit(chip, desc); 1611 /* now it may re-trigger */ 1612} 1613 1614static int at91_gpio_of_irq_setup(struct platform_device *pdev, 1615 struct at91_gpio_chip *at91_gpio) 1616{ 1617 struct at91_gpio_chip *prev = NULL; 1618 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1619 int ret; 1620 1621 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1622 1623 /* Setup proper .irq_set_type function */ 1624 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 1625 1626 /* Disable irqs of this PIO controller */ 1627 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1628 1629 /* 1630 * Let the generic code handle this edge IRQ, the the chained 1631 * handler will perform the actual work of handling the parent 1632 * interrupt. 1633 */ 1634 ret = gpiochip_irqchip_add(&at91_gpio->chip, 1635 &gpio_irqchip, 1636 0, 1637 handle_edge_irq, 1638 IRQ_TYPE_EDGE_BOTH); 1639 if (ret) { 1640 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", 1641 at91_gpio->pioc_idx); 1642 return ret; 1643 } 1644 1645 /* Setup chained handler */ 1646 if (at91_gpio->pioc_idx) 1647 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1648 1649 /* The top level handler handles one bank of GPIOs, except 1650 * on some SoC it can handle up to three... 1651 * We only set up the handler for the first of the list. 1652 */ 1653 if (prev && prev->next == at91_gpio) 1654 return 0; 1655 1656 /* Then register the chain on the parent IRQ */ 1657 gpiochip_set_chained_irqchip(&at91_gpio->chip, 1658 &gpio_irqchip, 1659 at91_gpio->pioc_virq, 1660 gpio_irq_handler); 1661 1662 return 0; 1663} 1664 1665/* This structure is replicated for each GPIO block allocated at probe time */ 1666static struct gpio_chip at91_gpio_template = { 1667 .request = at91_gpio_request, 1668 .free = at91_gpio_free, 1669 .get_direction = at91_gpio_get_direction, 1670 .direction_input = at91_gpio_direction_input, 1671 .get = at91_gpio_get, 1672 .direction_output = at91_gpio_direction_output, 1673 .set = at91_gpio_set, 1674 .dbg_show = at91_gpio_dbg_show, 1675 .can_sleep = false, 1676 .ngpio = MAX_NB_GPIO_PER_BANK, 1677}; 1678 1679static void at91_gpio_probe_fixup(void) 1680{ 1681 unsigned i; 1682 struct at91_gpio_chip *at91_gpio, *last = NULL; 1683 1684 for (i = 0; i < gpio_banks; i++) { 1685 at91_gpio = gpio_chips[i]; 1686 1687 /* 1688 * GPIO controller are grouped on some SoC: 1689 * PIOC, PIOD and PIOE can share the same IRQ line 1690 */ 1691 if (last && last->pioc_virq == at91_gpio->pioc_virq) 1692 last->next = at91_gpio; 1693 last = at91_gpio; 1694 } 1695} 1696 1697static struct of_device_id at91_gpio_of_match[] = { 1698 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1699 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1700 { /* sentinel */ } 1701}; 1702 1703static int at91_gpio_probe(struct platform_device *pdev) 1704{ 1705 struct device_node *np = pdev->dev.of_node; 1706 struct resource *res; 1707 struct at91_gpio_chip *at91_chip = NULL; 1708 struct gpio_chip *chip; 1709 struct pinctrl_gpio_range *range; 1710 int ret = 0; 1711 int irq, i; 1712 int alias_idx = of_alias_get_id(np, "gpio"); 1713 uint32_t ngpio; 1714 char **names; 1715 1716 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1717 if (gpio_chips[alias_idx]) { 1718 ret = -EBUSY; 1719 goto err; 1720 } 1721 1722 irq = platform_get_irq(pdev, 0); 1723 if (irq < 0) { 1724 ret = irq; 1725 goto err; 1726 } 1727 1728 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 1729 if (!at91_chip) { 1730 ret = -ENOMEM; 1731 goto err; 1732 } 1733 1734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1735 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1736 if (IS_ERR(at91_chip->regbase)) { 1737 ret = PTR_ERR(at91_chip->regbase); 1738 goto err; 1739 } 1740 1741 at91_chip->ops = (struct at91_pinctrl_mux_ops *) 1742 of_match_device(at91_gpio_of_match, &pdev->dev)->data; 1743 at91_chip->pioc_virq = irq; 1744 at91_chip->pioc_idx = alias_idx; 1745 1746 at91_chip->clock = devm_clk_get(&pdev->dev, NULL); 1747 if (IS_ERR(at91_chip->clock)) { 1748 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1749 ret = PTR_ERR(at91_chip->clock); 1750 goto err; 1751 } 1752 1753 ret = clk_prepare(at91_chip->clock); 1754 if (ret) 1755 goto clk_prepare_err; 1756 1757 /* enable PIO controller's clock */ 1758 ret = clk_enable(at91_chip->clock); 1759 if (ret) { 1760 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1761 goto clk_enable_err; 1762 } 1763 1764 at91_chip->chip = at91_gpio_template; 1765 1766 chip = &at91_chip->chip; 1767 chip->of_node = np; 1768 chip->label = dev_name(&pdev->dev); 1769 chip->dev = &pdev->dev; 1770 chip->owner = THIS_MODULE; 1771 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1772 1773 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1774 if (ngpio >= MAX_NB_GPIO_PER_BANK) 1775 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 1776 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 1777 else 1778 chip->ngpio = ngpio; 1779 } 1780 1781 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 1782 GFP_KERNEL); 1783 1784 if (!names) { 1785 ret = -ENOMEM; 1786 goto clk_enable_err; 1787 } 1788 1789 for (i = 0; i < chip->ngpio; i++) 1790 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 1791 1792 chip->names = (const char *const *)names; 1793 1794 range = &at91_chip->range; 1795 range->name = chip->label; 1796 range->id = alias_idx; 1797 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1798 1799 range->npins = chip->ngpio; 1800 range->gc = chip; 1801 1802 ret = gpiochip_add(chip); 1803 if (ret) 1804 goto gpiochip_add_err; 1805 1806 gpio_chips[alias_idx] = at91_chip; 1807 gpio_banks = max(gpio_banks, alias_idx + 1); 1808 1809 at91_gpio_probe_fixup(); 1810 1811 ret = at91_gpio_of_irq_setup(pdev, at91_chip); 1812 if (ret) 1813 goto irq_setup_err; 1814 1815 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1816 1817 return 0; 1818 1819irq_setup_err: 1820 gpiochip_remove(chip); 1821gpiochip_add_err: 1822 clk_disable(at91_chip->clock); 1823clk_enable_err: 1824 clk_unprepare(at91_chip->clock); 1825clk_prepare_err: 1826err: 1827 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1828 1829 return ret; 1830} 1831 1832static struct platform_driver at91_gpio_driver = { 1833 .driver = { 1834 .name = "gpio-at91", 1835 .owner = THIS_MODULE, 1836 .of_match_table = at91_gpio_of_match, 1837 }, 1838 .probe = at91_gpio_probe, 1839}; 1840 1841static struct platform_driver at91_pinctrl_driver = { 1842 .driver = { 1843 .name = "pinctrl-at91", 1844 .owner = THIS_MODULE, 1845 .of_match_table = at91_pinctrl_of_match, 1846 }, 1847 .probe = at91_pinctrl_probe, 1848 .remove = at91_pinctrl_remove, 1849}; 1850 1851static int __init at91_pinctrl_init(void) 1852{ 1853 int ret; 1854 1855 ret = platform_driver_register(&at91_gpio_driver); 1856 if (ret) 1857 return ret; 1858 return platform_driver_register(&at91_pinctrl_driver); 1859} 1860arch_initcall(at91_pinctrl_init); 1861 1862static void __exit at91_pinctrl_exit(void) 1863{ 1864 platform_driver_unregister(&at91_pinctrl_driver); 1865} 1866 1867module_exit(at91_pinctrl_exit); 1868MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 1869MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 1870MODULE_LICENSE("GPL v2"); 1871