1/* 2 * U300 GPIO module. 3 * 4 * Copyright (C) 2007-2012 ST-Ericsson AB 5 * License terms: GNU General Public License (GPL) version 2 6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 7 * Author: Linus Walleij <linus.walleij@linaro.org> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 9 */ 10#include <linux/module.h> 11#include <linux/interrupt.h> 12#include <linux/delay.h> 13#include <linux/errno.h> 14#include <linux/io.h> 15#include <linux/clk.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/gpio.h> 19#include <linux/slab.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/pinctrl/pinconf-generic.h> 22#include "pinctrl-coh901.h" 23 24#define U300_GPIO_PORT_STRIDE (0x30) 25/* 26 * Control Register 32bit (R/W) 27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores 28 * gives the number of GPIO pins. 29 * bit 8-2 (mask 0x000001FC) contains the core version ID. 30 */ 31#define U300_GPIO_CR (0x00) 32#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) 33#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) 34#define U300_GPIO_PXPDIR (0x04) 35#define U300_GPIO_PXPDOR (0x08) 36#define U300_GPIO_PXPCR (0x0C) 37#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) 38#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) 39#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) 40#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) 41#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) 42#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) 43#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) 44#define U300_GPIO_PXPER (0x10) 45#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) 46#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) 47#define U300_GPIO_PXIEV (0x14) 48#define U300_GPIO_PXIEN (0x18) 49#define U300_GPIO_PXIFR (0x1C) 50#define U300_GPIO_PXICR (0x20) 51#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) 52#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) 53#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) 54#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) 55 56/* 8 bits per port, no version has more than 7 ports */ 57#define U300_GPIO_NUM_PORTS 7 58#define U300_GPIO_PINS_PER_PORT 8 59#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) 60 61struct u300_gpio_port { 62 struct u300_gpio *gpio; 63 char name[8]; 64 int irq; 65 int number; 66 u8 toggle_edge_mode; 67}; 68 69struct u300_gpio { 70 struct gpio_chip chip; 71 struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; 72 struct clk *clk; 73 void __iomem *base; 74 struct device *dev; 75 u32 stride; 76 /* Register offsets */ 77 u32 pcr; 78 u32 dor; 79 u32 dir; 80 u32 per; 81 u32 icr; 82 u32 ien; 83 u32 iev; 84}; 85 86/* 87 * Macro to expand to read a specific register found in the "gpio" 88 * struct. It requires the struct u300_gpio *gpio variable to exist in 89 * its context. It calculates the port offset from the given pin 90 * offset, muliplies by the port stride and adds the register offset 91 * so it provides a pointer to the desired register. 92 */ 93#define U300_PIN_REG(pin, reg) \ 94 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) 95 96/* 97 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO 98 * register. 99 */ 100#define U300_PIN_BIT(pin) \ 101 (1 << (pin & 0x07)) 102 103struct u300_gpio_confdata { 104 u16 bias_mode; 105 bool output; 106 int outval; 107}; 108 109#define U300_FLOATING_INPUT { \ 110 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ 111 .output = false, \ 112} 113 114#define U300_PULL_UP_INPUT { \ 115 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ 116 .output = false, \ 117} 118 119#define U300_OUTPUT_LOW { \ 120 .output = true, \ 121 .outval = 0, \ 122} 123 124#define U300_OUTPUT_HIGH { \ 125 .output = true, \ 126 .outval = 1, \ 127} 128 129/* Initial configuration */ 130static const struct __initconst u300_gpio_confdata 131bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 132 /* Port 0, pins 0-7 */ 133 { 134 U300_FLOATING_INPUT, 135 U300_OUTPUT_HIGH, 136 U300_FLOATING_INPUT, 137 U300_OUTPUT_LOW, 138 U300_OUTPUT_LOW, 139 U300_OUTPUT_LOW, 140 U300_OUTPUT_LOW, 141 U300_OUTPUT_LOW, 142 }, 143 /* Port 1, pins 0-7 */ 144 { 145 U300_OUTPUT_LOW, 146 U300_OUTPUT_LOW, 147 U300_OUTPUT_LOW, 148 U300_PULL_UP_INPUT, 149 U300_FLOATING_INPUT, 150 U300_OUTPUT_HIGH, 151 U300_OUTPUT_LOW, 152 U300_OUTPUT_LOW, 153 }, 154 /* Port 2, pins 0-7 */ 155 { 156 U300_FLOATING_INPUT, 157 U300_FLOATING_INPUT, 158 U300_FLOATING_INPUT, 159 U300_FLOATING_INPUT, 160 U300_OUTPUT_LOW, 161 U300_PULL_UP_INPUT, 162 U300_OUTPUT_LOW, 163 U300_PULL_UP_INPUT, 164 }, 165 /* Port 3, pins 0-7 */ 166 { 167 U300_PULL_UP_INPUT, 168 U300_OUTPUT_LOW, 169 U300_FLOATING_INPUT, 170 U300_FLOATING_INPUT, 171 U300_FLOATING_INPUT, 172 U300_FLOATING_INPUT, 173 U300_FLOATING_INPUT, 174 U300_FLOATING_INPUT, 175 }, 176 /* Port 4, pins 0-7 */ 177 { 178 U300_FLOATING_INPUT, 179 U300_FLOATING_INPUT, 180 U300_FLOATING_INPUT, 181 U300_FLOATING_INPUT, 182 U300_FLOATING_INPUT, 183 U300_FLOATING_INPUT, 184 U300_FLOATING_INPUT, 185 U300_FLOATING_INPUT, 186 }, 187 /* Port 5, pins 0-7 */ 188 { 189 U300_FLOATING_INPUT, 190 U300_FLOATING_INPUT, 191 U300_FLOATING_INPUT, 192 U300_FLOATING_INPUT, 193 U300_FLOATING_INPUT, 194 U300_FLOATING_INPUT, 195 U300_FLOATING_INPUT, 196 U300_FLOATING_INPUT, 197 }, 198 /* Port 6, pind 0-7 */ 199 { 200 U300_FLOATING_INPUT, 201 U300_FLOATING_INPUT, 202 U300_FLOATING_INPUT, 203 U300_FLOATING_INPUT, 204 U300_FLOATING_INPUT, 205 U300_FLOATING_INPUT, 206 U300_FLOATING_INPUT, 207 U300_FLOATING_INPUT, 208 } 209}; 210 211/** 212 * to_u300_gpio() - get the pointer to u300_gpio 213 * @chip: the gpio chip member of the structure u300_gpio 214 */ 215static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) 216{ 217 return container_of(chip, struct u300_gpio, chip); 218} 219 220static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) 221{ 222 /* 223 * Map back to global GPIO space and request muxing, the direction 224 * parameter does not matter for this controller. 225 */ 226 int gpio = chip->base + offset; 227 228 return pinctrl_request_gpio(gpio); 229} 230 231static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) 232{ 233 int gpio = chip->base + offset; 234 235 pinctrl_free_gpio(gpio); 236} 237 238static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) 239{ 240 struct u300_gpio *gpio = to_u300_gpio(chip); 241 242 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); 243} 244 245static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 246{ 247 struct u300_gpio *gpio = to_u300_gpio(chip); 248 unsigned long flags; 249 u32 val; 250 251 local_irq_save(flags); 252 253 val = readl(U300_PIN_REG(offset, dor)); 254 if (value) 255 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 256 else 257 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 258 259 local_irq_restore(flags); 260} 261 262static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 263{ 264 struct u300_gpio *gpio = to_u300_gpio(chip); 265 unsigned long flags; 266 u32 val; 267 268 local_irq_save(flags); 269 val = readl(U300_PIN_REG(offset, pcr)); 270 /* Mask out this pin, note 2 bits per setting */ 271 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 272 writel(val, U300_PIN_REG(offset, pcr)); 273 local_irq_restore(flags); 274 return 0; 275} 276 277static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 278 int value) 279{ 280 struct u300_gpio *gpio = to_u300_gpio(chip); 281 unsigned long flags; 282 u32 oldmode; 283 u32 val; 284 285 local_irq_save(flags); 286 val = readl(U300_PIN_REG(offset, pcr)); 287 /* 288 * Drive mode must be set by the special mode set function, set 289 * push/pull mode by default if no mode has been selected. 290 */ 291 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << 292 ((offset & 0x07) << 1)); 293 /* mode = 0 means input, else some mode is already set */ 294 if (oldmode == 0) { 295 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << 296 ((offset & 0x07) << 1)); 297 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 298 << ((offset & 0x07) << 1)); 299 writel(val, U300_PIN_REG(offset, pcr)); 300 } 301 u300_gpio_set(chip, offset, value); 302 local_irq_restore(flags); 303 return 0; 304} 305 306/* Returning -EINVAL means "supported but not available" */ 307int u300_gpio_config_get(struct gpio_chip *chip, 308 unsigned offset, 309 unsigned long *config) 310{ 311 struct u300_gpio *gpio = to_u300_gpio(chip); 312 enum pin_config_param param = (enum pin_config_param) *config; 313 bool biasmode; 314 u32 drmode; 315 316 /* One bit per pin, clamp to bool range */ 317 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); 318 319 /* Mask out the two bits for this pin and shift to bits 0,1 */ 320 drmode = readl(U300_PIN_REG(offset, pcr)); 321 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 322 drmode >>= ((offset & 0x07) << 1); 323 324 switch (param) { 325 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 326 *config = 0; 327 if (biasmode) 328 return 0; 329 else 330 return -EINVAL; 331 break; 332 case PIN_CONFIG_BIAS_PULL_UP: 333 *config = 0; 334 if (!biasmode) 335 return 0; 336 else 337 return -EINVAL; 338 break; 339 case PIN_CONFIG_DRIVE_PUSH_PULL: 340 *config = 0; 341 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) 342 return 0; 343 else 344 return -EINVAL; 345 break; 346 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 347 *config = 0; 348 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) 349 return 0; 350 else 351 return -EINVAL; 352 break; 353 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 354 *config = 0; 355 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) 356 return 0; 357 else 358 return -EINVAL; 359 break; 360 default: 361 break; 362 } 363 return -ENOTSUPP; 364} 365 366int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, 367 enum pin_config_param param) 368{ 369 struct u300_gpio *gpio = to_u300_gpio(chip); 370 unsigned long flags; 371 u32 val; 372 373 local_irq_save(flags); 374 switch (param) { 375 case PIN_CONFIG_BIAS_DISABLE: 376 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 377 val = readl(U300_PIN_REG(offset, per)); 378 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 379 break; 380 case PIN_CONFIG_BIAS_PULL_UP: 381 val = readl(U300_PIN_REG(offset, per)); 382 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 383 break; 384 case PIN_CONFIG_DRIVE_PUSH_PULL: 385 val = readl(U300_PIN_REG(offset, pcr)); 386 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 387 << ((offset & 0x07) << 1)); 388 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 389 << ((offset & 0x07) << 1)); 390 writel(val, U300_PIN_REG(offset, pcr)); 391 break; 392 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 393 val = readl(U300_PIN_REG(offset, pcr)); 394 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 395 << ((offset & 0x07) << 1)); 396 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN 397 << ((offset & 0x07) << 1)); 398 writel(val, U300_PIN_REG(offset, pcr)); 399 break; 400 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 401 val = readl(U300_PIN_REG(offset, pcr)); 402 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 403 << ((offset & 0x07) << 1)); 404 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE 405 << ((offset & 0x07) << 1)); 406 writel(val, U300_PIN_REG(offset, pcr)); 407 break; 408 default: 409 local_irq_restore(flags); 410 dev_err(gpio->dev, "illegal configuration requested\n"); 411 return -EINVAL; 412 } 413 local_irq_restore(flags); 414 return 0; 415} 416 417static struct gpio_chip u300_gpio_chip = { 418 .label = "u300-gpio-chip", 419 .owner = THIS_MODULE, 420 .request = u300_gpio_request, 421 .free = u300_gpio_free, 422 .get = u300_gpio_get, 423 .set = u300_gpio_set, 424 .direction_input = u300_gpio_direction_input, 425 .direction_output = u300_gpio_direction_output, 426}; 427 428static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) 429{ 430 u32 val; 431 432 val = readl(U300_PIN_REG(offset, icr)); 433 /* Set mode depending on state */ 434 if (u300_gpio_get(&gpio->chip, offset)) { 435 /* High now, let's trigger on falling edge next then */ 436 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 437 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", 438 offset); 439 } else { 440 /* Low now, let's trigger on rising edge next then */ 441 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 442 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", 443 offset); 444 } 445} 446 447static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) 448{ 449 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 450 struct u300_gpio *gpio = to_u300_gpio(chip); 451 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 452 int offset = d->hwirq; 453 u32 val; 454 455 if ((trigger & IRQF_TRIGGER_RISING) && 456 (trigger & IRQF_TRIGGER_FALLING)) { 457 /* 458 * The GPIO block can only trigger on falling OR rising edges, 459 * not both. So we need to toggle the mode whenever the pin 460 * goes from one state to the other with a special state flag 461 */ 462 dev_dbg(gpio->dev, 463 "trigger on both rising and falling edge on pin %d\n", 464 offset); 465 port->toggle_edge_mode |= U300_PIN_BIT(offset); 466 u300_toggle_trigger(gpio, offset); 467 } else if (trigger & IRQF_TRIGGER_RISING) { 468 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", 469 offset); 470 val = readl(U300_PIN_REG(offset, icr)); 471 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 472 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 473 } else if (trigger & IRQF_TRIGGER_FALLING) { 474 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", 475 offset); 476 val = readl(U300_PIN_REG(offset, icr)); 477 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 478 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 479 } 480 481 return 0; 482} 483 484static void u300_gpio_irq_enable(struct irq_data *d) 485{ 486 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 487 struct u300_gpio *gpio = to_u300_gpio(chip); 488 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 489 int offset = d->hwirq; 490 u32 val; 491 unsigned long flags; 492 493 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", 494 d->hwirq, port->name, offset); 495 local_irq_save(flags); 496 val = readl(U300_PIN_REG(offset, ien)); 497 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 498 local_irq_restore(flags); 499} 500 501static void u300_gpio_irq_disable(struct irq_data *d) 502{ 503 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 504 struct u300_gpio *gpio = to_u300_gpio(chip); 505 int offset = d->hwirq; 506 u32 val; 507 unsigned long flags; 508 509 local_irq_save(flags); 510 val = readl(U300_PIN_REG(offset, ien)); 511 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 512 local_irq_restore(flags); 513} 514 515static struct irq_chip u300_gpio_irqchip = { 516 .name = "u300-gpio-irqchip", 517 .irq_enable = u300_gpio_irq_enable, 518 .irq_disable = u300_gpio_irq_disable, 519 .irq_set_type = u300_gpio_irq_type, 520}; 521 522static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 523{ 524 struct irq_chip *parent_chip = irq_get_chip(irq); 525 struct gpio_chip *chip = irq_get_handler_data(irq); 526 struct u300_gpio *gpio = to_u300_gpio(chip); 527 struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; 528 int pinoffset = port->number << 3; /* get the right stride */ 529 unsigned long val; 530 531 chained_irq_enter(parent_chip, desc); 532 533 /* Read event register */ 534 val = readl(U300_PIN_REG(pinoffset, iev)); 535 /* Mask relevant bits */ 536 val &= 0xFFU; /* 8 bits per port */ 537 /* ACK IRQ (clear event) */ 538 writel(val, U300_PIN_REG(pinoffset, iev)); 539 540 /* Call IRQ handler */ 541 if (val != 0) { 542 int irqoffset; 543 544 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { 545 int offset = pinoffset + irqoffset; 546 int pin_irq = irq_find_mapping(chip->irqdomain, offset); 547 548 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", 549 pin_irq, offset); 550 generic_handle_irq(pin_irq); 551 /* 552 * Triggering IRQ on both rising and falling edge 553 * needs mockery 554 */ 555 if (port->toggle_edge_mode & U300_PIN_BIT(offset)) 556 u300_toggle_trigger(gpio, offset); 557 } 558 } 559 560 chained_irq_exit(parent_chip, desc); 561} 562 563static void __init u300_gpio_init_pin(struct u300_gpio *gpio, 564 int offset, 565 const struct u300_gpio_confdata *conf) 566{ 567 /* Set mode: input or output */ 568 if (conf->output) { 569 u300_gpio_direction_output(&gpio->chip, offset, conf->outval); 570 571 /* Deactivate bias mode for output */ 572 u300_gpio_config_set(&gpio->chip, offset, 573 PIN_CONFIG_BIAS_HIGH_IMPEDANCE); 574 575 /* Set drive mode for output */ 576 u300_gpio_config_set(&gpio->chip, offset, 577 PIN_CONFIG_DRIVE_PUSH_PULL); 578 579 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", 580 offset, conf->outval); 581 } else { 582 u300_gpio_direction_input(&gpio->chip, offset); 583 584 /* Always set output low on input pins */ 585 u300_gpio_set(&gpio->chip, offset, 0); 586 587 /* Set bias mode for input */ 588 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); 589 590 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", 591 offset, conf->bias_mode); 592 } 593} 594 595static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) 596{ 597 int i, j; 598 599 /* Write default config and values to all pins */ 600 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 601 for (j = 0; j < 8; j++) { 602 const struct u300_gpio_confdata *conf; 603 int offset = (i*8) + j; 604 605 conf = &bs335_gpio_config[i][j]; 606 u300_gpio_init_pin(gpio, offset, conf); 607 } 608 } 609} 610 611/* 612 * Here we map a GPIO in the local gpio_chip pin space to a pin in 613 * the local pinctrl pin space. The pin controller used is 614 * pinctrl-u300. 615 */ 616struct coh901_pinpair { 617 unsigned int offset; 618 unsigned int pin_base; 619}; 620 621#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } 622 623static struct coh901_pinpair coh901_pintable[] = { 624 COH901_PINRANGE(10, 426), 625 COH901_PINRANGE(11, 180), 626 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ 627 COH901_PINRANGE(13, 179), 628 COH901_PINRANGE(14, 178), 629 COH901_PINRANGE(16, 194), 630 COH901_PINRANGE(17, 193), 631 COH901_PINRANGE(18, 192), 632 COH901_PINRANGE(19, 191), 633 COH901_PINRANGE(20, 186), 634 COH901_PINRANGE(21, 185), 635 COH901_PINRANGE(22, 184), 636 COH901_PINRANGE(23, 183), 637 COH901_PINRANGE(24, 182), 638 COH901_PINRANGE(25, 181), 639}; 640 641static int __init u300_gpio_probe(struct platform_device *pdev) 642{ 643 struct u300_gpio *gpio; 644 struct resource *memres; 645 int err = 0; 646 int portno; 647 u32 val; 648 u32 ifr; 649 int i; 650 651 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); 652 if (gpio == NULL) 653 return -ENOMEM; 654 655 gpio->chip = u300_gpio_chip; 656 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; 657 gpio->chip.dev = &pdev->dev; 658 gpio->chip.base = 0; 659 gpio->dev = &pdev->dev; 660 661 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 gpio->base = devm_ioremap_resource(&pdev->dev, memres); 663 if (IS_ERR(gpio->base)) 664 return PTR_ERR(gpio->base); 665 666 gpio->clk = devm_clk_get(gpio->dev, NULL); 667 if (IS_ERR(gpio->clk)) { 668 err = PTR_ERR(gpio->clk); 669 dev_err(gpio->dev, "could not get GPIO clock\n"); 670 return err; 671 } 672 673 err = clk_prepare_enable(gpio->clk); 674 if (err) { 675 dev_err(gpio->dev, "could not enable GPIO clock\n"); 676 return err; 677 } 678 679 dev_info(gpio->dev, 680 "initializing GPIO Controller COH 901 571/3\n"); 681 gpio->stride = U300_GPIO_PORT_STRIDE; 682 gpio->pcr = U300_GPIO_PXPCR; 683 gpio->dor = U300_GPIO_PXPDOR; 684 gpio->dir = U300_GPIO_PXPDIR; 685 gpio->per = U300_GPIO_PXPER; 686 gpio->icr = U300_GPIO_PXICR; 687 gpio->ien = U300_GPIO_PXIEN; 688 gpio->iev = U300_GPIO_PXIEV; 689 ifr = U300_GPIO_PXIFR; 690 691 val = readl(gpio->base + U300_GPIO_CR); 692 dev_info(gpio->dev, "COH901571/3 block version: %d, " \ 693 "number of cores: %d totalling %d pins\n", 694 ((val & 0x000001FC) >> 2), 695 ((val & 0x0000FE00) >> 9), 696 ((val & 0x0000FE00) >> 9) * 8); 697 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, 698 gpio->base + U300_GPIO_CR); 699 u300_gpio_init_coh901571(gpio); 700 701#ifdef CONFIG_OF_GPIO 702 gpio->chip.of_node = pdev->dev.of_node; 703#endif 704 err = gpiochip_add(&gpio->chip); 705 if (err) { 706 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); 707 goto err_no_chip; 708 } 709 710 err = gpiochip_irqchip_add(&gpio->chip, 711 &u300_gpio_irqchip, 712 0, 713 handle_simple_irq, 714 IRQ_TYPE_EDGE_FALLING); 715 if (err) { 716 dev_err(gpio->dev, "no GPIO irqchip\n"); 717 goto err_no_irqchip; 718 } 719 720 /* Add each port with its IRQ separately */ 721 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { 722 struct u300_gpio_port *port = &gpio->ports[portno]; 723 724 snprintf(port->name, 8, "gpio%d", portno); 725 port->number = portno; 726 port->gpio = gpio; 727 728 port->irq = platform_get_irq(pdev, portno); 729 730 gpiochip_set_chained_irqchip(&gpio->chip, 731 &u300_gpio_irqchip, 732 port->irq, 733 u300_gpio_irq_handler); 734 735 /* Turns off irq force (test register) for this port */ 736 writel(0x0, gpio->base + portno * gpio->stride + ifr); 737 } 738 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); 739 740 /* 741 * Add pinctrl pin ranges, the pin controller must be registered 742 * at this point 743 */ 744 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { 745 struct coh901_pinpair *p = &coh901_pintable[i]; 746 747 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", 748 p->offset, p->pin_base, 1); 749 if (err) 750 goto err_no_range; 751 } 752 753 platform_set_drvdata(pdev, gpio); 754 755 return 0; 756 757err_no_range: 758err_no_irqchip: 759 gpiochip_remove(&gpio->chip); 760err_no_chip: 761 clk_disable_unprepare(gpio->clk); 762 dev_err(&pdev->dev, "module ERROR:%d\n", err); 763 return err; 764} 765 766static int __exit u300_gpio_remove(struct platform_device *pdev) 767{ 768 struct u300_gpio *gpio = platform_get_drvdata(pdev); 769 770 /* Turn off the GPIO block */ 771 writel(0x00000000U, gpio->base + U300_GPIO_CR); 772 773 gpiochip_remove(&gpio->chip); 774 clk_disable_unprepare(gpio->clk); 775 return 0; 776} 777 778static const struct of_device_id u300_gpio_match[] = { 779 { .compatible = "stericsson,gpio-coh901" }, 780 {}, 781}; 782 783static struct platform_driver u300_gpio_driver = { 784 .driver = { 785 .name = "u300-gpio", 786 .of_match_table = u300_gpio_match, 787 }, 788 .remove = __exit_p(u300_gpio_remove), 789}; 790 791static int __init u300_gpio_init(void) 792{ 793 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); 794} 795 796static void __exit u300_gpio_exit(void) 797{ 798 platform_driver_unregister(&u300_gpio_driver); 799} 800 801arch_initcall(u300_gpio_init); 802module_exit(u300_gpio_exit); 803 804MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 805MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); 806MODULE_LICENSE("GPL"); 807