198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* 298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Driver for the U300 pin controller 398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Based on the original U300 padmux functions 598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Copyright (C) 2009-2011 ST-Ericsson AB 698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Author: Martin Persson <martin.persson@stericsson.com> 798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Author: Linus Walleij <linus.walleij@linaro.org> 898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * The DB3350 design and control registers are oriented around pads rather than 1098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * pins, so we enumerate the pads we can mux rather than actual pins. The pads 1198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * are connected to different pins in different packaging types, so it would 1298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * be confusing. 1398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 1498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/init.h> 1598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/module.h> 1698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/platform_device.h> 1798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/io.h> 1898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/slab.h> 1998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/err.h> 2098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/pinctrl/pinctrl.h> 2198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#include <linux/pinctrl/pinmux.h> 22dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij#include <linux/pinctrl/pinconf.h> 23dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij#include <linux/pinctrl/pinconf-generic.h> 24dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij#include "pinctrl-coh901.h" 2598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 2698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* 2798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Register definitions for the U300 Padmux control registers in the 2898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * system controller 2998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 3098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 3198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ 3298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR 0x007C 3398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MASK 0xFFFF 3498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_MASK 0xC000 3598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_CDI 0x0000 3698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000 3798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* For BS335 */ 3898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000 3998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000 4098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* For BS365 */ 4198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000 4298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000 4398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* Common defs */ 4498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_PDI_MASK 0x3000 4598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_PDI_PDI 0x0000 4698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_PDI_EGG 0x1000 4798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000 4898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00 4998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000 5098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400 5198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800 5298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00 5398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_ETM_MASK 0x0300 5498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_ETM_ACC 0x0000 5598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_ETM_APP 0x0100 5698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0 5798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000 5898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040 5998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080 6098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0 6198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030 6298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000 6398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010 6498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020 6598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030 6698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C 6798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000 6898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004 6998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008 7098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C 7198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003 7298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000 7398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001 7498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002 7598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1LR_EMIF_1 0x0003 7698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ 7798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR 0x007E 7898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MASK 0xFFFF 7998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000 8098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000 8198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000 8298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000 8398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000 8498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000 8598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000 8698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000 8798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000 8898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000 8998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00 9098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000 9198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400 9298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800 9398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00 9498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300 9598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000 9698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100 9798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300 9898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0 9998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000 10098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040 10198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0 10298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030 10398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000 10498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010 10598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020 10698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030 10798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C 10898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000 10998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004 11098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008 11198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C 11298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003 11398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000 11498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001 11598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003 11698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* Padmux 2 control */ 11798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R 0x100 11898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0 11998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000 12098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040 12198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080 12298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0 12398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300 12498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000 12598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100 12698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200 12798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300 12898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00 12998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000 13098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400 13198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800 13298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00 13398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000 13498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000 13598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000 13698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000 13798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000 13898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000 13998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000 14098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000 14198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000 14298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000 14398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* TODO: More SYSCON registers missing */ 14498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC3R 0x10C 14598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000 14698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000 14798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000 14898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000 14998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* TODO: Missing other configs */ 15098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R 0x168 15198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003 15298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000 15398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C 15498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000 15598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004 15698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008 15798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C 15898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030 15998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000 16098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010 16198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020 16298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030 16398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300 16498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000 16598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100 16698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200 16798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 168128a06d4bb997d90158e668173a6944d376c84cbLinus Walleij#define DRIVER_NAME "pinctrl-u300" 16998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 17098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* 17198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * The DB3350 has 467 pads, I have enumerated the pads clockwise around the 17298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * edges of the silicon, finger by finger. LTCORNER upper left is pad 0. 17398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Data taken from the PadRing chart, arranged like this: 17498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 17598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 0 ..... 104 17698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 466 105 17798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * . . 17898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * . . 17998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 358 224 18098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 357 .... 225 18198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 18298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij#define U300_NUM_PADS 467 18398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 18498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* Pad names for the pinmux subsystem */ 18525aec320d993950474a065b59585e8dd006c3e18Stephen Warrenstatic const struct pinctrl_pin_desc u300_pads[] = { 18698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Pads along the top edge of the chip */ 18798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(0, "P PAD VDD 28"), 18898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(1, "P PAD GND 28"), 18998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(2, "PO SIM RST N"), 19098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(3, "VSSIO 25"), 19198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(4, "VSSA ADDA ESDSUB"), 19298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(5, "PWR VSSCOMMON"), 19398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(6, "PI ADC I1 POS"), 19498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(7, "PI ADC I1 NEG"), 19598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(8, "PWR VSSAD0"), 19698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(9, "PWR VCCAD0"), 19798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(10, "PI ADC Q1 NEG"), 19898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(11, "PI ADC Q1 POS"), 19998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(12, "PWR VDDAD"), 20098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(13, "PWR GNDAD"), 20198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(14, "PI ADC I2 POS"), 20298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(15, "PI ADC I2 NEG"), 20398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(16, "PWR VSSAD1"), 20498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(17, "PWR VCCAD1"), 20598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(18, "PI ADC Q2 NEG"), 20698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(19, "PI ADC Q2 POS"), 20798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(20, "VSSA ADDA ESDSUB"), 20898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(21, "PWR VCCGPAD"), 20998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(22, "PI TX POW"), 21098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(23, "PWR VSSGPAD"), 21198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(24, "PO DAC I POS"), 21298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(25, "PO DAC I NEG"), 21398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(26, "PO DAC Q POS"), 21498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(27, "PO DAC Q NEG"), 21598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(28, "PWR VSSDA"), 21698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(29, "PWR VCCDA"), 21798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(30, "VSSA ADDA ESDSUB"), 21898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(31, "P PAD VDDIO 11"), 21998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(32, "PI PLL 26 FILTVDD"), 22098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(33, "PI PLL 26 VCONT"), 22198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"), 22298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"), 22398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(36, "VDDA PLL ESD"), 22498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(37, "VSSA PLL ESD"), 22598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(38, "VSS PLL"), 22698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(39, "VDDC PLL"), 22798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"), 22898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"), 22998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"), 23098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"), 23198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"), 23298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"), 23398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(46, "P PAD VSSIO 11"), 23498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(47, "P PAD VSSIO 12"), 23598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(48, "PI POW RST N"), 23698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(49, "VDDC IO"), 23798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(50, "P PAD VDDIO 16"), 23898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(51, "PO RF WCDMA EN 4"), 23998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(52, "PO RF WCDMA EN 3"), 24098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(53, "PO RF WCDMA EN 2"), 24198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(54, "PO RF WCDMA EN 1"), 24298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(55, "PO RF WCDMA EN 0"), 24398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(56, "PO GSM PA ENABLE"), 24498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(57, "PO RF DATA STRB"), 24598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(58, "PO RF DATA2"), 24698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(59, "PIO RF DATA1"), 24798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(60, "PIO RF DATA0"), 24898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(61, "P PAD VDD 11"), 24998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(62, "P PAD GND 11"), 25098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(63, "P PAD VSSIO 16"), 25198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(64, "P PAD VDDIO 18"), 25298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(65, "PO RF CTRL STRB2"), 25398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(66, "PO RF CTRL STRB1"), 25498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(67, "PO RF CTRL STRB0"), 25598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(68, "PIO RF CTRL DATA"), 25698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(69, "PO RF CTRL CLK"), 25798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(70, "PO TX ADC STRB"), 25898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(71, "PO ANT SW 2"), 25998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(72, "PO ANT SW 3"), 26098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(73, "PO ANT SW 0"), 26198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(74, "PO ANT SW 1"), 26298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(75, "PO M CLKRQ"), 26398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(76, "PI M CLK"), 26498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(77, "PI RTC CLK"), 26598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(78, "P PAD VDD 8"), 26698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(79, "P PAD GND 8"), 26798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(80, "P PAD VSSIO 13"), 26898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(81, "P PAD VDDIO 13"), 26998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(82, "PO SYS 1 CLK"), 27098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(83, "PO SYS 2 CLK"), 27198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(84, "PO SYS 0 CLK"), 27298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(85, "PI SYS 0 CLKRQ"), 27398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"), 27498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"), 27598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(88, "PO RESOUT2 RST N"), 27698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(89, "PO RESOUT1 RST N"), 27798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(90, "PO RESOUT0 RST N"), 27898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(91, "PI SERVICE N"), 27998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(92, "P PAD VDD 29"), 28098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(93, "P PAD GND 29"), 28198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(94, "P PAD VSSIO 8"), 28298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(95, "P PAD VDDIO 8"), 28398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(96, "PI EXT IRQ1 N"), 28498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(97, "PI EXT IRQ0 N"), 28598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(98, "PIO DC ON"), 28698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(99, "PIO ACC APP I2C DATA"), 28798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(100, "PIO ACC APP I2C CLK"), 28898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(101, "P PAD VDD 12"), 28998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(102, "P PAD GND 12"), 29098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(103, "P PAD VSSIO 14"), 29198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(104, "P PAD VDDIO 14"), 29298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Pads along the right edge of the chip */ 29398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(105, "PIO APP I2C1 DATA"), 29498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(106, "PIO APP I2C1 CLK"), 29598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(107, "PO KEY OUT0"), 29698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(108, "PO KEY OUT1"), 29798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(109, "PO KEY OUT2"), 29898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(110, "PO KEY OUT3"), 29998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(111, "PO KEY OUT4"), 30098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(112, "PI KEY IN0"), 30198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(113, "PI KEY IN1"), 30298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(114, "PI KEY IN2"), 30398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(115, "P PAD VDDIO 15"), 30498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(116, "P PAD VSSIO 15"), 30598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(117, "P PAD GND 13"), 30698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(118, "P PAD VDD 13"), 30798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(119, "PI KEY IN3"), 30898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(120, "PI KEY IN4"), 30998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(121, "PI KEY IN5"), 31098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"), 31198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"), 31298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"), 31398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"), 31498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"), 31598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"), 31698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"), 31798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"), 31898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(130, "P PAD VDD 17"), 31998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(131, "P PAD GND 17"), 32098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(132, "P PAD VSSIO 19"), 32198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(133, "P PAD VDDIO 19"), 32298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(134, "UART0 RTS"), 32398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(135, "UART0 CTS"), 32498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(136, "UART0 TX"), 32598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(137, "UART0 RX"), 32698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(138, "PIO ACC SPI DO"), 32798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(139, "PIO ACC SPI DI"), 32898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(140, "PIO ACC SPI CS0 N"), 32998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(141, "PIO ACC SPI CS1 N"), 33098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(142, "PIO ACC SPI CS2 N"), 33198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(143, "PIO ACC SPI CLK"), 33298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(144, "PO PDI EXT RST N"), 33398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(145, "P PAD VDDIO 22"), 33498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(146, "P PAD VSSIO 22"), 33598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(147, "P PAD GND 18"), 33698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(148, "P PAD VDD 18"), 33798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(149, "PIO PDI C0"), 33898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(150, "PIO PDI C1"), 33998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(151, "PIO PDI C2"), 34098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(152, "PIO PDI C3"), 34198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(153, "PIO PDI C4"), 34298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(154, "PIO PDI C5"), 34398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(155, "PIO PDI D0"), 34498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(156, "PIO PDI D1"), 34598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(157, "PIO PDI D2"), 34698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(158, "PIO PDI D3"), 34798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(159, "P PAD VDDIO 21"), 34898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(160, "P PAD VSSIO 21"), 34998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(161, "PIO PDI D4"), 35098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(162, "PIO PDI D5"), 35198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(163, "PIO PDI D6"), 35298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(164, "PIO PDI D7"), 35398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(165, "PIO MS INS"), 35498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(166, "MMC DATA DIR LS"), 35598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(167, "MMC DATA 3"), 35698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(168, "MMC DATA 2"), 35798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(169, "MMC DATA 1"), 35898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(170, "MMC DATA 0"), 35998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(171, "MMC CMD DIR LS"), 36098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(172, "P PAD VDD 27"), 36198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(173, "P PAD GND 27"), 36298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(174, "P PAD VSSIO 20"), 36398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(175, "P PAD VDDIO 20"), 36498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(176, "MMC CMD"), 36598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(177, "MMC CLK"), 36698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(178, "PIO APP GPIO 14"), 36798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(179, "PIO APP GPIO 13"), 36898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(180, "PIO APP GPIO 11"), 36998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(181, "PIO APP GPIO 25"), 37098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(182, "PIO APP GPIO 24"), 37198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(183, "PIO APP GPIO 23"), 37298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(184, "PIO APP GPIO 22"), 37398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(185, "PIO APP GPIO 21"), 37498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(186, "PIO APP GPIO 20"), 37598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(187, "P PAD VDD 19"), 37698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(188, "P PAD GND 19"), 37798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(189, "P PAD VSSIO 23"), 37898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(190, "P PAD VDDIO 23"), 37998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(191, "PIO APP GPIO 19"), 38098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(192, "PIO APP GPIO 18"), 38198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(193, "PIO APP GPIO 17"), 38298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(194, "PIO APP GPIO 16"), 38398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(195, "PI CI D1"), 38498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(196, "PI CI D0"), 38598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(197, "PI CI HSYNC"), 38698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(198, "PI CI VSYNC"), 38798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(199, "PI CI EXT CLK"), 38898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(200, "PO CI EXT RST N"), 38998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(201, "P PAD VSSIO 43"), 39098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(202, "P PAD VDDIO 43"), 39198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(203, "PI CI D6"), 39298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(204, "PI CI D7"), 39398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(205, "PI CI D2"), 39498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(206, "PI CI D3"), 39598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(207, "PI CI D4"), 39698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(208, "PI CI D5"), 39798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(209, "PI CI D8"), 39898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(210, "PI CI D9"), 39998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(211, "P PAD VDD 20"), 40098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(212, "P PAD GND 20"), 40198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(213, "P PAD VSSIO 24"), 40298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(214, "P PAD VDDIO 24"), 40398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(215, "P PAD VDDIO 26"), 40498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(216, "PO EMIF 1 A26"), 40598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(217, "PO EMIF 1 A25"), 40698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(218, "P PAD VSSIO 26"), 40798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(219, "PO EMIF 1 A24"), 40898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(220, "PO EMIF 1 A23"), 40998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Pads along the bottom edge of the chip */ 41098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(221, "PO EMIF 1 A22"), 41198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(222, "PO EMIF 1 A21"), 41298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(223, "P PAD VDD 21"), 41398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(224, "P PAD GND 21"), 41498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(225, "P PAD VSSIO 27"), 41598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(226, "P PAD VDDIO 27"), 41698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(227, "PO EMIF 1 A20"), 41798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(228, "PO EMIF 1 A19"), 41898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(229, "PO EMIF 1 A18"), 41998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(230, "PO EMIF 1 A17"), 42098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(231, "P PAD VDDIO 28"), 42198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(232, "P PAD VSSIO 28"), 42298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(233, "PO EMIF 1 A16"), 42398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(234, "PIO EMIF 1 D15"), 42498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(235, "PO EMIF 1 A15"), 42598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(236, "PIO EMIF 1 D14"), 42698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(237, "P PAD VDD 22"), 42798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(238, "P PAD GND 22"), 42898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(239, "P PAD VSSIO 29"), 42998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(240, "P PAD VDDIO 29"), 43098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(241, "PO EMIF 1 A14"), 43198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(242, "PIO EMIF 1 D13"), 43298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(243, "PO EMIF 1 A13"), 43398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(244, "PIO EMIF 1 D12"), 43498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(245, "P PAD VSSIO 30"), 43598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(246, "P PAD VDDIO 30"), 43698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(247, "PO EMIF 1 A12"), 43798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(248, "PIO EMIF 1 D11"), 43898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(249, "PO EMIF 1 A11"), 43998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(250, "PIO EMIF 1 D10"), 44098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(251, "P PAD VSSIO 31"), 44198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(252, "P PAD VDDIO 31"), 44298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(253, "PO EMIF 1 A10"), 44398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(254, "PIO EMIF 1 D09"), 44498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(255, "PO EMIF 1 A09"), 44598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(256, "P PAD VDDIO 32"), 44698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(257, "P PAD VSSIO 32"), 44798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(258, "P PAD GND 24"), 44898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(259, "P PAD VDD 24"), 44998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(260, "PIO EMIF 1 D08"), 45098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(261, "PO EMIF 1 A08"), 45198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(262, "PIO EMIF 1 D07"), 45298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(263, "PO EMIF 1 A07"), 45398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(264, "P PAD VDDIO 33"), 45498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(265, "P PAD VSSIO 33"), 45598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(266, "PIO EMIF 1 D06"), 45698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(267, "PO EMIF 1 A06"), 45798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(268, "PIO EMIF 1 D05"), 45898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(269, "PO EMIF 1 A05"), 45998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(270, "P PAD VDDIO 34"), 46098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(271, "P PAD VSSIO 34"), 46198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(272, "PIO EMIF 1 D04"), 46298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(273, "PO EMIF 1 A04"), 46398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(274, "PIO EMIF 1 D03"), 46498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(275, "PO EMIF 1 A03"), 46598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(276, "P PAD VDDIO 35"), 46698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(277, "P PAD VSSIO 35"), 46798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(278, "P PAD GND 23"), 46898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(279, "P PAD VDD 23"), 46998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(280, "PIO EMIF 1 D02"), 47098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(281, "PO EMIF 1 A02"), 47198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(282, "PIO EMIF 1 D01"), 47298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(283, "PO EMIF 1 A01"), 47398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(284, "P PAD VDDIO 36"), 47498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(285, "P PAD VSSIO 36"), 47598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(286, "PIO EMIF 1 D00"), 47698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(287, "PO EMIF 1 BE1 N"), 47798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(288, "PO EMIF 1 BE0 N"), 47898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(289, "PO EMIF 1 ADV N"), 47998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(290, "P PAD VDDIO 37"), 48098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(291, "P PAD VSSIO 37"), 48198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"), 48298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(293, "PO EMIF 1 OE N"), 48398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(294, "PO EMIF 1 WE N"), 48498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(295, "P PAD VDDIO 38"), 48598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(296, "P PAD VSSIO 38"), 48698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(297, "PO EMIF 1 CLK"), 48798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"), 48898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"), 48998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(300, "P PAD VDDIO 42"), 49098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(301, "P PAD VSSIO 42"), 49198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(302, "P PAD GND 31"), 49298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(303, "P PAD VDD 31"), 49398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(304, "PI EMIF 1 RET CLK"), 49498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(305, "PI EMIF 1 WAIT N"), 49598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"), 49698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"), 49798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(308, "PO EMIF 1 CS3 N"), 49898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(309, "P PAD VDD 25"), 49998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(310, "P PAD GND 25"), 50098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(311, "P PAD VSSIO 39"), 50198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(312, "P PAD VDDIO 39"), 50298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(313, "PO EMIF 1 CS2 N"), 50398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(314, "PO EMIF 1 CS1 N"), 50498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(315, "PO EMIF 1 CS0 N"), 50598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(316, "PO ETM TRACE PKT0"), 50698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(317, "PO ETM TRACE PKT1"), 50798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(318, "PO ETM TRACE PKT2"), 50898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(319, "P PAD VDD 30"), 50998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(320, "P PAD GND 30"), 51098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(321, "P PAD VSSIO 44"), 51198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(322, "P PAD VDDIO 44"), 51298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(323, "PO ETM TRACE PKT3"), 51398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(324, "PO ETM TRACE PKT4"), 51498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(325, "PO ETM TRACE PKT5"), 51598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(326, "PO ETM TRACE PKT6"), 51698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(327, "PO ETM TRACE PKT7"), 51798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(328, "PO ETM PIPE STAT0"), 51898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(329, "P PAD VDD 26"), 51998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(330, "P PAD GND 26"), 52098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(331, "P PAD VSSIO 40"), 52198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(332, "P PAD VDDIO 40"), 52298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(333, "PO ETM PIPE STAT1"), 52398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(334, "PO ETM PIPE STAT2"), 52498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(335, "PO ETM TRACE CLK"), 52598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(336, "PO ETM TRACE SYNC"), 52698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(337, "PIO ACC GPIO 33"), 52798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(338, "PIO ACC GPIO 32"), 52898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(339, "PIO ACC GPIO 30"), 52998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(340, "PIO ACC GPIO 29"), 53098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(341, "P PAD VDDIO 17"), 53198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(342, "P PAD VSSIO 17"), 53298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(343, "P PAD GND 15"), 53398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(344, "P PAD VDD 15"), 53498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(345, "PIO ACC GPIO 28"), 53598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(346, "PIO ACC GPIO 27"), 53698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(347, "PIO ACC GPIO 16"), 53798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(348, "PI TAP TMS"), 53898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(349, "PI TAP TDI"), 53998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(350, "PO TAP TDO"), 54098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(351, "PI TAP RST N"), 54198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Pads along the left edge of the chip */ 54298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(352, "PI EMU MODE 0"), 54398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(353, "PO TAP RET CLK"), 54498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(354, "PI TAP CLK"), 54598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(355, "PO EMIF 0 SD CS N"), 54698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"), 54798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(357, "PO EMIF 0 SD WE N"), 54898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(358, "P PAD VDDIO 1"), 54998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(359, "P PAD VSSIO 1"), 55098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(360, "P PAD GND 1"), 55198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(361, "P PAD VDD 1"), 55298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(362, "PO EMIF 0 SD CKE"), 55398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(363, "PO EMIF 0 SD DQML"), 55498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"), 55598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"), 55698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(366, "PIO EMIF 0 D15"), 55798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(367, "PO EMIF 0 A15"), 55898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(368, "PIO EMIF 0 D14"), 55998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(369, "PO EMIF 0 A14"), 56098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(370, "PIO EMIF 0 D13"), 56198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(371, "PO EMIF 0 A13"), 56298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(372, "P PAD VDDIO 2"), 56398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(373, "P PAD VSSIO 2"), 56498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(374, "P PAD GND 2"), 56598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(375, "P PAD VDD 2"), 56698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(376, "PIO EMIF 0 D12"), 56798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(377, "PO EMIF 0 A12"), 56898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(378, "PIO EMIF 0 D11"), 56998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(379, "PO EMIF 0 A11"), 57098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(380, "PIO EMIF 0 D10"), 57198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(381, "PO EMIF 0 A10"), 57298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(382, "PIO EMIF 0 D09"), 57398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(383, "PO EMIF 0 A09"), 57498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(384, "PIO EMIF 0 D08"), 57598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(385, "PO EMIF 0 A08"), 57698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(386, "PIO EMIF 0 D07"), 57798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(387, "PO EMIF 0 A07"), 57898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(388, "P PAD VDDIO 3"), 57998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(389, "P PAD VSSIO 3"), 58098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(390, "P PAD GND 3"), 58198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(391, "P PAD VDD 3"), 58298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(392, "PO EFUSE RDOUT1"), 58398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(393, "PIO EMIF 0 D06"), 58498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(394, "PO EMIF 0 A06"), 58598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(395, "PIO EMIF 0 D05"), 58698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(396, "PO EMIF 0 A05"), 58798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(397, "PIO EMIF 0 D04"), 58898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(398, "PO EMIF 0 A04"), 58998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"), 59098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(400, "PWR VDDCO AF"), 59198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(401, "PWR EFUSE HV1"), 59298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(402, "P PAD VSSIO 4"), 59398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(403, "P PAD VDDIO 4"), 59498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(404, "P PAD GND 4"), 59598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(405, "P PAD VDD 4"), 59698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(406, "PIO EMIF 0 D03"), 59798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(407, "PO EMIF 0 A03"), 59898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(408, "PWR EFUSE HV2"), 59998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(409, "PWR EFUSE HV3"), 60098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(410, "PIO EMIF 0 D02"), 60198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(411, "PO EMIF 0 A02"), 60298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(412, "PIO EMIF 0 D01"), 60398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(413, "P PAD VDDIO 5"), 60498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(414, "P PAD VSSIO 5"), 60598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(415, "P PAD GND 5"), 60698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(416, "P PAD VDD 5"), 60798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(417, "PO EMIF 0 A01"), 60898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(418, "PIO EMIF 0 D00"), 60998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(419, "IF 0 SD CLK"), 61098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(420, "APP SPI CLK"), 61198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(421, "APP SPI DO"), 61298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(422, "APP SPI DI"), 61398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(423, "APP SPI CS0"), 61498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(424, "APP SPI CS1"), 61598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(425, "APP SPI CS2"), 61698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(426, "PIO APP GPIO 10"), 61798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(427, "P PAD VDDIO 41"), 61898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(428, "P PAD VSSIO 41"), 61998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(429, "P PAD GND 6"), 62098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(430, "P PAD VDD 6"), 62198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"), 62298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(432, "PIO ACC SDIO0 CK"), 62398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(433, "PIO ACC SDIO0 D3"), 62498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(434, "PIO ACC SDIO0 D2"), 62598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(435, "PIO ACC SDIO0 D1"), 62698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(436, "PIO ACC SDIO0 D0"), 62798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(437, "PIO USB PU"), 62898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(438, "PIO USB SP"), 62998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(439, "PIO USB DAT VP"), 63098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(440, "PIO USB SE0 VM"), 63198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(441, "PIO USB OE"), 63298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(442, "PIO USB SUSP"), 63398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(443, "P PAD VSSIO 6"), 63498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(444, "P PAD VDDIO 6"), 63598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(445, "PIO USB PUEN"), 63698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(446, "PIO ACC UART0 RX"), 63798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(447, "PIO ACC UART0 TX"), 63898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(448, "PIO ACC UART0 CTS"), 63998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(449, "PIO ACC UART0 RTS"), 64098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(450, "PIO ACC UART3 RX"), 64198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(451, "PIO ACC UART3 TX"), 64298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(452, "PIO ACC UART3 CTS"), 64398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(453, "PIO ACC UART3 RTS"), 64498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(454, "PIO ACC IRDA TX"), 64598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(455, "P PAD VDDIO 7"), 64698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(456, "P PAD VSSIO 7"), 64798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(457, "P PAD GND 7"), 64898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(458, "P PAD VDD 7"), 64998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(459, "PIO ACC IRDA RX"), 65098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"), 65198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(461, "PIO ACC PCM I2S WS"), 65298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"), 65398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"), 65498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(464, "PO SIM CLK"), 65598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(465, "PIO ACC IRDA SD"), 65698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij PINCTRL_PIN(466, "PIO SIM DATA"), 65798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 65898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 65998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/** 66098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @dev: a pointer back to containing device 66198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @virtbase: the offset to the controller in virtual memory 66298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 66398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstruct u300_pmx { 66498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct device *dev; 66598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct pinctrl_dev *pctl; 66698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij void __iomem *virtbase; 66798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 66898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 66998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/** 67098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * u300_pmx_registers - the array of registers read/written for each pinmux 67198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * shunt setting 67298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 67398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijconst u32 u300_pmx_registers[] = { 67498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR, 67598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR, 67698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC2R, 67798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC3R, 67898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC4R, 67998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 68098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 68198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/** 68298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * struct u300_pin_group - describes a U300 pin group 68398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @name: the name of this specific pin group 68498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @pins: an array of discrete physical pins used in this group, taken 68598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * from the driver-local pin enumeration space 68698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @num_pins: the number of pins in this group array, i.e. the number of 68798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * elements in .pins so we can iterate over that array 68898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 68998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstruct u300_pin_group { 69098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const char *name; 69198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const unsigned int *pins; 69298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const unsigned num_pins; 69398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 69498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 69598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/** 69698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * struct pmx_onmask - mask bits to enable/disable padmux 69798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @mask: mask bits to disable 69898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @val: mask bits to enable 69998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 70098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * onmask lazy dog: 70198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * 70298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * {"PMC1LR" mask, "PMC1LR" value}, 70398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * {"PMC1HR" mask, "PMC1HR" value}, 70498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * {"PMC2R" mask, "PMC2R" value}, 70598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * {"PMC3R" mask, "PMC3R" value}, 70698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * {"PMC4R" mask, "PMC4R" value} 70798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * } 70898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 70998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstruct u300_pmx_mask { 71098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij u16 mask; 71198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij u16 bits; 71298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 71398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 71498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* The chip power pins are VDD, GND, VDDIO and VSSIO */ 71598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63, 71698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117, 71798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174, 71898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223, 71998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256, 72098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290, 72198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320, 72298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361, 72398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414, 72498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 }; 72598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366, 72698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384, 72798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412, 72898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 417, 418 }; 72998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228, 73098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250, 73198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274, 73298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298, 73398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 304, 305, 306, 307, 308, 313, 314, 315 }; 73498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned uart0_pins[] = { 134, 135, 136, 137 }; 73598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; 73698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; 73798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 73898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_mask emif0_mask[] = { 73998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 74098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 74198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 74298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 74398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 74498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 74598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 74698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_mask emif1_mask[] = { 74798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* 74898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * This connects the SDRAM to CS2 and a NAND flash to 74998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * CS0 on the EMIF. 75098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 75198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 75298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK | 75398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK | 75498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK | 75598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_MASK, 75698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM | 75798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC | 75898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF | 75998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 76098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 76198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 76298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 76398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 76498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 76598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 76698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 76798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_mask uart0_mask[] = { 76898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 76998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 77098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_UART0_1_MASK | 77198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_UART0_2_MASK, 77298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_UART0_1_UART0 | 77398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_UART0_2_UART0 77498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 77598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 77698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 77798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 77898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 77998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 78098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_mask mmc0_mask[] = { 78198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD}, 78298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 78398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 78498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 78598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { U300_SYSCON_PMC4R_APP_MISC_12_MASK, 78698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO } 78798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 78898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 78998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_mask spi0_mask[] = { 79098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 79198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 79298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_2_MASK | 79398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | 79498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, 79598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_2_SPI | 79698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | 79798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 79898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 79998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 80098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0}, 80198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij {0, 0} 80298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 80398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 80498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pin_group u300_pin_groups[] = { 80598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 80698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "powergrp", 80798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = power_pins, 80898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(power_pins), 80998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 81098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 81198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "emif0grp", 81298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = emif0_pins, 81398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(emif0_pins), 81498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 81598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 81698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "emif1grp", 81798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = emif1_pins, 81898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(emif1_pins), 81998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 82098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 82198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "uart0grp", 82298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = uart0_pins, 82398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(uart0_pins), 82498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 82598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 82698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "mmc0grp", 82798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = mmc0_pins, 82898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(mmc0_pins), 82998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 83098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 83198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "spi0grp", 83298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = spi0_pins, 83398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_pins = ARRAY_SIZE(spi0_pins), 83498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 83598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 83698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 837d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumarstatic int u300_get_groups_count(struct pinctrl_dev *pctldev) 83898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 839d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumar return ARRAY_SIZE(u300_pin_groups); 84098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 84198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 84298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char *u300_get_group_name(struct pinctrl_dev *pctldev, 84398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij unsigned selector) 84498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 84598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return u300_pin_groups[selector].name; 84698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 84798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 84898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 849a5818a8bd095a08cfb1871b63af9c8bed103e4b9Stephen Warren const unsigned **pins, 850a5818a8bd095a08cfb1871b63af9c8bed103e4b9Stephen Warren unsigned *num_pins) 85198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 852a5818a8bd095a08cfb1871b63af9c8bed103e4b9Stephen Warren *pins = u300_pin_groups[selector].pins; 85398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij *num_pins = u300_pin_groups[selector].num_pins; 85498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 85598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 85698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 85798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 85898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij unsigned offset) 85998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 86098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij seq_printf(s, " " DRIVER_NAME); 86198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 86298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 863022ab148d28e8466e45d28552224e3029f1cccd8Laurent Pinchartstatic const struct pinctrl_ops u300_pctrl_ops = { 864d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumar .get_groups_count = u300_get_groups_count, 86598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .get_group_name = u300_get_group_name, 86698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .get_group_pins = u300_get_group_pins, 86798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pin_dbg_show = u300_pin_dbg_show, 86898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 86998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 87098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/* 87198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * Here we define the available functions and their corresponding pin groups 87298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 87398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 87498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij/** 87598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * struct u300_pmx_func - describes U300 pinmux functions 87698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @name: the name of this specific function 87798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @groups: corresponding pin groups 87898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij * @onmask: bits to set to enable this when doing pin muxing 87998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij */ 88098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstruct u300_pmx_func { 88198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const char *name; 88298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const char * const *groups; 88398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const unsigned num_groups; 88498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const struct u300_pmx_mask *mask; 88598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 88698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 88798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const powergrps[] = { "powergrp" }; 88898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const emif0grps[] = { "emif0grp" }; 88998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const emif1grps[] = { "emif1grp" }; 89098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const uart0grps[] = { "uart0grp" }; 89198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const mmc0grps[] = { "mmc0grp" }; 89298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char * const spi0grps[] = { "spi0grp" }; 89398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 89498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const struct u300_pmx_func u300_pmx_functions[] = { 89598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 89698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "power", 89798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = powergrps, 89898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(powergrps), 89998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Mask is N/A */ 90098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 90198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 90298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "emif0", 90398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = emif0grps, 90498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(emif0grps), 90598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .mask = emif0_mask, 90698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 90798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 90898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "emif1", 90998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = emif1grps, 91098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(emif1grps), 91198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .mask = emif1_mask, 91298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 91398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 91498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "uart0", 91598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = uart0grps, 91698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(uart0grps), 91798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .mask = uart0_mask, 91898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 91998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 92098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "mmc0", 92198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = mmc0grps, 92298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(mmc0grps), 92398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .mask = mmc0_mask, 92498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 92598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij { 92698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = "spi0", 92798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .groups = spi0grps, 92898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .num_groups = ARRAY_SIZE(spi0grps), 92998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .mask = spi0_mask, 93098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 93198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 93298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 93398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, 93498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij bool enable) 93598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 93698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij u16 regval, val, mask; 93798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij int i; 938b84e673f51799a2d0bad7a7c1e7a74021c4eba4bRajendra Nayak const struct u300_pmx_mask *upmx_mask; 93998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 940b84e673f51799a2d0bad7a7c1e7a74021c4eba4bRajendra Nayak upmx_mask = u300_pmx_functions[selector].mask; 94198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { 94298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij if (enable) 943b84e673f51799a2d0bad7a7c1e7a74021c4eba4bRajendra Nayak val = upmx_mask->bits; 94498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij else 94598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij val = 0; 94698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 947b84e673f51799a2d0bad7a7c1e7a74021c4eba4bRajendra Nayak mask = upmx_mask->mask; 94898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij if (mask != 0) { 94998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij regval = readw(upmx->virtbase + u300_pmx_registers[i]); 95098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij regval &= ~mask; 95198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij regval |= val; 95298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij writew(regval, upmx->virtbase + u300_pmx_registers[i]); 95398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij } 954b84e673f51799a2d0bad7a7c1e7a74021c4eba4bRajendra Nayak upmx_mask++; 95598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij } 95698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 95798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 95803e9f0cac5da6af85758276cb4624caf5911f2b9Linus Walleijstatic int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 95903e9f0cac5da6af85758276cb4624caf5911f2b9Linus Walleij unsigned group) 96098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 96198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct u300_pmx *upmx; 96298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 96398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* There is nothing to do with the power pins */ 96498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij if (selector == 0) 96598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 96698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 96798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij upmx = pinctrl_dev_get_drvdata(pctldev); 96898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij u300_pmx_endisable(upmx, selector, true); 96998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 97098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 97198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 97298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 973d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumarstatic int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 97498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 975d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumar return ARRAY_SIZE(u300_pmx_functions); 97698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 97798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 97898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, 97998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij unsigned selector) 98098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 98198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return u300_pmx_functions[selector].name; 98298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 98398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 98498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 98598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij const char * const **groups, 98698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij unsigned * const num_groups) 98798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 98898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij *groups = u300_pmx_functions[selector].groups; 98998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij *num_groups = u300_pmx_functions[selector].num_groups; 99098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 99198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 99298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 993022ab148d28e8466e45d28552224e3029f1cccd8Laurent Pinchartstatic const struct pinmux_ops u300_pmx_ops = { 994d1e90e9e7467dbfe521b25ba79f520bf676ebc36Viresh Kumar .get_functions_count = u300_pmx_get_funcs_count, 99598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .get_function_name = u300_pmx_get_func_name, 99698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .get_function_groups = u300_pmx_get_groups, 99703e9f0cac5da6af85758276cb4624caf5911f2b9Linus Walleij .set_mux = u300_pmx_set_mux, 99898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 99998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 1000e1b29abef69e34a42169cd65d7249b18574c94e8Axel Linstatic int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1001e1b29abef69e34a42169cd65d7249b18574c94e8Axel Lin unsigned long *config) 1002dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij{ 1003387923c585ac68ff51e6bf673807438b5e5fdaf3Linus Walleij struct pinctrl_gpio_range *range = 1004387923c585ac68ff51e6bf673807438b5e5fdaf3Linus Walleij pinctrl_find_gpio_range_from_pin(pctldev, pin); 1005dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1006dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij /* We get config for those pins we CAN get it for and that's it */ 1007dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij if (!range) 1008dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij return -ENOTSUPP; 1009dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1010dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij return u300_gpio_config_get(range->gc, 1011dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij (pin - range->pin_base + range->base), 1012dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij config); 1013dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij} 1014dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1015e1b29abef69e34a42169cd65d7249b18574c94e8Axel Linstatic int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 101603b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin unsigned long *configs, unsigned num_configs) 1017dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij{ 1018387923c585ac68ff51e6bf673807438b5e5fdaf3Linus Walleij struct pinctrl_gpio_range *range = 1019387923c585ac68ff51e6bf673807438b5e5fdaf3Linus Walleij pinctrl_find_gpio_range_from_pin(pctldev, pin); 102003b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin int ret, i; 1021dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1022dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij if (!range) 1023dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij return -EINVAL; 1024dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 102503b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin for (i = 0; i < num_configs; i++) { 102603b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin /* Note: none of these configurations take any argument */ 102703b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin ret = u300_gpio_config_set(range->gc, 102803b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin (pin - range->pin_base + range->base), 102903b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin pinconf_to_config_param(configs[i])); 103003b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin if (ret) 103103b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin return ret; 103203b054e9696c3cbd3d5905ec96da15acd0a2fe8dSherman Yin } /* for each config */ 1033dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1034dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij return 0; 1035dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij} 1036dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 1037022ab148d28e8466e45d28552224e3029f1cccd8Laurent Pinchartstatic const struct pinconf_ops u300_pconf_ops = { 1038dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij .is_generic = true, 1039dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij .pin_config_get = u300_pin_config_get, 1040dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij .pin_config_set = u300_pin_config_set, 1041dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij}; 1042dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij 104398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic struct pinctrl_desc u300_pmx_desc = { 104498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = DRIVER_NAME, 104598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pins = u300_pads, 104698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .npins = ARRAY_SIZE(u300_pads), 104798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pctlops = &u300_pctrl_ops, 104898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .pmxops = &u300_pmx_ops, 1049dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5Linus Walleij .confops = &u300_pconf_ops, 105098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .owner = THIS_MODULE, 105198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 105298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 1053150632b09aadf1996f5cb6c0c2620d63a01fe2deGreg Kroah-Hartmanstatic int u300_pmx_probe(struct platform_device *pdev) 105498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 105598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct u300_pmx *upmx; 105698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct resource *res; 105798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 105898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij /* Create state holders etc for this driver */ 105998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL); 106098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij if (!upmx) 106198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return -ENOMEM; 106298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 106398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij upmx->dev = &pdev->dev; 106498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 106598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10669e0c1fb29a7c257a31c321c2437617b6b4d66168Thierry Reding upmx->virtbase = devm_ioremap_resource(&pdev->dev, res); 10679e0c1fb29a7c257a31c321c2437617b6b4d66168Thierry Reding if (IS_ERR(upmx->virtbase)) 10689e0c1fb29a7c257a31c321c2437617b6b4d66168Thierry Reding return PTR_ERR(upmx->virtbase); 106998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 107098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx); 107198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij if (!upmx->pctl) { 107298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); 1073b36bdc5911effe819e415b144388853bf07a543bLinus Walleij return -EINVAL; 107498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij } 107598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 107698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij platform_set_drvdata(pdev, upmx); 107798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 1078128a06d4bb997d90158e668173a6944d376c84cbLinus Walleij dev_info(&pdev->dev, "initialized U300 pin control driver\n"); 107998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 108098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 108198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 108298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 1083f90f54b3f3c4d1c9168d5f8e97c6ac5b9ad25f5eBill Pembertonstatic int u300_pmx_remove(struct platform_device *pdev) 108498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 108598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij struct u300_pmx *upmx = platform_get_drvdata(pdev); 108698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 108798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij pinctrl_unregister(upmx->pctl); 108898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 108998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij return 0; 109098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 109198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 109221a035db897975a5195dfb1525433637f30aeebfLinus Walleijstatic const struct of_device_id u300_pinctrl_match[] = { 109321a035db897975a5195dfb1525433637f30aeebfLinus Walleij { .compatible = "stericsson,pinctrl-u300" }, 109421a035db897975a5195dfb1525433637f30aeebfLinus Walleij {}, 109521a035db897975a5195dfb1525433637f30aeebfLinus Walleij}; 109621a035db897975a5195dfb1525433637f30aeebfLinus Walleij 109721a035db897975a5195dfb1525433637f30aeebfLinus Walleij 109898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic struct platform_driver u300_pmx_driver = { 109998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .driver = { 110098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .name = DRIVER_NAME, 110198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij .owner = THIS_MODULE, 110221a035db897975a5195dfb1525433637f30aeebfLinus Walleij .of_match_table = u300_pinctrl_match, 110398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij }, 1104128a06d4bb997d90158e668173a6944d376c84cbLinus Walleij .probe = u300_pmx_probe, 11052a36f08636665d63ec2bfa49a815509e71d44ebaBill Pemberton .remove = u300_pmx_remove, 110698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij}; 110798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 110898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic int __init u300_pmx_init(void) 110998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 1110128a06d4bb997d90158e668173a6944d376c84cbLinus Walleij return platform_driver_register(&u300_pmx_driver); 111198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 111298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijarch_initcall(u300_pmx_init); 111398da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 111498da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijstatic void __exit u300_pmx_exit(void) 111598da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij{ 111698da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij platform_driver_unregister(&u300_pmx_driver); 111798da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij} 111898da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleijmodule_exit(u300_pmx_exit); 111998da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus Walleij 112098da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus WalleijMODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 112198da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus WalleijMODULE_DESCRIPTION("U300 pin control driver"); 112298da3529536ed3c78ae493f4cc3d7ac8d43fc72cLinus WalleijMODULE_LICENSE("GPL v2"); 1123