1/* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <linux/delay.h> 16#include <linux/err.h> 17#include <linux/io.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/platform_device.h> 21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinconf.h> 25#include <linux/pinctrl/pinconf-generic.h> 26#include <linux/slab.h> 27#include <linux/gpio.h> 28#include <linux/interrupt.h> 29#include <linux/spinlock.h> 30#include <linux/reboot.h> 31 32#include "../core.h" 33#include "../pinconf.h" 34#include "pinctrl-msm.h" 35#include "../pinctrl-utils.h" 36 37#define MAX_NR_GPIO 300 38#define PS_HOLD_OFFSET 0x820 39 40/** 41 * struct msm_pinctrl - state for a pinctrl-msm device 42 * @dev: device handle. 43 * @pctrl: pinctrl handle. 44 * @chip: gpiochip handle. 45 * @restart_nb: restart notifier block. 46 * @irq: parent irq for the TLMM irq_chip. 47 * @lock: Spinlock to protect register resources as well 48 * as msm_pinctrl data structures. 49 * @enabled_irqs: Bitmap of currently enabled irqs. 50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 51 * detection. 52 * @soc; Reference to soc_data of platform specific data. 53 * @regs: Base address for the TLMM register map. 54 */ 55struct msm_pinctrl { 56 struct device *dev; 57 struct pinctrl_dev *pctrl; 58 struct gpio_chip chip; 59 struct notifier_block restart_nb; 60 int irq; 61 62 spinlock_t lock; 63 64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 66 67 const struct msm_pinctrl_soc_data *soc; 68 void __iomem *regs; 69}; 70 71static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) 72{ 73 return container_of(gc, struct msm_pinctrl, chip); 74} 75 76static int msm_get_groups_count(struct pinctrl_dev *pctldev) 77{ 78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 79 80 return pctrl->soc->ngroups; 81} 82 83static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 84 unsigned group) 85{ 86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 87 88 return pctrl->soc->groups[group].name; 89} 90 91static int msm_get_group_pins(struct pinctrl_dev *pctldev, 92 unsigned group, 93 const unsigned **pins, 94 unsigned *num_pins) 95{ 96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 97 98 *pins = pctrl->soc->groups[group].pins; 99 *num_pins = pctrl->soc->groups[group].npins; 100 return 0; 101} 102 103static const struct pinctrl_ops msm_pinctrl_ops = { 104 .get_groups_count = msm_get_groups_count, 105 .get_group_name = msm_get_group_name, 106 .get_group_pins = msm_get_group_pins, 107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 108 .dt_free_map = pinctrl_utils_dt_free_map, 109}; 110 111static int msm_get_functions_count(struct pinctrl_dev *pctldev) 112{ 113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 114 115 return pctrl->soc->nfunctions; 116} 117 118static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 119 unsigned function) 120{ 121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 123 return pctrl->soc->functions[function].name; 124} 125 126static int msm_get_function_groups(struct pinctrl_dev *pctldev, 127 unsigned function, 128 const char * const **groups, 129 unsigned * const num_groups) 130{ 131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 132 133 *groups = pctrl->soc->functions[function].groups; 134 *num_groups = pctrl->soc->functions[function].ngroups; 135 return 0; 136} 137 138static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 139 unsigned function, 140 unsigned group) 141{ 142 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 143 const struct msm_pingroup *g; 144 unsigned long flags; 145 u32 val; 146 int i; 147 148 g = &pctrl->soc->groups[group]; 149 150 for (i = 0; i < g->nfuncs; i++) { 151 if (g->funcs[i] == function) 152 break; 153 } 154 155 if (WARN_ON(i == g->nfuncs)) 156 return -EINVAL; 157 158 spin_lock_irqsave(&pctrl->lock, flags); 159 160 val = readl(pctrl->regs + g->ctl_reg); 161 val &= ~(0x7 << g->mux_bit); 162 val |= i << g->mux_bit; 163 writel(val, pctrl->regs + g->ctl_reg); 164 165 spin_unlock_irqrestore(&pctrl->lock, flags); 166 167 return 0; 168} 169 170static const struct pinmux_ops msm_pinmux_ops = { 171 .get_functions_count = msm_get_functions_count, 172 .get_function_name = msm_get_function_name, 173 .get_function_groups = msm_get_function_groups, 174 .set_mux = msm_pinmux_set_mux, 175}; 176 177static int msm_config_reg(struct msm_pinctrl *pctrl, 178 const struct msm_pingroup *g, 179 unsigned param, 180 unsigned *mask, 181 unsigned *bit) 182{ 183 switch (param) { 184 case PIN_CONFIG_BIAS_DISABLE: 185 case PIN_CONFIG_BIAS_PULL_DOWN: 186 case PIN_CONFIG_BIAS_BUS_HOLD: 187 case PIN_CONFIG_BIAS_PULL_UP: 188 *bit = g->pull_bit; 189 *mask = 3; 190 break; 191 case PIN_CONFIG_DRIVE_STRENGTH: 192 *bit = g->drv_bit; 193 *mask = 7; 194 break; 195 case PIN_CONFIG_OUTPUT: 196 *bit = g->oe_bit; 197 *mask = 1; 198 break; 199 default: 200 dev_err(pctrl->dev, "Invalid config param %04x\n", param); 201 return -ENOTSUPP; 202 } 203 204 return 0; 205} 206 207static int msm_config_get(struct pinctrl_dev *pctldev, 208 unsigned int pin, 209 unsigned long *config) 210{ 211 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 212 return -ENOTSUPP; 213} 214 215static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 216 unsigned long *configs, unsigned num_configs) 217{ 218 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 219 return -ENOTSUPP; 220} 221 222#define MSM_NO_PULL 0 223#define MSM_PULL_DOWN 1 224#define MSM_KEEPER 2 225#define MSM_PULL_UP 3 226 227static unsigned msm_regval_to_drive(u32 val) 228{ 229 return (val + 1) * 2; 230} 231 232static int msm_config_group_get(struct pinctrl_dev *pctldev, 233 unsigned int group, 234 unsigned long *config) 235{ 236 const struct msm_pingroup *g; 237 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 238 unsigned param = pinconf_to_config_param(*config); 239 unsigned mask; 240 unsigned arg; 241 unsigned bit; 242 int ret; 243 u32 val; 244 245 g = &pctrl->soc->groups[group]; 246 247 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 248 if (ret < 0) 249 return ret; 250 251 val = readl(pctrl->regs + g->ctl_reg); 252 arg = (val >> bit) & mask; 253 254 /* Convert register value to pinconf value */ 255 switch (param) { 256 case PIN_CONFIG_BIAS_DISABLE: 257 arg = arg == MSM_NO_PULL; 258 break; 259 case PIN_CONFIG_BIAS_PULL_DOWN: 260 arg = arg == MSM_PULL_DOWN; 261 break; 262 case PIN_CONFIG_BIAS_BUS_HOLD: 263 arg = arg == MSM_KEEPER; 264 break; 265 case PIN_CONFIG_BIAS_PULL_UP: 266 arg = arg == MSM_PULL_UP; 267 break; 268 case PIN_CONFIG_DRIVE_STRENGTH: 269 arg = msm_regval_to_drive(arg); 270 break; 271 case PIN_CONFIG_OUTPUT: 272 /* Pin is not output */ 273 if (!arg) 274 return -EINVAL; 275 276 val = readl(pctrl->regs + g->io_reg); 277 arg = !!(val & BIT(g->in_bit)); 278 break; 279 default: 280 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 281 param); 282 return -EINVAL; 283 } 284 285 *config = pinconf_to_config_packed(param, arg); 286 287 return 0; 288} 289 290static int msm_config_group_set(struct pinctrl_dev *pctldev, 291 unsigned group, 292 unsigned long *configs, 293 unsigned num_configs) 294{ 295 const struct msm_pingroup *g; 296 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 297 unsigned long flags; 298 unsigned param; 299 unsigned mask; 300 unsigned arg; 301 unsigned bit; 302 int ret; 303 u32 val; 304 int i; 305 306 g = &pctrl->soc->groups[group]; 307 308 for (i = 0; i < num_configs; i++) { 309 param = pinconf_to_config_param(configs[i]); 310 arg = pinconf_to_config_argument(configs[i]); 311 312 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 313 if (ret < 0) 314 return ret; 315 316 /* Convert pinconf values to register values */ 317 switch (param) { 318 case PIN_CONFIG_BIAS_DISABLE: 319 arg = MSM_NO_PULL; 320 break; 321 case PIN_CONFIG_BIAS_PULL_DOWN: 322 arg = MSM_PULL_DOWN; 323 break; 324 case PIN_CONFIG_BIAS_BUS_HOLD: 325 arg = MSM_KEEPER; 326 break; 327 case PIN_CONFIG_BIAS_PULL_UP: 328 arg = MSM_PULL_UP; 329 break; 330 case PIN_CONFIG_DRIVE_STRENGTH: 331 /* Check for invalid values */ 332 if (arg > 16 || arg < 2 || (arg % 2) != 0) 333 arg = -1; 334 else 335 arg = (arg / 2) - 1; 336 break; 337 case PIN_CONFIG_OUTPUT: 338 /* set output value */ 339 spin_lock_irqsave(&pctrl->lock, flags); 340 val = readl(pctrl->regs + g->io_reg); 341 if (arg) 342 val |= BIT(g->out_bit); 343 else 344 val &= ~BIT(g->out_bit); 345 writel(val, pctrl->regs + g->io_reg); 346 spin_unlock_irqrestore(&pctrl->lock, flags); 347 348 /* enable output */ 349 arg = 1; 350 break; 351 default: 352 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 353 param); 354 return -EINVAL; 355 } 356 357 /* Range-check user-supplied value */ 358 if (arg & ~mask) { 359 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 360 return -EINVAL; 361 } 362 363 spin_lock_irqsave(&pctrl->lock, flags); 364 val = readl(pctrl->regs + g->ctl_reg); 365 val &= ~(mask << bit); 366 val |= arg << bit; 367 writel(val, pctrl->regs + g->ctl_reg); 368 spin_unlock_irqrestore(&pctrl->lock, flags); 369 } 370 371 return 0; 372} 373 374static const struct pinconf_ops msm_pinconf_ops = { 375 .pin_config_get = msm_config_get, 376 .pin_config_set = msm_config_set, 377 .pin_config_group_get = msm_config_group_get, 378 .pin_config_group_set = msm_config_group_set, 379}; 380 381static struct pinctrl_desc msm_pinctrl_desc = { 382 .pctlops = &msm_pinctrl_ops, 383 .pmxops = &msm_pinmux_ops, 384 .confops = &msm_pinconf_ops, 385 .owner = THIS_MODULE, 386}; 387 388static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 389{ 390 const struct msm_pingroup *g; 391 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 392 unsigned long flags; 393 u32 val; 394 395 g = &pctrl->soc->groups[offset]; 396 397 spin_lock_irqsave(&pctrl->lock, flags); 398 399 val = readl(pctrl->regs + g->ctl_reg); 400 val &= ~BIT(g->oe_bit); 401 writel(val, pctrl->regs + g->ctl_reg); 402 403 spin_unlock_irqrestore(&pctrl->lock, flags); 404 405 return 0; 406} 407 408static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 409{ 410 const struct msm_pingroup *g; 411 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 412 unsigned long flags; 413 u32 val; 414 415 g = &pctrl->soc->groups[offset]; 416 417 spin_lock_irqsave(&pctrl->lock, flags); 418 419 val = readl(pctrl->regs + g->io_reg); 420 if (value) 421 val |= BIT(g->out_bit); 422 else 423 val &= ~BIT(g->out_bit); 424 writel(val, pctrl->regs + g->io_reg); 425 426 val = readl(pctrl->regs + g->ctl_reg); 427 val |= BIT(g->oe_bit); 428 writel(val, pctrl->regs + g->ctl_reg); 429 430 spin_unlock_irqrestore(&pctrl->lock, flags); 431 432 return 0; 433} 434 435static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 436{ 437 const struct msm_pingroup *g; 438 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 439 u32 val; 440 441 g = &pctrl->soc->groups[offset]; 442 443 val = readl(pctrl->regs + g->io_reg); 444 return !!(val & BIT(g->in_bit)); 445} 446 447static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 448{ 449 const struct msm_pingroup *g; 450 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 451 unsigned long flags; 452 u32 val; 453 454 g = &pctrl->soc->groups[offset]; 455 456 spin_lock_irqsave(&pctrl->lock, flags); 457 458 val = readl(pctrl->regs + g->io_reg); 459 if (value) 460 val |= BIT(g->out_bit); 461 else 462 val &= ~BIT(g->out_bit); 463 writel(val, pctrl->regs + g->io_reg); 464 465 spin_unlock_irqrestore(&pctrl->lock, flags); 466} 467 468static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) 469{ 470 int gpio = chip->base + offset; 471 return pinctrl_request_gpio(gpio); 472} 473 474static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) 475{ 476 int gpio = chip->base + offset; 477 return pinctrl_free_gpio(gpio); 478} 479 480#ifdef CONFIG_DEBUG_FS 481#include <linux/seq_file.h> 482 483static void msm_gpio_dbg_show_one(struct seq_file *s, 484 struct pinctrl_dev *pctldev, 485 struct gpio_chip *chip, 486 unsigned offset, 487 unsigned gpio) 488{ 489 const struct msm_pingroup *g; 490 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 491 unsigned func; 492 int is_out; 493 int drive; 494 int pull; 495 u32 ctl_reg; 496 497 static const char * const pulls[] = { 498 "no pull", 499 "pull down", 500 "keeper", 501 "pull up" 502 }; 503 504 g = &pctrl->soc->groups[offset]; 505 ctl_reg = readl(pctrl->regs + g->ctl_reg); 506 507 is_out = !!(ctl_reg & BIT(g->oe_bit)); 508 func = (ctl_reg >> g->mux_bit) & 7; 509 drive = (ctl_reg >> g->drv_bit) & 7; 510 pull = (ctl_reg >> g->pull_bit) & 3; 511 512 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 513 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 514 seq_printf(s, " %s", pulls[pull]); 515} 516 517static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 518{ 519 unsigned gpio = chip->base; 520 unsigned i; 521 522 for (i = 0; i < chip->ngpio; i++, gpio++) { 523 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 524 seq_puts(s, "\n"); 525 } 526} 527 528#else 529#define msm_gpio_dbg_show NULL 530#endif 531 532static struct gpio_chip msm_gpio_template = { 533 .direction_input = msm_gpio_direction_input, 534 .direction_output = msm_gpio_direction_output, 535 .get = msm_gpio_get, 536 .set = msm_gpio_set, 537 .request = msm_gpio_request, 538 .free = msm_gpio_free, 539 .dbg_show = msm_gpio_dbg_show, 540}; 541 542/* For dual-edge interrupts in software, since some hardware has no 543 * such support: 544 * 545 * At appropriate moments, this function may be called to flip the polarity 546 * settings of both-edge irq lines to try and catch the next edge. 547 * 548 * The attempt is considered successful if: 549 * - the status bit goes high, indicating that an edge was caught, or 550 * - the input value of the gpio doesn't change during the attempt. 551 * If the value changes twice during the process, that would cause the first 552 * test to fail but would force the second, as two opposite 553 * transitions would cause a detection no matter the polarity setting. 554 * 555 * The do-loop tries to sledge-hammer closed the timing hole between 556 * the initial value-read and the polarity-write - if the line value changes 557 * during that window, an interrupt is lost, the new polarity setting is 558 * incorrect, and the first success test will fail, causing a retry. 559 * 560 * Algorithm comes from Google's msmgpio driver. 561 */ 562static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 563 const struct msm_pingroup *g, 564 struct irq_data *d) 565{ 566 int loop_limit = 100; 567 unsigned val, val2, intstat; 568 unsigned pol; 569 570 do { 571 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 572 573 pol = readl(pctrl->regs + g->intr_cfg_reg); 574 pol ^= BIT(g->intr_polarity_bit); 575 writel(pol, pctrl->regs + g->intr_cfg_reg); 576 577 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 578 intstat = readl(pctrl->regs + g->intr_status_reg); 579 if (intstat || (val == val2)) 580 return; 581 } while (loop_limit-- > 0); 582 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 583 val, val2); 584} 585 586static void msm_gpio_irq_mask(struct irq_data *d) 587{ 588 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 589 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 590 const struct msm_pingroup *g; 591 unsigned long flags; 592 u32 val; 593 594 g = &pctrl->soc->groups[d->hwirq]; 595 596 spin_lock_irqsave(&pctrl->lock, flags); 597 598 val = readl(pctrl->regs + g->intr_cfg_reg); 599 val &= ~BIT(g->intr_enable_bit); 600 writel(val, pctrl->regs + g->intr_cfg_reg); 601 602 clear_bit(d->hwirq, pctrl->enabled_irqs); 603 604 spin_unlock_irqrestore(&pctrl->lock, flags); 605} 606 607static void msm_gpio_irq_unmask(struct irq_data *d) 608{ 609 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 610 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 611 const struct msm_pingroup *g; 612 unsigned long flags; 613 u32 val; 614 615 g = &pctrl->soc->groups[d->hwirq]; 616 617 spin_lock_irqsave(&pctrl->lock, flags); 618 619 val = readl(pctrl->regs + g->intr_status_reg); 620 val &= ~BIT(g->intr_status_bit); 621 writel(val, pctrl->regs + g->intr_status_reg); 622 623 val = readl(pctrl->regs + g->intr_cfg_reg); 624 val |= BIT(g->intr_enable_bit); 625 writel(val, pctrl->regs + g->intr_cfg_reg); 626 627 set_bit(d->hwirq, pctrl->enabled_irqs); 628 629 spin_unlock_irqrestore(&pctrl->lock, flags); 630} 631 632static void msm_gpio_irq_ack(struct irq_data *d) 633{ 634 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 635 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 636 const struct msm_pingroup *g; 637 unsigned long flags; 638 u32 val; 639 640 g = &pctrl->soc->groups[d->hwirq]; 641 642 spin_lock_irqsave(&pctrl->lock, flags); 643 644 val = readl(pctrl->regs + g->intr_status_reg); 645 if (g->intr_ack_high) 646 val |= BIT(g->intr_status_bit); 647 else 648 val &= ~BIT(g->intr_status_bit); 649 writel(val, pctrl->regs + g->intr_status_reg); 650 651 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 652 msm_gpio_update_dual_edge_pos(pctrl, g, d); 653 654 spin_unlock_irqrestore(&pctrl->lock, flags); 655} 656 657static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 658{ 659 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 660 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 661 const struct msm_pingroup *g; 662 unsigned long flags; 663 u32 val; 664 665 g = &pctrl->soc->groups[d->hwirq]; 666 667 spin_lock_irqsave(&pctrl->lock, flags); 668 669 /* 670 * For hw without possibility of detecting both edges 671 */ 672 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 673 set_bit(d->hwirq, pctrl->dual_edge_irqs); 674 else 675 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 676 677 /* Route interrupts to application cpu */ 678 val = readl(pctrl->regs + g->intr_target_reg); 679 val &= ~(7 << g->intr_target_bit); 680 val |= g->intr_target_kpss_val << g->intr_target_bit; 681 writel(val, pctrl->regs + g->intr_target_reg); 682 683 /* Update configuration for gpio. 684 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 685 * internal circuitry of TLMM, toggling the RAW_STATUS 686 * could cause the INTR_STATUS to be set for EDGE interrupts. 687 */ 688 val = readl(pctrl->regs + g->intr_cfg_reg); 689 val |= BIT(g->intr_raw_status_bit); 690 if (g->intr_detection_width == 2) { 691 val &= ~(3 << g->intr_detection_bit); 692 val &= ~(1 << g->intr_polarity_bit); 693 switch (type) { 694 case IRQ_TYPE_EDGE_RISING: 695 val |= 1 << g->intr_detection_bit; 696 val |= BIT(g->intr_polarity_bit); 697 break; 698 case IRQ_TYPE_EDGE_FALLING: 699 val |= 2 << g->intr_detection_bit; 700 val |= BIT(g->intr_polarity_bit); 701 break; 702 case IRQ_TYPE_EDGE_BOTH: 703 val |= 3 << g->intr_detection_bit; 704 val |= BIT(g->intr_polarity_bit); 705 break; 706 case IRQ_TYPE_LEVEL_LOW: 707 break; 708 case IRQ_TYPE_LEVEL_HIGH: 709 val |= BIT(g->intr_polarity_bit); 710 break; 711 } 712 } else if (g->intr_detection_width == 1) { 713 val &= ~(1 << g->intr_detection_bit); 714 val &= ~(1 << g->intr_polarity_bit); 715 switch (type) { 716 case IRQ_TYPE_EDGE_RISING: 717 val |= BIT(g->intr_detection_bit); 718 val |= BIT(g->intr_polarity_bit); 719 break; 720 case IRQ_TYPE_EDGE_FALLING: 721 val |= BIT(g->intr_detection_bit); 722 break; 723 case IRQ_TYPE_EDGE_BOTH: 724 val |= BIT(g->intr_detection_bit); 725 val |= BIT(g->intr_polarity_bit); 726 break; 727 case IRQ_TYPE_LEVEL_LOW: 728 break; 729 case IRQ_TYPE_LEVEL_HIGH: 730 val |= BIT(g->intr_polarity_bit); 731 break; 732 } 733 } else { 734 BUG(); 735 } 736 writel(val, pctrl->regs + g->intr_cfg_reg); 737 738 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 739 msm_gpio_update_dual_edge_pos(pctrl, g, d); 740 741 spin_unlock_irqrestore(&pctrl->lock, flags); 742 743 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 744 __irq_set_handler_locked(d->irq, handle_level_irq); 745 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 746 __irq_set_handler_locked(d->irq, handle_edge_irq); 747 748 return 0; 749} 750 751static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 752{ 753 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 754 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 755 unsigned long flags; 756 757 spin_lock_irqsave(&pctrl->lock, flags); 758 759 irq_set_irq_wake(pctrl->irq, on); 760 761 spin_unlock_irqrestore(&pctrl->lock, flags); 762 763 return 0; 764} 765 766static struct irq_chip msm_gpio_irq_chip = { 767 .name = "msmgpio", 768 .irq_mask = msm_gpio_irq_mask, 769 .irq_unmask = msm_gpio_irq_unmask, 770 .irq_ack = msm_gpio_irq_ack, 771 .irq_set_type = msm_gpio_irq_set_type, 772 .irq_set_wake = msm_gpio_irq_set_wake, 773}; 774 775static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 776{ 777 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 778 const struct msm_pingroup *g; 779 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 780 struct irq_chip *chip = irq_get_chip(irq); 781 int irq_pin; 782 int handled = 0; 783 u32 val; 784 int i; 785 786 chained_irq_enter(chip, desc); 787 788 /* 789 * Each pin has it's own IRQ status register, so use 790 * enabled_irq bitmap to limit the number of reads. 791 */ 792 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 793 g = &pctrl->soc->groups[i]; 794 val = readl(pctrl->regs + g->intr_status_reg); 795 if (val & BIT(g->intr_status_bit)) { 796 irq_pin = irq_find_mapping(gc->irqdomain, i); 797 generic_handle_irq(irq_pin); 798 handled++; 799 } 800 } 801 802 /* No interrupts were flagged */ 803 if (handled == 0) 804 handle_bad_irq(irq, desc); 805 806 chained_irq_exit(chip, desc); 807} 808 809static int msm_gpio_init(struct msm_pinctrl *pctrl) 810{ 811 struct gpio_chip *chip; 812 int ret; 813 unsigned ngpio = pctrl->soc->ngpios; 814 815 if (WARN_ON(ngpio > MAX_NR_GPIO)) 816 return -EINVAL; 817 818 chip = &pctrl->chip; 819 chip->base = 0; 820 chip->ngpio = ngpio; 821 chip->label = dev_name(pctrl->dev); 822 chip->dev = pctrl->dev; 823 chip->owner = THIS_MODULE; 824 chip->of_node = pctrl->dev->of_node; 825 826 ret = gpiochip_add(&pctrl->chip); 827 if (ret) { 828 dev_err(pctrl->dev, "Failed register gpiochip\n"); 829 return ret; 830 } 831 832 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 833 if (ret) { 834 dev_err(pctrl->dev, "Failed to add pin range\n"); 835 gpiochip_remove(&pctrl->chip); 836 return ret; 837 } 838 839 ret = gpiochip_irqchip_add(chip, 840 &msm_gpio_irq_chip, 841 0, 842 handle_edge_irq, 843 IRQ_TYPE_NONE); 844 if (ret) { 845 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 846 gpiochip_remove(&pctrl->chip); 847 return -ENOSYS; 848 } 849 850 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, 851 msm_gpio_irq_handler); 852 853 return 0; 854} 855 856static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 857 void *data) 858{ 859 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 860 861 writel(0, pctrl->regs + PS_HOLD_OFFSET); 862 mdelay(1000); 863 return NOTIFY_DONE; 864} 865 866static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 867{ 868 int i = 0; 869 const struct msm_function *func = pctrl->soc->functions; 870 871 for (; i <= pctrl->soc->nfunctions; i++) 872 if (!strcmp(func[i].name, "ps_hold")) { 873 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 874 pctrl->restart_nb.priority = 128; 875 if (register_restart_handler(&pctrl->restart_nb)) 876 dev_err(pctrl->dev, 877 "failed to setup restart handler.\n"); 878 break; 879 } 880} 881 882int msm_pinctrl_probe(struct platform_device *pdev, 883 const struct msm_pinctrl_soc_data *soc_data) 884{ 885 struct msm_pinctrl *pctrl; 886 struct resource *res; 887 int ret; 888 889 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 890 if (!pctrl) { 891 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); 892 return -ENOMEM; 893 } 894 pctrl->dev = &pdev->dev; 895 pctrl->soc = soc_data; 896 pctrl->chip = msm_gpio_template; 897 898 spin_lock_init(&pctrl->lock); 899 900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 901 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 902 if (IS_ERR(pctrl->regs)) 903 return PTR_ERR(pctrl->regs); 904 905 msm_pinctrl_setup_pm_reset(pctrl); 906 907 pctrl->irq = platform_get_irq(pdev, 0); 908 if (pctrl->irq < 0) { 909 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 910 return pctrl->irq; 911 } 912 913 msm_pinctrl_desc.name = dev_name(&pdev->dev); 914 msm_pinctrl_desc.pins = pctrl->soc->pins; 915 msm_pinctrl_desc.npins = pctrl->soc->npins; 916 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); 917 if (!pctrl->pctrl) { 918 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 919 return -ENODEV; 920 } 921 922 ret = msm_gpio_init(pctrl); 923 if (ret) { 924 pinctrl_unregister(pctrl->pctrl); 925 return ret; 926 } 927 928 platform_set_drvdata(pdev, pctrl); 929 930 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 931 932 return 0; 933} 934EXPORT_SYMBOL(msm_pinctrl_probe); 935 936int msm_pinctrl_remove(struct platform_device *pdev) 937{ 938 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 939 940 gpiochip_remove(&pctrl->chip); 941 pinctrl_unregister(pctrl->pctrl); 942 943 unregister_restart_handler(&pctrl->restart_nb); 944 945 return 0; 946} 947EXPORT_SYMBOL(msm_pinctrl_remove); 948 949