1/* 2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/module.h> 14#include <linux/platform_device.h> 15#include <linux/io.h> 16#include <linux/slab.h> 17#include <linux/err.h> 18#include <linux/gpio.h> 19#include <linux/device.h> 20#include <linux/pinctrl/pinctrl.h> 21#include <linux/pinctrl/pinmux.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/interrupt.h> 24#include <linux/irqdomain.h> 25#include <linux/of_irq.h> 26#include "../core.h" 27 28/* EXYNOS5440 GPIO and Pinctrl register offsets */ 29#define GPIO_MUX 0x00 30#define GPIO_IE 0x04 31#define GPIO_INT 0x08 32#define GPIO_TYPE 0x0C 33#define GPIO_VAL 0x10 34#define GPIO_OE 0x14 35#define GPIO_IN 0x18 36#define GPIO_PE 0x1C 37#define GPIO_PS 0x20 38#define GPIO_SR 0x24 39#define GPIO_DS0 0x28 40#define GPIO_DS1 0x2C 41 42#define EXYNOS5440_MAX_PINS 23 43#define EXYNOS5440_MAX_GPIO_INT 8 44#define PIN_NAME_LENGTH 10 45 46#define GROUP_SUFFIX "-grp" 47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX) 48#define FUNCTION_SUFFIX "-mux" 49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX) 50 51/* 52 * pin configuration type and its value are packed together into a 16-bits. 53 * The upper 8-bits represent the configuration type and the lower 8-bits 54 * hold the value of the configuration type. 55 */ 56#define PINCFG_TYPE_MASK 0xFF 57#define PINCFG_VALUE_SHIFT 8 58#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) 59#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) 60#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) 61#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ 62 PINCFG_VALUE_SHIFT) 63 64/** 65 * enum pincfg_type - possible pin configuration types supported. 66 * @PINCFG_TYPE_PUD: Pull up/down configuration. 67 * @PINCFG_TYPE_DRV: Drive strength configuration. 68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration. 69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration. 70 */ 71enum pincfg_type { 72 PINCFG_TYPE_PUD, 73 PINCFG_TYPE_DRV, 74 PINCFG_TYPE_SKEW_RATE, 75 PINCFG_TYPE_INPUT_TYPE 76}; 77 78/** 79 * struct exynos5440_pin_group: represent group of pins for pincfg setting. 80 * @name: name of the pin group, used to lookup the group. 81 * @pins: the pins included in this group. 82 * @num_pins: number of pins included in this group. 83 */ 84struct exynos5440_pin_group { 85 const char *name; 86 const unsigned int *pins; 87 u8 num_pins; 88}; 89 90/** 91 * struct exynos5440_pmx_func: represent a pin function. 92 * @name: name of the pin function, used to lookup the function. 93 * @groups: one or more names of pin groups that provide this function. 94 * @num_groups: number of groups included in @groups. 95 * @function: the function number to be programmed when selected. 96 */ 97struct exynos5440_pmx_func { 98 const char *name; 99 const char **groups; 100 u8 num_groups; 101 unsigned long function; 102}; 103 104/** 105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data. 106 * @reg_base: ioremapped based address of the register space. 107 * @gc: gpio chip registered with gpiolib. 108 * @pin_groups: list of pin groups parsed from device tree. 109 * @nr_groups: number of pin groups available. 110 * @pmx_functions: list of pin functions parsed from device tree. 111 * @nr_functions: number of pin functions available. 112 */ 113struct exynos5440_pinctrl_priv_data { 114 void __iomem *reg_base; 115 struct gpio_chip *gc; 116 struct irq_domain *irq_domain; 117 118 const struct exynos5440_pin_group *pin_groups; 119 unsigned int nr_groups; 120 const struct exynos5440_pmx_func *pmx_functions; 121 unsigned int nr_functions; 122}; 123 124/** 125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts. 126 * @priv: driver's private runtime data. 127 * @gpio_int: gpio interrupt number. 128 */ 129struct exynos5440_gpio_intr_data { 130 struct exynos5440_pinctrl_priv_data *priv; 131 unsigned int gpio_int; 132}; 133 134/* list of all possible config options supported */ 135static struct pin_config { 136 char *prop_cfg; 137 unsigned int cfg_type; 138} pcfgs[] = { 139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD }, 140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV }, 141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE }, 142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE }, 143}; 144 145/* check if the selector is a valid pin group selector */ 146static int exynos5440_get_group_count(struct pinctrl_dev *pctldev) 147{ 148 struct exynos5440_pinctrl_priv_data *priv; 149 150 priv = pinctrl_dev_get_drvdata(pctldev); 151 return priv->nr_groups; 152} 153 154/* return the name of the group selected by the group selector */ 155static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev, 156 unsigned selector) 157{ 158 struct exynos5440_pinctrl_priv_data *priv; 159 160 priv = pinctrl_dev_get_drvdata(pctldev); 161 return priv->pin_groups[selector].name; 162} 163 164/* return the pin numbers associated with the specified group */ 165static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev, 166 unsigned selector, const unsigned **pins, unsigned *num_pins) 167{ 168 struct exynos5440_pinctrl_priv_data *priv; 169 170 priv = pinctrl_dev_get_drvdata(pctldev); 171 *pins = priv->pin_groups[selector].pins; 172 *num_pins = priv->pin_groups[selector].num_pins; 173 return 0; 174} 175 176/* create pinctrl_map entries by parsing device tree nodes */ 177static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, 178 struct device_node *np, struct pinctrl_map **maps, 179 unsigned *nmaps) 180{ 181 struct device *dev = pctldev->dev; 182 struct pinctrl_map *map; 183 unsigned long *cfg = NULL; 184 char *gname, *fname; 185 int cfg_cnt = 0, map_cnt = 0, idx = 0; 186 187 /* count the number of config options specfied in the node */ 188 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) 189 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) 190 cfg_cnt++; 191 192 /* 193 * Find out the number of map entries to create. All the config options 194 * can be accomadated into a single config map entry. 195 */ 196 if (cfg_cnt) 197 map_cnt = 1; 198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) 199 map_cnt++; 200 if (!map_cnt) { 201 dev_err(dev, "node %s does not have either config or function " 202 "configurations\n", np->name); 203 return -EINVAL; 204 } 205 206 /* Allocate memory for pin-map entries */ 207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); 208 if (!map) { 209 dev_err(dev, "could not alloc memory for pin-maps\n"); 210 return -ENOMEM; 211 } 212 *nmaps = 0; 213 214 /* 215 * Allocate memory for pin group name. The pin group name is derived 216 * from the node name from which these map entries are be created. 217 */ 218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); 219 if (!gname) { 220 dev_err(dev, "failed to alloc memory for group name\n"); 221 goto free_map; 222 } 223 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX); 224 225 /* 226 * don't have config options? then skip over to creating function 227 * map entries. 228 */ 229 if (!cfg_cnt) 230 goto skip_cfgs; 231 232 /* Allocate memory for config entries */ 233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); 234 if (!cfg) { 235 dev_err(dev, "failed to alloc memory for configs\n"); 236 goto free_gname; 237 } 238 239 /* Prepare a list of config settings */ 240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { 241 u32 value; 242 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) 243 cfg[cfg_cnt++] = 244 PINCFG_PACK(pcfgs[idx].cfg_type, value); 245 } 246 247 /* create the config map entry */ 248 map[*nmaps].data.configs.group_or_pin = gname; 249 map[*nmaps].data.configs.configs = cfg; 250 map[*nmaps].data.configs.num_configs = cfg_cnt; 251 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 252 *nmaps += 1; 253 254skip_cfgs: 255 /* create the function map entry */ 256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { 257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); 258 if (!fname) { 259 dev_err(dev, "failed to alloc memory for func name\n"); 260 goto free_cfg; 261 } 262 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name, 263 FUNCTION_SUFFIX); 264 265 map[*nmaps].data.mux.group = gname; 266 map[*nmaps].data.mux.function = fname; 267 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 268 *nmaps += 1; 269 } 270 271 *maps = map; 272 return 0; 273 274free_cfg: 275 kfree(cfg); 276free_gname: 277 kfree(gname); 278free_map: 279 kfree(map); 280 return -ENOMEM; 281} 282 283/* free the memory allocated to hold the pin-map table */ 284static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, 285 struct pinctrl_map *map, unsigned num_maps) 286{ 287 int idx; 288 289 for (idx = 0; idx < num_maps; idx++) { 290 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { 291 kfree(map[idx].data.mux.function); 292 if (!idx) 293 kfree(map[idx].data.mux.group); 294 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { 295 kfree(map[idx].data.configs.configs); 296 if (!idx) 297 kfree(map[idx].data.configs.group_or_pin); 298 } 299 }; 300 301 kfree(map); 302} 303 304/* list of pinctrl callbacks for the pinctrl core */ 305static const struct pinctrl_ops exynos5440_pctrl_ops = { 306 .get_groups_count = exynos5440_get_group_count, 307 .get_group_name = exynos5440_get_group_name, 308 .get_group_pins = exynos5440_get_group_pins, 309 .dt_node_to_map = exynos5440_dt_node_to_map, 310 .dt_free_map = exynos5440_dt_free_map, 311}; 312 313/* check if the selector is a valid pin function selector */ 314static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev) 315{ 316 struct exynos5440_pinctrl_priv_data *priv; 317 318 priv = pinctrl_dev_get_drvdata(pctldev); 319 return priv->nr_functions; 320} 321 322/* return the name of the pin function specified */ 323static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev, 324 unsigned selector) 325{ 326 struct exynos5440_pinctrl_priv_data *priv; 327 328 priv = pinctrl_dev_get_drvdata(pctldev); 329 return priv->pmx_functions[selector].name; 330} 331 332/* return the groups associated for the specified function selector */ 333static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev, 334 unsigned selector, const char * const **groups, 335 unsigned * const num_groups) 336{ 337 struct exynos5440_pinctrl_priv_data *priv; 338 339 priv = pinctrl_dev_get_drvdata(pctldev); 340 *groups = priv->pmx_functions[selector].groups; 341 *num_groups = priv->pmx_functions[selector].num_groups; 342 return 0; 343} 344 345/* enable or disable a pinmux function */ 346static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, 347 unsigned group, bool enable) 348{ 349 struct exynos5440_pinctrl_priv_data *priv; 350 void __iomem *base; 351 u32 function; 352 u32 data; 353 354 priv = pinctrl_dev_get_drvdata(pctldev); 355 base = priv->reg_base; 356 function = priv->pmx_functions[selector].function; 357 358 data = readl(base + GPIO_MUX); 359 if (enable) 360 data |= (1 << function); 361 else 362 data &= ~(1 << function); 363 writel(data, base + GPIO_MUX); 364} 365 366/* enable a specified pinmux by writing to registers */ 367static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev, 368 unsigned selector, 369 unsigned group) 370{ 371 exynos5440_pinmux_setup(pctldev, selector, group, true); 372 return 0; 373} 374 375/* 376 * The calls to gpio_direction_output() and gpio_direction_input() 377 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 378 * function called from the gpiolib interface). 379 */ 380static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 381 struct pinctrl_gpio_range *range, unsigned offset, bool input) 382{ 383 return 0; 384} 385 386/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ 387static const struct pinmux_ops exynos5440_pinmux_ops = { 388 .get_functions_count = exynos5440_get_functions_count, 389 .get_function_name = exynos5440_pinmux_get_fname, 390 .get_function_groups = exynos5440_pinmux_get_groups, 391 .set_mux = exynos5440_pinmux_set_mux, 392 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, 393}; 394 395/* set the pin config settings for a specified pin */ 396static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 397 unsigned long *configs, 398 unsigned num_configs) 399{ 400 struct exynos5440_pinctrl_priv_data *priv; 401 void __iomem *base; 402 enum pincfg_type cfg_type; 403 u32 cfg_value; 404 u32 data; 405 int i; 406 407 priv = pinctrl_dev_get_drvdata(pctldev); 408 base = priv->reg_base; 409 410 for (i = 0; i < num_configs; i++) { 411 cfg_type = PINCFG_UNPACK_TYPE(configs[i]); 412 cfg_value = PINCFG_UNPACK_VALUE(configs[i]); 413 414 switch (cfg_type) { 415 case PINCFG_TYPE_PUD: 416 /* first set pull enable/disable bit */ 417 data = readl(base + GPIO_PE); 418 data &= ~(1 << pin); 419 if (cfg_value) 420 data |= (1 << pin); 421 writel(data, base + GPIO_PE); 422 423 /* then set pull up/down bit */ 424 data = readl(base + GPIO_PS); 425 data &= ~(1 << pin); 426 if (cfg_value == 2) 427 data |= (1 << pin); 428 writel(data, base + GPIO_PS); 429 break; 430 431 case PINCFG_TYPE_DRV: 432 /* set the first bit of the drive strength */ 433 data = readl(base + GPIO_DS0); 434 data &= ~(1 << pin); 435 data |= ((cfg_value & 1) << pin); 436 writel(data, base + GPIO_DS0); 437 cfg_value >>= 1; 438 439 /* set the second bit of the driver strength */ 440 data = readl(base + GPIO_DS1); 441 data &= ~(1 << pin); 442 data |= ((cfg_value & 1) << pin); 443 writel(data, base + GPIO_DS1); 444 break; 445 case PINCFG_TYPE_SKEW_RATE: 446 data = readl(base + GPIO_SR); 447 data &= ~(1 << pin); 448 data |= ((cfg_value & 1) << pin); 449 writel(data, base + GPIO_SR); 450 break; 451 case PINCFG_TYPE_INPUT_TYPE: 452 data = readl(base + GPIO_TYPE); 453 data &= ~(1 << pin); 454 data |= ((cfg_value & 1) << pin); 455 writel(data, base + GPIO_TYPE); 456 break; 457 default: 458 WARN_ON(1); 459 return -EINVAL; 460 } 461 } /* for each config */ 462 463 return 0; 464} 465 466/* get the pin config settings for a specified pin */ 467static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 468 unsigned long *config) 469{ 470 struct exynos5440_pinctrl_priv_data *priv; 471 void __iomem *base; 472 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); 473 u32 data; 474 475 priv = pinctrl_dev_get_drvdata(pctldev); 476 base = priv->reg_base; 477 478 switch (cfg_type) { 479 case PINCFG_TYPE_PUD: 480 data = readl(base + GPIO_PE); 481 data = (data >> pin) & 1; 482 if (!data) 483 *config = 0; 484 else 485 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; 486 break; 487 case PINCFG_TYPE_DRV: 488 data = readl(base + GPIO_DS0); 489 data = (data >> pin) & 1; 490 *config = data; 491 data = readl(base + GPIO_DS1); 492 data = (data >> pin) & 1; 493 *config |= (data << 1); 494 break; 495 case PINCFG_TYPE_SKEW_RATE: 496 data = readl(base + GPIO_SR); 497 *config = (data >> pin) & 1; 498 break; 499 case PINCFG_TYPE_INPUT_TYPE: 500 data = readl(base + GPIO_TYPE); 501 *config = (data >> pin) & 1; 502 break; 503 default: 504 WARN_ON(1); 505 return -EINVAL; 506 } 507 508 return 0; 509} 510 511/* set the pin config settings for a specified pin group */ 512static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, 513 unsigned group, unsigned long *configs, 514 unsigned num_configs) 515{ 516 struct exynos5440_pinctrl_priv_data *priv; 517 const unsigned int *pins; 518 unsigned int cnt; 519 520 priv = pinctrl_dev_get_drvdata(pctldev); 521 pins = priv->pin_groups[group].pins; 522 523 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) 524 exynos5440_pinconf_set(pctldev, pins[cnt], configs, 525 num_configs); 526 527 return 0; 528} 529 530/* get the pin config settings for a specified pin group */ 531static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, 532 unsigned int group, unsigned long *config) 533{ 534 struct exynos5440_pinctrl_priv_data *priv; 535 const unsigned int *pins; 536 537 priv = pinctrl_dev_get_drvdata(pctldev); 538 pins = priv->pin_groups[group].pins; 539 exynos5440_pinconf_get(pctldev, pins[0], config); 540 return 0; 541} 542 543/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ 544static const struct pinconf_ops exynos5440_pinconf_ops = { 545 .pin_config_get = exynos5440_pinconf_get, 546 .pin_config_set = exynos5440_pinconf_set, 547 .pin_config_group_get = exynos5440_pinconf_group_get, 548 .pin_config_group_set = exynos5440_pinconf_group_set, 549}; 550 551/* gpiolib gpio_set callback function */ 552static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 553{ 554 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 555 void __iomem *base = priv->reg_base; 556 u32 data; 557 558 data = readl(base + GPIO_VAL); 559 data &= ~(1 << offset); 560 if (value) 561 data |= 1 << offset; 562 writel(data, base + GPIO_VAL); 563} 564 565/* gpiolib gpio_get callback function */ 566static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset) 567{ 568 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 569 void __iomem *base = priv->reg_base; 570 u32 data; 571 572 data = readl(base + GPIO_IN); 573 data >>= offset; 574 data &= 1; 575 return data; 576} 577 578/* gpiolib gpio_direction_input callback function */ 579static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 580{ 581 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 582 void __iomem *base = priv->reg_base; 583 u32 data; 584 585 /* first disable the data output enable on this pin */ 586 data = readl(base + GPIO_OE); 587 data &= ~(1 << offset); 588 writel(data, base + GPIO_OE); 589 590 /* now enable input on this pin */ 591 data = readl(base + GPIO_IE); 592 data |= 1 << offset; 593 writel(data, base + GPIO_IE); 594 return 0; 595} 596 597/* gpiolib gpio_direction_output callback function */ 598static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 599 int value) 600{ 601 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 602 void __iomem *base = priv->reg_base; 603 u32 data; 604 605 exynos5440_gpio_set(gc, offset, value); 606 607 /* first disable the data input enable on this pin */ 608 data = readl(base + GPIO_IE); 609 data &= ~(1 << offset); 610 writel(data, base + GPIO_IE); 611 612 /* now enable output on this pin */ 613 data = readl(base + GPIO_OE); 614 data |= 1 << offset; 615 writel(data, base + GPIO_OE); 616 return 0; 617} 618 619/* gpiolib gpio_to_irq callback function */ 620static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 621{ 622 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev); 623 unsigned int virq; 624 625 if (offset < 16 || offset > 23) 626 return -ENXIO; 627 628 if (!priv->irq_domain) 629 return -ENXIO; 630 631 virq = irq_create_mapping(priv->irq_domain, offset - 16); 632 return virq ? : -ENXIO; 633} 634 635/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ 636static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, 637 struct device_node *cfg_np, unsigned int **pin_list, 638 unsigned int *npins) 639{ 640 struct device *dev = &pdev->dev; 641 struct property *prop; 642 643 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL); 644 if (!prop) 645 return -ENOENT; 646 647 *npins = prop->length / sizeof(unsigned long); 648 if (!*npins) { 649 dev_err(dev, "invalid pin list in %s node", cfg_np->name); 650 return -EINVAL; 651 } 652 653 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); 654 if (!*pin_list) { 655 dev_err(dev, "failed to allocate memory for pin list\n"); 656 return -ENOMEM; 657 } 658 659 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", 660 *pin_list, *npins); 661} 662 663/* 664 * Parse the information about all the available pin groups and pin functions 665 * from device node of the pin-controller. 666 */ 667static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, 668 struct exynos5440_pinctrl_priv_data *priv) 669{ 670 struct device *dev = &pdev->dev; 671 struct device_node *dev_np = dev->of_node; 672 struct device_node *cfg_np; 673 struct exynos5440_pin_group *groups, *grp; 674 struct exynos5440_pmx_func *functions, *func; 675 unsigned *pin_list; 676 unsigned int npins, grp_cnt, func_idx = 0; 677 char *gname, *fname; 678 int ret; 679 680 grp_cnt = of_get_child_count(dev_np); 681 if (!grp_cnt) 682 return -EINVAL; 683 684 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); 685 if (!groups) { 686 dev_err(dev, "failed allocate memory for ping group list\n"); 687 return -EINVAL; 688 } 689 grp = groups; 690 691 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); 692 if (!functions) { 693 dev_err(dev, "failed to allocate memory for function list\n"); 694 return -EINVAL; 695 } 696 func = functions; 697 698 /* 699 * Iterate over all the child nodes of the pin controller node 700 * and create pin groups and pin function lists. 701 */ 702 for_each_child_of_node(dev_np, cfg_np) { 703 u32 function; 704 705 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np, 706 &pin_list, &npins); 707 if (ret) { 708 gname = NULL; 709 goto skip_to_pin_function; 710 } 711 712 /* derive pin group name from the node name */ 713 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, 714 GFP_KERNEL); 715 if (!gname) { 716 dev_err(dev, "failed to alloc memory for group name\n"); 717 return -ENOMEM; 718 } 719 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, 720 GROUP_SUFFIX); 721 722 grp->name = gname; 723 grp->pins = pin_list; 724 grp->num_pins = npins; 725 grp++; 726 727skip_to_pin_function: 728 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", 729 &function); 730 if (ret) 731 continue; 732 733 /* derive function name from the node name */ 734 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, 735 GFP_KERNEL); 736 if (!fname) { 737 dev_err(dev, "failed to alloc memory for func name\n"); 738 return -ENOMEM; 739 } 740 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name, 741 FUNCTION_SUFFIX); 742 743 func->name = fname; 744 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 745 if (!func->groups) { 746 dev_err(dev, "failed to alloc memory for group list " 747 "in pin function"); 748 return -ENOMEM; 749 } 750 func->groups[0] = gname; 751 func->num_groups = gname ? 1 : 0; 752 func->function = function; 753 func++; 754 func_idx++; 755 } 756 757 priv->pin_groups = groups; 758 priv->nr_groups = grp_cnt; 759 priv->pmx_functions = functions; 760 priv->nr_functions = func_idx; 761 return 0; 762} 763 764/* register the pinctrl interface with the pinctrl subsystem */ 765static int exynos5440_pinctrl_register(struct platform_device *pdev, 766 struct exynos5440_pinctrl_priv_data *priv) 767{ 768 struct device *dev = &pdev->dev; 769 struct pinctrl_desc *ctrldesc; 770 struct pinctrl_dev *pctl_dev; 771 struct pinctrl_pin_desc *pindesc, *pdesc; 772 struct pinctrl_gpio_range grange; 773 char *pin_names; 774 int pin, ret; 775 776 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); 777 if (!ctrldesc) { 778 dev_err(dev, "could not allocate memory for pinctrl desc\n"); 779 return -ENOMEM; 780 } 781 782 ctrldesc->name = "exynos5440-pinctrl"; 783 ctrldesc->owner = THIS_MODULE; 784 ctrldesc->pctlops = &exynos5440_pctrl_ops; 785 ctrldesc->pmxops = &exynos5440_pinmux_ops; 786 ctrldesc->confops = &exynos5440_pinconf_ops; 787 788 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 789 EXYNOS5440_MAX_PINS, GFP_KERNEL); 790 if (!pindesc) { 791 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 792 return -ENOMEM; 793 } 794 ctrldesc->pins = pindesc; 795 ctrldesc->npins = EXYNOS5440_MAX_PINS; 796 797 /* dynamically populate the pin number and pin name for pindesc */ 798 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) 799 pdesc->number = pin; 800 801 /* 802 * allocate space for storing the dynamically generated names for all 803 * the pins which belong to this pin-controller. 804 */ 805 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * 806 ctrldesc->npins, GFP_KERNEL); 807 if (!pin_names) { 808 dev_err(&pdev->dev, "mem alloc for pin names failed\n"); 809 return -ENOMEM; 810 } 811 812 /* for each pin, set the name of the pin */ 813 for (pin = 0; pin < ctrldesc->npins; pin++) { 814 snprintf(pin_names, 6, "gpio%02d", pin); 815 pdesc = pindesc + pin; 816 pdesc->name = pin_names; 817 pin_names += PIN_NAME_LENGTH; 818 } 819 820 ret = exynos5440_pinctrl_parse_dt(pdev, priv); 821 if (ret) 822 return ret; 823 824 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv); 825 if (!pctl_dev) { 826 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 827 return -EINVAL; 828 } 829 830 grange.name = "exynos5440-pctrl-gpio-range"; 831 grange.id = 0; 832 grange.base = 0; 833 grange.npins = EXYNOS5440_MAX_PINS; 834 grange.gc = priv->gc; 835 pinctrl_add_gpio_range(pctl_dev, &grange); 836 return 0; 837} 838 839/* register the gpiolib interface with the gpiolib subsystem */ 840static int exynos5440_gpiolib_register(struct platform_device *pdev, 841 struct exynos5440_pinctrl_priv_data *priv) 842{ 843 struct gpio_chip *gc; 844 int ret; 845 846 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 847 if (!gc) { 848 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); 849 return -ENOMEM; 850 } 851 852 priv->gc = gc; 853 gc->base = 0; 854 gc->ngpio = EXYNOS5440_MAX_PINS; 855 gc->dev = &pdev->dev; 856 gc->set = exynos5440_gpio_set; 857 gc->get = exynos5440_gpio_get; 858 gc->direction_input = exynos5440_gpio_direction_input; 859 gc->direction_output = exynos5440_gpio_direction_output; 860 gc->to_irq = exynos5440_gpio_to_irq; 861 gc->label = "gpiolib-exynos5440"; 862 gc->owner = THIS_MODULE; 863 ret = gpiochip_add(gc); 864 if (ret) { 865 dev_err(&pdev->dev, "failed to register gpio_chip %s, error " 866 "code: %d\n", gc->label, ret); 867 return ret; 868 } 869 870 return 0; 871} 872 873/* unregister the gpiolib interface with the gpiolib subsystem */ 874static int exynos5440_gpiolib_unregister(struct platform_device *pdev, 875 struct exynos5440_pinctrl_priv_data *priv) 876{ 877 gpiochip_remove(priv->gc); 878 return 0; 879} 880 881static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) 882{ 883 struct exynos5440_pinctrl_priv_data *d; 884 unsigned long gpio_int; 885 886 d = irq_data_get_irq_chip_data(irqd); 887 gpio_int = readl(d->reg_base + GPIO_INT); 888 gpio_int |= 1 << irqd->hwirq; 889 writel(gpio_int, d->reg_base + GPIO_INT); 890} 891 892static void exynos5440_gpio_irq_mask(struct irq_data *irqd) 893{ 894 struct exynos5440_pinctrl_priv_data *d; 895 unsigned long gpio_int; 896 897 d = irq_data_get_irq_chip_data(irqd); 898 gpio_int = readl(d->reg_base + GPIO_INT); 899 gpio_int &= ~(1 << irqd->hwirq); 900 writel(gpio_int, d->reg_base + GPIO_INT); 901} 902 903/* irq_chip for gpio interrupts */ 904static struct irq_chip exynos5440_gpio_irq_chip = { 905 .name = "exynos5440_gpio_irq_chip", 906 .irq_unmask = exynos5440_gpio_irq_unmask, 907 .irq_mask = exynos5440_gpio_irq_mask, 908}; 909 910/* interrupt handler for GPIO interrupts 0..7 */ 911static irqreturn_t exynos5440_gpio_irq(int irq, void *data) 912{ 913 struct exynos5440_gpio_intr_data *intd = data; 914 struct exynos5440_pinctrl_priv_data *d = intd->priv; 915 int virq; 916 917 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); 918 if (!virq) 919 return IRQ_NONE; 920 generic_handle_irq(virq); 921 return IRQ_HANDLED; 922} 923 924static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, 925 irq_hw_number_t hw) 926{ 927 struct exynos5440_pinctrl_priv_data *d = h->host_data; 928 929 irq_set_chip_data(virq, d); 930 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, 931 handle_level_irq); 932 set_irq_flags(virq, IRQF_VALID); 933 return 0; 934} 935 936/* irq domain callbacks for gpio interrupt controller */ 937static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { 938 .map = exynos5440_gpio_irq_map, 939 .xlate = irq_domain_xlate_twocell, 940}; 941 942/* setup handling of gpio interrupts */ 943static int exynos5440_gpio_irq_init(struct platform_device *pdev, 944 struct exynos5440_pinctrl_priv_data *priv) 945{ 946 struct device *dev = &pdev->dev; 947 struct exynos5440_gpio_intr_data *intd; 948 int i, irq, ret; 949 950 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, 951 GFP_KERNEL); 952 if (!intd) { 953 dev_err(dev, "failed to allocate memory for gpio intr data\n"); 954 return -ENOMEM; 955 } 956 957 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { 958 irq = irq_of_parse_and_map(dev->of_node, i); 959 if (irq <= 0) { 960 dev_err(dev, "irq parsing failed\n"); 961 return -EINVAL; 962 } 963 964 intd->gpio_int = i; 965 intd->priv = priv; 966 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, 967 0, dev_name(dev), intd++); 968 if (ret) { 969 dev_err(dev, "irq request failed\n"); 970 return -ENXIO; 971 } 972 } 973 974 priv->irq_domain = irq_domain_add_linear(dev->of_node, 975 EXYNOS5440_MAX_GPIO_INT, 976 &exynos5440_gpio_irqd_ops, priv); 977 if (!priv->irq_domain) { 978 dev_err(dev, "failed to create irq domain\n"); 979 return -ENXIO; 980 } 981 982 return 0; 983} 984 985static int exynos5440_pinctrl_probe(struct platform_device *pdev) 986{ 987 struct device *dev = &pdev->dev; 988 struct exynos5440_pinctrl_priv_data *priv; 989 struct resource *res; 990 int ret; 991 992 if (!dev->of_node) { 993 dev_err(dev, "device tree node not found\n"); 994 return -ENODEV; 995 } 996 997 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 998 if (!priv) { 999 dev_err(dev, "could not allocate memory for private data\n"); 1000 return -ENOMEM; 1001 } 1002 1003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1004 priv->reg_base = devm_ioremap_resource(&pdev->dev, res); 1005 if (IS_ERR(priv->reg_base)) 1006 return PTR_ERR(priv->reg_base); 1007 1008 ret = exynos5440_gpiolib_register(pdev, priv); 1009 if (ret) 1010 return ret; 1011 1012 ret = exynos5440_pinctrl_register(pdev, priv); 1013 if (ret) { 1014 exynos5440_gpiolib_unregister(pdev, priv); 1015 return ret; 1016 } 1017 1018 ret = exynos5440_gpio_irq_init(pdev, priv); 1019 if (ret) { 1020 dev_err(dev, "failed to setup gpio interrupts\n"); 1021 return ret; 1022 } 1023 1024 platform_set_drvdata(pdev, priv); 1025 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); 1026 return 0; 1027} 1028 1029static const struct of_device_id exynos5440_pinctrl_dt_match[] = { 1030 { .compatible = "samsung,exynos5440-pinctrl" }, 1031 {}, 1032}; 1033MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); 1034 1035static struct platform_driver exynos5440_pinctrl_driver = { 1036 .probe = exynos5440_pinctrl_probe, 1037 .driver = { 1038 .name = "exynos5440-pinctrl", 1039 .owner = THIS_MODULE, 1040 .of_match_table = exynos5440_pinctrl_dt_match, 1041 }, 1042}; 1043 1044static int __init exynos5440_pinctrl_drv_register(void) 1045{ 1046 return platform_driver_register(&exynos5440_pinctrl_driver); 1047} 1048postcore_initcall(exynos5440_pinctrl_drv_register); 1049 1050static void __exit exynos5440_pinctrl_drv_unregister(void) 1051{ 1052 platform_driver_unregister(&exynos5440_pinctrl_driver); 1053} 1054module_exit(exynos5440_pinctrl_drv_unregister); 1055 1056MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>"); 1057MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); 1058MODULE_LICENSE("GPL v2"); 1059