[go: nahoru, domu]

1/*
2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear320-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG			0x0C
23#define MODE_CONFIG_REG			0x10
24#define MODE_EXT_CONFIG_REG		0x18
25
26/* modes */
27#define AUTO_NET_SMII_MODE	(1 << 0)
28#define AUTO_NET_MII_MODE	(1 << 1)
29#define AUTO_EXP_MODE		(1 << 2)
30#define SMALL_PRINTERS_MODE	(1 << 3)
31#define EXTENDED_MODE		(1 << 4)
32
33static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34	.name = "Automation Networking SMII mode",
35	.mode = AUTO_NET_SMII_MODE,
36	.reg = MODE_CONFIG_REG,
37	.mask = 0x00000007,
38	.val = 0x0,
39};
40
41static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42	.name = "Automation Networking MII mode",
43	.mode = AUTO_NET_MII_MODE,
44	.reg = MODE_CONFIG_REG,
45	.mask = 0x00000007,
46	.val = 0x1,
47};
48
49static struct spear_pmx_mode pmx_mode_auto_exp = {
50	.name = "Automation Expanded mode",
51	.mode = AUTO_EXP_MODE,
52	.reg = MODE_CONFIG_REG,
53	.mask = 0x00000007,
54	.val = 0x2,
55};
56
57static struct spear_pmx_mode pmx_mode_small_printers = {
58	.name = "Small Printers mode",
59	.mode = SMALL_PRINTERS_MODE,
60	.reg = MODE_CONFIG_REG,
61	.mask = 0x00000007,
62	.val = 0x3,
63};
64
65static struct spear_pmx_mode pmx_mode_extended = {
66	.name = "extended mode",
67	.mode = EXTENDED_MODE,
68	.reg = MODE_EXT_CONFIG_REG,
69	.mask = 0x00000001,
70	.val = 0x1,
71};
72
73static struct spear_pmx_mode *spear320_pmx_modes[] = {
74	&pmx_mode_auto_net_smii,
75	&pmx_mode_auto_net_mii,
76	&pmx_mode_auto_exp,
77	&pmx_mode_small_printers,
78	&pmx_mode_extended,
79};
80
81/* Extended mode registers and their offsets */
82#define EXT_CTRL_REG				0x0018
83	#define MII_MDIO_MASK			(1 << 4)
84	#define MII_MDIO_10_11_VAL		0
85	#define MII_MDIO_81_VAL			(1 << 4)
86	#define EMI_FSMC_DYNAMIC_MUX_MASK	(1 << 5)
87	#define MAC_MODE_MII			0
88	#define MAC_MODE_RMII			1
89	#define MAC_MODE_SMII			2
90	#define MAC_MODE_SS_SMII		3
91	#define MAC_MODE_MASK			0x3
92	#define MAC1_MODE_SHIFT			16
93	#define MAC2_MODE_SHIFT			18
94
95#define IP_SEL_PAD_0_9_REG			0x00A4
96	#define PMX_PL_0_1_MASK			(0x3F << 0)
97	#define PMX_UART2_PL_0_1_VAL		0x0
98	#define PMX_I2C2_PL_0_1_VAL		(0x4 | (0x4 << 3))
99
100	#define PMX_PL_2_3_MASK			(0x3F << 6)
101	#define PMX_I2C2_PL_2_3_VAL		0x0
102	#define PMX_UART6_PL_2_3_VAL		((0x1 << 6) | (0x1 << 9))
103	#define PMX_UART1_ENH_PL_2_3_VAL	((0x4 << 6) | (0x4 << 9))
104
105	#define PMX_PL_4_5_MASK			(0x3F << 12)
106	#define PMX_UART5_PL_4_5_VAL		((0x1 << 12) | (0x1 << 15))
107	#define PMX_UART1_ENH_PL_4_5_VAL	((0x4 << 12) | (0x4 << 15))
108	#define PMX_PL_5_MASK			(0x7 << 15)
109	#define PMX_TOUCH_Y_PL_5_VAL		0x0
110
111	#define PMX_PL_6_7_MASK			(0x3F << 18)
112	#define PMX_PL_6_MASK			(0x7 << 18)
113	#define PMX_PL_7_MASK			(0x7 << 21)
114	#define PMX_UART4_PL_6_7_VAL		((0x1 << 18) | (0x1 << 21))
115	#define PMX_PWM_3_PL_6_VAL		(0x2 << 18)
116	#define PMX_PWM_2_PL_7_VAL		(0x2 << 21)
117	#define PMX_UART1_ENH_PL_6_7_VAL	((0x4 << 18) | (0x4 << 21))
118
119	#define PMX_PL_8_9_MASK			(0x3F << 24)
120	#define PMX_UART3_PL_8_9_VAL		((0x1 << 24) | (0x1 << 27))
121	#define PMX_PWM_0_1_PL_8_9_VAL		((0x2 << 24) | (0x2 << 27))
122	#define PMX_I2C1_PL_8_9_VAL		((0x4 << 24) | (0x4 << 27))
123
124#define IP_SEL_PAD_10_19_REG			0x00A8
125	#define PMX_PL_10_11_MASK		(0x3F << 0)
126	#define PMX_SMII_PL_10_11_VAL		0
127	#define PMX_RMII_PL_10_11_VAL		((0x4 << 0) | (0x4 << 3))
128
129	#define PMX_PL_12_MASK			(0x7 << 6)
130	#define PMX_PWM3_PL_12_VAL		0
131	#define PMX_SDHCI_CD_PL_12_VAL		(0x4 << 6)
132
133	#define PMX_PL_13_14_MASK		(0x3F << 9)
134	#define PMX_PL_13_MASK			(0x7 << 9)
135	#define PMX_PL_14_MASK			(0x7 << 12)
136	#define PMX_SSP2_PL_13_14_15_16_VAL	0
137	#define PMX_UART4_PL_13_14_VAL		((0x1 << 9) | (0x1 << 12))
138	#define PMX_RMII_PL_13_14_VAL		((0x4 << 9) | (0x4 << 12))
139	#define PMX_PWM2_PL_13_VAL		(0x2 << 9)
140	#define PMX_PWM1_PL_14_VAL		(0x2 << 12)
141
142	#define PMX_PL_15_MASK			(0x7 << 15)
143	#define PMX_PWM0_PL_15_VAL		(0x2 << 15)
144	#define PMX_PL_15_16_MASK		(0x3F << 15)
145	#define PMX_UART3_PL_15_16_VAL		((0x1 << 15) | (0x1 << 18))
146	#define PMX_RMII_PL_15_16_VAL		((0x4 << 15) | (0x4 << 18))
147
148	#define PMX_PL_17_18_MASK		(0x3F << 21)
149	#define PMX_SSP1_PL_17_18_19_20_VAL	0
150	#define PMX_RMII_PL_17_18_VAL		((0x4 << 21) | (0x4 << 24))
151
152	#define PMX_PL_19_MASK			(0x7 << 27)
153	#define PMX_I2C2_PL_19_VAL		(0x1 << 27)
154	#define PMX_RMII_PL_19_VAL		(0x4 << 27)
155
156#define IP_SEL_PAD_20_29_REG			0x00AC
157	#define PMX_PL_20_MASK			(0x7 << 0)
158	#define PMX_I2C2_PL_20_VAL		(0x1 << 0)
159	#define PMX_RMII_PL_20_VAL		(0x4 << 0)
160
161	#define PMX_PL_21_TO_27_MASK		(0x1FFFFF << 3)
162	#define PMX_SMII_PL_21_TO_27_VAL	0
163	#define PMX_RMII_PL_21_TO_27_VAL	((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
165	#define PMX_PL_28_29_MASK		(0x3F << 24)
166	#define PMX_PL_28_MASK			(0x7 << 24)
167	#define PMX_PL_29_MASK			(0x7 << 27)
168	#define PMX_UART1_PL_28_29_VAL		0
169	#define PMX_PWM_3_PL_28_VAL		(0x4 << 24)
170	#define PMX_PWM_2_PL_29_VAL		(0x4 << 27)
171
172#define IP_SEL_PAD_30_39_REG			0x00B0
173	#define PMX_PL_30_31_MASK		(0x3F << 0)
174	#define PMX_CAN1_PL_30_31_VAL		(0)
175	#define PMX_PL_30_MASK			(0x7 << 0)
176	#define PMX_PL_31_MASK			(0x7 << 3)
177	#define PMX_PWM1_EXT_PL_30_VAL		(0x4 << 0)
178	#define PMX_PWM0_EXT_PL_31_VAL		(0x4 << 3)
179	#define PMX_UART1_ENH_PL_31_VAL		(0x3 << 3)
180
181	#define PMX_PL_32_33_MASK		(0x3F << 6)
182	#define PMX_CAN0_PL_32_33_VAL		0
183	#define PMX_UART1_ENH_PL_32_33_VAL	((0x3 << 6) | (0x3 << 9))
184	#define PMX_SSP2_PL_32_33_VAL		((0x4 << 6) | (0x4 << 9))
185
186	#define PMX_PL_34_MASK			(0x7 << 12)
187	#define PMX_PWM2_PL_34_VAL		0
188	#define PMX_UART1_ENH_PL_34_VAL		(0x2 << 12)
189	#define PMX_SSP2_PL_34_VAL		(0x4 << 12)
190
191	#define PMX_PL_35_MASK			(0x7 << 15)
192	#define PMX_I2S_REF_CLK_PL_35_VAL	0
193	#define PMX_UART1_ENH_PL_35_VAL		(0x2 << 15)
194	#define PMX_SSP2_PL_35_VAL		(0x4 << 15)
195
196	#define PMX_PL_36_MASK			(0x7 << 18)
197	#define PMX_TOUCH_X_PL_36_VAL		0
198	#define PMX_UART1_ENH_PL_36_VAL		(0x2 << 18)
199	#define PMX_SSP1_PL_36_VAL		(0x4 << 18)
200
201	#define PMX_PL_37_38_MASK		(0x3F << 21)
202	#define PMX_PWM0_1_PL_37_38_VAL		0
203	#define PMX_UART5_PL_37_38_VAL		((0x2 << 21) | (0x2 << 24))
204	#define PMX_SSP1_PL_37_38_VAL		((0x4 << 21) | (0x4 << 24))
205
206	#define PMX_PL_39_MASK			(0x7 << 27)
207	#define PMX_I2S_PL_39_VAL		0
208	#define PMX_UART4_PL_39_VAL		(0x2 << 27)
209	#define PMX_SSP1_PL_39_VAL		(0x4 << 27)
210
211#define IP_SEL_PAD_40_49_REG			0x00B4
212	#define PMX_PL_40_MASK			(0x7 << 0)
213	#define PMX_I2S_PL_40_VAL		0
214	#define PMX_UART4_PL_40_VAL		(0x2 << 0)
215	#define PMX_PWM3_PL_40_VAL		(0x4 << 0)
216
217	#define PMX_PL_41_42_MASK		(0x3F << 3)
218	#define PMX_PL_41_MASK			(0x7 << 3)
219	#define PMX_PL_42_MASK			(0x7 << 6)
220	#define PMX_I2S_PL_41_42_VAL		0
221	#define PMX_UART3_PL_41_42_VAL		((0x2 << 3) | (0x2 << 6))
222	#define PMX_PWM2_PL_41_VAL		(0x4 << 3)
223	#define PMX_PWM1_PL_42_VAL		(0x4 << 6)
224
225	#define PMX_PL_43_MASK			(0x7 << 9)
226	#define PMX_SDHCI_PL_43_VAL		0
227	#define PMX_UART1_ENH_PL_43_VAL		(0x2 << 9)
228	#define PMX_PWM0_PL_43_VAL		(0x4 << 9)
229
230	#define PMX_PL_44_45_MASK		(0x3F << 12)
231	#define PMX_SDHCI_PL_44_45_VAL	0
232	#define PMX_UART1_ENH_PL_44_45_VAL	((0x2 << 12) | (0x2 << 15))
233	#define PMX_SSP2_PL_44_45_VAL		((0x4 << 12) | (0x4 << 15))
234
235	#define PMX_PL_46_47_MASK		(0x3F << 18)
236	#define PMX_SDHCI_PL_46_47_VAL	0
237	#define PMX_FSMC_EMI_PL_46_47_VAL	((0x2 << 18) | (0x2 << 21))
238	#define PMX_SSP2_PL_46_47_VAL		((0x4 << 18) | (0x4 << 21))
239
240	#define PMX_PL_48_49_MASK		(0x3F << 24)
241	#define PMX_SDHCI_PL_48_49_VAL	0
242	#define PMX_FSMC_EMI_PL_48_49_VAL	((0x2 << 24) | (0x2 << 27))
243	#define PMX_SSP1_PL_48_49_VAL		((0x4 << 24) | (0x4 << 27))
244
245#define IP_SEL_PAD_50_59_REG			0x00B8
246	#define PMX_PL_50_51_MASK		(0x3F << 0)
247	#define PMX_EMI_PL_50_51_VAL		((0x2 << 0) | (0x2 << 3))
248	#define PMX_SSP1_PL_50_51_VAL		((0x4 << 0) | (0x4 << 3))
249	#define PMX_PL_50_MASK			(0x7 << 0)
250	#define PMX_PL_51_MASK			(0x7 << 3)
251	#define PMX_SDHCI_PL_50_VAL		0
252	#define PMX_SDHCI_CD_PL_51_VAL		0
253
254	#define PMX_PL_52_53_MASK		(0x3F << 6)
255	#define PMX_FSMC_PL_52_53_VAL		0
256	#define PMX_EMI_PL_52_53_VAL		((0x2 << 6) | (0x2 << 9))
257	#define PMX_UART3_PL_52_53_VAL		((0x4 << 6) | (0x4 << 9))
258
259	#define PMX_PL_54_55_56_MASK		(0x1FF << 12)
260	#define PMX_FSMC_EMI_PL_54_55_56_VAL	((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
262	#define PMX_PL_57_MASK			(0x7 << 21)
263	#define PMX_FSMC_PL_57_VAL		0
264	#define PMX_PWM3_PL_57_VAL		(0x4 << 21)
265
266	#define PMX_PL_58_59_MASK		(0x3F << 24)
267	#define PMX_PL_58_MASK			(0x7 << 24)
268	#define PMX_PL_59_MASK			(0x7 << 27)
269	#define PMX_FSMC_EMI_PL_58_59_VAL	((0x2 << 24) | (0x2 << 27))
270	#define PMX_PWM2_PL_58_VAL		(0x4 << 24)
271	#define PMX_PWM1_PL_59_VAL		(0x4 << 27)
272
273#define IP_SEL_PAD_60_69_REG			0x00BC
274	#define PMX_PL_60_MASK			(0x7 << 0)
275	#define PMX_FSMC_PL_60_VAL		0
276	#define PMX_PWM0_PL_60_VAL		(0x4 << 0)
277
278	#define PMX_PL_61_TO_64_MASK		(0xFFF << 3)
279	#define PMX_FSMC_PL_61_TO_64_VAL	((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280	#define PMX_SSP2_PL_61_TO_64_VAL	((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
282	#define PMX_PL_65_TO_68_MASK		(0xFFF << 15)
283	#define PMX_FSMC_PL_65_TO_68_VAL	((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284	#define PMX_SSP1_PL_65_TO_68_VAL	((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
286	#define PMX_PL_69_MASK			(0x7 << 27)
287	#define PMX_CLCD_PL_69_VAL		(0)
288	#define PMX_EMI_PL_69_VAL		(0x2 << 27)
289	#define PMX_SPP_PL_69_VAL		(0x3 << 27)
290	#define PMX_UART5_PL_69_VAL		(0x4 << 27)
291
292#define IP_SEL_PAD_70_79_REG			0x00C0
293	#define PMX_PL_70_MASK			(0x7 << 0)
294	#define PMX_CLCD_PL_70_VAL		(0)
295	#define PMX_FSMC_EMI_PL_70_VAL		(0x2 << 0)
296	#define PMX_SPP_PL_70_VAL		(0x3 << 0)
297	#define PMX_UART5_PL_70_VAL		(0x4 << 0)
298
299	#define PMX_PL_71_72_MASK		(0x3F << 3)
300	#define PMX_CLCD_PL_71_72_VAL		(0)
301	#define PMX_FSMC_EMI_PL_71_72_VAL	((0x2 << 3) | (0x2 << 6))
302	#define PMX_SPP_PL_71_72_VAL		((0x3 << 3) | (0x3 << 6))
303	#define PMX_UART4_PL_71_72_VAL		((0x4 << 3) | (0x4 << 6))
304
305	#define PMX_PL_73_MASK			(0x7 << 9)
306	#define PMX_CLCD_PL_73_VAL		(0)
307	#define PMX_FSMC_EMI_PL_73_VAL		(0x2 << 9)
308	#define PMX_SPP_PL_73_VAL		(0x3 << 9)
309	#define PMX_UART3_PL_73_VAL		(0x4 << 9)
310
311	#define PMX_PL_74_MASK			(0x7 << 12)
312	#define PMX_CLCD_PL_74_VAL		(0)
313	#define PMX_EMI_PL_74_VAL		(0x2 << 12)
314	#define PMX_SPP_PL_74_VAL		(0x3 << 12)
315	#define PMX_UART3_PL_74_VAL		(0x4 << 12)
316
317	#define PMX_PL_75_76_MASK		(0x3F << 15)
318	#define PMX_CLCD_PL_75_76_VAL		(0)
319	#define PMX_EMI_PL_75_76_VAL		((0x2 << 15) | (0x2 << 18))
320	#define PMX_SPP_PL_75_76_VAL		((0x3 << 15) | (0x3 << 18))
321	#define PMX_I2C2_PL_75_76_VAL		((0x4 << 15) | (0x4 << 18))
322
323	#define PMX_PL_77_78_79_MASK		(0x1FF << 21)
324	#define PMX_CLCD_PL_77_78_79_VAL	(0)
325	#define PMX_EMI_PL_77_78_79_VAL		((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326	#define PMX_SPP_PL_77_78_79_VAL		((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327	#define PMX_RS485_PL_77_78_79_VAL	((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
329#define IP_SEL_PAD_80_89_REG			0x00C4
330	#define PMX_PL_80_TO_85_MASK		(0x3FFFF << 0)
331	#define PMX_CLCD_PL_80_TO_85_VAL	0
332	#define PMX_MII2_PL_80_TO_85_VAL	((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333	#define PMX_EMI_PL_80_TO_85_VAL		((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334	#define PMX_SPP_PL_80_TO_85_VAL		((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335	#define PMX_UART1_ENH_PL_80_TO_85_VAL	((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
337	#define PMX_PL_86_87_MASK		(0x3F << 18)
338	#define PMX_PL_86_MASK			(0x7 << 18)
339	#define PMX_PL_87_MASK			(0x7 << 21)
340	#define PMX_CLCD_PL_86_87_VAL		0
341	#define PMX_MII2_PL_86_87_VAL		((0x1 << 18) | (0x1 << 21))
342	#define PMX_EMI_PL_86_87_VAL		((0x2 << 18) | (0x2 << 21))
343	#define PMX_PWM3_PL_86_VAL		(0x4 << 18)
344	#define PMX_PWM2_PL_87_VAL		(0x4 << 21)
345
346	#define PMX_PL_88_89_MASK		(0x3F << 24)
347	#define PMX_CLCD_PL_88_89_VAL		0
348	#define PMX_MII2_PL_88_89_VAL		((0x1 << 24) | (0x1 << 27))
349	#define PMX_EMI_PL_88_89_VAL		((0x2 << 24) | (0x2 << 27))
350	#define PMX_UART6_PL_88_89_VAL		((0x3 << 24) | (0x3 << 27))
351	#define PMX_PWM0_1_PL_88_89_VAL		((0x4 << 24) | (0x4 << 27))
352
353#define IP_SEL_PAD_90_99_REG			0x00C8
354	#define PMX_PL_90_91_MASK		(0x3F << 0)
355	#define PMX_CLCD_PL_90_91_VAL		0
356	#define PMX_MII2_PL_90_91_VAL		((0x1 << 0) | (0x1 << 3))
357	#define PMX_EMI1_PL_90_91_VAL		((0x2 << 0) | (0x2 << 3))
358	#define PMX_UART5_PL_90_91_VAL		((0x3 << 0) | (0x3 << 3))
359	#define PMX_SSP2_PL_90_91_VAL		((0x4 << 0) | (0x4 << 3))
360
361	#define PMX_PL_92_93_MASK		(0x3F << 6)
362	#define PMX_CLCD_PL_92_93_VAL		0
363	#define PMX_MII2_PL_92_93_VAL		((0x1 << 6) | (0x1 << 9))
364	#define PMX_EMI1_PL_92_93_VAL		((0x2 << 6) | (0x2 << 9))
365	#define PMX_UART4_PL_92_93_VAL		((0x3 << 6) | (0x3 << 9))
366	#define PMX_SSP2_PL_92_93_VAL		((0x4 << 6) | (0x4 << 9))
367
368	#define PMX_PL_94_95_MASK		(0x3F << 12)
369	#define PMX_CLCD_PL_94_95_VAL		0
370	#define PMX_MII2_PL_94_95_VAL		((0x1 << 12) | (0x1 << 15))
371	#define PMX_EMI1_PL_94_95_VAL		((0x2 << 12) | (0x2 << 15))
372	#define PMX_UART3_PL_94_95_VAL		((0x3 << 12) | (0x3 << 15))
373	#define PMX_SSP1_PL_94_95_VAL		((0x4 << 12) | (0x4 << 15))
374
375	#define PMX_PL_96_97_MASK		(0x3F << 18)
376	#define PMX_CLCD_PL_96_97_VAL		0
377	#define PMX_MII2_PL_96_97_VAL		((0x1 << 18) | (0x1 << 21))
378	#define PMX_EMI1_PL_96_97_VAL		((0x2 << 18) | (0x2 << 21))
379	#define PMX_I2C2_PL_96_97_VAL		((0x3 << 18) | (0x3 << 21))
380	#define PMX_SSP1_PL_96_97_VAL		((0x4 << 18) | (0x4 << 21))
381
382	#define PMX_PL_98_MASK			(0x7 << 24)
383	#define PMX_CLCD_PL_98_VAL		0
384	#define PMX_I2C1_PL_98_VAL		(0x2 << 24)
385	#define PMX_UART3_PL_98_VAL		(0x4 << 24)
386
387	#define PMX_PL_99_MASK			(0x7 << 27)
388	#define PMX_SDHCI_PL_99_VAL		0
389	#define PMX_I2C1_PL_99_VAL		(0x2 << 27)
390	#define PMX_UART3_PL_99_VAL		(0x4 << 27)
391
392#define IP_SEL_MIX_PAD_REG			0x00CC
393	#define PMX_PL_100_101_MASK		(0x3F << 0)
394	#define PMX_SDHCI_PL_100_101_VAL	0
395	#define PMX_UART4_PL_100_101_VAL	((0x4 << 0) | (0x4 << 3))
396
397	#define PMX_SSP1_PORT_SEL_MASK		(0x7 << 8)
398	#define PMX_SSP1_PORT_94_TO_97_VAL	0
399	#define PMX_SSP1_PORT_65_TO_68_VAL	(0x1 << 8)
400	#define PMX_SSP1_PORT_48_TO_51_VAL	(0x2 << 8)
401	#define PMX_SSP1_PORT_36_TO_39_VAL	(0x3 << 8)
402	#define PMX_SSP1_PORT_17_TO_20_VAL	(0x4 << 8)
403
404	#define PMX_SSP2_PORT_SEL_MASK		(0x7 << 11)
405	#define PMX_SSP2_PORT_90_TO_93_VAL	0
406	#define PMX_SSP2_PORT_61_TO_64_VAL	(0x1 << 11)
407	#define PMX_SSP2_PORT_44_TO_47_VAL	(0x2 << 11)
408	#define PMX_SSP2_PORT_32_TO_35_VAL	(0x3 << 11)
409	#define PMX_SSP2_PORT_13_TO_16_VAL	(0x4 << 11)
410
411	#define PMX_UART1_ENH_PORT_SEL_MASK		(0x3 << 14)
412	#define PMX_UART1_ENH_PORT_81_TO_85_VAL		0
413	#define PMX_UART1_ENH_PORT_44_45_34_36_VAL	(0x1 << 14)
414	#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL	(0x2 << 14)
415	#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL		(0x3 << 14)
416
417	#define PMX_UART3_PORT_SEL_MASK		(0x7 << 16)
418	#define PMX_UART3_PORT_94_VAL		0
419	#define PMX_UART3_PORT_73_VAL		(0x1 << 16)
420	#define PMX_UART3_PORT_52_VAL		(0x2 << 16)
421	#define PMX_UART3_PORT_41_VAL		(0x3 << 16)
422	#define PMX_UART3_PORT_15_VAL		(0x4 << 16)
423	#define PMX_UART3_PORT_8_VAL		(0x5 << 16)
424	#define PMX_UART3_PORT_99_VAL		(0x6 << 16)
425
426	#define PMX_UART4_PORT_SEL_MASK		(0x7 << 19)
427	#define PMX_UART4_PORT_92_VAL		0
428	#define PMX_UART4_PORT_71_VAL		(0x1 << 19)
429	#define PMX_UART4_PORT_39_VAL		(0x2 << 19)
430	#define PMX_UART4_PORT_13_VAL		(0x3 << 19)
431	#define PMX_UART4_PORT_6_VAL		(0x4 << 19)
432	#define PMX_UART4_PORT_101_VAL		(0x5 << 19)
433
434	#define PMX_UART5_PORT_SEL_MASK		(0x3 << 22)
435	#define PMX_UART5_PORT_90_VAL		0
436	#define PMX_UART5_PORT_69_VAL		(0x1 << 22)
437	#define PMX_UART5_PORT_37_VAL		(0x2 << 22)
438	#define PMX_UART5_PORT_4_VAL		(0x3 << 22)
439
440	#define PMX_UART6_PORT_SEL_MASK		(0x1 << 24)
441	#define PMX_UART6_PORT_88_VAL		0
442	#define PMX_UART6_PORT_2_VAL		(0x1 << 24)
443
444	#define PMX_I2C1_PORT_SEL_MASK		(0x1 << 25)
445	#define PMX_I2C1_PORT_8_9_VAL		0
446	#define PMX_I2C1_PORT_98_99_VAL		(0x1 << 25)
447
448	#define PMX_I2C2_PORT_SEL_MASK		(0x3 << 26)
449	#define PMX_I2C2_PORT_96_97_VAL		0
450	#define PMX_I2C2_PORT_75_76_VAL		(0x1 << 26)
451	#define PMX_I2C2_PORT_19_20_VAL		(0x2 << 26)
452	#define PMX_I2C2_PORT_2_3_VAL		(0x3 << 26)
453	#define PMX_I2C2_PORT_0_1_VAL		(0x4 << 26)
454
455	#define PMX_SDHCI_CD_PORT_SEL_MASK	(0x1 << 29)
456	#define PMX_SDHCI_CD_PORT_12_VAL	0
457	#define PMX_SDHCI_CD_PORT_51_VAL	(0x1 << 29)
458
459/* Pad multiplexing for CLCD device */
460static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461	79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462	97 };
463static struct spear_muxreg clcd_muxreg[] = {
464	{
465		.reg = IP_SEL_PAD_60_69_REG,
466		.mask = PMX_PL_69_MASK,
467		.val = PMX_CLCD_PL_69_VAL,
468	}, {
469		.reg = IP_SEL_PAD_70_79_REG,
470		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472			PMX_PL_77_78_79_MASK,
473		.val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474			PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475			PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476	}, {
477		.reg = IP_SEL_PAD_80_89_REG,
478		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479			PMX_PL_88_89_MASK,
480		.val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481			PMX_CLCD_PL_88_89_VAL,
482	}, {
483		.reg = IP_SEL_PAD_90_99_REG,
484		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486		.val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487			PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488			PMX_CLCD_PL_98_VAL,
489	},
490};
491
492static struct spear_modemux clcd_modemux[] = {
493	{
494		.modes = EXTENDED_MODE,
495		.muxregs = clcd_muxreg,
496		.nmuxregs = ARRAY_SIZE(clcd_muxreg),
497	},
498};
499
500static struct spear_pingroup clcd_pingroup = {
501	.name = "clcd_grp",
502	.pins = clcd_pins,
503	.npins = ARRAY_SIZE(clcd_pins),
504	.modemuxs = clcd_modemux,
505	.nmodemuxs = ARRAY_SIZE(clcd_modemux),
506};
507
508static const char *const clcd_grps[] = { "clcd_grp" };
509static struct spear_function clcd_function = {
510	.name = "clcd",
511	.groups = clcd_grps,
512	.ngroups = ARRAY_SIZE(clcd_grps),
513};
514
515/* Pad multiplexing for EMI (Parallel NOR flash) device */
516static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517	57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518	75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519	93, 94, 95, 96, 97 };
520static struct spear_muxreg emi_muxreg[] = {
521	{
522		.reg = PMX_CONFIG_REG,
523		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524		.val = 0,
525	},
526};
527
528static struct spear_muxreg emi_ext_muxreg[] = {
529	{
530		.reg = IP_SEL_PAD_40_49_REG,
531		.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532		.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533	}, {
534		.reg = IP_SEL_PAD_50_59_REG,
535		.mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536			PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537		.val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538			PMX_FSMC_EMI_PL_54_55_56_VAL |
539			PMX_FSMC_EMI_PL_58_59_VAL,
540	}, {
541		.reg = IP_SEL_PAD_60_69_REG,
542		.mask = PMX_PL_69_MASK,
543		.val = PMX_EMI_PL_69_VAL,
544	}, {
545		.reg = IP_SEL_PAD_70_79_REG,
546		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548			PMX_PL_77_78_79_MASK,
549		.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550			PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551			PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552	}, {
553		.reg = IP_SEL_PAD_80_89_REG,
554		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555			PMX_PL_88_89_MASK,
556		.val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557			PMX_EMI_PL_88_89_VAL,
558	}, {
559		.reg = IP_SEL_PAD_90_99_REG,
560		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562		.val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563			PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564	}, {
565		.reg = EXT_CTRL_REG,
566		.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567		.val = EMI_FSMC_DYNAMIC_MUX_MASK,
568	},
569};
570
571static struct spear_modemux emi_modemux[] = {
572	{
573		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
574		.muxregs = emi_muxreg,
575		.nmuxregs = ARRAY_SIZE(emi_muxreg),
576	}, {
577		.modes = EXTENDED_MODE,
578		.muxregs = emi_ext_muxreg,
579		.nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580	},
581};
582
583static struct spear_pingroup emi_pingroup = {
584	.name = "emi_grp",
585	.pins = emi_pins,
586	.npins = ARRAY_SIZE(emi_pins),
587	.modemuxs = emi_modemux,
588	.nmodemuxs = ARRAY_SIZE(emi_modemux),
589};
590
591static const char *const emi_grps[] = { "emi_grp" };
592static struct spear_function emi_function = {
593	.name = "emi",
594	.groups = emi_grps,
595	.ngroups = ARRAY_SIZE(emi_grps),
596};
597
598/* Pad multiplexing for FSMC (NAND flash) device */
599static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600	61, 62, 63, 64, 65, 66, 67, 68 };
601static struct spear_muxreg fsmc_8bit_muxreg[] = {
602	{
603		.reg = IP_SEL_PAD_50_59_REG,
604		.mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605			PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606		.val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607			PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608	}, {
609		.reg = IP_SEL_PAD_60_69_REG,
610		.mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611			PMX_PL_65_TO_68_MASK,
612		.val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613			PMX_FSMC_PL_65_TO_68_VAL,
614	}, {
615		.reg = EXT_CTRL_REG,
616		.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617		.val = EMI_FSMC_DYNAMIC_MUX_MASK,
618	},
619};
620
621static struct spear_modemux fsmc_8bit_modemux[] = {
622	{
623		.modes = EXTENDED_MODE,
624		.muxregs = fsmc_8bit_muxreg,
625		.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626	},
627};
628
629static struct spear_pingroup fsmc_8bit_pingroup = {
630	.name = "fsmc_8bit_grp",
631	.pins = fsmc_8bit_pins,
632	.npins = ARRAY_SIZE(fsmc_8bit_pins),
633	.modemuxs = fsmc_8bit_modemux,
634	.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635};
636
637static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638	57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640	{
641		.reg = PMX_CONFIG_REG,
642		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643		.val = 0,
644	},
645};
646
647static struct spear_muxreg fsmc_16bit_muxreg[] = {
648	{
649		.reg = IP_SEL_PAD_40_49_REG,
650		.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651		.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652	}, {
653		.reg = IP_SEL_PAD_70_79_REG,
654		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655		.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656			PMX_FSMC_EMI_PL_73_VAL,
657	}
658};
659
660static struct spear_modemux fsmc_16bit_modemux[] = {
661	{
662		.modes = EXTENDED_MODE,
663		.muxregs = fsmc_8bit_muxreg,
664		.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665	}, {
666		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
667		.muxregs = fsmc_16bit_autoexp_muxreg,
668		.nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669	}, {
670		.modes = EXTENDED_MODE,
671		.muxregs = fsmc_16bit_muxreg,
672		.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673	},
674};
675
676static struct spear_pingroup fsmc_16bit_pingroup = {
677	.name = "fsmc_16bit_grp",
678	.pins = fsmc_16bit_pins,
679	.npins = ARRAY_SIZE(fsmc_16bit_pins),
680	.modemuxs = fsmc_16bit_modemux,
681	.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682};
683
684static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685static struct spear_function fsmc_function = {
686	.name = "fsmc",
687	.groups = fsmc_grps,
688	.ngroups = ARRAY_SIZE(fsmc_grps),
689};
690
691/* Pad multiplexing for SPP device */
692static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693	80, 81, 82, 83, 84, 85 };
694static struct spear_muxreg spp_muxreg[] = {
695	{
696		.reg = IP_SEL_PAD_60_69_REG,
697		.mask = PMX_PL_69_MASK,
698		.val = PMX_SPP_PL_69_VAL,
699	}, {
700		.reg = IP_SEL_PAD_70_79_REG,
701		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703			PMX_PL_77_78_79_MASK,
704		.val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705			PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706			PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707	}, {
708		.reg = IP_SEL_PAD_80_89_REG,
709		.mask = PMX_PL_80_TO_85_MASK,
710		.val = PMX_SPP_PL_80_TO_85_VAL,
711	},
712};
713
714static struct spear_modemux spp_modemux[] = {
715	{
716		.modes = EXTENDED_MODE,
717		.muxregs = spp_muxreg,
718		.nmuxregs = ARRAY_SIZE(spp_muxreg),
719	},
720};
721
722static struct spear_pingroup spp_pingroup = {
723	.name = "spp_grp",
724	.pins = spp_pins,
725	.npins = ARRAY_SIZE(spp_pins),
726	.modemuxs = spp_modemux,
727	.nmodemuxs = ARRAY_SIZE(spp_modemux),
728};
729
730static const char *const spp_grps[] = { "spp_grp" };
731static struct spear_function spp_function = {
732	.name = "spp",
733	.groups = spp_grps,
734	.ngroups = ARRAY_SIZE(spp_grps),
735};
736
737/* Pad multiplexing for SDHCI device */
738static const unsigned sdhci_led_pins[] = { 34 };
739static struct spear_muxreg sdhci_led_muxreg[] = {
740	{
741		.reg = PMX_CONFIG_REG,
742		.mask = PMX_SSP_CS_MASK,
743		.val = 0,
744	},
745};
746
747static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748	{
749		.reg = IP_SEL_PAD_30_39_REG,
750		.mask = PMX_PL_34_MASK,
751		.val = PMX_PWM2_PL_34_VAL,
752	},
753};
754
755static struct spear_modemux sdhci_led_modemux[] = {
756	{
757		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758		.muxregs = sdhci_led_muxreg,
759		.nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760	}, {
761		.modes = EXTENDED_MODE,
762		.muxregs = sdhci_led_ext_muxreg,
763		.nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764	},
765};
766
767static struct spear_pingroup sdhci_led_pingroup = {
768	.name = "sdhci_led_grp",
769	.pins = sdhci_led_pins,
770	.npins = ARRAY_SIZE(sdhci_led_pins),
771	.modemuxs = sdhci_led_modemux,
772	.nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773};
774
775static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776	50};
777static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778};
779static struct spear_muxreg sdhci_muxreg[] = {
780	{
781		.reg = PMX_CONFIG_REG,
782		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783		.val = 0,
784	},
785};
786
787static struct spear_muxreg sdhci_ext_muxreg[] = {
788	{
789		.reg = IP_SEL_PAD_40_49_REG,
790		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791			PMX_PL_48_49_MASK,
792		.val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793			PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794	}, {
795		.reg = IP_SEL_PAD_50_59_REG,
796		.mask = PMX_PL_50_MASK,
797		.val = PMX_SDHCI_PL_50_VAL,
798	}, {
799		.reg = IP_SEL_PAD_90_99_REG,
800		.mask = PMX_PL_99_MASK,
801		.val = PMX_SDHCI_PL_99_VAL,
802	}, {
803		.reg = IP_SEL_MIX_PAD_REG,
804		.mask = PMX_PL_100_101_MASK,
805		.val = PMX_SDHCI_PL_100_101_VAL,
806	},
807};
808
809static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810	{
811		.reg = PMX_CONFIG_REG,
812		.mask = PMX_MII_MASK,
813		.val = 0,
814	}, {
815		.reg = IP_SEL_PAD_10_19_REG,
816		.mask = PMX_PL_12_MASK,
817		.val = PMX_SDHCI_CD_PL_12_VAL,
818	}, {
819		.reg = IP_SEL_MIX_PAD_REG,
820		.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821		.val = PMX_SDHCI_CD_PORT_12_VAL,
822	},
823};
824
825static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826	{
827		.reg = IP_SEL_PAD_50_59_REG,
828		.mask = PMX_PL_51_MASK,
829		.val = PMX_SDHCI_CD_PL_51_VAL,
830	}, {
831		.reg = IP_SEL_MIX_PAD_REG,
832		.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833		.val = PMX_SDHCI_CD_PORT_51_VAL,
834	},
835};
836
837#define pmx_sdhci_common_modemux					\
838	{								\
839		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |	\
840			SMALL_PRINTERS_MODE | EXTENDED_MODE,		\
841		.muxregs = sdhci_muxreg,				\
842		.nmuxregs = ARRAY_SIZE(sdhci_muxreg),			\
843	}, {								\
844		.modes = EXTENDED_MODE,					\
845		.muxregs = sdhci_ext_muxreg,				\
846		.nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg),		\
847	}
848
849static struct spear_modemux sdhci_modemux[][3] = {
850	{
851		/* select pin 12 for cd */
852		pmx_sdhci_common_modemux,
853		{
854			.modes = EXTENDED_MODE,
855			.muxregs = sdhci_cd_12_muxreg,
856			.nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857		},
858	}, {
859		/* select pin 51 for cd */
860		pmx_sdhci_common_modemux,
861		{
862			.modes = EXTENDED_MODE,
863			.muxregs = sdhci_cd_51_muxreg,
864			.nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865		},
866	}
867};
868
869static struct spear_pingroup sdhci_pingroup[] = {
870	{
871		.name = "sdhci_cd_12_grp",
872		.pins = sdhci_cd_12_pins,
873		.npins = ARRAY_SIZE(sdhci_cd_12_pins),
874		.modemuxs = sdhci_modemux[0],
875		.nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876	}, {
877		.name = "sdhci_cd_51_grp",
878		.pins = sdhci_cd_51_pins,
879		.npins = ARRAY_SIZE(sdhci_cd_51_pins),
880		.modemuxs = sdhci_modemux[1],
881		.nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882	},
883};
884
885static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886	"sdhci_led_grp" };
887
888static struct spear_function sdhci_function = {
889	.name = "sdhci",
890	.groups = sdhci_grps,
891	.ngroups = ARRAY_SIZE(sdhci_grps),
892};
893
894/* Pad multiplexing for I2S device */
895static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896static struct spear_muxreg i2s_muxreg[] = {
897	{
898		.reg = PMX_CONFIG_REG,
899		.mask = PMX_SSP_CS_MASK,
900		.val = 0,
901	}, {
902		.reg = PMX_CONFIG_REG,
903		.mask = PMX_UART0_MODEM_MASK,
904		.val = 0,
905	},
906};
907
908static struct spear_muxreg i2s_ext_muxreg[] = {
909	{
910		.reg = IP_SEL_PAD_30_39_REG,
911		.mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912		.val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913	}, {
914		.reg = IP_SEL_PAD_40_49_REG,
915		.mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916		.val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917	},
918};
919
920static struct spear_modemux i2s_modemux[] = {
921	{
922		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923		.muxregs = i2s_muxreg,
924		.nmuxregs = ARRAY_SIZE(i2s_muxreg),
925	}, {
926		.modes = EXTENDED_MODE,
927		.muxregs = i2s_ext_muxreg,
928		.nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929	},
930};
931
932static struct spear_pingroup i2s_pingroup = {
933	.name = "i2s_grp",
934	.pins = i2s_pins,
935	.npins = ARRAY_SIZE(i2s_pins),
936	.modemuxs = i2s_modemux,
937	.nmodemuxs = ARRAY_SIZE(i2s_modemux),
938};
939
940static const char *const i2s_grps[] = { "i2s_grp" };
941static struct spear_function i2s_function = {
942	.name = "i2s",
943	.groups = i2s_grps,
944	.ngroups = ARRAY_SIZE(i2s_grps),
945};
946
947/* Pad multiplexing for UART1 device */
948static const unsigned uart1_pins[] = { 28, 29 };
949static struct spear_muxreg uart1_muxreg[] = {
950	{
951		.reg = PMX_CONFIG_REG,
952		.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953		.val = 0,
954	},
955};
956
957static struct spear_muxreg uart1_ext_muxreg[] = {
958	{
959		.reg = IP_SEL_PAD_20_29_REG,
960		.mask = PMX_PL_28_29_MASK,
961		.val = PMX_UART1_PL_28_29_VAL,
962	},
963};
964
965static struct spear_modemux uart1_modemux[] = {
966	{
967		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968			| SMALL_PRINTERS_MODE | EXTENDED_MODE,
969		.muxregs = uart1_muxreg,
970		.nmuxregs = ARRAY_SIZE(uart1_muxreg),
971	}, {
972		.modes = EXTENDED_MODE,
973		.muxregs = uart1_ext_muxreg,
974		.nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975	},
976};
977
978static struct spear_pingroup uart1_pingroup = {
979	.name = "uart1_grp",
980	.pins = uart1_pins,
981	.npins = ARRAY_SIZE(uart1_pins),
982	.modemuxs = uart1_modemux,
983	.nmodemuxs = ARRAY_SIZE(uart1_modemux),
984};
985
986static const char *const uart1_grps[] = { "uart1_grp" };
987static struct spear_function uart1_function = {
988	.name = "uart1",
989	.groups = uart1_grps,
990	.ngroups = ARRAY_SIZE(uart1_grps),
991};
992
993/* Pad multiplexing for UART1 Modem device */
994static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
999static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000	{
1001		.reg = PMX_CONFIG_REG,
1002		.mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003		.val = 0,
1004	}, {
1005		.reg = IP_SEL_PAD_0_9_REG,
1006		.mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007		.val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008			PMX_UART1_ENH_PL_6_7_VAL,
1009	}, {
1010		.reg = IP_SEL_MIX_PAD_REG,
1011		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012		.val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013	},
1014};
1015
1016static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017	{
1018		.reg = PMX_CONFIG_REG,
1019		.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020			PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021		.val = 0,
1022	},
1023};
1024
1025static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026	{
1027		.reg = IP_SEL_PAD_30_39_REG,
1028		.mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029			PMX_PL_35_MASK | PMX_PL_36_MASK,
1030		.val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031			PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032			PMX_UART1_ENH_PL_36_VAL,
1033	}, {
1034		.reg = IP_SEL_MIX_PAD_REG,
1035		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036		.val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037	},
1038};
1039
1040static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041	{
1042		.reg = PMX_CONFIG_REG,
1043		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044			PMX_SSP_CS_MASK,
1045		.val = 0,
1046	},
1047};
1048
1049static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050	{
1051		.reg = IP_SEL_PAD_30_39_REG,
1052		.mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053		.val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054			PMX_UART1_ENH_PL_36_VAL,
1055	}, {
1056		.reg = IP_SEL_PAD_40_49_REG,
1057		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058		.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059	}, {
1060		.reg = IP_SEL_MIX_PAD_REG,
1061		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062		.val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063	},
1064};
1065
1066static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067	{
1068		.reg = IP_SEL_PAD_80_89_REG,
1069		.mask = PMX_PL_80_TO_85_MASK,
1070		.val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071	}, {
1072		.reg = IP_SEL_PAD_40_49_REG,
1073		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074		.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075	}, {
1076		.reg = IP_SEL_MIX_PAD_REG,
1077		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078		.val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079	},
1080};
1081
1082static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083	{
1084		.modes = EXTENDED_MODE,
1085		.muxregs = uart1_modem_ext_2_to_7_muxreg,
1086		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087	},
1088};
1089
1090static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091	{
1092		.modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093		.muxregs = uart1_modem_31_to_36_muxreg,
1094		.nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095	}, {
1096		.modes = EXTENDED_MODE,
1097		.muxregs = uart1_modem_ext_31_to_36_muxreg,
1098		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099	},
1100};
1101
1102static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103	{
1104		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105		.muxregs = uart1_modem_34_to_45_muxreg,
1106		.nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107	}, {
1108		.modes = EXTENDED_MODE,
1109		.muxregs = uart1_modem_ext_34_to_45_muxreg,
1110		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111	},
1112};
1113
1114static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115	{
1116		.modes = EXTENDED_MODE,
1117		.muxregs = uart1_modem_ext_80_to_85_muxreg,
1118		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119	},
1120};
1121
1122static struct spear_pingroup uart1_modem_pingroup[] = {
1123	{
1124		.name = "uart1_modem_2_to_7_grp",
1125		.pins = uart1_modem_2_to_7_pins,
1126		.npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127		.modemuxs = uart1_modem_2_to_7_modemux,
1128		.nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129	}, {
1130		.name = "uart1_modem_31_to_36_grp",
1131		.pins = uart1_modem_31_to_36_pins,
1132		.npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133		.modemuxs = uart1_modem_31_to_36_modemux,
1134		.nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135	}, {
1136		.name = "uart1_modem_34_to_45_grp",
1137		.pins = uart1_modem_34_to_45_pins,
1138		.npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139		.modemuxs = uart1_modem_34_to_45_modemux,
1140		.nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141	}, {
1142		.name = "uart1_modem_80_to_85_grp",
1143		.pins = uart1_modem_80_to_85_pins,
1144		.npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145		.modemuxs = uart1_modem_80_to_85_modemux,
1146		.nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147	},
1148};
1149
1150static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151	"uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152	"uart1_modem_80_to_85_grp" };
1153static struct spear_function uart1_modem_function = {
1154	.name = "uart1_modem",
1155	.groups = uart1_modem_grps,
1156	.ngroups = ARRAY_SIZE(uart1_modem_grps),
1157};
1158
1159/* Pad multiplexing for UART2 device */
1160static const unsigned uart2_pins[] = { 0, 1 };
1161static struct spear_muxreg uart2_muxreg[] = {
1162	{
1163		.reg = PMX_CONFIG_REG,
1164		.mask = PMX_FIRDA_MASK,
1165		.val = 0,
1166	},
1167};
1168
1169static struct spear_muxreg uart2_ext_muxreg[] = {
1170	{
1171		.reg = IP_SEL_PAD_0_9_REG,
1172		.mask = PMX_PL_0_1_MASK,
1173		.val = PMX_UART2_PL_0_1_VAL,
1174	},
1175};
1176
1177static struct spear_modemux uart2_modemux[] = {
1178	{
1179		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180			| SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181		.muxregs = uart2_muxreg,
1182		.nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183	}, {
1184		.modes = EXTENDED_MODE,
1185		.muxregs = uart2_ext_muxreg,
1186		.nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187	},
1188};
1189
1190static struct spear_pingroup uart2_pingroup = {
1191	.name = "uart2_grp",
1192	.pins = uart2_pins,
1193	.npins = ARRAY_SIZE(uart2_pins),
1194	.modemuxs = uart2_modemux,
1195	.nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196};
1197
1198static const char *const uart2_grps[] = { "uart2_grp" };
1199static struct spear_function uart2_function = {
1200	.name = "uart2",
1201	.groups = uart2_grps,
1202	.ngroups = ARRAY_SIZE(uart2_grps),
1203};
1204
1205/* Pad multiplexing for uart3 device */
1206static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207	{ 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
1209static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210	{
1211		.reg = PMX_CONFIG_REG,
1212		.mask = PMX_SSP_MASK,
1213		.val = 0,
1214	}, {
1215		.reg = IP_SEL_PAD_0_9_REG,
1216		.mask = PMX_PL_8_9_MASK,
1217		.val = PMX_UART3_PL_8_9_VAL,
1218	}, {
1219		.reg = IP_SEL_MIX_PAD_REG,
1220		.mask = PMX_UART3_PORT_SEL_MASK,
1221		.val = PMX_UART3_PORT_8_VAL,
1222	},
1223};
1224
1225static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226	{
1227		.reg = PMX_CONFIG_REG,
1228		.mask = PMX_MII_MASK,
1229		.val = 0,
1230	}, {
1231		.reg = IP_SEL_PAD_10_19_REG,
1232		.mask = PMX_PL_15_16_MASK,
1233		.val = PMX_UART3_PL_15_16_VAL,
1234	}, {
1235		.reg = IP_SEL_MIX_PAD_REG,
1236		.mask = PMX_UART3_PORT_SEL_MASK,
1237		.val = PMX_UART3_PORT_15_VAL,
1238	},
1239};
1240
1241static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242	{
1243		.reg = PMX_CONFIG_REG,
1244		.mask = PMX_UART0_MODEM_MASK,
1245		.val = 0,
1246	}, {
1247		.reg = IP_SEL_PAD_40_49_REG,
1248		.mask = PMX_PL_41_42_MASK,
1249		.val = PMX_UART3_PL_41_42_VAL,
1250	}, {
1251		.reg = IP_SEL_MIX_PAD_REG,
1252		.mask = PMX_UART3_PORT_SEL_MASK,
1253		.val = PMX_UART3_PORT_41_VAL,
1254	},
1255};
1256
1257static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258	{
1259		.reg = IP_SEL_PAD_50_59_REG,
1260		.mask = PMX_PL_52_53_MASK,
1261		.val = PMX_UART3_PL_52_53_VAL,
1262	}, {
1263		.reg = IP_SEL_MIX_PAD_REG,
1264		.mask = PMX_UART3_PORT_SEL_MASK,
1265		.val = PMX_UART3_PORT_52_VAL,
1266	},
1267};
1268
1269static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270	{
1271		.reg = IP_SEL_PAD_70_79_REG,
1272		.mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273		.val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274	}, {
1275		.reg = IP_SEL_MIX_PAD_REG,
1276		.mask = PMX_UART3_PORT_SEL_MASK,
1277		.val = PMX_UART3_PORT_73_VAL,
1278	},
1279};
1280
1281static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282	{
1283		.reg = IP_SEL_PAD_90_99_REG,
1284		.mask = PMX_PL_94_95_MASK,
1285		.val = PMX_UART3_PL_94_95_VAL,
1286	}, {
1287		.reg = IP_SEL_MIX_PAD_REG,
1288		.mask = PMX_UART3_PORT_SEL_MASK,
1289		.val = PMX_UART3_PORT_94_VAL,
1290	},
1291};
1292
1293static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294	{
1295		.reg = IP_SEL_PAD_90_99_REG,
1296		.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297		.val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298	}, {
1299		.reg = IP_SEL_MIX_PAD_REG,
1300		.mask = PMX_UART3_PORT_SEL_MASK,
1301		.val = PMX_UART3_PORT_99_VAL,
1302	},
1303};
1304
1305static struct spear_modemux uart3_modemux[][1] = {
1306	{
1307		/* Select signals on pins 8_9 */
1308		{
1309			.modes = EXTENDED_MODE,
1310			.muxregs = uart3_ext_8_9_muxreg,
1311			.nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312		},
1313	}, {
1314		/* Select signals on pins 15_16 */
1315		{
1316			.modes = EXTENDED_MODE,
1317			.muxregs = uart3_ext_15_16_muxreg,
1318			.nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319		},
1320	}, {
1321		/* Select signals on pins 41_42 */
1322		{
1323			.modes = EXTENDED_MODE,
1324			.muxregs = uart3_ext_41_42_muxreg,
1325			.nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326		},
1327	}, {
1328		/* Select signals on pins 52_53 */
1329		{
1330			.modes = EXTENDED_MODE,
1331			.muxregs = uart3_ext_52_53_muxreg,
1332			.nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333		},
1334	}, {
1335		/* Select signals on pins 73_74 */
1336		{
1337			.modes = EXTENDED_MODE,
1338			.muxregs = uart3_ext_73_74_muxreg,
1339			.nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340		},
1341	}, {
1342		/* Select signals on pins 94_95 */
1343		{
1344			.modes = EXTENDED_MODE,
1345			.muxregs = uart3_ext_94_95_muxreg,
1346			.nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347		},
1348	}, {
1349		/* Select signals on pins 98_99 */
1350		{
1351			.modes = EXTENDED_MODE,
1352			.muxregs = uart3_ext_98_99_muxreg,
1353			.nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354		},
1355	},
1356};
1357
1358static struct spear_pingroup uart3_pingroup[] = {
1359	{
1360		.name = "uart3_8_9_grp",
1361		.pins = uart3_pins[0],
1362		.npins = ARRAY_SIZE(uart3_pins[0]),
1363		.modemuxs = uart3_modemux[0],
1364		.nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365	}, {
1366		.name = "uart3_15_16_grp",
1367		.pins = uart3_pins[1],
1368		.npins = ARRAY_SIZE(uart3_pins[1]),
1369		.modemuxs = uart3_modemux[1],
1370		.nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371	}, {
1372		.name = "uart3_41_42_grp",
1373		.pins = uart3_pins[2],
1374		.npins = ARRAY_SIZE(uart3_pins[2]),
1375		.modemuxs = uart3_modemux[2],
1376		.nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377	}, {
1378		.name = "uart3_52_53_grp",
1379		.pins = uart3_pins[3],
1380		.npins = ARRAY_SIZE(uart3_pins[3]),
1381		.modemuxs = uart3_modemux[3],
1382		.nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383	}, {
1384		.name = "uart3_73_74_grp",
1385		.pins = uart3_pins[4],
1386		.npins = ARRAY_SIZE(uart3_pins[4]),
1387		.modemuxs = uart3_modemux[4],
1388		.nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389	}, {
1390		.name = "uart3_94_95_grp",
1391		.pins = uart3_pins[5],
1392		.npins = ARRAY_SIZE(uart3_pins[5]),
1393		.modemuxs = uart3_modemux[5],
1394		.nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395	}, {
1396		.name = "uart3_98_99_grp",
1397		.pins = uart3_pins[6],
1398		.npins = ARRAY_SIZE(uart3_pins[6]),
1399		.modemuxs = uart3_modemux[6],
1400		.nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401	},
1402};
1403
1404static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405	"uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406	"uart3_94_95_grp", "uart3_98_99_grp" };
1407
1408static struct spear_function uart3_function = {
1409	.name = "uart3",
1410	.groups = uart3_grps,
1411	.ngroups = ARRAY_SIZE(uart3_grps),
1412};
1413
1414/* Pad multiplexing for uart4 device */
1415static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416	{ 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
1418static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419	{
1420		.reg = PMX_CONFIG_REG,
1421		.mask = PMX_SSP_MASK,
1422		.val = 0,
1423	}, {
1424		.reg = IP_SEL_PAD_0_9_REG,
1425		.mask = PMX_PL_6_7_MASK,
1426		.val = PMX_UART4_PL_6_7_VAL,
1427	}, {
1428		.reg = IP_SEL_MIX_PAD_REG,
1429		.mask = PMX_UART4_PORT_SEL_MASK,
1430		.val = PMX_UART4_PORT_6_VAL,
1431	},
1432};
1433
1434static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435	{
1436		.reg = PMX_CONFIG_REG,
1437		.mask = PMX_MII_MASK,
1438		.val = 0,
1439	}, {
1440		.reg = IP_SEL_PAD_10_19_REG,
1441		.mask = PMX_PL_13_14_MASK,
1442		.val = PMX_UART4_PL_13_14_VAL,
1443	}, {
1444		.reg = IP_SEL_MIX_PAD_REG,
1445		.mask = PMX_UART4_PORT_SEL_MASK,
1446		.val = PMX_UART4_PORT_13_VAL,
1447	},
1448};
1449
1450static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451	{
1452		.reg = PMX_CONFIG_REG,
1453		.mask = PMX_UART0_MODEM_MASK,
1454		.val = 0,
1455	}, {
1456		.reg = IP_SEL_PAD_30_39_REG,
1457		.mask = PMX_PL_39_MASK,
1458		.val = PMX_UART4_PL_39_VAL,
1459	}, {
1460		.reg = IP_SEL_PAD_40_49_REG,
1461		.mask = PMX_PL_40_MASK,
1462		.val = PMX_UART4_PL_40_VAL,
1463	}, {
1464		.reg = IP_SEL_MIX_PAD_REG,
1465		.mask = PMX_UART4_PORT_SEL_MASK,
1466		.val = PMX_UART4_PORT_39_VAL,
1467	},
1468};
1469
1470static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471	{
1472		.reg = IP_SEL_PAD_70_79_REG,
1473		.mask = PMX_PL_71_72_MASK,
1474		.val = PMX_UART4_PL_71_72_VAL,
1475	}, {
1476		.reg = IP_SEL_MIX_PAD_REG,
1477		.mask = PMX_UART4_PORT_SEL_MASK,
1478		.val = PMX_UART4_PORT_71_VAL,
1479	},
1480};
1481
1482static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483	{
1484		.reg = IP_SEL_PAD_90_99_REG,
1485		.mask = PMX_PL_92_93_MASK,
1486		.val = PMX_UART4_PL_92_93_VAL,
1487	}, {
1488		.reg = IP_SEL_MIX_PAD_REG,
1489		.mask = PMX_UART4_PORT_SEL_MASK,
1490		.val = PMX_UART4_PORT_92_VAL,
1491	},
1492};
1493
1494static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495	{
1496		.reg = IP_SEL_MIX_PAD_REG,
1497		.mask = PMX_PL_100_101_MASK |
1498			PMX_UART4_PORT_SEL_MASK,
1499		.val = PMX_UART4_PL_100_101_VAL |
1500			PMX_UART4_PORT_101_VAL,
1501	},
1502};
1503
1504static struct spear_modemux uart4_modemux[][1] = {
1505	{
1506		/* Select signals on pins 6_7 */
1507		{
1508			.modes = EXTENDED_MODE,
1509			.muxregs = uart4_ext_6_7_muxreg,
1510			.nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511		},
1512	}, {
1513		/* Select signals on pins 13_14 */
1514		{
1515			.modes = EXTENDED_MODE,
1516			.muxregs = uart4_ext_13_14_muxreg,
1517			.nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518		},
1519	}, {
1520		/* Select signals on pins 39_40 */
1521		{
1522			.modes = EXTENDED_MODE,
1523			.muxregs = uart4_ext_39_40_muxreg,
1524			.nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525		},
1526	}, {
1527		/* Select signals on pins 71_72 */
1528		{
1529			.modes = EXTENDED_MODE,
1530			.muxregs = uart4_ext_71_72_muxreg,
1531			.nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532		},
1533	}, {
1534		/* Select signals on pins 92_93 */
1535		{
1536			.modes = EXTENDED_MODE,
1537			.muxregs = uart4_ext_92_93_muxreg,
1538			.nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539		},
1540	}, {
1541		/* Select signals on pins 100_101_ */
1542		{
1543			.modes = EXTENDED_MODE,
1544			.muxregs = uart4_ext_100_101_muxreg,
1545			.nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546		},
1547	},
1548};
1549
1550static struct spear_pingroup uart4_pingroup[] = {
1551	{
1552		.name = "uart4_6_7_grp",
1553		.pins = uart4_pins[0],
1554		.npins = ARRAY_SIZE(uart4_pins[0]),
1555		.modemuxs = uart4_modemux[0],
1556		.nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557	}, {
1558		.name = "uart4_13_14_grp",
1559		.pins = uart4_pins[1],
1560		.npins = ARRAY_SIZE(uart4_pins[1]),
1561		.modemuxs = uart4_modemux[1],
1562		.nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563	}, {
1564		.name = "uart4_39_40_grp",
1565		.pins = uart4_pins[2],
1566		.npins = ARRAY_SIZE(uart4_pins[2]),
1567		.modemuxs = uart4_modemux[2],
1568		.nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569	}, {
1570		.name = "uart4_71_72_grp",
1571		.pins = uart4_pins[3],
1572		.npins = ARRAY_SIZE(uart4_pins[3]),
1573		.modemuxs = uart4_modemux[3],
1574		.nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575	}, {
1576		.name = "uart4_92_93_grp",
1577		.pins = uart4_pins[4],
1578		.npins = ARRAY_SIZE(uart4_pins[4]),
1579		.modemuxs = uart4_modemux[4],
1580		.nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581	}, {
1582		.name = "uart4_100_101_grp",
1583		.pins = uart4_pins[5],
1584		.npins = ARRAY_SIZE(uart4_pins[5]),
1585		.modemuxs = uart4_modemux[5],
1586		.nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587	},
1588};
1589
1590static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591	"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592	"uart4_100_101_grp" };
1593
1594static struct spear_function uart4_function = {
1595	.name = "uart4",
1596	.groups = uart4_grps,
1597	.ngroups = ARRAY_SIZE(uart4_grps),
1598};
1599
1600/* Pad multiplexing for uart5 device */
1601static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602	{ 90, 91 } };
1603
1604static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605	{
1606		.reg = PMX_CONFIG_REG,
1607		.mask = PMX_I2C_MASK,
1608		.val = 0,
1609	}, {
1610		.reg = IP_SEL_PAD_0_9_REG,
1611		.mask = PMX_PL_4_5_MASK,
1612		.val = PMX_UART5_PL_4_5_VAL,
1613	}, {
1614		.reg = IP_SEL_MIX_PAD_REG,
1615		.mask = PMX_UART5_PORT_SEL_MASK,
1616		.val = PMX_UART5_PORT_4_VAL,
1617	},
1618};
1619
1620static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621	{
1622		.reg = PMX_CONFIG_REG,
1623		.mask = PMX_UART0_MODEM_MASK,
1624		.val = 0,
1625	}, {
1626		.reg = IP_SEL_PAD_30_39_REG,
1627		.mask = PMX_PL_37_38_MASK,
1628		.val = PMX_UART5_PL_37_38_VAL,
1629	}, {
1630		.reg = IP_SEL_MIX_PAD_REG,
1631		.mask = PMX_UART5_PORT_SEL_MASK,
1632		.val = PMX_UART5_PORT_37_VAL,
1633	},
1634};
1635
1636static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637	{
1638		.reg = IP_SEL_PAD_60_69_REG,
1639		.mask = PMX_PL_69_MASK,
1640		.val = PMX_UART5_PL_69_VAL,
1641	}, {
1642		.reg = IP_SEL_PAD_70_79_REG,
1643		.mask = PMX_PL_70_MASK,
1644		.val = PMX_UART5_PL_70_VAL,
1645	}, {
1646		.reg = IP_SEL_MIX_PAD_REG,
1647		.mask = PMX_UART5_PORT_SEL_MASK,
1648		.val = PMX_UART5_PORT_69_VAL,
1649	},
1650};
1651
1652static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653	{
1654		.reg = IP_SEL_PAD_90_99_REG,
1655		.mask = PMX_PL_90_91_MASK,
1656		.val = PMX_UART5_PL_90_91_VAL,
1657	}, {
1658		.reg = IP_SEL_MIX_PAD_REG,
1659		.mask = PMX_UART5_PORT_SEL_MASK,
1660		.val = PMX_UART5_PORT_90_VAL,
1661	},
1662};
1663
1664static struct spear_modemux uart5_modemux[][1] = {
1665	{
1666		/* Select signals on pins 4_5 */
1667		{
1668			.modes = EXTENDED_MODE,
1669			.muxregs = uart5_ext_4_5_muxreg,
1670			.nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671		},
1672	}, {
1673		/* Select signals on pins 37_38 */
1674		{
1675			.modes = EXTENDED_MODE,
1676			.muxregs = uart5_ext_37_38_muxreg,
1677			.nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678		},
1679	}, {
1680		/* Select signals on pins 69_70 */
1681		{
1682			.modes = EXTENDED_MODE,
1683			.muxregs = uart5_ext_69_70_muxreg,
1684			.nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685		},
1686	}, {
1687		/* Select signals on pins 90_91 */
1688		{
1689			.modes = EXTENDED_MODE,
1690			.muxregs = uart5_ext_90_91_muxreg,
1691			.nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692		},
1693	},
1694};
1695
1696static struct spear_pingroup uart5_pingroup[] = {
1697	{
1698		.name = "uart5_4_5_grp",
1699		.pins = uart5_pins[0],
1700		.npins = ARRAY_SIZE(uart5_pins[0]),
1701		.modemuxs = uart5_modemux[0],
1702		.nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703	}, {
1704		.name = "uart5_37_38_grp",
1705		.pins = uart5_pins[1],
1706		.npins = ARRAY_SIZE(uart5_pins[1]),
1707		.modemuxs = uart5_modemux[1],
1708		.nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709	}, {
1710		.name = "uart5_69_70_grp",
1711		.pins = uart5_pins[2],
1712		.npins = ARRAY_SIZE(uart5_pins[2]),
1713		.modemuxs = uart5_modemux[2],
1714		.nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715	}, {
1716		.name = "uart5_90_91_grp",
1717		.pins = uart5_pins[3],
1718		.npins = ARRAY_SIZE(uart5_pins[3]),
1719		.modemuxs = uart5_modemux[3],
1720		.nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721	},
1722};
1723
1724static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725	"uart5_69_70_grp", "uart5_90_91_grp" };
1726static struct spear_function uart5_function = {
1727	.name = "uart5",
1728	.groups = uart5_grps,
1729	.ngroups = ARRAY_SIZE(uart5_grps),
1730};
1731
1732/* Pad multiplexing for uart6 device */
1733static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735	{
1736		.reg = PMX_CONFIG_REG,
1737		.mask = PMX_UART0_MASK,
1738		.val = 0,
1739	}, {
1740		.reg = IP_SEL_PAD_0_9_REG,
1741		.mask = PMX_PL_2_3_MASK,
1742		.val = PMX_UART6_PL_2_3_VAL,
1743	}, {
1744		.reg = IP_SEL_MIX_PAD_REG,
1745		.mask = PMX_UART6_PORT_SEL_MASK,
1746		.val = PMX_UART6_PORT_2_VAL,
1747	},
1748};
1749
1750static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751	{
1752		.reg = IP_SEL_PAD_80_89_REG,
1753		.mask = PMX_PL_88_89_MASK,
1754		.val = PMX_UART6_PL_88_89_VAL,
1755	}, {
1756		.reg = IP_SEL_MIX_PAD_REG,
1757		.mask = PMX_UART6_PORT_SEL_MASK,
1758		.val = PMX_UART6_PORT_88_VAL,
1759	},
1760};
1761
1762static struct spear_modemux uart6_modemux[][1] = {
1763	{
1764		/* Select signals on pins 2_3 */
1765		{
1766			.modes = EXTENDED_MODE,
1767			.muxregs = uart6_ext_2_3_muxreg,
1768			.nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769		},
1770	}, {
1771		/* Select signals on pins 88_89 */
1772		{
1773			.modes = EXTENDED_MODE,
1774			.muxregs = uart6_ext_88_89_muxreg,
1775			.nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776		},
1777	},
1778};
1779
1780static struct spear_pingroup uart6_pingroup[] = {
1781	{
1782		.name = "uart6_2_3_grp",
1783		.pins = uart6_pins[0],
1784		.npins = ARRAY_SIZE(uart6_pins[0]),
1785		.modemuxs = uart6_modemux[0],
1786		.nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787	}, {
1788		.name = "uart6_88_89_grp",
1789		.pins = uart6_pins[1],
1790		.npins = ARRAY_SIZE(uart6_pins[1]),
1791		.modemuxs = uart6_modemux[1],
1792		.nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793	},
1794};
1795
1796static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797static struct spear_function uart6_function = {
1798	.name = "uart6",
1799	.groups = uart6_grps,
1800	.ngroups = ARRAY_SIZE(uart6_grps),
1801};
1802
1803/* UART - RS485 pmx */
1804static const unsigned rs485_pins[] = { 77, 78, 79 };
1805static struct spear_muxreg rs485_muxreg[] = {
1806	{
1807		.reg = IP_SEL_PAD_70_79_REG,
1808		.mask = PMX_PL_77_78_79_MASK,
1809		.val = PMX_RS485_PL_77_78_79_VAL,
1810	},
1811};
1812
1813static struct spear_modemux rs485_modemux[] = {
1814	{
1815		.modes = EXTENDED_MODE,
1816		.muxregs = rs485_muxreg,
1817		.nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818	},
1819};
1820
1821static struct spear_pingroup rs485_pingroup = {
1822	.name = "rs485_grp",
1823	.pins = rs485_pins,
1824	.npins = ARRAY_SIZE(rs485_pins),
1825	.modemuxs = rs485_modemux,
1826	.nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827};
1828
1829static const char *const rs485_grps[] = { "rs485_grp" };
1830static struct spear_function rs485_function = {
1831	.name = "rs485",
1832	.groups = rs485_grps,
1833	.ngroups = ARRAY_SIZE(rs485_grps),
1834};
1835
1836/* Pad multiplexing for Touchscreen device */
1837static const unsigned touchscreen_pins[] = { 5, 36 };
1838static struct spear_muxreg touchscreen_muxreg[] = {
1839	{
1840		.reg = PMX_CONFIG_REG,
1841		.mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842		.val = 0,
1843	},
1844};
1845
1846static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847	{
1848		.reg = IP_SEL_PAD_0_9_REG,
1849		.mask = PMX_PL_5_MASK,
1850		.val = PMX_TOUCH_Y_PL_5_VAL,
1851	}, {
1852		.reg = IP_SEL_PAD_30_39_REG,
1853		.mask = PMX_PL_36_MASK,
1854		.val = PMX_TOUCH_X_PL_36_VAL,
1855	},
1856};
1857
1858static struct spear_modemux touchscreen_modemux[] = {
1859	{
1860		.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861		.muxregs = touchscreen_muxreg,
1862		.nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863	}, {
1864		.modes = EXTENDED_MODE,
1865		.muxregs = touchscreen_ext_muxreg,
1866		.nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867	},
1868};
1869
1870static struct spear_pingroup touchscreen_pingroup = {
1871	.name = "touchscreen_grp",
1872	.pins = touchscreen_pins,
1873	.npins = ARRAY_SIZE(touchscreen_pins),
1874	.modemuxs = touchscreen_modemux,
1875	.nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876};
1877
1878static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879static struct spear_function touchscreen_function = {
1880	.name = "touchscreen",
1881	.groups = touchscreen_grps,
1882	.ngroups = ARRAY_SIZE(touchscreen_grps),
1883};
1884
1885/* Pad multiplexing for CAN device */
1886static const unsigned can0_pins[] = { 32, 33 };
1887static struct spear_muxreg can0_muxreg[] = {
1888	{
1889		.reg = PMX_CONFIG_REG,
1890		.mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891		.val = 0,
1892	},
1893};
1894
1895static struct spear_muxreg can0_ext_muxreg[] = {
1896	{
1897		.reg = IP_SEL_PAD_30_39_REG,
1898		.mask = PMX_PL_32_33_MASK,
1899		.val = PMX_CAN0_PL_32_33_VAL,
1900	},
1901};
1902
1903static struct spear_modemux can0_modemux[] = {
1904	{
1905		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906			| EXTENDED_MODE,
1907		.muxregs = can0_muxreg,
1908		.nmuxregs = ARRAY_SIZE(can0_muxreg),
1909	}, {
1910		.modes = EXTENDED_MODE,
1911		.muxregs = can0_ext_muxreg,
1912		.nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913	},
1914};
1915
1916static struct spear_pingroup can0_pingroup = {
1917	.name = "can0_grp",
1918	.pins = can0_pins,
1919	.npins = ARRAY_SIZE(can0_pins),
1920	.modemuxs = can0_modemux,
1921	.nmodemuxs = ARRAY_SIZE(can0_modemux),
1922};
1923
1924static const char *const can0_grps[] = { "can0_grp" };
1925static struct spear_function can0_function = {
1926	.name = "can0",
1927	.groups = can0_grps,
1928	.ngroups = ARRAY_SIZE(can0_grps),
1929};
1930
1931static const unsigned can1_pins[] = { 30, 31 };
1932static struct spear_muxreg can1_muxreg[] = {
1933	{
1934		.reg = PMX_CONFIG_REG,
1935		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936		.val = 0,
1937	},
1938};
1939
1940static struct spear_muxreg can1_ext_muxreg[] = {
1941	{
1942		.reg = IP_SEL_PAD_30_39_REG,
1943		.mask = PMX_PL_30_31_MASK,
1944		.val = PMX_CAN1_PL_30_31_VAL,
1945	},
1946};
1947
1948static struct spear_modemux can1_modemux[] = {
1949	{
1950		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951			| EXTENDED_MODE,
1952		.muxregs = can1_muxreg,
1953		.nmuxregs = ARRAY_SIZE(can1_muxreg),
1954	}, {
1955		.modes = EXTENDED_MODE,
1956		.muxregs = can1_ext_muxreg,
1957		.nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958	},
1959};
1960
1961static struct spear_pingroup can1_pingroup = {
1962	.name = "can1_grp",
1963	.pins = can1_pins,
1964	.npins = ARRAY_SIZE(can1_pins),
1965	.modemuxs = can1_modemux,
1966	.nmodemuxs = ARRAY_SIZE(can1_modemux),
1967};
1968
1969static const char *const can1_grps[] = { "can1_grp" };
1970static struct spear_function can1_function = {
1971	.name = "can1",
1972	.groups = can1_grps,
1973	.ngroups = ARRAY_SIZE(can1_grps),
1974};
1975
1976/* Pad multiplexing for PWM0_1 device */
1977static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978	{ 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
1980static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981	{
1982		.reg = PMX_CONFIG_REG,
1983		.mask = PMX_SSP_MASK,
1984		.val = 0,
1985	}, {
1986		.reg = IP_SEL_PAD_0_9_REG,
1987		.mask = PMX_PL_8_9_MASK,
1988		.val = PMX_PWM_0_1_PL_8_9_VAL,
1989	},
1990};
1991
1992static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993	{
1994		.reg = PMX_CONFIG_REG,
1995		.mask = PMX_MII_MASK,
1996		.val = 0,
1997	},
1998};
1999
2000static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001	{
2002		.reg = IP_SEL_PAD_10_19_REG,
2003		.mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004		.val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005	},
2006};
2007
2008static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009	{
2010		.reg = PMX_CONFIG_REG,
2011		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012		.val = 0,
2013	}, {
2014		.reg = IP_SEL_PAD_30_39_REG,
2015		.mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016		.val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017	},
2018};
2019
2020static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021	{
2022		.reg = PMX_CONFIG_REG,
2023		.mask = PMX_UART0_MODEM_MASK,
2024		.val = 0,
2025	},
2026};
2027
2028static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029	{
2030		.reg = IP_SEL_PAD_30_39_REG,
2031		.mask = PMX_PL_37_38_MASK,
2032		.val = PMX_PWM0_1_PL_37_38_VAL,
2033	},
2034};
2035
2036static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037	{
2038		.reg = PMX_CONFIG_REG,
2039		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040		.val = 0,
2041	}, {
2042		.reg = IP_SEL_PAD_40_49_REG,
2043		.mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044		.val = PMX_PWM1_PL_42_VAL |
2045			PMX_PWM0_PL_43_VAL,
2046	},
2047};
2048
2049static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050	{
2051		.reg = IP_SEL_PAD_50_59_REG,
2052		.mask = PMX_PL_59_MASK,
2053		.val = PMX_PWM1_PL_59_VAL,
2054	}, {
2055		.reg = IP_SEL_PAD_60_69_REG,
2056		.mask = PMX_PL_60_MASK,
2057		.val = PMX_PWM0_PL_60_VAL,
2058	},
2059};
2060
2061static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062	{
2063		.reg = IP_SEL_PAD_80_89_REG,
2064		.mask = PMX_PL_88_89_MASK,
2065		.val = PMX_PWM0_1_PL_88_89_VAL,
2066	},
2067};
2068
2069static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070	{
2071		.modes = EXTENDED_MODE,
2072		.muxregs = pwm0_1_pin_8_9_muxreg,
2073		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074	},
2075};
2076
2077static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078	{
2079		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080		.muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081		.nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082	}, {
2083		.modes = EXTENDED_MODE,
2084		.muxregs = pwm0_1_pin_14_15_muxreg,
2085		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086	},
2087};
2088
2089static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090	{
2091		.modes = EXTENDED_MODE,
2092		.muxregs = pwm0_1_pin_30_31_muxreg,
2093		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094	},
2095};
2096
2097static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098	{
2099		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100		.muxregs = pwm0_1_net_muxreg,
2101		.nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102	}, {
2103		.modes = EXTENDED_MODE,
2104		.muxregs = pwm0_1_pin_37_38_muxreg,
2105		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106	},
2107};
2108
2109static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110	{
2111		.modes = EXTENDED_MODE,
2112		.muxregs = pwm0_1_pin_42_43_muxreg,
2113		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114	},
2115};
2116
2117static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118	{
2119		.modes = EXTENDED_MODE,
2120		.muxregs = pwm0_1_pin_59_60_muxreg,
2121		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122	},
2123};
2124
2125static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126	{
2127		.modes = EXTENDED_MODE,
2128		.muxregs = pwm0_1_pin_88_89_muxreg,
2129		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130	},
2131};
2132
2133static struct spear_pingroup pwm0_1_pingroup[] = {
2134	{
2135		.name = "pwm0_1_pin_8_9_grp",
2136		.pins = pwm0_1_pins[0],
2137		.npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138		.modemuxs = pwm0_1_pin_8_9_modemux,
2139		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140	}, {
2141		.name = "pwm0_1_pin_14_15_grp",
2142		.pins = pwm0_1_pins[1],
2143		.npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144		.modemuxs = pwm0_1_pin_14_15_modemux,
2145		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146	}, {
2147		.name = "pwm0_1_pin_30_31_grp",
2148		.pins = pwm0_1_pins[2],
2149		.npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150		.modemuxs = pwm0_1_pin_30_31_modemux,
2151		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152	}, {
2153		.name = "pwm0_1_pin_37_38_grp",
2154		.pins = pwm0_1_pins[3],
2155		.npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156		.modemuxs = pwm0_1_pin_37_38_modemux,
2157		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158	}, {
2159		.name = "pwm0_1_pin_42_43_grp",
2160		.pins = pwm0_1_pins[4],
2161		.npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162		.modemuxs = pwm0_1_pin_42_43_modemux,
2163		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164	}, {
2165		.name = "pwm0_1_pin_59_60_grp",
2166		.pins = pwm0_1_pins[5],
2167		.npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168		.modemuxs = pwm0_1_pin_59_60_modemux,
2169		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170	}, {
2171		.name = "pwm0_1_pin_88_89_grp",
2172		.pins = pwm0_1_pins[6],
2173		.npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174		.modemuxs = pwm0_1_pin_88_89_modemux,
2175		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176	},
2177};
2178
2179static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180	"pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181	"pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182};
2183
2184static struct spear_function pwm0_1_function = {
2185	.name = "pwm0_1",
2186	.groups = pwm0_1_grps,
2187	.ngroups = ARRAY_SIZE(pwm0_1_grps),
2188};
2189
2190/* Pad multiplexing for PWM2 device */
2191static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192	{ 58 }, { 87 } };
2193static struct spear_muxreg pwm2_net_muxreg[] = {
2194	{
2195		.reg = PMX_CONFIG_REG,
2196		.mask = PMX_SSP_CS_MASK,
2197		.val = 0,
2198	},
2199};
2200
2201static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202	{
2203		.reg = IP_SEL_PAD_0_9_REG,
2204		.mask = PMX_PL_7_MASK,
2205		.val = PMX_PWM_2_PL_7_VAL,
2206	},
2207};
2208
2209static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210	{
2211		.reg = PMX_CONFIG_REG,
2212		.mask = PMX_MII_MASK,
2213		.val = 0,
2214	},
2215};
2216
2217static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218	{
2219		.reg = IP_SEL_PAD_10_19_REG,
2220		.mask = PMX_PL_13_MASK,
2221		.val = PMX_PWM2_PL_13_VAL,
2222	},
2223};
2224
2225static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226	{
2227		.reg = PMX_CONFIG_REG,
2228		.mask = PMX_GPIO_PIN1_MASK,
2229		.val = 0,
2230	}, {
2231		.reg = IP_SEL_PAD_20_29_REG,
2232		.mask = PMX_PL_29_MASK,
2233		.val = PMX_PWM_2_PL_29_VAL,
2234	},
2235};
2236
2237static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238	{
2239		.reg = PMX_CONFIG_REG,
2240		.mask = PMX_SSP_CS_MASK,
2241		.val = 0,
2242	}, {
2243		.reg = MODE_CONFIG_REG,
2244		.mask = PMX_PWM_MASK,
2245		.val = PMX_PWM_MASK,
2246	}, {
2247		.reg = IP_SEL_PAD_30_39_REG,
2248		.mask = PMX_PL_34_MASK,
2249		.val = PMX_PWM2_PL_34_VAL,
2250	},
2251};
2252
2253static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2254	{
2255		.reg = PMX_CONFIG_REG,
2256		.mask = PMX_UART0_MODEM_MASK,
2257		.val = 0,
2258	}, {
2259		.reg = IP_SEL_PAD_40_49_REG,
2260		.mask = PMX_PL_41_MASK,
2261		.val = PMX_PWM2_PL_41_VAL,
2262	},
2263};
2264
2265static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2266	{
2267		.reg = IP_SEL_PAD_50_59_REG,
2268		.mask = PMX_PL_58_MASK,
2269		.val = PMX_PWM2_PL_58_VAL,
2270	},
2271};
2272
2273static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2274	{
2275		.reg = IP_SEL_PAD_80_89_REG,
2276		.mask = PMX_PL_87_MASK,
2277		.val = PMX_PWM2_PL_87_VAL,
2278	},
2279};
2280
2281static struct spear_modemux pwm2_pin_7_modemux[] = {
2282	{
2283		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2284		.muxregs = pwm2_net_muxreg,
2285		.nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2286	}, {
2287		.modes = EXTENDED_MODE,
2288		.muxregs = pwm2_pin_7_muxreg,
2289		.nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2290	},
2291};
2292static struct spear_modemux pwm2_pin_13_modemux[] = {
2293	{
2294		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2295		.muxregs = pwm2_autoexpsmallpri_muxreg,
2296		.nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2297	}, {
2298		.modes = EXTENDED_MODE,
2299		.muxregs = pwm2_pin_13_muxreg,
2300		.nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2301	},
2302};
2303static struct spear_modemux pwm2_pin_29_modemux[] = {
2304	{
2305		.modes = EXTENDED_MODE,
2306		.muxregs = pwm2_pin_29_muxreg,
2307		.nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2308	},
2309};
2310static struct spear_modemux pwm2_pin_34_modemux[] = {
2311	{
2312		.modes = EXTENDED_MODE,
2313		.muxregs = pwm2_pin_34_muxreg,
2314		.nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2315	},
2316};
2317
2318static struct spear_modemux pwm2_pin_41_modemux[] = {
2319	{
2320		.modes = EXTENDED_MODE,
2321		.muxregs = pwm2_pin_41_muxreg,
2322		.nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2323	},
2324};
2325
2326static struct spear_modemux pwm2_pin_58_modemux[] = {
2327	{
2328		.modes = EXTENDED_MODE,
2329		.muxregs = pwm2_pin_58_muxreg,
2330		.nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2331	},
2332};
2333
2334static struct spear_modemux pwm2_pin_87_modemux[] = {
2335	{
2336		.modes = EXTENDED_MODE,
2337		.muxregs = pwm2_pin_87_muxreg,
2338		.nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2339	},
2340};
2341
2342static struct spear_pingroup pwm2_pingroup[] = {
2343	{
2344		.name = "pwm2_pin_7_grp",
2345		.pins = pwm2_pins[0],
2346		.npins = ARRAY_SIZE(pwm2_pins[0]),
2347		.modemuxs = pwm2_pin_7_modemux,
2348		.nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2349	}, {
2350		.name = "pwm2_pin_13_grp",
2351		.pins = pwm2_pins[1],
2352		.npins = ARRAY_SIZE(pwm2_pins[1]),
2353		.modemuxs = pwm2_pin_13_modemux,
2354		.nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2355	}, {
2356		.name = "pwm2_pin_29_grp",
2357		.pins = pwm2_pins[2],
2358		.npins = ARRAY_SIZE(pwm2_pins[2]),
2359		.modemuxs = pwm2_pin_29_modemux,
2360		.nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2361	}, {
2362		.name = "pwm2_pin_34_grp",
2363		.pins = pwm2_pins[3],
2364		.npins = ARRAY_SIZE(pwm2_pins[3]),
2365		.modemuxs = pwm2_pin_34_modemux,
2366		.nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2367	}, {
2368		.name = "pwm2_pin_41_grp",
2369		.pins = pwm2_pins[4],
2370		.npins = ARRAY_SIZE(pwm2_pins[4]),
2371		.modemuxs = pwm2_pin_41_modemux,
2372		.nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2373	}, {
2374		.name = "pwm2_pin_58_grp",
2375		.pins = pwm2_pins[5],
2376		.npins = ARRAY_SIZE(pwm2_pins[5]),
2377		.modemuxs = pwm2_pin_58_modemux,
2378		.nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2379	}, {
2380		.name = "pwm2_pin_87_grp",
2381		.pins = pwm2_pins[6],
2382		.npins = ARRAY_SIZE(pwm2_pins[6]),
2383		.modemuxs = pwm2_pin_87_modemux,
2384		.nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2385	},
2386};
2387
2388static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2389	"pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2390	"pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2391static struct spear_function pwm2_function = {
2392	.name = "pwm2",
2393	.groups = pwm2_grps,
2394	.ngroups = ARRAY_SIZE(pwm2_grps),
2395};
2396
2397/* Pad multiplexing for PWM3 device */
2398static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2399	{ 86 } };
2400static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2401	{
2402		.reg = PMX_CONFIG_REG,
2403		.mask = PMX_SSP_MASK,
2404		.val = 0,
2405	}, {
2406		.reg = IP_SEL_PAD_0_9_REG,
2407		.mask = PMX_PL_6_MASK,
2408		.val = PMX_PWM_3_PL_6_VAL,
2409	},
2410};
2411
2412static struct spear_muxreg pwm3_muxreg[] = {
2413	{
2414		.reg = PMX_CONFIG_REG,
2415		.mask = PMX_MII_MASK,
2416		.val = 0,
2417	},
2418};
2419
2420static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2421	{
2422		.reg = IP_SEL_PAD_10_19_REG,
2423		.mask = PMX_PL_12_MASK,
2424		.val = PMX_PWM3_PL_12_VAL,
2425	},
2426};
2427
2428static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2429	{
2430		.reg = PMX_CONFIG_REG,
2431		.mask = PMX_GPIO_PIN0_MASK,
2432		.val = 0,
2433	}, {
2434		.reg = IP_SEL_PAD_20_29_REG,
2435		.mask = PMX_PL_28_MASK,
2436		.val = PMX_PWM_3_PL_28_VAL,
2437	},
2438};
2439
2440static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2441	{
2442		.reg = PMX_CONFIG_REG,
2443		.mask = PMX_UART0_MODEM_MASK,
2444		.val = 0,
2445	}, {
2446		.reg = IP_SEL_PAD_40_49_REG,
2447		.mask = PMX_PL_40_MASK,
2448		.val = PMX_PWM3_PL_40_VAL,
2449	},
2450};
2451
2452static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2453	{
2454		.reg = IP_SEL_PAD_50_59_REG,
2455		.mask = PMX_PL_57_MASK,
2456		.val = PMX_PWM3_PL_57_VAL,
2457	},
2458};
2459
2460static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2461	{
2462		.reg = IP_SEL_PAD_80_89_REG,
2463		.mask = PMX_PL_86_MASK,
2464		.val = PMX_PWM3_PL_86_VAL,
2465	},
2466};
2467
2468static struct spear_modemux pwm3_pin_6_modemux[] = {
2469	{
2470		.modes = EXTENDED_MODE,
2471		.muxregs = pwm3_pin_6_muxreg,
2472		.nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2473	},
2474};
2475
2476static struct spear_modemux pwm3_pin_12_modemux[] = {
2477	{
2478		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2479			AUTO_NET_SMII_MODE | EXTENDED_MODE,
2480		.muxregs = pwm3_muxreg,
2481		.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2482	}, {
2483		.modes = EXTENDED_MODE,
2484		.muxregs = pwm3_pin_12_muxreg,
2485		.nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2486	},
2487};
2488
2489static struct spear_modemux pwm3_pin_28_modemux[] = {
2490	{
2491		.modes = EXTENDED_MODE,
2492		.muxregs = pwm3_pin_28_muxreg,
2493		.nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2494	},
2495};
2496
2497static struct spear_modemux pwm3_pin_40_modemux[] = {
2498	{
2499		.modes = EXTENDED_MODE,
2500		.muxregs = pwm3_pin_40_muxreg,
2501		.nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2502	},
2503};
2504
2505static struct spear_modemux pwm3_pin_57_modemux[] = {
2506	{
2507		.modes = EXTENDED_MODE,
2508		.muxregs = pwm3_pin_57_muxreg,
2509		.nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2510	},
2511};
2512
2513static struct spear_modemux pwm3_pin_86_modemux[] = {
2514	{
2515		.modes = EXTENDED_MODE,
2516		.muxregs = pwm3_pin_86_muxreg,
2517		.nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2518	},
2519};
2520
2521static struct spear_pingroup pwm3_pingroup[] = {
2522	{
2523		.name = "pwm3_pin_6_grp",
2524		.pins = pwm3_pins[0],
2525		.npins = ARRAY_SIZE(pwm3_pins[0]),
2526		.modemuxs = pwm3_pin_6_modemux,
2527		.nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2528	}, {
2529		.name = "pwm3_pin_12_grp",
2530		.pins = pwm3_pins[1],
2531		.npins = ARRAY_SIZE(pwm3_pins[1]),
2532		.modemuxs = pwm3_pin_12_modemux,
2533		.nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2534	}, {
2535		.name = "pwm3_pin_28_grp",
2536		.pins = pwm3_pins[2],
2537		.npins = ARRAY_SIZE(pwm3_pins[2]),
2538		.modemuxs = pwm3_pin_28_modemux,
2539		.nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2540	}, {
2541		.name = "pwm3_pin_40_grp",
2542		.pins = pwm3_pins[3],
2543		.npins = ARRAY_SIZE(pwm3_pins[3]),
2544		.modemuxs = pwm3_pin_40_modemux,
2545		.nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2546	}, {
2547		.name = "pwm3_pin_57_grp",
2548		.pins = pwm3_pins[4],
2549		.npins = ARRAY_SIZE(pwm3_pins[4]),
2550		.modemuxs = pwm3_pin_57_modemux,
2551		.nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2552	}, {
2553		.name = "pwm3_pin_86_grp",
2554		.pins = pwm3_pins[5],
2555		.npins = ARRAY_SIZE(pwm3_pins[5]),
2556		.modemuxs = pwm3_pin_86_modemux,
2557		.nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2558	},
2559};
2560
2561static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2562	"pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2563	"pwm3_pin_86_grp" };
2564static struct spear_function pwm3_function = {
2565	.name = "pwm3",
2566	.groups = pwm3_grps,
2567	.ngroups = ARRAY_SIZE(pwm3_grps),
2568};
2569
2570/* Pad multiplexing for SSP1 device */
2571static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2572	{ 65, 68 }, { 94, 97 } };
2573static struct spear_muxreg ssp1_muxreg[] = {
2574	{
2575		.reg = PMX_CONFIG_REG,
2576		.mask = PMX_MII_MASK,
2577		.val = 0,
2578	},
2579};
2580
2581static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2582	{
2583		.reg = IP_SEL_PAD_10_19_REG,
2584		.mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2585		.val = PMX_SSP1_PL_17_18_19_20_VAL,
2586	}, {
2587		.reg = IP_SEL_PAD_20_29_REG,
2588		.mask = PMX_PL_20_MASK,
2589		.val = PMX_SSP1_PL_17_18_19_20_VAL,
2590	}, {
2591		.reg = IP_SEL_MIX_PAD_REG,
2592		.mask = PMX_SSP1_PORT_SEL_MASK,
2593		.val = PMX_SSP1_PORT_17_TO_20_VAL,
2594	},
2595};
2596
2597static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2598	{
2599		.reg = PMX_CONFIG_REG,
2600		.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2601		.val = 0,
2602	}, {
2603		.reg = IP_SEL_PAD_30_39_REG,
2604		.mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2605		.val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2606			PMX_SSP1_PL_39_VAL,
2607	}, {
2608		.reg = IP_SEL_MIX_PAD_REG,
2609		.mask = PMX_SSP1_PORT_SEL_MASK,
2610		.val = PMX_SSP1_PORT_36_TO_39_VAL,
2611	},
2612};
2613
2614static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2615	{
2616		.reg = PMX_CONFIG_REG,
2617		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2618		.val = 0,
2619	}, {
2620		.reg = IP_SEL_PAD_40_49_REG,
2621		.mask = PMX_PL_48_49_MASK,
2622		.val = PMX_SSP1_PL_48_49_VAL,
2623	}, {
2624		.reg = IP_SEL_PAD_50_59_REG,
2625		.mask = PMX_PL_50_51_MASK,
2626		.val = PMX_SSP1_PL_50_51_VAL,
2627	}, {
2628		.reg = IP_SEL_MIX_PAD_REG,
2629		.mask = PMX_SSP1_PORT_SEL_MASK,
2630		.val = PMX_SSP1_PORT_48_TO_51_VAL,
2631	},
2632};
2633
2634static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2635	{
2636		.reg = IP_SEL_PAD_60_69_REG,
2637		.mask = PMX_PL_65_TO_68_MASK,
2638		.val = PMX_SSP1_PL_65_TO_68_VAL,
2639	}, {
2640		.reg = IP_SEL_MIX_PAD_REG,
2641		.mask = PMX_SSP1_PORT_SEL_MASK,
2642		.val = PMX_SSP1_PORT_65_TO_68_VAL,
2643	},
2644};
2645
2646static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2647	{
2648		.reg = IP_SEL_PAD_90_99_REG,
2649		.mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2650		.val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2651	}, {
2652		.reg = IP_SEL_MIX_PAD_REG,
2653		.mask = PMX_SSP1_PORT_SEL_MASK,
2654		.val = PMX_SSP1_PORT_94_TO_97_VAL,
2655	},
2656};
2657
2658static struct spear_modemux ssp1_17_20_modemux[] = {
2659	{
2660		.modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2661			EXTENDED_MODE,
2662		.muxregs = ssp1_muxreg,
2663		.nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2664	}, {
2665		.modes = EXTENDED_MODE,
2666		.muxregs = ssp1_ext_17_20_muxreg,
2667		.nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2668	},
2669};
2670
2671static struct spear_modemux ssp1_36_39_modemux[] = {
2672	{
2673		.modes = EXTENDED_MODE,
2674		.muxregs = ssp1_ext_36_39_muxreg,
2675		.nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2676	},
2677};
2678
2679static struct spear_modemux ssp1_48_51_modemux[] = {
2680	{
2681		.modes = EXTENDED_MODE,
2682		.muxregs = ssp1_ext_48_51_muxreg,
2683		.nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2684	},
2685};
2686static struct spear_modemux ssp1_65_68_modemux[] = {
2687	{
2688		.modes = EXTENDED_MODE,
2689		.muxregs = ssp1_ext_65_68_muxreg,
2690		.nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2691	},
2692};
2693
2694static struct spear_modemux ssp1_94_97_modemux[] = {
2695	{
2696		.modes = EXTENDED_MODE,
2697		.muxregs = ssp1_ext_94_97_muxreg,
2698		.nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2699	},
2700};
2701
2702static struct spear_pingroup ssp1_pingroup[] = {
2703	{
2704		.name = "ssp1_17_20_grp",
2705		.pins = ssp1_pins[0],
2706		.npins = ARRAY_SIZE(ssp1_pins[0]),
2707		.modemuxs = ssp1_17_20_modemux,
2708		.nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2709	}, {
2710		.name = "ssp1_36_39_grp",
2711		.pins = ssp1_pins[1],
2712		.npins = ARRAY_SIZE(ssp1_pins[1]),
2713		.modemuxs = ssp1_36_39_modemux,
2714		.nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2715	}, {
2716		.name = "ssp1_48_51_grp",
2717		.pins = ssp1_pins[2],
2718		.npins = ARRAY_SIZE(ssp1_pins[2]),
2719		.modemuxs = ssp1_48_51_modemux,
2720		.nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2721	}, {
2722		.name = "ssp1_65_68_grp",
2723		.pins = ssp1_pins[3],
2724		.npins = ARRAY_SIZE(ssp1_pins[3]),
2725		.modemuxs = ssp1_65_68_modemux,
2726		.nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2727	}, {
2728		.name = "ssp1_94_97_grp",
2729		.pins = ssp1_pins[4],
2730		.npins = ARRAY_SIZE(ssp1_pins[4]),
2731		.modemuxs = ssp1_94_97_modemux,
2732		.nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2733	},
2734};
2735
2736static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2737	"ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2738};
2739static struct spear_function ssp1_function = {
2740	.name = "ssp1",
2741	.groups = ssp1_grps,
2742	.ngroups = ARRAY_SIZE(ssp1_grps),
2743};
2744
2745/* Pad multiplexing for SSP2 device */
2746static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2747	{ 61, 64 }, { 90, 93 } };
2748static struct spear_muxreg ssp2_muxreg[] = {
2749	{
2750		.reg = PMX_CONFIG_REG,
2751		.mask = PMX_MII_MASK,
2752		.val = 0,
2753	},
2754};
2755
2756static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2757	{
2758		.reg = IP_SEL_PAD_10_19_REG,
2759		.mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2760		.val = PMX_SSP2_PL_13_14_15_16_VAL,
2761	}, {
2762		.reg = IP_SEL_MIX_PAD_REG,
2763		.mask = PMX_SSP2_PORT_SEL_MASK,
2764		.val = PMX_SSP2_PORT_13_TO_16_VAL,
2765	},
2766};
2767
2768static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2769	{
2770		.reg = PMX_CONFIG_REG,
2771		.mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2772			PMX_GPIO_PIN5_MASK,
2773		.val = 0,
2774	}, {
2775		.reg = IP_SEL_PAD_30_39_REG,
2776		.mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2777		.val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2778			PMX_SSP2_PL_35_VAL,
2779	}, {
2780		.reg = IP_SEL_MIX_PAD_REG,
2781		.mask = PMX_SSP2_PORT_SEL_MASK,
2782		.val = PMX_SSP2_PORT_32_TO_35_VAL,
2783	},
2784};
2785
2786static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2787	{
2788		.reg = PMX_CONFIG_REG,
2789		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2790		.val = 0,
2791	}, {
2792		.reg = IP_SEL_PAD_40_49_REG,
2793		.mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2794		.val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2795	}, {
2796		.reg = IP_SEL_MIX_PAD_REG,
2797		.mask = PMX_SSP2_PORT_SEL_MASK,
2798		.val = PMX_SSP2_PORT_44_TO_47_VAL,
2799	},
2800};
2801
2802static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2803	{
2804		.reg = IP_SEL_PAD_60_69_REG,
2805		.mask = PMX_PL_61_TO_64_MASK,
2806		.val = PMX_SSP2_PL_61_TO_64_VAL,
2807	}, {
2808		.reg = IP_SEL_MIX_PAD_REG,
2809		.mask = PMX_SSP2_PORT_SEL_MASK,
2810		.val = PMX_SSP2_PORT_61_TO_64_VAL,
2811	},
2812};
2813
2814static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2815	{
2816		.reg = IP_SEL_PAD_90_99_REG,
2817		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2818		.val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2819	}, {
2820		.reg = IP_SEL_MIX_PAD_REG,
2821		.mask = PMX_SSP2_PORT_SEL_MASK,
2822		.val = PMX_SSP2_PORT_90_TO_93_VAL,
2823	},
2824};
2825
2826static struct spear_modemux ssp2_13_16_modemux[] = {
2827	{
2828		.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2829		.muxregs = ssp2_muxreg,
2830		.nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2831	}, {
2832		.modes = EXTENDED_MODE,
2833		.muxregs = ssp2_ext_13_16_muxreg,
2834		.nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2835	},
2836};
2837
2838static struct spear_modemux ssp2_32_35_modemux[] = {
2839	{
2840		.modes = EXTENDED_MODE,
2841		.muxregs = ssp2_ext_32_35_muxreg,
2842		.nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2843	},
2844};
2845
2846static struct spear_modemux ssp2_44_47_modemux[] = {
2847	{
2848		.modes = EXTENDED_MODE,
2849		.muxregs = ssp2_ext_44_47_muxreg,
2850		.nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2851	},
2852};
2853
2854static struct spear_modemux ssp2_61_64_modemux[] = {
2855	{
2856		.modes = EXTENDED_MODE,
2857		.muxregs = ssp2_ext_61_64_muxreg,
2858		.nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2859	},
2860};
2861
2862static struct spear_modemux ssp2_90_93_modemux[] = {
2863	{
2864		.modes = EXTENDED_MODE,
2865		.muxregs = ssp2_ext_90_93_muxreg,
2866		.nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2867	},
2868};
2869
2870static struct spear_pingroup ssp2_pingroup[] = {
2871	{
2872		.name = "ssp2_13_16_grp",
2873		.pins = ssp2_pins[0],
2874		.npins = ARRAY_SIZE(ssp2_pins[0]),
2875		.modemuxs = ssp2_13_16_modemux,
2876		.nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2877	}, {
2878		.name = "ssp2_32_35_grp",
2879		.pins = ssp2_pins[1],
2880		.npins = ARRAY_SIZE(ssp2_pins[1]),
2881		.modemuxs = ssp2_32_35_modemux,
2882		.nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2883	}, {
2884		.name = "ssp2_44_47_grp",
2885		.pins = ssp2_pins[2],
2886		.npins = ARRAY_SIZE(ssp2_pins[2]),
2887		.modemuxs = ssp2_44_47_modemux,
2888		.nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2889	}, {
2890		.name = "ssp2_61_64_grp",
2891		.pins = ssp2_pins[3],
2892		.npins = ARRAY_SIZE(ssp2_pins[3]),
2893		.modemuxs = ssp2_61_64_modemux,
2894		.nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2895	}, {
2896		.name = "ssp2_90_93_grp",
2897		.pins = ssp2_pins[4],
2898		.npins = ARRAY_SIZE(ssp2_pins[4]),
2899		.modemuxs = ssp2_90_93_modemux,
2900		.nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2901	},
2902};
2903
2904static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2905	"ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2906static struct spear_function ssp2_function = {
2907	.name = "ssp2",
2908	.groups = ssp2_grps,
2909	.ngroups = ARRAY_SIZE(ssp2_grps),
2910};
2911
2912/* Pad multiplexing for cadence mii2 as mii device */
2913static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2914	90, 91, 92, 93, 94, 95, 96, 97 };
2915static struct spear_muxreg mii2_muxreg[] = {
2916	{
2917		.reg = IP_SEL_PAD_80_89_REG,
2918		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2919			PMX_PL_88_89_MASK,
2920		.val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2921			PMX_MII2_PL_88_89_VAL,
2922	}, {
2923		.reg = IP_SEL_PAD_90_99_REG,
2924		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2925			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2926		.val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2927			PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2928	}, {
2929		.reg = EXT_CTRL_REG,
2930		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2931			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2932			MII_MDIO_MASK,
2933		.val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2934			(MAC_MODE_MII << MAC1_MODE_SHIFT) |
2935			MII_MDIO_81_VAL,
2936	},
2937};
2938
2939static struct spear_modemux mii2_modemux[] = {
2940	{
2941		.modes = EXTENDED_MODE,
2942		.muxregs = mii2_muxreg,
2943		.nmuxregs = ARRAY_SIZE(mii2_muxreg),
2944	},
2945};
2946
2947static struct spear_pingroup mii2_pingroup = {
2948	.name = "mii2_grp",
2949	.pins = mii2_pins,
2950	.npins = ARRAY_SIZE(mii2_pins),
2951	.modemuxs = mii2_modemux,
2952	.nmodemuxs = ARRAY_SIZE(mii2_modemux),
2953};
2954
2955static const char *const mii2_grps[] = { "mii2_grp" };
2956static struct spear_function mii2_function = {
2957	.name = "mii2",
2958	.groups = mii2_grps,
2959	.ngroups = ARRAY_SIZE(mii2_grps),
2960};
2961
2962/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2963static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2964	21, 22, 23, 24, 25, 26, 27 };
2965static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2966static struct spear_muxreg mii0_1_muxreg[] = {
2967	{
2968		.reg = PMX_CONFIG_REG,
2969		.mask = PMX_MII_MASK,
2970		.val = 0,
2971	},
2972};
2973
2974static struct spear_muxreg smii0_1_ext_muxreg[] = {
2975	{
2976		.reg = IP_SEL_PAD_10_19_REG,
2977		.mask = PMX_PL_10_11_MASK,
2978		.val = PMX_SMII_PL_10_11_VAL,
2979	}, {
2980		.reg = IP_SEL_PAD_20_29_REG,
2981		.mask = PMX_PL_21_TO_27_MASK,
2982		.val = PMX_SMII_PL_21_TO_27_VAL,
2983	}, {
2984		.reg = EXT_CTRL_REG,
2985		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2986			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2987			MII_MDIO_MASK,
2988		.val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2989			| (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2990			| MII_MDIO_10_11_VAL,
2991	},
2992};
2993
2994static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2995	{
2996		.reg = IP_SEL_PAD_10_19_REG,
2997		.mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2998			PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2999		.val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
3000			PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
3001			PMX_RMII_PL_19_VAL,
3002	}, {
3003		.reg = IP_SEL_PAD_20_29_REG,
3004		.mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3005		.val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3006	}, {
3007		.reg = EXT_CTRL_REG,
3008		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3009			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3010			MII_MDIO_MASK,
3011		.val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3012			| (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3013			| MII_MDIO_10_11_VAL,
3014	},
3015};
3016
3017static struct spear_modemux mii0_1_modemux[][2] = {
3018	{
3019		/* configure as smii */
3020		{
3021			.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3022				SMALL_PRINTERS_MODE | EXTENDED_MODE,
3023			.muxregs = mii0_1_muxreg,
3024			.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3025		}, {
3026			.modes = EXTENDED_MODE,
3027			.muxregs = smii0_1_ext_muxreg,
3028			.nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3029		},
3030	}, {
3031		/* configure as rmii */
3032		{
3033			.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3034				SMALL_PRINTERS_MODE | EXTENDED_MODE,
3035			.muxregs = mii0_1_muxreg,
3036			.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3037		}, {
3038			.modes = EXTENDED_MODE,
3039			.muxregs = rmii0_1_ext_muxreg,
3040			.nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3041		},
3042	},
3043};
3044
3045static struct spear_pingroup mii0_1_pingroup[] = {
3046	{
3047		.name = "smii0_1_grp",
3048		.pins = smii0_1_pins,
3049		.npins = ARRAY_SIZE(smii0_1_pins),
3050		.modemuxs = mii0_1_modemux[0],
3051		.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3052	}, {
3053		.name = "rmii0_1_grp",
3054		.pins = rmii0_1_pins,
3055		.npins = ARRAY_SIZE(rmii0_1_pins),
3056		.modemuxs = mii0_1_modemux[1],
3057		.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3058	},
3059};
3060
3061static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3062static struct spear_function mii0_1_function = {
3063	.name = "mii0_1",
3064	.groups = mii0_1_grps,
3065	.ngroups = ARRAY_SIZE(mii0_1_grps),
3066};
3067
3068/* Pad multiplexing for i2c1 device */
3069static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3070static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3071	{
3072		.reg = PMX_CONFIG_REG,
3073		.mask = PMX_SSP_CS_MASK,
3074		.val = 0,
3075	}, {
3076		.reg = IP_SEL_PAD_0_9_REG,
3077		.mask = PMX_PL_8_9_MASK,
3078		.val = PMX_I2C1_PL_8_9_VAL,
3079	}, {
3080		.reg = IP_SEL_MIX_PAD_REG,
3081		.mask = PMX_I2C1_PORT_SEL_MASK,
3082		.val = PMX_I2C1_PORT_8_9_VAL,
3083	},
3084};
3085
3086static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3087	{
3088		.reg = IP_SEL_PAD_90_99_REG,
3089		.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3090		.val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3091	}, {
3092		.reg = IP_SEL_MIX_PAD_REG,
3093		.mask = PMX_I2C1_PORT_SEL_MASK,
3094		.val = PMX_I2C1_PORT_98_99_VAL,
3095	},
3096};
3097
3098static struct spear_modemux i2c1_modemux[][1] = {
3099	{
3100		/* Select signals on pins 8-9 */
3101		{
3102			.modes = EXTENDED_MODE,
3103			.muxregs = i2c1_ext_8_9_muxreg,
3104			.nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3105		},
3106	}, {
3107		/* Select signals on pins 98-99 */
3108		{
3109			.modes = EXTENDED_MODE,
3110			.muxregs = i2c1_ext_98_99_muxreg,
3111			.nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3112		},
3113	},
3114};
3115
3116static struct spear_pingroup i2c1_pingroup[] = {
3117	{
3118		.name = "i2c1_8_9_grp",
3119		.pins = i2c1_pins[0],
3120		.npins = ARRAY_SIZE(i2c1_pins[0]),
3121		.modemuxs = i2c1_modemux[0],
3122		.nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3123	}, {
3124		.name = "i2c1_98_99_grp",
3125		.pins = i2c1_pins[1],
3126		.npins = ARRAY_SIZE(i2c1_pins[1]),
3127		.modemuxs = i2c1_modemux[1],
3128		.nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3129	},
3130};
3131
3132static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3133static struct spear_function i2c1_function = {
3134	.name = "i2c1",
3135	.groups = i2c1_grps,
3136	.ngroups = ARRAY_SIZE(i2c1_grps),
3137};
3138
3139/* Pad multiplexing for i2c2 device */
3140static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3141	{ 75, 76 }, { 96, 97 } };
3142static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3143	{
3144		.reg = PMX_CONFIG_REG,
3145		.mask = PMX_FIRDA_MASK,
3146		.val = 0,
3147	}, {
3148		.reg = IP_SEL_PAD_0_9_REG,
3149		.mask = PMX_PL_0_1_MASK,
3150		.val = PMX_I2C2_PL_0_1_VAL,
3151	}, {
3152		.reg = IP_SEL_MIX_PAD_REG,
3153		.mask = PMX_I2C2_PORT_SEL_MASK,
3154		.val = PMX_I2C2_PORT_0_1_VAL,
3155	},
3156};
3157
3158static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3159	{
3160		.reg = PMX_CONFIG_REG,
3161		.mask = PMX_UART0_MASK,
3162		.val = 0,
3163	}, {
3164		.reg = IP_SEL_PAD_0_9_REG,
3165		.mask = PMX_PL_2_3_MASK,
3166		.val = PMX_I2C2_PL_2_3_VAL,
3167	}, {
3168		.reg = IP_SEL_MIX_PAD_REG,
3169		.mask = PMX_I2C2_PORT_SEL_MASK,
3170		.val = PMX_I2C2_PORT_2_3_VAL,
3171	},
3172};
3173
3174static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3175	{
3176		.reg = PMX_CONFIG_REG,
3177		.mask = PMX_MII_MASK,
3178		.val = 0,
3179	}, {
3180		.reg = IP_SEL_PAD_10_19_REG,
3181		.mask = PMX_PL_19_MASK,
3182		.val = PMX_I2C2_PL_19_VAL,
3183	}, {
3184		.reg = IP_SEL_PAD_20_29_REG,
3185		.mask = PMX_PL_20_MASK,
3186		.val = PMX_I2C2_PL_20_VAL,
3187	}, {
3188		.reg = IP_SEL_MIX_PAD_REG,
3189		.mask = PMX_I2C2_PORT_SEL_MASK,
3190		.val = PMX_I2C2_PORT_19_20_VAL,
3191	},
3192};
3193
3194static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3195	{
3196		.reg = IP_SEL_PAD_70_79_REG,
3197		.mask = PMX_PL_75_76_MASK,
3198		.val = PMX_I2C2_PL_75_76_VAL,
3199	}, {
3200		.reg = IP_SEL_MIX_PAD_REG,
3201		.mask = PMX_I2C2_PORT_SEL_MASK,
3202		.val = PMX_I2C2_PORT_75_76_VAL,
3203	},
3204};
3205
3206static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3207	{
3208		.reg = IP_SEL_PAD_90_99_REG,
3209		.mask = PMX_PL_96_97_MASK,
3210		.val = PMX_I2C2_PL_96_97_VAL,
3211	}, {
3212		.reg = IP_SEL_MIX_PAD_REG,
3213		.mask = PMX_I2C2_PORT_SEL_MASK,
3214		.val = PMX_I2C2_PORT_96_97_VAL,
3215	},
3216};
3217
3218static struct spear_modemux i2c2_modemux[][1] = {
3219	{
3220		/* Select signals on pins 0_1 */
3221		{
3222			.modes = EXTENDED_MODE,
3223			.muxregs = i2c2_ext_0_1_muxreg,
3224			.nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3225		},
3226	}, {
3227		/* Select signals on pins 2_3 */
3228		{
3229			.modes = EXTENDED_MODE,
3230			.muxregs = i2c2_ext_2_3_muxreg,
3231			.nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3232		},
3233	}, {
3234		/* Select signals on pins 19_20 */
3235		{
3236			.modes = EXTENDED_MODE,
3237			.muxregs = i2c2_ext_19_20_muxreg,
3238			.nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3239		},
3240	}, {
3241		/* Select signals on pins 75_76 */
3242		{
3243			.modes = EXTENDED_MODE,
3244			.muxregs = i2c2_ext_75_76_muxreg,
3245			.nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3246		},
3247	}, {
3248		/* Select signals on pins 96_97 */
3249		{
3250			.modes = EXTENDED_MODE,
3251			.muxregs = i2c2_ext_96_97_muxreg,
3252			.nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3253		},
3254	},
3255};
3256
3257static struct spear_pingroup i2c2_pingroup[] = {
3258	{
3259		.name = "i2c2_0_1_grp",
3260		.pins = i2c2_pins[0],
3261		.npins = ARRAY_SIZE(i2c2_pins[0]),
3262		.modemuxs = i2c2_modemux[0],
3263		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3264	}, {
3265		.name = "i2c2_2_3_grp",
3266		.pins = i2c2_pins[1],
3267		.npins = ARRAY_SIZE(i2c2_pins[1]),
3268		.modemuxs = i2c2_modemux[1],
3269		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3270	}, {
3271		.name = "i2c2_19_20_grp",
3272		.pins = i2c2_pins[2],
3273		.npins = ARRAY_SIZE(i2c2_pins[2]),
3274		.modemuxs = i2c2_modemux[2],
3275		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3276	}, {
3277		.name = "i2c2_75_76_grp",
3278		.pins = i2c2_pins[3],
3279		.npins = ARRAY_SIZE(i2c2_pins[3]),
3280		.modemuxs = i2c2_modemux[3],
3281		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3282	}, {
3283		.name = "i2c2_96_97_grp",
3284		.pins = i2c2_pins[4],
3285		.npins = ARRAY_SIZE(i2c2_pins[4]),
3286		.modemuxs = i2c2_modemux[4],
3287		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3288	},
3289};
3290
3291static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3292	"i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3293static struct spear_function i2c2_function = {
3294	.name = "i2c2",
3295	.groups = i2c2_grps,
3296	.ngroups = ARRAY_SIZE(i2c2_grps),
3297};
3298
3299/* pingroups */
3300static struct spear_pingroup *spear320_pingroups[] = {
3301	SPEAR3XX_COMMON_PINGROUPS,
3302	&clcd_pingroup,
3303	&emi_pingroup,
3304	&fsmc_8bit_pingroup,
3305	&fsmc_16bit_pingroup,
3306	&spp_pingroup,
3307	&sdhci_led_pingroup,
3308	&sdhci_pingroup[0],
3309	&sdhci_pingroup[1],
3310	&i2s_pingroup,
3311	&uart1_pingroup,
3312	&uart1_modem_pingroup[0],
3313	&uart1_modem_pingroup[1],
3314	&uart1_modem_pingroup[2],
3315	&uart1_modem_pingroup[3],
3316	&uart2_pingroup,
3317	&uart3_pingroup[0],
3318	&uart3_pingroup[1],
3319	&uart3_pingroup[2],
3320	&uart3_pingroup[3],
3321	&uart3_pingroup[4],
3322	&uart3_pingroup[5],
3323	&uart3_pingroup[6],
3324	&uart4_pingroup[0],
3325	&uart4_pingroup[1],
3326	&uart4_pingroup[2],
3327	&uart4_pingroup[3],
3328	&uart4_pingroup[4],
3329	&uart4_pingroup[5],
3330	&uart5_pingroup[0],
3331	&uart5_pingroup[1],
3332	&uart5_pingroup[2],
3333	&uart5_pingroup[3],
3334	&uart6_pingroup[0],
3335	&uart6_pingroup[1],
3336	&rs485_pingroup,
3337	&touchscreen_pingroup,
3338	&can0_pingroup,
3339	&can1_pingroup,
3340	&pwm0_1_pingroup[0],
3341	&pwm0_1_pingroup[1],
3342	&pwm0_1_pingroup[2],
3343	&pwm0_1_pingroup[3],
3344	&pwm0_1_pingroup[4],
3345	&pwm0_1_pingroup[5],
3346	&pwm0_1_pingroup[6],
3347	&pwm2_pingroup[0],
3348	&pwm2_pingroup[1],
3349	&pwm2_pingroup[2],
3350	&pwm2_pingroup[3],
3351	&pwm2_pingroup[4],
3352	&pwm2_pingroup[5],
3353	&pwm2_pingroup[6],
3354	&pwm3_pingroup[0],
3355	&pwm3_pingroup[1],
3356	&pwm3_pingroup[2],
3357	&pwm3_pingroup[3],
3358	&pwm3_pingroup[4],
3359	&pwm3_pingroup[5],
3360	&ssp1_pingroup[0],
3361	&ssp1_pingroup[1],
3362	&ssp1_pingroup[2],
3363	&ssp1_pingroup[3],
3364	&ssp1_pingroup[4],
3365	&ssp2_pingroup[0],
3366	&ssp2_pingroup[1],
3367	&ssp2_pingroup[2],
3368	&ssp2_pingroup[3],
3369	&ssp2_pingroup[4],
3370	&mii2_pingroup,
3371	&mii0_1_pingroup[0],
3372	&mii0_1_pingroup[1],
3373	&i2c1_pingroup[0],
3374	&i2c1_pingroup[1],
3375	&i2c2_pingroup[0],
3376	&i2c2_pingroup[1],
3377	&i2c2_pingroup[2],
3378	&i2c2_pingroup[3],
3379	&i2c2_pingroup[4],
3380};
3381
3382/* functions */
3383static struct spear_function *spear320_functions[] = {
3384	SPEAR3XX_COMMON_FUNCTIONS,
3385	&clcd_function,
3386	&emi_function,
3387	&fsmc_function,
3388	&spp_function,
3389	&sdhci_function,
3390	&i2s_function,
3391	&uart1_function,
3392	&uart1_modem_function,
3393	&uart2_function,
3394	&uart3_function,
3395	&uart4_function,
3396	&uart5_function,
3397	&uart6_function,
3398	&rs485_function,
3399	&touchscreen_function,
3400	&can0_function,
3401	&can1_function,
3402	&pwm0_1_function,
3403	&pwm2_function,
3404	&pwm3_function,
3405	&ssp1_function,
3406	&ssp2_function,
3407	&mii2_function,
3408	&mii0_1_function,
3409	&i2c1_function,
3410	&i2c2_function,
3411};
3412
3413static const struct of_device_id spear320_pinctrl_of_match[] = {
3414	{
3415		.compatible = "st,spear320-pinmux",
3416	},
3417	{},
3418};
3419
3420static int spear320_pinctrl_probe(struct platform_device *pdev)
3421{
3422	int ret;
3423
3424	spear3xx_machdata.groups = spear320_pingroups;
3425	spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3426	spear3xx_machdata.functions = spear320_functions;
3427	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3428
3429	spear3xx_machdata.modes_supported = true;
3430	spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3431	spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3432
3433	pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3434	pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
3435			spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
3436
3437	ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3438	if (ret)
3439		return ret;
3440
3441	return 0;
3442}
3443
3444static int spear320_pinctrl_remove(struct platform_device *pdev)
3445{
3446	return spear_pinctrl_remove(pdev);
3447}
3448
3449static struct platform_driver spear320_pinctrl_driver = {
3450	.driver = {
3451		.name = DRIVER_NAME,
3452		.owner = THIS_MODULE,
3453		.of_match_table = spear320_pinctrl_of_match,
3454	},
3455	.probe = spear320_pinctrl_probe,
3456	.remove = spear320_pinctrl_remove,
3457};
3458
3459static int __init spear320_pinctrl_init(void)
3460{
3461	return platform_driver_register(&spear320_pinctrl_driver);
3462}
3463arch_initcall(spear320_pinctrl_init);
3464
3465static void __exit spear320_pinctrl_exit(void)
3466{
3467	platform_driver_unregister(&spear320_pinctrl_driver);
3468}
3469module_exit(spear320_pinctrl_exit);
3470
3471MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
3472MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3473MODULE_LICENSE("GPL v2");
3474MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
3475