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1/*
2 *
3 * Includes for cdc-acm.c
4 *
5 * Mainly take from usbnet's cdc-ether part
6 *
7 */
8
9/*
10 * CMSPAR, some architectures can't have space and mark parity.
11 */
12
13#ifndef CMSPAR
14#define CMSPAR			0
15#endif
16
17/*
18 * Major and minor numbers.
19 */
20
21#define ACM_TTY_MAJOR		166
22#define ACM_TTY_MINORS		32
23
24/*
25 * Requests.
26 */
27
28#define USB_RT_ACM		(USB_TYPE_CLASS | USB_RECIP_INTERFACE)
29
30/*
31 * Output control lines.
32 */
33
34#define ACM_CTRL_DTR		0x01
35#define ACM_CTRL_RTS		0x02
36
37/*
38 * Input control lines and line errors.
39 */
40
41#define ACM_CTRL_DCD		0x01
42#define ACM_CTRL_DSR		0x02
43#define ACM_CTRL_BRK		0x04
44#define ACM_CTRL_RI		0x08
45
46#define ACM_CTRL_FRAMING	0x10
47#define ACM_CTRL_PARITY		0x20
48#define ACM_CTRL_OVERRUN	0x40
49
50/*
51 * Internal driver structures.
52 */
53
54/*
55 * The only reason to have several buffers is to accommodate assumptions
56 * in line disciplines. They ask for empty space amount, receive our URB size,
57 * and proceed to issue several 1-character writes, assuming they will fit.
58 * The very first write takes a complete URB. Fortunately, this only happens
59 * when processing onlcr, so we only need 2 buffers. These values must be
60 * powers of 2.
61 */
62#define ACM_NW  16
63#define ACM_NR  16
64
65struct acm_wb {
66	unsigned char *buf;
67	dma_addr_t dmah;
68	int len;
69	int use;
70	struct urb		*urb;
71	struct acm		*instance;
72};
73
74struct acm_rb {
75	int			size;
76	unsigned char		*base;
77	dma_addr_t		dma;
78	int			index;
79	struct acm		*instance;
80};
81
82struct acm {
83	struct usb_device *dev;				/* the corresponding usb device */
84	struct usb_interface *control;			/* control interface */
85	struct usb_interface *data;			/* data interface */
86	struct tty_port port;			 	/* our tty port data */
87	struct urb *ctrlurb;				/* urbs */
88	u8 *ctrl_buffer;				/* buffers of urbs */
89	dma_addr_t ctrl_dma;				/* dma handles of buffers */
90	u8 *country_codes;				/* country codes from device */
91	unsigned int country_code_size;			/* size of this buffer */
92	unsigned int country_rel_date;			/* release date of version */
93	struct acm_wb wb[ACM_NW];
94	unsigned long read_urbs_free;
95	struct urb *read_urbs[ACM_NR];
96	struct acm_rb read_buffers[ACM_NR];
97	int rx_buflimit;
98	int rx_endpoint;
99	spinlock_t read_lock;
100	int write_used;					/* number of non-empty write buffers */
101	int transmitting;
102	spinlock_t write_lock;
103	struct mutex mutex;
104	bool disconnected;
105	struct usb_cdc_line_coding line;		/* bits, stop, parity */
106	struct work_struct work;			/* work queue entry for line discipline waking up */
107	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
108	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
109	struct async_icount iocount;			/* counters for control line changes */
110	struct async_icount oldcount;			/* for comparison of counter */
111	wait_queue_head_t wioctl;			/* for ioctl */
112	unsigned int writesize;				/* max packet size for the output bulk endpoint */
113	unsigned int readsize,ctrlsize;			/* buffer sizes for freeing */
114	unsigned int minor;				/* acm minor number */
115	unsigned char clocal;				/* termios CLOCAL */
116	unsigned int ctrl_caps;				/* control capabilities from the class specific header */
117	unsigned int susp_count;			/* number of suspended interfaces */
118	unsigned int combined_interfaces:1;		/* control and data collapsed */
119	unsigned int is_int_ep:1;			/* interrupt endpoints contrary to spec used */
120	unsigned int throttled:1;			/* actually throttled */
121	unsigned int throttle_req:1;			/* throttle requested */
122	u8 bInterval;
123	struct usb_anchor delayed;			/* writes queued for a device about to be woken */
124	unsigned long quirks;
125};
126
127#define CDC_DATA_INTERFACE_TYPE	0x0a
128
129/* constants describing various quirks and errors */
130#define NO_UNION_NORMAL			BIT(0)
131#define SINGLE_RX_URB			BIT(1)
132#define NO_CAP_LINE			BIT(2)
133#define NOT_A_MODEM			BIT(3)
134#define NO_DATA_INTERFACE		BIT(4)
135#define IGNORE_DEVICE			BIT(5)
136#define QUIRK_CONTROL_LINE_STATE	BIT(6)
137