1/* 2 * Copyright (C) 2008 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * 5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/platform_device.h> 15#include <linux/sched.h> 16#include <linux/errno.h> 17#include <linux/string.h> 18#include <linux/interrupt.h> 19#include <linux/slab.h> 20#include <linux/fb.h> 21#include <linux/delay.h> 22#include <linux/init.h> 23#include <linux/ioport.h> 24#include <linux/dma-mapping.h> 25#include <linux/dmaengine.h> 26#include <linux/console.h> 27#include <linux/clk.h> 28#include <linux/mutex.h> 29#include <linux/dma/ipu-dma.h> 30#include <linux/backlight.h> 31 32#include <linux/platform_data/dma-imx.h> 33#include <linux/platform_data/video-mx3fb.h> 34 35#include <asm/io.h> 36#include <asm/uaccess.h> 37 38#define MX3FB_NAME "mx3_sdc_fb" 39 40#define MX3FB_REG_OFFSET 0xB4 41 42/* SDC Registers */ 43#define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) 44#define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) 45#define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) 46#define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) 47#define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) 48#define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) 49#define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) 50#define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) 51#define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) 52#define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) 53#define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) 54 55/* Register bits */ 56#define SDC_COM_TFT_COLOR 0x00000001UL 57#define SDC_COM_FG_EN 0x00000010UL 58#define SDC_COM_GWSEL 0x00000020UL 59#define SDC_COM_GLB_A 0x00000040UL 60#define SDC_COM_KEY_COLOR_G 0x00000080UL 61#define SDC_COM_BG_EN 0x00000200UL 62#define SDC_COM_SHARP 0x00001000UL 63 64#define SDC_V_SYNC_WIDTH_L 0x00000001UL 65 66/* Display Interface registers */ 67#define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) 68#define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) 69#define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) 70#define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) 71#define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) 72#define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) 73#define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) 74#define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) 75#define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) 76#define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) 77#define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) 78#define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) 79#define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) 80#define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) 81#define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) 82#define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) 83#define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) 84#define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) 85#define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) 86#define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) 87#define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) 88#define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) 89#define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) 90#define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) 91#define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) 92#define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) 93#define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) 94#define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) 95#define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) 96#define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) 97#define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) 98#define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) 99#define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) 100#define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) 101#define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) 102#define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) 103#define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) 104#define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) 105#define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) 106 107/* DI_DISP_SIG_POL bits */ 108#define DI_D3_VSYNC_POL_SHIFT 28 109#define DI_D3_HSYNC_POL_SHIFT 27 110#define DI_D3_DRDY_SHARP_POL_SHIFT 26 111#define DI_D3_CLK_POL_SHIFT 25 112#define DI_D3_DATA_POL_SHIFT 24 113 114/* DI_DISP_IF_CONF bits */ 115#define DI_D3_CLK_IDLE_SHIFT 26 116#define DI_D3_CLK_SEL_SHIFT 25 117#define DI_D3_DATAMSK_SHIFT 24 118 119enum ipu_panel { 120 IPU_PANEL_SHARP_TFT, 121 IPU_PANEL_TFT, 122}; 123 124struct ipu_di_signal_cfg { 125 unsigned datamask_en:1; 126 unsigned clksel_en:1; 127 unsigned clkidle_en:1; 128 unsigned data_pol:1; /* true = inverted */ 129 unsigned clk_pol:1; /* true = rising edge */ 130 unsigned enable_pol:1; 131 unsigned Hsync_pol:1; /* true = active high */ 132 unsigned Vsync_pol:1; 133}; 134 135static const struct fb_videomode mx3fb_modedb[] = { 136 { 137 /* 240x320 @ 60 Hz */ 138 .name = "Sharp-QVGA", 139 .refresh = 60, 140 .xres = 240, 141 .yres = 320, 142 .pixclock = 185925, 143 .left_margin = 9, 144 .right_margin = 16, 145 .upper_margin = 7, 146 .lower_margin = 9, 147 .hsync_len = 1, 148 .vsync_len = 1, 149 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | 150 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | 151 FB_SYNC_CLK_IDLE_EN, 152 .vmode = FB_VMODE_NONINTERLACED, 153 .flag = 0, 154 }, { 155 /* 240x33 @ 60 Hz */ 156 .name = "Sharp-CLI", 157 .refresh = 60, 158 .xres = 240, 159 .yres = 33, 160 .pixclock = 185925, 161 .left_margin = 9, 162 .right_margin = 16, 163 .upper_margin = 7, 164 .lower_margin = 9 + 287, 165 .hsync_len = 1, 166 .vsync_len = 1, 167 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | 168 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | 169 FB_SYNC_CLK_IDLE_EN, 170 .vmode = FB_VMODE_NONINTERLACED, 171 .flag = 0, 172 }, { 173 /* 640x480 @ 60 Hz */ 174 .name = "NEC-VGA", 175 .refresh = 60, 176 .xres = 640, 177 .yres = 480, 178 .pixclock = 38255, 179 .left_margin = 144, 180 .right_margin = 0, 181 .upper_margin = 34, 182 .lower_margin = 40, 183 .hsync_len = 1, 184 .vsync_len = 1, 185 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, 186 .vmode = FB_VMODE_NONINTERLACED, 187 .flag = 0, 188 }, { 189 /* NTSC TV output */ 190 .name = "TV-NTSC", 191 .refresh = 60, 192 .xres = 640, 193 .yres = 480, 194 .pixclock = 37538, 195 .left_margin = 38, 196 .right_margin = 858 - 640 - 38 - 3, 197 .upper_margin = 36, 198 .lower_margin = 518 - 480 - 36 - 1, 199 .hsync_len = 3, 200 .vsync_len = 1, 201 .sync = 0, 202 .vmode = FB_VMODE_NONINTERLACED, 203 .flag = 0, 204 }, { 205 /* PAL TV output */ 206 .name = "TV-PAL", 207 .refresh = 50, 208 .xres = 640, 209 .yres = 480, 210 .pixclock = 37538, 211 .left_margin = 38, 212 .right_margin = 960 - 640 - 38 - 32, 213 .upper_margin = 32, 214 .lower_margin = 555 - 480 - 32 - 3, 215 .hsync_len = 32, 216 .vsync_len = 3, 217 .sync = 0, 218 .vmode = FB_VMODE_NONINTERLACED, 219 .flag = 0, 220 }, { 221 /* TV output VGA mode, 640x480 @ 65 Hz */ 222 .name = "TV-VGA", 223 .refresh = 60, 224 .xres = 640, 225 .yres = 480, 226 .pixclock = 40574, 227 .left_margin = 35, 228 .right_margin = 45, 229 .upper_margin = 9, 230 .lower_margin = 1, 231 .hsync_len = 46, 232 .vsync_len = 5, 233 .sync = 0, 234 .vmode = FB_VMODE_NONINTERLACED, 235 .flag = 0, 236 }, 237}; 238 239struct mx3fb_data { 240 struct fb_info *fbi; 241 int backlight_level; 242 void __iomem *reg_base; 243 spinlock_t lock; 244 struct device *dev; 245 struct backlight_device *bl; 246 247 uint32_t h_start_width; 248 uint32_t v_start_width; 249 enum disp_data_mapping disp_data_fmt; 250}; 251 252struct dma_chan_request { 253 struct mx3fb_data *mx3fb; 254 enum ipu_channel id; 255}; 256 257/* MX3 specific framebuffer information. */ 258struct mx3fb_info { 259 int blank; 260 enum ipu_channel ipu_ch; 261 uint32_t cur_ipu_buf; 262 263 u32 pseudo_palette[16]; 264 265 struct completion flip_cmpl; 266 struct mutex mutex; /* Protects fb-ops */ 267 struct mx3fb_data *mx3fb; 268 struct idmac_channel *idmac_channel; 269 struct dma_async_tx_descriptor *txd; 270 dma_cookie_t cookie; 271 struct scatterlist sg[2]; 272 273 struct fb_var_screeninfo cur_var; /* current var info */ 274}; 275 276static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value); 277static u32 sdc_get_brightness(struct mx3fb_data *mx3fb); 278 279static int mx3fb_bl_get_brightness(struct backlight_device *bl) 280{ 281 struct mx3fb_data *fbd = bl_get_data(bl); 282 283 return sdc_get_brightness(fbd); 284} 285 286static int mx3fb_bl_update_status(struct backlight_device *bl) 287{ 288 struct mx3fb_data *fbd = bl_get_data(bl); 289 int brightness = bl->props.brightness; 290 291 if (bl->props.power != FB_BLANK_UNBLANK) 292 brightness = 0; 293 if (bl->props.fb_blank != FB_BLANK_UNBLANK) 294 brightness = 0; 295 296 fbd->backlight_level = (fbd->backlight_level & ~0xFF) | brightness; 297 298 sdc_set_brightness(fbd, fbd->backlight_level); 299 300 return 0; 301} 302 303static const struct backlight_ops mx3fb_lcdc_bl_ops = { 304 .update_status = mx3fb_bl_update_status, 305 .get_brightness = mx3fb_bl_get_brightness, 306}; 307 308static void mx3fb_init_backlight(struct mx3fb_data *fbd) 309{ 310 struct backlight_properties props; 311 struct backlight_device *bl; 312 313 if (fbd->bl) 314 return; 315 316 memset(&props, 0, sizeof(struct backlight_properties)); 317 props.max_brightness = 0xff; 318 props.type = BACKLIGHT_RAW; 319 sdc_set_brightness(fbd, fbd->backlight_level); 320 321 bl = backlight_device_register("mx3fb-bl", fbd->dev, fbd, 322 &mx3fb_lcdc_bl_ops, &props); 323 if (IS_ERR(bl)) { 324 dev_err(fbd->dev, "error %ld on backlight register\n", 325 PTR_ERR(bl)); 326 return; 327 } 328 329 fbd->bl = bl; 330 bl->props.power = FB_BLANK_UNBLANK; 331 bl->props.fb_blank = FB_BLANK_UNBLANK; 332 bl->props.brightness = mx3fb_bl_get_brightness(bl); 333} 334 335static void mx3fb_exit_backlight(struct mx3fb_data *fbd) 336{ 337 if (fbd->bl) 338 backlight_device_unregister(fbd->bl); 339} 340 341static void mx3fb_dma_done(void *); 342 343/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */ 344static const char *fb_mode; 345static unsigned long default_bpp = 16; 346 347static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) 348{ 349 return __raw_readl(mx3fb->reg_base + reg); 350} 351 352static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) 353{ 354 __raw_writel(value, mx3fb->reg_base + reg); 355} 356 357struct di_mapping { 358 uint32_t b0, b1, b2; 359}; 360 361static const struct di_mapping di_mappings[] = { 362 [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f }, 363 [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f }, 364 [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 }, 365}; 366 367static void sdc_fb_init(struct mx3fb_info *fbi) 368{ 369 struct mx3fb_data *mx3fb = fbi->mx3fb; 370 uint32_t reg; 371 372 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); 373 374 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); 375} 376 377/* Returns enabled flag before uninit */ 378static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) 379{ 380 struct mx3fb_data *mx3fb = fbi->mx3fb; 381 uint32_t reg; 382 383 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); 384 385 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); 386 387 return reg & SDC_COM_BG_EN; 388} 389 390static void sdc_enable_channel(struct mx3fb_info *mx3_fbi) 391{ 392 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 393 struct idmac_channel *ichan = mx3_fbi->idmac_channel; 394 struct dma_chan *dma_chan = &ichan->dma_chan; 395 unsigned long flags; 396 dma_cookie_t cookie; 397 398 if (mx3_fbi->txd) 399 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi, 400 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg); 401 else 402 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi); 403 404 /* This enables the channel */ 405 if (mx3_fbi->cookie < 0) { 406 mx3_fbi->txd = dmaengine_prep_slave_sg(dma_chan, 407 &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 408 if (!mx3_fbi->txd) { 409 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n", 410 dma_chan->chan_id); 411 return; 412 } 413 414 mx3_fbi->txd->callback_param = mx3_fbi->txd; 415 mx3_fbi->txd->callback = mx3fb_dma_done; 416 417 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd); 418 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__, 419 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); 420 } else { 421 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) { 422 dev_err(mx3fb->dev, "Cannot enable channel %d\n", 423 dma_chan->chan_id); 424 return; 425 } 426 427 /* Just re-activate the same buffer */ 428 dma_async_issue_pending(dma_chan); 429 cookie = mx3_fbi->cookie; 430 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__, 431 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); 432 } 433 434 if (cookie >= 0) { 435 spin_lock_irqsave(&mx3fb->lock, flags); 436 sdc_fb_init(mx3_fbi); 437 mx3_fbi->cookie = cookie; 438 spin_unlock_irqrestore(&mx3fb->lock, flags); 439 } 440 441 /* 442 * Attention! Without this msleep the channel keeps generating 443 * interrupts. Next sdc_set_brightness() is going to be called 444 * from mx3fb_blank(). 445 */ 446 msleep(2); 447} 448 449static void sdc_disable_channel(struct mx3fb_info *mx3_fbi) 450{ 451 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 452 uint32_t enabled; 453 unsigned long flags; 454 455 if (mx3_fbi->txd == NULL) 456 return; 457 458 spin_lock_irqsave(&mx3fb->lock, flags); 459 460 enabled = sdc_fb_uninit(mx3_fbi); 461 462 spin_unlock_irqrestore(&mx3fb->lock, flags); 463 464 dmaengine_terminate_all(mx3_fbi->txd->chan); 465 mx3_fbi->txd = NULL; 466 mx3_fbi->cookie = -EINVAL; 467} 468 469/** 470 * sdc_set_window_pos() - set window position of the respective plane. 471 * @mx3fb: mx3fb context. 472 * @channel: IPU DMAC channel ID. 473 * @x_pos: X coordinate relative to the top left corner to place window at. 474 * @y_pos: Y coordinate relative to the top left corner to place window at. 475 * @return: 0 on success or negative error code on failure. 476 */ 477static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel, 478 int16_t x_pos, int16_t y_pos) 479{ 480 if (channel != IDMAC_SDC_0) 481 return -EINVAL; 482 483 x_pos += mx3fb->h_start_width; 484 y_pos += mx3fb->v_start_width; 485 486 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS); 487 return 0; 488} 489 490/** 491 * sdc_init_panel() - initialize a synchronous LCD panel. 492 * @mx3fb: mx3fb context. 493 * @panel: panel type. 494 * @pixel_clk: desired pixel clock frequency in Hz. 495 * @width: width of panel in pixels. 496 * @height: height of panel in pixels. 497 * @h_start_width: number of pixel clocks between the HSYNC signal pulse 498 * and the start of valid data. 499 * @h_sync_width: width of the HSYNC signal in units of pixel clocks. 500 * @h_end_width: number of pixel clocks between the end of valid data 501 * and the HSYNC signal for next line. 502 * @v_start_width: number of lines between the VSYNC signal pulse and the 503 * start of valid data. 504 * @v_sync_width: width of the VSYNC signal in units of lines 505 * @v_end_width: number of lines between the end of valid data and the 506 * VSYNC signal for next frame. 507 * @sig: bitfield of signal polarities for LCD interface. 508 * @return: 0 on success or negative error code on failure. 509 */ 510static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, 511 uint32_t pixel_clk, 512 uint16_t width, uint16_t height, 513 uint16_t h_start_width, uint16_t h_sync_width, 514 uint16_t h_end_width, uint16_t v_start_width, 515 uint16_t v_sync_width, uint16_t v_end_width, 516 struct ipu_di_signal_cfg sig) 517{ 518 unsigned long lock_flags; 519 uint32_t reg; 520 uint32_t old_conf; 521 uint32_t div; 522 struct clk *ipu_clk; 523 const struct di_mapping *map; 524 525 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); 526 527 if (v_sync_width == 0 || h_sync_width == 0) 528 return -EINVAL; 529 530 /* Init panel size and blanking periods */ 531 reg = ((uint32_t) (h_sync_width - 1) << 26) | 532 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); 533 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); 534 535#ifdef DEBUG 536 printk(KERN_CONT " hor_conf %x,", reg); 537#endif 538 539 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | 540 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); 541 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); 542 543#ifdef DEBUG 544 printk(KERN_CONT " ver_conf %x\n", reg); 545#endif 546 547 mx3fb->h_start_width = h_start_width; 548 mx3fb->v_start_width = v_start_width; 549 550 switch (panel) { 551 case IPU_PANEL_SHARP_TFT: 552 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); 553 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); 554 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); 555 break; 556 case IPU_PANEL_TFT: 557 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); 558 break; 559 default: 560 return -EINVAL; 561 } 562 563 /* Init clocking */ 564 565 /* 566 * Calculate divider: fractional part is 4 bits so simply multiple by 567 * 2^4 to get fractional part, as long as we stay under ~250MHz and on 568 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz 569 */ 570 ipu_clk = clk_get(mx3fb->dev, NULL); 571 if (!IS_ERR(ipu_clk)) { 572 div = clk_get_rate(ipu_clk) * 16 / pixel_clk; 573 clk_put(ipu_clk); 574 } else { 575 div = 0; 576 } 577 578 if (div < 0x40) { /* Divider less than 4 */ 579 dev_dbg(mx3fb->dev, 580 "InitPanel() - Pixel clock divider less than 4\n"); 581 div = 0x40; 582 } 583 584 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n", 585 pixel_clk, div >> 4, (div & 7) * 125); 586 587 spin_lock_irqsave(&mx3fb->lock, lock_flags); 588 589 /* 590 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits 591 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing 592 * debug. DISP3_IF_CLK_UP_WR is 0 593 */ 594 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); 595 596 /* DI settings */ 597 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; 598 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | 599 sig.clksel_en << DI_D3_CLK_SEL_SHIFT | 600 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; 601 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); 602 603 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; 604 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | 605 sig.clk_pol << DI_D3_CLK_POL_SHIFT | 606 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | 607 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | 608 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; 609 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); 610 611 map = &di_mappings[mx3fb->disp_data_fmt]; 612 mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP); 613 mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP); 614 mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP); 615 616 spin_unlock_irqrestore(&mx3fb->lock, lock_flags); 617 618 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", 619 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); 620 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", 621 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); 622 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", 623 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); 624 625 return 0; 626} 627 628/** 629 * sdc_set_color_key() - set the transparent color key for SDC graphic plane. 630 * @mx3fb: mx3fb context. 631 * @channel: IPU DMAC channel ID. 632 * @enable: boolean to enable or disable color keyl. 633 * @color_key: 24-bit RGB color to use as transparent color key. 634 * @return: 0 on success or negative error code on failure. 635 */ 636static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel, 637 bool enable, uint32_t color_key) 638{ 639 uint32_t reg, sdc_conf; 640 unsigned long lock_flags; 641 642 spin_lock_irqsave(&mx3fb->lock, lock_flags); 643 644 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF); 645 if (channel == IDMAC_SDC_0) 646 sdc_conf &= ~SDC_COM_GWSEL; 647 else 648 sdc_conf |= SDC_COM_GWSEL; 649 650 if (enable) { 651 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; 652 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), 653 SDC_GW_CTRL); 654 655 sdc_conf |= SDC_COM_KEY_COLOR_G; 656 } else { 657 sdc_conf &= ~SDC_COM_KEY_COLOR_G; 658 } 659 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF); 660 661 spin_unlock_irqrestore(&mx3fb->lock, lock_flags); 662 663 return 0; 664} 665 666/** 667 * sdc_set_global_alpha() - set global alpha blending modes. 668 * @mx3fb: mx3fb context. 669 * @enable: boolean to enable or disable global alpha blending. If disabled, 670 * per pixel blending is used. 671 * @alpha: global alpha value. 672 * @return: 0 on success or negative error code on failure. 673 */ 674static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha) 675{ 676 uint32_t reg; 677 unsigned long lock_flags; 678 679 spin_lock_irqsave(&mx3fb->lock, lock_flags); 680 681 if (enable) { 682 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; 683 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); 684 685 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); 686 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); 687 } else { 688 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); 689 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); 690 } 691 692 spin_unlock_irqrestore(&mx3fb->lock, lock_flags); 693 694 return 0; 695} 696 697static u32 sdc_get_brightness(struct mx3fb_data *mx3fb) 698{ 699 u32 brightness; 700 701 brightness = mx3fb_read_reg(mx3fb, SDC_PWM_CTRL); 702 brightness = (brightness >> 16) & 0xFF; 703 704 return brightness; 705} 706 707static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) 708{ 709 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value); 710 /* This might be board-specific */ 711 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL); 712 return; 713} 714 715static uint32_t bpp_to_pixfmt(int bpp) 716{ 717 uint32_t pixfmt = 0; 718 switch (bpp) { 719 case 24: 720 pixfmt = IPU_PIX_FMT_BGR24; 721 break; 722 case 32: 723 pixfmt = IPU_PIX_FMT_BGR32; 724 break; 725 case 16: 726 pixfmt = IPU_PIX_FMT_RGB565; 727 break; 728 } 729 return pixfmt; 730} 731 732static int mx3fb_blank(int blank, struct fb_info *fbi); 733static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len, 734 bool lock); 735static int mx3fb_unmap_video_memory(struct fb_info *fbi); 736 737/** 738 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings. 739 * @info: framebuffer information pointer 740 * @return: 0 on success or negative error code on failure. 741 */ 742static int mx3fb_set_fix(struct fb_info *fbi) 743{ 744 struct fb_fix_screeninfo *fix = &fbi->fix; 745 struct fb_var_screeninfo *var = &fbi->var; 746 747 strncpy(fix->id, "DISP3 BG", 8); 748 749 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; 750 751 fix->type = FB_TYPE_PACKED_PIXELS; 752 fix->accel = FB_ACCEL_NONE; 753 fix->visual = FB_VISUAL_TRUECOLOR; 754 fix->xpanstep = 1; 755 fix->ypanstep = 1; 756 757 return 0; 758} 759 760static void mx3fb_dma_done(void *arg) 761{ 762 struct idmac_tx_desc *tx_desc = to_tx_desc(arg); 763 struct dma_chan *chan = tx_desc->txd.chan; 764 struct idmac_channel *ichannel = to_idmac_chan(chan); 765 struct mx3fb_data *mx3fb = ichannel->client; 766 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; 767 768 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq); 769 770 /* We only need one interrupt, it will be re-enabled as needed */ 771 disable_irq_nosync(ichannel->eof_irq); 772 773 complete(&mx3_fbi->flip_cmpl); 774} 775 776static bool mx3fb_must_set_par(struct fb_info *fbi) 777{ 778 struct mx3fb_info *mx3_fbi = fbi->par; 779 struct fb_var_screeninfo old_var = mx3_fbi->cur_var; 780 struct fb_var_screeninfo new_var = fbi->var; 781 782 if ((fbi->var.activate & FB_ACTIVATE_FORCE) && 783 (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 784 return true; 785 786 /* 787 * Ignore xoffset and yoffset update, 788 * because pan display handles this case. 789 */ 790 old_var.xoffset = new_var.xoffset; 791 old_var.yoffset = new_var.yoffset; 792 793 return !!memcmp(&old_var, &new_var, sizeof(struct fb_var_screeninfo)); 794} 795 796static int __set_par(struct fb_info *fbi, bool lock) 797{ 798 u32 mem_len, cur_xoffset, cur_yoffset; 799 struct ipu_di_signal_cfg sig_cfg; 800 enum ipu_panel mode = IPU_PANEL_TFT; 801 struct mx3fb_info *mx3_fbi = fbi->par; 802 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 803 struct idmac_channel *ichan = mx3_fbi->idmac_channel; 804 struct idmac_video_param *video = &ichan->params.video; 805 struct scatterlist *sg = mx3_fbi->sg; 806 807 /* Total cleanup */ 808 if (mx3_fbi->txd) 809 sdc_disable_channel(mx3_fbi); 810 811 mx3fb_set_fix(fbi); 812 813 mem_len = fbi->var.yres_virtual * fbi->fix.line_length; 814 if (mem_len > fbi->fix.smem_len) { 815 if (fbi->fix.smem_start) 816 mx3fb_unmap_video_memory(fbi); 817 818 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0) 819 return -ENOMEM; 820 } 821 822 sg_init_table(&sg[0], 1); 823 sg_init_table(&sg[1], 1); 824 825 sg_dma_address(&sg[0]) = fbi->fix.smem_start; 826 sg_set_page(&sg[0], virt_to_page(fbi->screen_base), 827 fbi->fix.smem_len, 828 offset_in_page(fbi->screen_base)); 829 830 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) { 831 memset(&sig_cfg, 0, sizeof(sig_cfg)); 832 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) 833 sig_cfg.Hsync_pol = true; 834 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) 835 sig_cfg.Vsync_pol = true; 836 if (fbi->var.sync & FB_SYNC_CLK_INVERT) 837 sig_cfg.clk_pol = true; 838 if (fbi->var.sync & FB_SYNC_DATA_INVERT) 839 sig_cfg.data_pol = true; 840 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH) 841 sig_cfg.enable_pol = true; 842 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) 843 sig_cfg.clkidle_en = true; 844 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN) 845 sig_cfg.clksel_en = true; 846 if (fbi->var.sync & FB_SYNC_SHARP_MODE) 847 mode = IPU_PANEL_SHARP_TFT; 848 849 dev_dbg(fbi->device, "pixclock = %ul Hz\n", 850 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); 851 852 if (sdc_init_panel(mx3fb, mode, 853 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, 854 fbi->var.xres, fbi->var.yres, 855 fbi->var.left_margin, 856 fbi->var.hsync_len, 857 fbi->var.right_margin + 858 fbi->var.hsync_len, 859 fbi->var.upper_margin, 860 fbi->var.vsync_len, 861 fbi->var.lower_margin + 862 fbi->var.vsync_len, sig_cfg) != 0) { 863 dev_err(fbi->device, 864 "mx3fb: Error initializing panel.\n"); 865 return -EINVAL; 866 } 867 } 868 869 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0); 870 871 mx3_fbi->cur_ipu_buf = 0; 872 873 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel); 874 video->out_width = fbi->var.xres; 875 video->out_height = fbi->var.yres; 876 video->out_stride = fbi->var.xres_virtual; 877 878 if (mx3_fbi->blank == FB_BLANK_UNBLANK) { 879 sdc_enable_channel(mx3_fbi); 880 /* 881 * sg[0] points to fb smem_start address 882 * and is actually active in controller. 883 */ 884 mx3_fbi->cur_var.xoffset = 0; 885 mx3_fbi->cur_var.yoffset = 0; 886 } 887 888 /* 889 * Preserve xoffset and yoffest in case they are 890 * inactive in controller as fb is blanked. 891 */ 892 cur_xoffset = mx3_fbi->cur_var.xoffset; 893 cur_yoffset = mx3_fbi->cur_var.yoffset; 894 mx3_fbi->cur_var = fbi->var; 895 mx3_fbi->cur_var.xoffset = cur_xoffset; 896 mx3_fbi->cur_var.yoffset = cur_yoffset; 897 898 return 0; 899} 900 901/** 902 * mx3fb_set_par() - set framebuffer parameters and change the operating mode. 903 * @fbi: framebuffer information pointer. 904 * @return: 0 on success or negative error code on failure. 905 */ 906static int mx3fb_set_par(struct fb_info *fbi) 907{ 908 struct mx3fb_info *mx3_fbi = fbi->par; 909 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 910 struct idmac_channel *ichan = mx3_fbi->idmac_channel; 911 int ret; 912 913 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+'); 914 915 mutex_lock(&mx3_fbi->mutex); 916 917 ret = mx3fb_must_set_par(fbi) ? __set_par(fbi, true) : 0; 918 919 mutex_unlock(&mx3_fbi->mutex); 920 921 return ret; 922} 923 924/** 925 * mx3fb_check_var() - check and adjust framebuffer variable parameters. 926 * @var: framebuffer variable parameters 927 * @fbi: framebuffer information pointer 928 */ 929static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) 930{ 931 struct mx3fb_info *mx3_fbi = fbi->par; 932 u32 vtotal; 933 u32 htotal; 934 935 dev_dbg(fbi->device, "%s\n", __func__); 936 937 if (var->xres_virtual < var->xres) 938 var->xres_virtual = var->xres; 939 if (var->yres_virtual < var->yres) 940 var->yres_virtual = var->yres; 941 942 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && 943 (var->bits_per_pixel != 16)) 944 var->bits_per_pixel = default_bpp; 945 946 switch (var->bits_per_pixel) { 947 case 16: 948 var->red.length = 5; 949 var->red.offset = 11; 950 var->red.msb_right = 0; 951 952 var->green.length = 6; 953 var->green.offset = 5; 954 var->green.msb_right = 0; 955 956 var->blue.length = 5; 957 var->blue.offset = 0; 958 var->blue.msb_right = 0; 959 960 var->transp.length = 0; 961 var->transp.offset = 0; 962 var->transp.msb_right = 0; 963 break; 964 case 24: 965 var->red.length = 8; 966 var->red.offset = 16; 967 var->red.msb_right = 0; 968 969 var->green.length = 8; 970 var->green.offset = 8; 971 var->green.msb_right = 0; 972 973 var->blue.length = 8; 974 var->blue.offset = 0; 975 var->blue.msb_right = 0; 976 977 var->transp.length = 0; 978 var->transp.offset = 0; 979 var->transp.msb_right = 0; 980 break; 981 case 32: 982 var->red.length = 8; 983 var->red.offset = 16; 984 var->red.msb_right = 0; 985 986 var->green.length = 8; 987 var->green.offset = 8; 988 var->green.msb_right = 0; 989 990 var->blue.length = 8; 991 var->blue.offset = 0; 992 var->blue.msb_right = 0; 993 994 var->transp.length = 8; 995 var->transp.offset = 24; 996 var->transp.msb_right = 0; 997 break; 998 } 999 1000 if (var->pixclock < 1000) { 1001 htotal = var->xres + var->right_margin + var->hsync_len + 1002 var->left_margin; 1003 vtotal = var->yres + var->lower_margin + var->vsync_len + 1004 var->upper_margin; 1005 var->pixclock = (vtotal * htotal * 6UL) / 100UL; 1006 var->pixclock = KHZ2PICOS(var->pixclock); 1007 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n", 1008 var->pixclock); 1009 } 1010 1011 var->height = -1; 1012 var->width = -1; 1013 var->grayscale = 0; 1014 1015 /* Preserve sync flags */ 1016 var->sync |= mx3_fbi->cur_var.sync; 1017 mx3_fbi->cur_var.sync |= var->sync; 1018 1019 return 0; 1020} 1021 1022static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf) 1023{ 1024 chan &= 0xffff; 1025 chan >>= 16 - bf->length; 1026 return chan << bf->offset; 1027} 1028 1029static int mx3fb_setcolreg(unsigned int regno, unsigned int red, 1030 unsigned int green, unsigned int blue, 1031 unsigned int trans, struct fb_info *fbi) 1032{ 1033 struct mx3fb_info *mx3_fbi = fbi->par; 1034 u32 val; 1035 int ret = 1; 1036 1037 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno); 1038 1039 mutex_lock(&mx3_fbi->mutex); 1040 /* 1041 * If greyscale is true, then we convert the RGB value 1042 * to greyscale no matter what visual we are using. 1043 */ 1044 if (fbi->var.grayscale) 1045 red = green = blue = (19595 * red + 38470 * green + 1046 7471 * blue) >> 16; 1047 switch (fbi->fix.visual) { 1048 case FB_VISUAL_TRUECOLOR: 1049 /* 1050 * 16-bit True Colour. We encode the RGB value 1051 * according to the RGB bitfield information. 1052 */ 1053 if (regno < 16) { 1054 u32 *pal = fbi->pseudo_palette; 1055 1056 val = chan_to_field(red, &fbi->var.red); 1057 val |= chan_to_field(green, &fbi->var.green); 1058 val |= chan_to_field(blue, &fbi->var.blue); 1059 1060 pal[regno] = val; 1061 1062 ret = 0; 1063 } 1064 break; 1065 1066 case FB_VISUAL_STATIC_PSEUDOCOLOR: 1067 case FB_VISUAL_PSEUDOCOLOR: 1068 break; 1069 } 1070 mutex_unlock(&mx3_fbi->mutex); 1071 1072 return ret; 1073} 1074 1075static void __blank(int blank, struct fb_info *fbi) 1076{ 1077 struct mx3fb_info *mx3_fbi = fbi->par; 1078 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 1079 int was_blank = mx3_fbi->blank; 1080 1081 mx3_fbi->blank = blank; 1082 1083 /* Attention! 1084 * Do not call sdc_disable_channel() for a channel that is disabled 1085 * already! This will result in a kernel NULL pointer dereference 1086 * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are 1087 * handled equally by this driver. 1088 */ 1089 if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK) 1090 return; 1091 1092 switch (blank) { 1093 case FB_BLANK_POWERDOWN: 1094 case FB_BLANK_VSYNC_SUSPEND: 1095 case FB_BLANK_HSYNC_SUSPEND: 1096 case FB_BLANK_NORMAL: 1097 sdc_set_brightness(mx3fb, 0); 1098 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); 1099 /* Give LCD time to update - enough for 50 and 60 Hz */ 1100 msleep(25); 1101 sdc_disable_channel(mx3_fbi); 1102 break; 1103 case FB_BLANK_UNBLANK: 1104 sdc_enable_channel(mx3_fbi); 1105 sdc_set_brightness(mx3fb, mx3fb->backlight_level); 1106 break; 1107 } 1108} 1109 1110/** 1111 * mx3fb_blank() - blank the display. 1112 */ 1113static int mx3fb_blank(int blank, struct fb_info *fbi) 1114{ 1115 struct mx3fb_info *mx3_fbi = fbi->par; 1116 1117 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__, 1118 blank, fbi->screen_base, fbi->fix.smem_len); 1119 1120 if (mx3_fbi->blank == blank) 1121 return 0; 1122 1123 mutex_lock(&mx3_fbi->mutex); 1124 __blank(blank, fbi); 1125 mutex_unlock(&mx3_fbi->mutex); 1126 1127 return 0; 1128} 1129 1130/** 1131 * mx3fb_pan_display() - pan or wrap the display 1132 * @var: variable screen buffer information. 1133 * @info: framebuffer information pointer. 1134 * 1135 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1136 */ 1137static int mx3fb_pan_display(struct fb_var_screeninfo *var, 1138 struct fb_info *fbi) 1139{ 1140 struct mx3fb_info *mx3_fbi = fbi->par; 1141 u32 y_bottom; 1142 unsigned long base; 1143 off_t offset; 1144 dma_cookie_t cookie; 1145 struct scatterlist *sg = mx3_fbi->sg; 1146 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan; 1147 struct dma_async_tx_descriptor *txd; 1148 int ret; 1149 1150 dev_dbg(fbi->device, "%s [%c]\n", __func__, 1151 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+'); 1152 1153 if (var->xoffset > 0) { 1154 dev_dbg(fbi->device, "x panning not supported\n"); 1155 return -EINVAL; 1156 } 1157 1158 if (mx3_fbi->cur_var.xoffset == var->xoffset && 1159 mx3_fbi->cur_var.yoffset == var->yoffset) 1160 return 0; /* No change, do nothing */ 1161 1162 y_bottom = var->yoffset; 1163 1164 if (!(var->vmode & FB_VMODE_YWRAP)) 1165 y_bottom += fbi->var.yres; 1166 1167 if (y_bottom > fbi->var.yres_virtual) 1168 return -EINVAL; 1169 1170 mutex_lock(&mx3_fbi->mutex); 1171 1172 offset = var->yoffset * fbi->fix.line_length 1173 + var->xoffset * (fbi->var.bits_per_pixel / 8); 1174 base = fbi->fix.smem_start + offset; 1175 1176 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n", 1177 mx3_fbi->cur_ipu_buf, base); 1178 1179 /* 1180 * We enable the End of Frame interrupt, which will free a tx-descriptor, 1181 * which we will need for the next dmaengine_prep_slave_sg(). The 1182 * IRQ-handler will disable the IRQ again. 1183 */ 1184 init_completion(&mx3_fbi->flip_cmpl); 1185 enable_irq(mx3_fbi->idmac_channel->eof_irq); 1186 1187 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10); 1188 if (ret <= 0) { 1189 mutex_unlock(&mx3_fbi->mutex); 1190 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ? 1191 "user interrupt" : "timeout"); 1192 disable_irq(mx3_fbi->idmac_channel->eof_irq); 1193 return ret ? : -ETIMEDOUT; 1194 } 1195 1196 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf; 1197 1198 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; 1199 sg_set_page(&sg[mx3_fbi->cur_ipu_buf], 1200 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len, 1201 offset_in_page(fbi->screen_base + offset)); 1202 1203 if (mx3_fbi->txd) 1204 async_tx_ack(mx3_fbi->txd); 1205 1206 txd = dmaengine_prep_slave_sg(dma_chan, sg + 1207 mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 1208 if (!txd) { 1209 dev_err(fbi->device, 1210 "Error preparing a DMA transaction descriptor.\n"); 1211 mutex_unlock(&mx3_fbi->mutex); 1212 return -EIO; 1213 } 1214 1215 txd->callback_param = txd; 1216 txd->callback = mx3fb_dma_done; 1217 1218 /* 1219 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit() 1220 * should switch to another buffer 1221 */ 1222 cookie = txd->tx_submit(txd); 1223 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie); 1224 if (cookie < 0) { 1225 dev_err(fbi->device, 1226 "Error updating SDC buf %d to address=0x%08lX\n", 1227 mx3_fbi->cur_ipu_buf, base); 1228 mutex_unlock(&mx3_fbi->mutex); 1229 return -EIO; 1230 } 1231 1232 mx3_fbi->txd = txd; 1233 1234 fbi->var.xoffset = var->xoffset; 1235 fbi->var.yoffset = var->yoffset; 1236 1237 if (var->vmode & FB_VMODE_YWRAP) 1238 fbi->var.vmode |= FB_VMODE_YWRAP; 1239 else 1240 fbi->var.vmode &= ~FB_VMODE_YWRAP; 1241 1242 mx3_fbi->cur_var = fbi->var; 1243 1244 mutex_unlock(&mx3_fbi->mutex); 1245 1246 dev_dbg(fbi->device, "Update complete\n"); 1247 1248 return 0; 1249} 1250 1251/* 1252 * This structure contains the pointers to the control functions that are 1253 * invoked by the core framebuffer driver to perform operations like 1254 * blitting, rectangle filling, copy regions and cursor definition. 1255 */ 1256static struct fb_ops mx3fb_ops = { 1257 .owner = THIS_MODULE, 1258 .fb_set_par = mx3fb_set_par, 1259 .fb_check_var = mx3fb_check_var, 1260 .fb_setcolreg = mx3fb_setcolreg, 1261 .fb_pan_display = mx3fb_pan_display, 1262 .fb_fillrect = cfb_fillrect, 1263 .fb_copyarea = cfb_copyarea, 1264 .fb_imageblit = cfb_imageblit, 1265 .fb_blank = mx3fb_blank, 1266}; 1267 1268#ifdef CONFIG_PM 1269/* 1270 * Power management hooks. Note that we won't be called from IRQ context, 1271 * unlike the blank functions above, so we may sleep. 1272 */ 1273 1274/* 1275 * Suspends the framebuffer and blanks the screen. Power management support 1276 */ 1277static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) 1278{ 1279 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev); 1280 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; 1281 1282 console_lock(); 1283 fb_set_suspend(mx3fb->fbi, 1); 1284 console_unlock(); 1285 1286 if (mx3_fbi->blank == FB_BLANK_UNBLANK) { 1287 sdc_disable_channel(mx3_fbi); 1288 sdc_set_brightness(mx3fb, 0); 1289 1290 } 1291 return 0; 1292} 1293 1294/* 1295 * Resumes the framebuffer and unblanks the screen. Power management support 1296 */ 1297static int mx3fb_resume(struct platform_device *pdev) 1298{ 1299 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev); 1300 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; 1301 1302 if (mx3_fbi->blank == FB_BLANK_UNBLANK) { 1303 sdc_enable_channel(mx3_fbi); 1304 sdc_set_brightness(mx3fb, mx3fb->backlight_level); 1305 } 1306 1307 console_lock(); 1308 fb_set_suspend(mx3fb->fbi, 0); 1309 console_unlock(); 1310 1311 return 0; 1312} 1313#else 1314#define mx3fb_suspend NULL 1315#define mx3fb_resume NULL 1316#endif 1317 1318/* 1319 * Main framebuffer functions 1320 */ 1321 1322/** 1323 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. 1324 * @fbi: framebuffer information pointer 1325 * @mem_len: length of mapped memory 1326 * @lock: do not lock during initialisation 1327 * @return: Error code indicating success or failure 1328 * 1329 * This buffer is remapped into a non-cached, non-buffered, memory region to 1330 * allow palette and pixel writes to occur without flushing the cache. Once this 1331 * area is remapped, all virtual memory access to the video memory should occur 1332 * at the new region. 1333 */ 1334static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len, 1335 bool lock) 1336{ 1337 int retval = 0; 1338 dma_addr_t addr; 1339 1340 fbi->screen_base = dma_alloc_writecombine(fbi->device, 1341 mem_len, 1342 &addr, GFP_DMA | GFP_KERNEL); 1343 1344 if (!fbi->screen_base) { 1345 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", 1346 mem_len); 1347 retval = -EBUSY; 1348 goto err0; 1349 } 1350 1351 if (lock) 1352 mutex_lock(&fbi->mm_lock); 1353 fbi->fix.smem_start = addr; 1354 fbi->fix.smem_len = mem_len; 1355 if (lock) 1356 mutex_unlock(&fbi->mm_lock); 1357 1358 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", 1359 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); 1360 1361 fbi->screen_size = fbi->fix.smem_len; 1362 1363 /* Clear the screen */ 1364 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); 1365 1366 return 0; 1367 1368err0: 1369 fbi->fix.smem_len = 0; 1370 fbi->fix.smem_start = 0; 1371 fbi->screen_base = NULL; 1372 return retval; 1373} 1374 1375/** 1376 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory. 1377 * @fbi: framebuffer information pointer 1378 * @return: error code indicating success or failure 1379 */ 1380static int mx3fb_unmap_video_memory(struct fb_info *fbi) 1381{ 1382 dma_free_writecombine(fbi->device, fbi->fix.smem_len, 1383 fbi->screen_base, fbi->fix.smem_start); 1384 1385 fbi->screen_base = NULL; 1386 mutex_lock(&fbi->mm_lock); 1387 fbi->fix.smem_start = 0; 1388 fbi->fix.smem_len = 0; 1389 mutex_unlock(&fbi->mm_lock); 1390 return 0; 1391} 1392 1393/** 1394 * mx3fb_init_fbinfo() - initialize framebuffer information object. 1395 * @return: initialized framebuffer structure. 1396 */ 1397static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) 1398{ 1399 struct fb_info *fbi; 1400 struct mx3fb_info *mx3fbi; 1401 int ret; 1402 1403 /* Allocate sufficient memory for the fb structure */ 1404 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev); 1405 if (!fbi) 1406 return NULL; 1407 1408 mx3fbi = fbi->par; 1409 mx3fbi->cookie = -EINVAL; 1410 mx3fbi->cur_ipu_buf = 0; 1411 1412 fbi->var.activate = FB_ACTIVATE_NOW; 1413 1414 fbi->fbops = ops; 1415 fbi->flags = FBINFO_FLAG_DEFAULT; 1416 fbi->pseudo_palette = mx3fbi->pseudo_palette; 1417 1418 mutex_init(&mx3fbi->mutex); 1419 1420 /* Allocate colormap */ 1421 ret = fb_alloc_cmap(&fbi->cmap, 16, 0); 1422 if (ret < 0) { 1423 framebuffer_release(fbi); 1424 return NULL; 1425 } 1426 1427 return fbi; 1428} 1429 1430static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) 1431{ 1432 struct device *dev = mx3fb->dev; 1433 struct mx3fb_platform_data *mx3fb_pdata = dev_get_platdata(dev); 1434 const char *name = mx3fb_pdata->name; 1435 unsigned int irq; 1436 struct fb_info *fbi; 1437 struct mx3fb_info *mx3fbi; 1438 const struct fb_videomode *mode; 1439 int ret, num_modes; 1440 1441 if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) { 1442 dev_err(dev, "Illegal display data format %d\n", 1443 mx3fb_pdata->disp_data_fmt); 1444 return -EINVAL; 1445 } 1446 1447 ichan->client = mx3fb; 1448 irq = ichan->eof_irq; 1449 1450 if (ichan->dma_chan.chan_id != IDMAC_SDC_0) 1451 return -EINVAL; 1452 1453 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops); 1454 if (!fbi) 1455 return -ENOMEM; 1456 1457 if (!fb_mode) 1458 fb_mode = name; 1459 1460 if (!fb_mode) { 1461 ret = -EINVAL; 1462 goto emode; 1463 } 1464 1465 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) { 1466 mode = mx3fb_pdata->mode; 1467 num_modes = mx3fb_pdata->num_modes; 1468 } else { 1469 mode = mx3fb_modedb; 1470 num_modes = ARRAY_SIZE(mx3fb_modedb); 1471 } 1472 1473 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode, 1474 num_modes, NULL, default_bpp)) { 1475 ret = -EBUSY; 1476 goto emode; 1477 } 1478 1479 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist); 1480 1481 /* Default Y virtual size is 2x panel size */ 1482 fbi->var.yres_virtual = fbi->var.yres * 2; 1483 1484 mx3fb->fbi = fbi; 1485 1486 /* set Display Interface clock period */ 1487 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER); 1488 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ 1489 1490 sdc_set_brightness(mx3fb, 255); 1491 sdc_set_global_alpha(mx3fb, true, 0xFF); 1492 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0); 1493 1494 mx3fbi = fbi->par; 1495 mx3fbi->idmac_channel = ichan; 1496 mx3fbi->ipu_ch = ichan->dma_chan.chan_id; 1497 mx3fbi->mx3fb = mx3fb; 1498 mx3fbi->blank = FB_BLANK_NORMAL; 1499 1500 mx3fb->disp_data_fmt = mx3fb_pdata->disp_data_fmt; 1501 1502 init_completion(&mx3fbi->flip_cmpl); 1503 disable_irq(ichan->eof_irq); 1504 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); 1505 ret = __set_par(fbi, false); 1506 if (ret < 0) 1507 goto esetpar; 1508 1509 __blank(FB_BLANK_UNBLANK, fbi); 1510 1511 dev_info(dev, "registered, using mode %s\n", fb_mode); 1512 1513 ret = register_framebuffer(fbi); 1514 if (ret < 0) 1515 goto erfb; 1516 1517 return 0; 1518 1519erfb: 1520esetpar: 1521emode: 1522 fb_dealloc_cmap(&fbi->cmap); 1523 framebuffer_release(fbi); 1524 1525 return ret; 1526} 1527 1528static bool chan_filter(struct dma_chan *chan, void *arg) 1529{ 1530 struct dma_chan_request *rq = arg; 1531 struct device *dev; 1532 struct mx3fb_platform_data *mx3fb_pdata; 1533 1534 if (!imx_dma_is_ipu(chan)) 1535 return false; 1536 1537 if (!rq) 1538 return false; 1539 1540 dev = rq->mx3fb->dev; 1541 mx3fb_pdata = dev_get_platdata(dev); 1542 1543 return rq->id == chan->chan_id && 1544 mx3fb_pdata->dma_dev == chan->device->dev; 1545} 1546 1547static void release_fbi(struct fb_info *fbi) 1548{ 1549 mx3fb_unmap_video_memory(fbi); 1550 1551 fb_dealloc_cmap(&fbi->cmap); 1552 1553 unregister_framebuffer(fbi); 1554 framebuffer_release(fbi); 1555} 1556 1557static int mx3fb_probe(struct platform_device *pdev) 1558{ 1559 struct device *dev = &pdev->dev; 1560 int ret; 1561 struct resource *sdc_reg; 1562 struct mx3fb_data *mx3fb; 1563 dma_cap_mask_t mask; 1564 struct dma_chan *chan; 1565 struct dma_chan_request rq; 1566 1567 /* 1568 * Display Interface (DI) and Synchronous Display Controller (SDC) 1569 * registers 1570 */ 1571 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1572 if (!sdc_reg) 1573 return -EINVAL; 1574 1575 mx3fb = devm_kzalloc(&pdev->dev, sizeof(*mx3fb), GFP_KERNEL); 1576 if (!mx3fb) 1577 return -ENOMEM; 1578 1579 spin_lock_init(&mx3fb->lock); 1580 1581 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); 1582 if (!mx3fb->reg_base) { 1583 ret = -ENOMEM; 1584 goto eremap; 1585 } 1586 1587 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base); 1588 1589 /* IDMAC interface */ 1590 dmaengine_get(); 1591 1592 mx3fb->dev = dev; 1593 platform_set_drvdata(pdev, mx3fb); 1594 1595 rq.mx3fb = mx3fb; 1596 1597 dma_cap_zero(mask); 1598 dma_cap_set(DMA_SLAVE, mask); 1599 dma_cap_set(DMA_PRIVATE, mask); 1600 rq.id = IDMAC_SDC_0; 1601 chan = dma_request_channel(mask, chan_filter, &rq); 1602 if (!chan) { 1603 ret = -EBUSY; 1604 goto ersdc0; 1605 } 1606 1607 mx3fb->backlight_level = 255; 1608 1609 ret = init_fb_chan(mx3fb, to_idmac_chan(chan)); 1610 if (ret < 0) 1611 goto eisdc0; 1612 1613 mx3fb_init_backlight(mx3fb); 1614 1615 return 0; 1616 1617eisdc0: 1618 dma_release_channel(chan); 1619ersdc0: 1620 dmaengine_put(); 1621 iounmap(mx3fb->reg_base); 1622eremap: 1623 dev_err(dev, "mx3fb: failed to register fb\n"); 1624 return ret; 1625} 1626 1627static int mx3fb_remove(struct platform_device *dev) 1628{ 1629 struct mx3fb_data *mx3fb = platform_get_drvdata(dev); 1630 struct fb_info *fbi = mx3fb->fbi; 1631 struct mx3fb_info *mx3_fbi = fbi->par; 1632 struct dma_chan *chan; 1633 1634 chan = &mx3_fbi->idmac_channel->dma_chan; 1635 release_fbi(fbi); 1636 1637 mx3fb_exit_backlight(mx3fb); 1638 1639 dma_release_channel(chan); 1640 dmaengine_put(); 1641 1642 iounmap(mx3fb->reg_base); 1643 return 0; 1644} 1645 1646static struct platform_driver mx3fb_driver = { 1647 .driver = { 1648 .name = MX3FB_NAME, 1649 .owner = THIS_MODULE, 1650 }, 1651 .probe = mx3fb_probe, 1652 .remove = mx3fb_remove, 1653 .suspend = mx3fb_suspend, 1654 .resume = mx3fb_resume, 1655}; 1656 1657/* 1658 * Parse user specified options (`video=mx3fb:') 1659 * example: 1660 * video=mx3fb:bpp=16 1661 */ 1662static int __init mx3fb_setup(void) 1663{ 1664#ifndef MODULE 1665 char *opt, *options = NULL; 1666 1667 if (fb_get_options("mx3fb", &options)) 1668 return -ENODEV; 1669 1670 if (!options || !*options) 1671 return 0; 1672 1673 while ((opt = strsep(&options, ",")) != NULL) { 1674 if (!*opt) 1675 continue; 1676 if (!strncmp(opt, "bpp=", 4)) 1677 default_bpp = simple_strtoul(opt + 4, NULL, 0); 1678 else 1679 fb_mode = opt; 1680 } 1681#endif 1682 1683 return 0; 1684} 1685 1686static int __init mx3fb_init(void) 1687{ 1688 int ret = mx3fb_setup(); 1689 1690 if (ret < 0) 1691 return ret; 1692 1693 ret = platform_driver_register(&mx3fb_driver); 1694 return ret; 1695} 1696 1697static void __exit mx3fb_exit(void) 1698{ 1699 platform_driver_unregister(&mx3fb_driver); 1700} 1701 1702module_init(mx3fb_init); 1703module_exit(mx3fb_exit); 1704 1705MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1706MODULE_DESCRIPTION("MX3 framebuffer driver"); 1707MODULE_ALIAS("platform:" MX3FB_NAME); 1708MODULE_LICENSE("GPL v2"); 1709