1/* 2 * linux/drivers/video/sa1100fb.c 3 * 4 * Copyright (C) 1999 Eric A. Thomas 5 * Based on acornfb.c Copyright (C) Russell King. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 * 11 * StrongARM 1100 LCD Controller Frame Buffer Driver 12 * 13 * Please direct your questions and comments on this driver to the following 14 * email address: 15 * 16 * linux-arm-kernel@lists.arm.linux.org.uk 17 * 18 * Clean patches should be sent to the ARM Linux Patch System. Please see the 19 * following web page for more information: 20 * 21 * http://www.arm.linux.org.uk/developer/patches/info.shtml 22 * 23 * Thank you. 24 * 25 * Known problems: 26 * - With the Neponset plugged into an Assabet, LCD powerdown 27 * doesn't work (LCD stays powered up). Therefore we shouldn't 28 * blank the screen. 29 * - We don't limit the CPU clock rate nor the mode selection 30 * according to the available SDRAM bandwidth. 31 * 32 * Other notes: 33 * - Linear grayscale palettes and the kernel. 34 * Such code does not belong in the kernel. The kernel frame buffer 35 * drivers do not expect a linear colourmap, but a colourmap based on 36 * the VT100 standard mapping. 37 * 38 * If your _userspace_ requires a linear colourmap, then the setup of 39 * such a colourmap belongs _in userspace_, not in the kernel. Code 40 * to set the colourmap correctly from user space has been sent to 41 * David Neuer. It's around 8 lines of C code, plus another 4 to 42 * detect if we are using grayscale. 43 * 44 * - The following must never be specified in a panel definition: 45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL 46 * 47 * - The following should be specified: 48 * either LCCR0_Color or LCCR0_Mono 49 * either LCCR0_Sngl or LCCR0_Dual 50 * either LCCR0_Act or LCCR0_Pas 51 * either LCCR3_OutEnH or LCCD3_OutEnL 52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg 53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff 54 * 55 * Code Status: 56 * 1999/04/01: 57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other 58 * resolutions are working, but only the 8bpp mode is supported. 59 * Changes need to be made to the palette encode and decode routines 60 * to support 4 and 16 bpp modes. 61 * Driver is not designed to be a module. The FrameBuffer is statically 62 * allocated since dynamic allocation of a 300k buffer cannot be 63 * guaranteed. 64 * 65 * 1999/06/17: 66 * - FrameBuffer memory is now allocated at run-time when the 67 * driver is initialized. 68 * 69 * 2000/04/10: Nicolas Pitre <nico@fluxnic.net> 70 * - Big cleanup for dynamic selection of machine type at run time. 71 * 72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com> 73 * - Support for Bitsy aka Compaq iPAQ H3600 added. 74 * 75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com> 76 * Jeff Sutherland <jsutherland@accelent.com> 77 * - Resolved an issue caused by a change made to the Assabet's PLD 78 * earlier this year which broke the framebuffer driver for newer 79 * Phase 4 Assabets. Some other parameters were changed to optimize 80 * for the Sharp display. 81 * 82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp> 83 * - XP860 support added 84 * 85 * 2000/08/19: Mark Huang <mhuang@livetoy.com> 86 * - Allows standard options to be passed on the kernel command line 87 * for most common passive displays. 88 * 89 * 2000/08/29: 90 * - s/save_flags_cli/local_irq_save/ 91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller 92 * 93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl> 94 * - Updated LART stuff. Fixed some minor bugs. 95 * 96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw> 97 * - Pangolin support added 98 * 99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de> 100 * - Huw Webpanel support added 101 * 102 * 2000/11/23: Eric Peng <ericpeng@coventive.com> 103 * - Freebird add 104 * 105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com> 106 * Cliff Brake <cbrake@accelent.com> 107 * - Added PM callback 108 * 109 * 2001/05/26: <rmk@arm.linux.org.uk> 110 * - Fix 16bpp so that (a) we use the right colours rather than some 111 * totally random colour depending on what was in page 0, and (b) 112 * we don't de-reference a NULL pointer. 113 * - remove duplicated implementation of consistent_alloc() 114 * - convert dma address types to dma_addr_t 115 * - remove unused 'montype' stuff 116 * - remove redundant zero inits of init_var after the initial 117 * memset. 118 * - remove allow_modeset (acornfb idea does not belong here) 119 * 120 * 2001/05/28: <rmk@arm.linux.org.uk> 121 * - massive cleanup - move machine dependent data into structures 122 * - I've left various #warnings in - if you see one, and know 123 * the hardware concerned, please get in contact with me. 124 * 125 * 2001/05/31: <rmk@arm.linux.org.uk> 126 * - Fix LCCR1 HSW value, fix all machine type specifications to 127 * keep values in line. (Please check your machine type specs) 128 * 129 * 2001/06/10: <rmk@arm.linux.org.uk> 130 * - Fiddle with the LCD controller from task context only; mainly 131 * so that we can run with interrupts on, and sleep. 132 * - Convert #warnings into #errors. No pain, no gain. ;) 133 * 134 * 2001/06/14: <rmk@arm.linux.org.uk> 135 * - Make the palette BPS value for 12bpp come out correctly. 136 * - Take notice of "greyscale" on any colour depth. 137 * - Make truecolor visuals use the RGB channel encoding information. 138 * 139 * 2001/07/02: <rmk@arm.linux.org.uk> 140 * - Fix colourmap problems. 141 * 142 * 2001/07/13: <abraham@2d3d.co.za> 143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is 144 * manufactured by Prime View, model no V16C6448AB 145 * 146 * 2001/07/23: <rmk@arm.linux.org.uk> 147 * - Hand merge version from handhelds.org CVS tree. See patch 148 * notes for 595/1 for more information. 149 * - Drop 12bpp (it's 16bpp with different colour register mappings). 150 * - This hardware can not do direct colour. Therefore we don't 151 * support it. 152 * 153 * 2001/07/27: <rmk@arm.linux.org.uk> 154 * - Halve YRES on dual scan LCDs. 155 * 156 * 2001/08/22: <rmk@arm.linux.org.uk> 157 * - Add b/w iPAQ pixclock value. 158 * 159 * 2001/10/12: <rmk@arm.linux.org.uk> 160 * - Add patch 681/1 and clean up stork definitions. 161 */ 162 163#include <linux/module.h> 164#include <linux/kernel.h> 165#include <linux/sched.h> 166#include <linux/errno.h> 167#include <linux/string.h> 168#include <linux/interrupt.h> 169#include <linux/slab.h> 170#include <linux/mm.h> 171#include <linux/fb.h> 172#include <linux/delay.h> 173#include <linux/init.h> 174#include <linux/ioport.h> 175#include <linux/cpufreq.h> 176#include <linux/gpio.h> 177#include <linux/platform_device.h> 178#include <linux/dma-mapping.h> 179#include <linux/mutex.h> 180#include <linux/io.h> 181 182#include <video/sa1100fb.h> 183 184#include <mach/hardware.h> 185#include <asm/mach-types.h> 186#include <mach/shannon.h> 187 188/* 189 * Complain if VAR is out of range. 190 */ 191#define DEBUG_VAR 1 192 193#include "sa1100fb.h" 194 195static const struct sa1100fb_rgb rgb_4 = { 196 .red = { .offset = 0, .length = 4, }, 197 .green = { .offset = 0, .length = 4, }, 198 .blue = { .offset = 0, .length = 4, }, 199 .transp = { .offset = 0, .length = 0, }, 200}; 201 202static const struct sa1100fb_rgb rgb_8 = { 203 .red = { .offset = 0, .length = 8, }, 204 .green = { .offset = 0, .length = 8, }, 205 .blue = { .offset = 0, .length = 8, }, 206 .transp = { .offset = 0, .length = 0, }, 207}; 208 209static const struct sa1100fb_rgb def_rgb_16 = { 210 .red = { .offset = 11, .length = 5, }, 211 .green = { .offset = 5, .length = 6, }, 212 .blue = { .offset = 0, .length = 5, }, 213 .transp = { .offset = 0, .length = 0, }, 214}; 215 216 217 218static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *); 219static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state); 220 221static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state) 222{ 223 unsigned long flags; 224 225 local_irq_save(flags); 226 /* 227 * We need to handle two requests being made at the same time. 228 * There are two important cases: 229 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE) 230 * We must perform the unblanking, which will do our REENABLE for us. 231 * 2. When we are blanking, but immediately unblank before we have 232 * blanked. We do the "REENABLE" thing here as well, just to be sure. 233 */ 234 if (fbi->task_state == C_ENABLE && state == C_REENABLE) 235 state = (u_int) -1; 236 if (fbi->task_state == C_DISABLE && state == C_ENABLE) 237 state = C_REENABLE; 238 239 if (state != (u_int)-1) { 240 fbi->task_state = state; 241 schedule_work(&fbi->task); 242 } 243 local_irq_restore(flags); 244} 245 246static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 247{ 248 chan &= 0xffff; 249 chan >>= 16 - bf->length; 250 return chan << bf->offset; 251} 252 253/* 254 * Convert bits-per-pixel to a hardware palette PBS value. 255 */ 256static inline u_int palette_pbs(struct fb_var_screeninfo *var) 257{ 258 int ret = 0; 259 switch (var->bits_per_pixel) { 260 case 4: ret = 0 << 12; break; 261 case 8: ret = 1 << 12; break; 262 case 16: ret = 2 << 12; break; 263 } 264 return ret; 265} 266 267static int 268sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 269 u_int trans, struct fb_info *info) 270{ 271 struct sa1100fb_info *fbi = 272 container_of(info, struct sa1100fb_info, fb); 273 u_int val, ret = 1; 274 275 if (regno < fbi->palette_size) { 276 val = ((red >> 4) & 0xf00); 277 val |= ((green >> 8) & 0x0f0); 278 val |= ((blue >> 12) & 0x00f); 279 280 if (regno == 0) 281 val |= palette_pbs(&fbi->fb.var); 282 283 fbi->palette_cpu[regno] = val; 284 ret = 0; 285 } 286 return ret; 287} 288 289static int 290sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 291 u_int trans, struct fb_info *info) 292{ 293 struct sa1100fb_info *fbi = 294 container_of(info, struct sa1100fb_info, fb); 295 unsigned int val; 296 int ret = 1; 297 298 /* 299 * If inverse mode was selected, invert all the colours 300 * rather than the register number. The register number 301 * is what you poke into the framebuffer to produce the 302 * colour you requested. 303 */ 304 if (fbi->inf->cmap_inverse) { 305 red = 0xffff - red; 306 green = 0xffff - green; 307 blue = 0xffff - blue; 308 } 309 310 /* 311 * If greyscale is true, then we convert the RGB value 312 * to greyscale no mater what visual we are using. 313 */ 314 if (fbi->fb.var.grayscale) 315 red = green = blue = (19595 * red + 38470 * green + 316 7471 * blue) >> 16; 317 318 switch (fbi->fb.fix.visual) { 319 case FB_VISUAL_TRUECOLOR: 320 /* 321 * 12 or 16-bit True Colour. We encode the RGB value 322 * according to the RGB bitfield information. 323 */ 324 if (regno < 16) { 325 u32 *pal = fbi->fb.pseudo_palette; 326 327 val = chan_to_field(red, &fbi->fb.var.red); 328 val |= chan_to_field(green, &fbi->fb.var.green); 329 val |= chan_to_field(blue, &fbi->fb.var.blue); 330 331 pal[regno] = val; 332 ret = 0; 333 } 334 break; 335 336 case FB_VISUAL_STATIC_PSEUDOCOLOR: 337 case FB_VISUAL_PSEUDOCOLOR: 338 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info); 339 break; 340 } 341 342 return ret; 343} 344 345#ifdef CONFIG_CPU_FREQ 346/* 347 * sa1100fb_display_dma_period() 348 * Calculate the minimum period (in picoseconds) between two DMA 349 * requests for the LCD controller. If we hit this, it means we're 350 * doing nothing but LCD DMA. 351 */ 352static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var) 353{ 354 /* 355 * Period = pixclock * bits_per_byte * bytes_per_transfer 356 * / memory_bits_per_pixel; 357 */ 358 return var->pixclock * 8 * 16 / var->bits_per_pixel; 359} 360#endif 361 362/* 363 * sa1100fb_check_var(): 364 * Round up in the following order: bits_per_pixel, xres, 365 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 366 * bitfields, horizontal timing, vertical timing. 367 */ 368static int 369sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 370{ 371 struct sa1100fb_info *fbi = 372 container_of(info, struct sa1100fb_info, fb); 373 int rgbidx; 374 375 if (var->xres < MIN_XRES) 376 var->xres = MIN_XRES; 377 if (var->yres < MIN_YRES) 378 var->yres = MIN_YRES; 379 if (var->xres > fbi->inf->xres) 380 var->xres = fbi->inf->xres; 381 if (var->yres > fbi->inf->yres) 382 var->yres = fbi->inf->yres; 383 var->xres_virtual = max(var->xres_virtual, var->xres); 384 var->yres_virtual = max(var->yres_virtual, var->yres); 385 386 dev_dbg(fbi->dev, "var->bits_per_pixel=%d\n", var->bits_per_pixel); 387 switch (var->bits_per_pixel) { 388 case 4: 389 rgbidx = RGB_4; 390 break; 391 case 8: 392 rgbidx = RGB_8; 393 break; 394 case 16: 395 rgbidx = RGB_16; 396 break; 397 default: 398 return -EINVAL; 399 } 400 401 /* 402 * Copy the RGB parameters for this display 403 * from the machine specific parameters. 404 */ 405 var->red = fbi->rgb[rgbidx]->red; 406 var->green = fbi->rgb[rgbidx]->green; 407 var->blue = fbi->rgb[rgbidx]->blue; 408 var->transp = fbi->rgb[rgbidx]->transp; 409 410 dev_dbg(fbi->dev, "RGBT length = %d:%d:%d:%d\n", 411 var->red.length, var->green.length, var->blue.length, 412 var->transp.length); 413 414 dev_dbg(fbi->dev, "RGBT offset = %d:%d:%d:%d\n", 415 var->red.offset, var->green.offset, var->blue.offset, 416 var->transp.offset); 417 418#ifdef CONFIG_CPU_FREQ 419 dev_dbg(fbi->dev, "dma period = %d ps, clock = %d kHz\n", 420 sa1100fb_display_dma_period(var), 421 cpufreq_get(smp_processor_id())); 422#endif 423 424 return 0; 425} 426 427static void sa1100fb_set_visual(struct sa1100fb_info *fbi, u32 visual) 428{ 429 if (fbi->inf->set_visual) 430 fbi->inf->set_visual(visual); 431} 432 433/* 434 * sa1100fb_set_par(): 435 * Set the user defined part of the display for the specified console 436 */ 437static int sa1100fb_set_par(struct fb_info *info) 438{ 439 struct sa1100fb_info *fbi = 440 container_of(info, struct sa1100fb_info, fb); 441 struct fb_var_screeninfo *var = &info->var; 442 unsigned long palette_mem_size; 443 444 dev_dbg(fbi->dev, "set_par\n"); 445 446 if (var->bits_per_pixel == 16) 447 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; 448 else if (!fbi->inf->cmap_static) 449 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 450 else { 451 /* 452 * Some people have weird ideas about wanting static 453 * pseudocolor maps. I suspect their user space 454 * applications are broken. 455 */ 456 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 457 } 458 459 fbi->fb.fix.line_length = var->xres_virtual * 460 var->bits_per_pixel / 8; 461 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 462 463 palette_mem_size = fbi->palette_size * sizeof(u16); 464 465 dev_dbg(fbi->dev, "palette_mem_size = 0x%08lx\n", palette_mem_size); 466 467 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); 468 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; 469 470 /* 471 * Set (any) board control register to handle new color depth 472 */ 473 sa1100fb_set_visual(fbi, fbi->fb.fix.visual); 474 sa1100fb_activate_var(var, fbi); 475 476 return 0; 477} 478 479#if 0 480static int 481sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con, 482 struct fb_info *info) 483{ 484 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info; 485 486 /* 487 * Make sure the user isn't doing something stupid. 488 */ 489 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->inf->cmap_static)) 490 return -EINVAL; 491 492 return gen_set_cmap(cmap, kspc, con, info); 493} 494#endif 495 496/* 497 * Formal definition of the VESA spec: 498 * On 499 * This refers to the state of the display when it is in full operation 500 * Stand-By 501 * This defines an optional operating state of minimal power reduction with 502 * the shortest recovery time 503 * Suspend 504 * This refers to a level of power management in which substantial power 505 * reduction is achieved by the display. The display can have a longer 506 * recovery time from this state than from the Stand-by state 507 * Off 508 * This indicates that the display is consuming the lowest level of power 509 * and is non-operational. Recovery from this state may optionally require 510 * the user to manually power on the monitor 511 * 512 * Now, the fbdev driver adds an additional state, (blank), where they 513 * turn off the video (maybe by colormap tricks), but don't mess with the 514 * video itself: think of it semantically between on and Stand-By. 515 * 516 * So here's what we should do in our fbdev blank routine: 517 * 518 * VESA_NO_BLANKING (mode 0) Video on, front/back light on 519 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off 520 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off 521 * VESA_POWERDOWN (mode 3) Video off, front/back light off 522 * 523 * This will match the matrox implementation. 524 */ 525/* 526 * sa1100fb_blank(): 527 * Blank the display by setting all palette values to zero. Note, the 528 * 12 and 16 bpp modes don't really use the palette, so this will not 529 * blank the display in all modes. 530 */ 531static int sa1100fb_blank(int blank, struct fb_info *info) 532{ 533 struct sa1100fb_info *fbi = 534 container_of(info, struct sa1100fb_info, fb); 535 int i; 536 537 dev_dbg(fbi->dev, "sa1100fb_blank: blank=%d\n", blank); 538 539 switch (blank) { 540 case FB_BLANK_POWERDOWN: 541 case FB_BLANK_VSYNC_SUSPEND: 542 case FB_BLANK_HSYNC_SUSPEND: 543 case FB_BLANK_NORMAL: 544 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 545 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 546 for (i = 0; i < fbi->palette_size; i++) 547 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info); 548 sa1100fb_schedule_work(fbi, C_DISABLE); 549 break; 550 551 case FB_BLANK_UNBLANK: 552 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 553 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 554 fb_set_cmap(&fbi->fb.cmap, info); 555 sa1100fb_schedule_work(fbi, C_ENABLE); 556 } 557 return 0; 558} 559 560static int sa1100fb_mmap(struct fb_info *info, 561 struct vm_area_struct *vma) 562{ 563 struct sa1100fb_info *fbi = 564 container_of(info, struct sa1100fb_info, fb); 565 unsigned long off = vma->vm_pgoff << PAGE_SHIFT; 566 567 if (off < info->fix.smem_len) { 568 vma->vm_pgoff += 1; /* skip over the palette */ 569 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, 570 fbi->map_dma, fbi->map_size); 571 } 572 573 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 574 575 return vm_iomap_memory(vma, info->fix.mmio_start, info->fix.mmio_len); 576} 577 578static struct fb_ops sa1100fb_ops = { 579 .owner = THIS_MODULE, 580 .fb_check_var = sa1100fb_check_var, 581 .fb_set_par = sa1100fb_set_par, 582// .fb_set_cmap = sa1100fb_set_cmap, 583 .fb_setcolreg = sa1100fb_setcolreg, 584 .fb_fillrect = cfb_fillrect, 585 .fb_copyarea = cfb_copyarea, 586 .fb_imageblit = cfb_imageblit, 587 .fb_blank = sa1100fb_blank, 588 .fb_mmap = sa1100fb_mmap, 589}; 590 591/* 592 * Calculate the PCD value from the clock rate (in picoseconds). 593 * We take account of the PPCR clock setting. 594 */ 595static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock) 596{ 597 unsigned int pcd = cpuclock / 100; 598 599 pcd *= pixclock; 600 pcd /= 10000000; 601 602 return pcd + 1; /* make up for integer math truncations */ 603} 604 605/* 606 * sa1100fb_activate_var(): 607 * Configures LCD Controller based on entries in var parameter. Settings are 608 * only written to the controller if changes were made. 609 */ 610static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi) 611{ 612 struct sa1100fb_lcd_reg new_regs; 613 u_int half_screen_size, yres, pcd; 614 u_long flags; 615 616 dev_dbg(fbi->dev, "Configuring SA1100 LCD\n"); 617 618 dev_dbg(fbi->dev, "var: xres=%d hslen=%d lm=%d rm=%d\n", 619 var->xres, var->hsync_len, 620 var->left_margin, var->right_margin); 621 dev_dbg(fbi->dev, "var: yres=%d vslen=%d um=%d bm=%d\n", 622 var->yres, var->vsync_len, 623 var->upper_margin, var->lower_margin); 624 625#if DEBUG_VAR 626 if (var->xres < 16 || var->xres > 1024) 627 dev_err(fbi->dev, "%s: invalid xres %d\n", 628 fbi->fb.fix.id, var->xres); 629 if (var->hsync_len < 1 || var->hsync_len > 64) 630 dev_err(fbi->dev, "%s: invalid hsync_len %d\n", 631 fbi->fb.fix.id, var->hsync_len); 632 if (var->left_margin < 1 || var->left_margin > 255) 633 dev_err(fbi->dev, "%s: invalid left_margin %d\n", 634 fbi->fb.fix.id, var->left_margin); 635 if (var->right_margin < 1 || var->right_margin > 255) 636 dev_err(fbi->dev, "%s: invalid right_margin %d\n", 637 fbi->fb.fix.id, var->right_margin); 638 if (var->yres < 1 || var->yres > 1024) 639 dev_err(fbi->dev, "%s: invalid yres %d\n", 640 fbi->fb.fix.id, var->yres); 641 if (var->vsync_len < 1 || var->vsync_len > 64) 642 dev_err(fbi->dev, "%s: invalid vsync_len %d\n", 643 fbi->fb.fix.id, var->vsync_len); 644 if (var->upper_margin < 0 || var->upper_margin > 255) 645 dev_err(fbi->dev, "%s: invalid upper_margin %d\n", 646 fbi->fb.fix.id, var->upper_margin); 647 if (var->lower_margin < 0 || var->lower_margin > 255) 648 dev_err(fbi->dev, "%s: invalid lower_margin %d\n", 649 fbi->fb.fix.id, var->lower_margin); 650#endif 651 652 new_regs.lccr0 = fbi->inf->lccr0 | 653 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM | 654 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0); 655 656 new_regs.lccr1 = 657 LCCR1_DisWdth(var->xres) + 658 LCCR1_HorSnchWdth(var->hsync_len) + 659 LCCR1_BegLnDel(var->left_margin) + 660 LCCR1_EndLnDel(var->right_margin); 661 662 /* 663 * If we have a dual scan LCD, then we need to halve 664 * the YRES parameter. 665 */ 666 yres = var->yres; 667 if (fbi->inf->lccr0 & LCCR0_Dual) 668 yres /= 2; 669 670 new_regs.lccr2 = 671 LCCR2_DisHght(yres) + 672 LCCR2_VrtSnchWdth(var->vsync_len) + 673 LCCR2_BegFrmDel(var->upper_margin) + 674 LCCR2_EndFrmDel(var->lower_margin); 675 676 pcd = get_pcd(var->pixclock, cpufreq_get(0)); 677 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->inf->lccr3 | 678 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) | 679 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL); 680 681 dev_dbg(fbi->dev, "nlccr0 = 0x%08lx\n", new_regs.lccr0); 682 dev_dbg(fbi->dev, "nlccr1 = 0x%08lx\n", new_regs.lccr1); 683 dev_dbg(fbi->dev, "nlccr2 = 0x%08lx\n", new_regs.lccr2); 684 dev_dbg(fbi->dev, "nlccr3 = 0x%08lx\n", new_regs.lccr3); 685 686 half_screen_size = var->bits_per_pixel; 687 half_screen_size = half_screen_size * var->xres * var->yres / 16; 688 689 /* Update shadow copy atomically */ 690 local_irq_save(flags); 691 fbi->dbar1 = fbi->palette_dma; 692 fbi->dbar2 = fbi->screen_dma + half_screen_size; 693 694 fbi->reg_lccr0 = new_regs.lccr0; 695 fbi->reg_lccr1 = new_regs.lccr1; 696 fbi->reg_lccr2 = new_regs.lccr2; 697 fbi->reg_lccr3 = new_regs.lccr3; 698 local_irq_restore(flags); 699 700 /* 701 * Only update the registers if the controller is enabled 702 * and something has changed. 703 */ 704 if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 || 705 readl_relaxed(fbi->base + LCCR1) != fbi->reg_lccr1 || 706 readl_relaxed(fbi->base + LCCR2) != fbi->reg_lccr2 || 707 readl_relaxed(fbi->base + LCCR3) != fbi->reg_lccr3 || 708 readl_relaxed(fbi->base + DBAR1) != fbi->dbar1 || 709 readl_relaxed(fbi->base + DBAR2) != fbi->dbar2) 710 sa1100fb_schedule_work(fbi, C_REENABLE); 711 712 return 0; 713} 714 715/* 716 * NOTE! The following functions are purely helpers for set_ctrlr_state. 717 * Do not call them directly; set_ctrlr_state does the correct serialisation 718 * to ensure that things happen in the right way 100% of time time. 719 * -- rmk 720 */ 721static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on) 722{ 723 dev_dbg(fbi->dev, "backlight o%s\n", on ? "n" : "ff"); 724 725 if (fbi->inf->backlight_power) 726 fbi->inf->backlight_power(on); 727} 728 729static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on) 730{ 731 dev_dbg(fbi->dev, "LCD power o%s\n", on ? "n" : "ff"); 732 733 if (fbi->inf->lcd_power) 734 fbi->inf->lcd_power(on); 735} 736 737static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi) 738{ 739 u_int mask = 0; 740 741 /* 742 * Enable GPIO<9:2> for LCD use if: 743 * 1. Active display, or 744 * 2. Color Dual Passive display 745 * 746 * see table 11.8 on page 11-27 in the SA1100 manual 747 * -- Erik. 748 * 749 * SA1110 spec update nr. 25 says we can and should 750 * clear LDD15 to 12 for 4 or 8bpp modes with active 751 * panels. 752 */ 753 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color && 754 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) { 755 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; 756 757 if (fbi->fb.var.bits_per_pixel > 8 || 758 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual) 759 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12; 760 761 } 762 763 if (mask) { 764 unsigned long flags; 765 766 /* 767 * SA-1100 requires the GPIO direction register set 768 * appropriately for the alternate function. Hence 769 * we set it here via bitmask rather than excessive 770 * fiddling via the GPIO subsystem - and even then 771 * we'll still have to deal with GAFR. 772 */ 773 local_irq_save(flags); 774 GPDR |= mask; 775 GAFR |= mask; 776 local_irq_restore(flags); 777 } 778} 779 780static void sa1100fb_enable_controller(struct sa1100fb_info *fbi) 781{ 782 dev_dbg(fbi->dev, "Enabling LCD controller\n"); 783 784 /* 785 * Make sure the mode bits are present in the first palette entry 786 */ 787 fbi->palette_cpu[0] &= 0xcfff; 788 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var); 789 790 /* Sequence from 11.7.10 */ 791 writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3); 792 writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2); 793 writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1); 794 writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0); 795 writel_relaxed(fbi->dbar1, fbi->base + DBAR1); 796 writel_relaxed(fbi->dbar2, fbi->base + DBAR2); 797 writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0); 798 799 if (machine_is_shannon()) 800 gpio_set_value(SHANNON_GPIO_DISP_EN, 1); 801 802 dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1)); 803 dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2)); 804 dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0)); 805 dev_dbg(fbi->dev, "LCCR1: 0x%08x\n", readl_relaxed(fbi->base + LCCR1)); 806 dev_dbg(fbi->dev, "LCCR2: 0x%08x\n", readl_relaxed(fbi->base + LCCR2)); 807 dev_dbg(fbi->dev, "LCCR3: 0x%08x\n", readl_relaxed(fbi->base + LCCR3)); 808} 809 810static void sa1100fb_disable_controller(struct sa1100fb_info *fbi) 811{ 812 DECLARE_WAITQUEUE(wait, current); 813 u32 lccr0; 814 815 dev_dbg(fbi->dev, "Disabling LCD controller\n"); 816 817 if (machine_is_shannon()) 818 gpio_set_value(SHANNON_GPIO_DISP_EN, 0); 819 820 set_current_state(TASK_UNINTERRUPTIBLE); 821 add_wait_queue(&fbi->ctrlr_wait, &wait); 822 823 /* Clear LCD Status Register */ 824 writel_relaxed(~0, fbi->base + LCSR); 825 826 lccr0 = readl_relaxed(fbi->base + LCCR0); 827 lccr0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ 828 writel_relaxed(lccr0, fbi->base + LCCR0); 829 lccr0 &= ~LCCR0_LEN; /* Disable LCD Controller */ 830 writel_relaxed(lccr0, fbi->base + LCCR0); 831 832 schedule_timeout(20 * HZ / 1000); 833 remove_wait_queue(&fbi->ctrlr_wait, &wait); 834} 835 836/* 837 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts. 838 */ 839static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id) 840{ 841 struct sa1100fb_info *fbi = dev_id; 842 unsigned int lcsr = readl_relaxed(fbi->base + LCSR); 843 844 if (lcsr & LCSR_LDD) { 845 u32 lccr0 = readl_relaxed(fbi->base + LCCR0) | LCCR0_LDM; 846 writel_relaxed(lccr0, fbi->base + LCCR0); 847 wake_up(&fbi->ctrlr_wait); 848 } 849 850 writel_relaxed(lcsr, fbi->base + LCSR); 851 return IRQ_HANDLED; 852} 853 854/* 855 * This function must be called from task context only, since it will 856 * sleep when disabling the LCD controller, or if we get two contending 857 * processes trying to alter state. 858 */ 859static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state) 860{ 861 u_int old_state; 862 863 mutex_lock(&fbi->ctrlr_lock); 864 865 old_state = fbi->state; 866 867 /* 868 * Hack around fbcon initialisation. 869 */ 870 if (old_state == C_STARTUP && state == C_REENABLE) 871 state = C_ENABLE; 872 873 switch (state) { 874 case C_DISABLE_CLKCHANGE: 875 /* 876 * Disable controller for clock change. If the 877 * controller is already disabled, then do nothing. 878 */ 879 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { 880 fbi->state = state; 881 sa1100fb_disable_controller(fbi); 882 } 883 break; 884 885 case C_DISABLE_PM: 886 case C_DISABLE: 887 /* 888 * Disable controller 889 */ 890 if (old_state != C_DISABLE) { 891 fbi->state = state; 892 893 __sa1100fb_backlight_power(fbi, 0); 894 if (old_state != C_DISABLE_CLKCHANGE) 895 sa1100fb_disable_controller(fbi); 896 __sa1100fb_lcd_power(fbi, 0); 897 } 898 break; 899 900 case C_ENABLE_CLKCHANGE: 901 /* 902 * Enable the controller after clock change. Only 903 * do this if we were disabled for the clock change. 904 */ 905 if (old_state == C_DISABLE_CLKCHANGE) { 906 fbi->state = C_ENABLE; 907 sa1100fb_enable_controller(fbi); 908 } 909 break; 910 911 case C_REENABLE: 912 /* 913 * Re-enable the controller only if it was already 914 * enabled. This is so we reprogram the control 915 * registers. 916 */ 917 if (old_state == C_ENABLE) { 918 sa1100fb_disable_controller(fbi); 919 sa1100fb_setup_gpio(fbi); 920 sa1100fb_enable_controller(fbi); 921 } 922 break; 923 924 case C_ENABLE_PM: 925 /* 926 * Re-enable the controller after PM. This is not 927 * perfect - think about the case where we were doing 928 * a clock change, and we suspended half-way through. 929 */ 930 if (old_state != C_DISABLE_PM) 931 break; 932 /* fall through */ 933 934 case C_ENABLE: 935 /* 936 * Power up the LCD screen, enable controller, and 937 * turn on the backlight. 938 */ 939 if (old_state != C_ENABLE) { 940 fbi->state = C_ENABLE; 941 sa1100fb_setup_gpio(fbi); 942 __sa1100fb_lcd_power(fbi, 1); 943 sa1100fb_enable_controller(fbi); 944 __sa1100fb_backlight_power(fbi, 1); 945 } 946 break; 947 } 948 mutex_unlock(&fbi->ctrlr_lock); 949} 950 951/* 952 * Our LCD controller task (which is called when we blank or unblank) 953 * via keventd. 954 */ 955static void sa1100fb_task(struct work_struct *w) 956{ 957 struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task); 958 u_int state = xchg(&fbi->task_state, -1); 959 960 set_ctrlr_state(fbi, state); 961} 962 963#ifdef CONFIG_CPU_FREQ 964/* 965 * Calculate the minimum DMA period over all displays that we own. 966 * This, together with the SDRAM bandwidth defines the slowest CPU 967 * frequency that can be selected. 968 */ 969static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi) 970{ 971#if 0 972 unsigned int min_period = (unsigned int)-1; 973 int i; 974 975 for (i = 0; i < MAX_NR_CONSOLES; i++) { 976 struct display *disp = &fb_display[i]; 977 unsigned int period; 978 979 /* 980 * Do we own this display? 981 */ 982 if (disp->fb_info != &fbi->fb) 983 continue; 984 985 /* 986 * Ok, calculate its DMA period 987 */ 988 period = sa1100fb_display_dma_period(&disp->var); 989 if (period < min_period) 990 min_period = period; 991 } 992 993 return min_period; 994#else 995 /* 996 * FIXME: we need to verify _all_ consoles. 997 */ 998 return sa1100fb_display_dma_period(&fbi->fb.var); 999#endif 1000} 1001 1002/* 1003 * CPU clock speed change handler. We need to adjust the LCD timing 1004 * parameters when the CPU clock is adjusted by the power management 1005 * subsystem. 1006 */ 1007static int 1008sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val, 1009 void *data) 1010{ 1011 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition); 1012 struct cpufreq_freqs *f = data; 1013 u_int pcd; 1014 1015 switch (val) { 1016 case CPUFREQ_PRECHANGE: 1017 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); 1018 break; 1019 1020 case CPUFREQ_POSTCHANGE: 1021 pcd = get_pcd(fbi->fb.var.pixclock, f->new); 1022 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); 1023 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 1024 break; 1025 } 1026 return 0; 1027} 1028 1029static int 1030sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val, 1031 void *data) 1032{ 1033 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy); 1034 struct cpufreq_policy *policy = data; 1035 1036 switch (val) { 1037 case CPUFREQ_ADJUST: 1038 case CPUFREQ_INCOMPATIBLE: 1039 dev_dbg(fbi->dev, "min dma period: %d ps, " 1040 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi), 1041 policy->max); 1042 /* todo: fill in min/max values */ 1043 break; 1044 case CPUFREQ_NOTIFY: 1045 do {} while(0); 1046 /* todo: panic if min/max values aren't fulfilled 1047 * [can't really happen unless there's a bug in the 1048 * CPU policy verififcation process * 1049 */ 1050 break; 1051 } 1052 return 0; 1053} 1054#endif 1055 1056#ifdef CONFIG_PM 1057/* 1058 * Power management hooks. Note that we won't be called from IRQ context, 1059 * unlike the blank functions above, so we may sleep. 1060 */ 1061static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state) 1062{ 1063 struct sa1100fb_info *fbi = platform_get_drvdata(dev); 1064 1065 set_ctrlr_state(fbi, C_DISABLE_PM); 1066 return 0; 1067} 1068 1069static int sa1100fb_resume(struct platform_device *dev) 1070{ 1071 struct sa1100fb_info *fbi = platform_get_drvdata(dev); 1072 1073 set_ctrlr_state(fbi, C_ENABLE_PM); 1074 return 0; 1075} 1076#else 1077#define sa1100fb_suspend NULL 1078#define sa1100fb_resume NULL 1079#endif 1080 1081/* 1082 * sa1100fb_map_video_memory(): 1083 * Allocates the DRAM memory for the frame buffer. This buffer is 1084 * remapped into a non-cached, non-buffered, memory region to 1085 * allow palette and pixel writes to occur without flushing the 1086 * cache. Once this area is remapped, all virtual memory 1087 * access to the video memory should occur at the new region. 1088 */ 1089static int sa1100fb_map_video_memory(struct sa1100fb_info *fbi) 1090{ 1091 /* 1092 * We reserve one page for the palette, plus the size 1093 * of the framebuffer. 1094 */ 1095 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); 1096 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, 1097 &fbi->map_dma, GFP_KERNEL); 1098 1099 if (fbi->map_cpu) { 1100 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; 1101 fbi->screen_dma = fbi->map_dma + PAGE_SIZE; 1102 /* 1103 * FIXME: this is actually the wrong thing to place in 1104 * smem_start. But fbdev suffers from the problem that 1105 * it needs an API which doesn't exist (in this case, 1106 * dma_writecombine_mmap) 1107 */ 1108 fbi->fb.fix.smem_start = fbi->screen_dma; 1109 } 1110 1111 return fbi->map_cpu ? 0 : -ENOMEM; 1112} 1113 1114/* Fake monspecs to fill in fbinfo structure */ 1115static struct fb_monspecs monspecs = { 1116 .hfmin = 30000, 1117 .hfmax = 70000, 1118 .vfmin = 50, 1119 .vfmax = 65, 1120}; 1121 1122 1123static struct sa1100fb_info *sa1100fb_init_fbinfo(struct device *dev) 1124{ 1125 struct sa1100fb_mach_info *inf = dev_get_platdata(dev); 1126 struct sa1100fb_info *fbi; 1127 unsigned i; 1128 1129 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16, 1130 GFP_KERNEL); 1131 if (!fbi) 1132 return NULL; 1133 1134 memset(fbi, 0, sizeof(struct sa1100fb_info)); 1135 fbi->dev = dev; 1136 1137 strcpy(fbi->fb.fix.id, SA1100_NAME); 1138 1139 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1140 fbi->fb.fix.type_aux = 0; 1141 fbi->fb.fix.xpanstep = 0; 1142 fbi->fb.fix.ypanstep = 0; 1143 fbi->fb.fix.ywrapstep = 0; 1144 fbi->fb.fix.accel = FB_ACCEL_NONE; 1145 1146 fbi->fb.var.nonstd = 0; 1147 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1148 fbi->fb.var.height = -1; 1149 fbi->fb.var.width = -1; 1150 fbi->fb.var.accel_flags = 0; 1151 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1152 1153 fbi->fb.fbops = &sa1100fb_ops; 1154 fbi->fb.flags = FBINFO_DEFAULT; 1155 fbi->fb.monspecs = monspecs; 1156 fbi->fb.pseudo_palette = (fbi + 1); 1157 1158 fbi->rgb[RGB_4] = &rgb_4; 1159 fbi->rgb[RGB_8] = &rgb_8; 1160 fbi->rgb[RGB_16] = &def_rgb_16; 1161 1162 /* 1163 * People just don't seem to get this. We don't support 1164 * anything but correct entries now, so panic if someone 1165 * does something stupid. 1166 */ 1167 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) || 1168 inf->pixclock == 0) 1169 panic("sa1100fb error: invalid LCCR3 fields set or zero " 1170 "pixclock."); 1171 1172 fbi->fb.var.xres = inf->xres; 1173 fbi->fb.var.xres_virtual = inf->xres; 1174 fbi->fb.var.yres = inf->yres; 1175 fbi->fb.var.yres_virtual = inf->yres; 1176 fbi->fb.var.bits_per_pixel = inf->bpp; 1177 fbi->fb.var.pixclock = inf->pixclock; 1178 fbi->fb.var.hsync_len = inf->hsync_len; 1179 fbi->fb.var.left_margin = inf->left_margin; 1180 fbi->fb.var.right_margin = inf->right_margin; 1181 fbi->fb.var.vsync_len = inf->vsync_len; 1182 fbi->fb.var.upper_margin = inf->upper_margin; 1183 fbi->fb.var.lower_margin = inf->lower_margin; 1184 fbi->fb.var.sync = inf->sync; 1185 fbi->fb.var.grayscale = inf->cmap_greyscale; 1186 fbi->state = C_STARTUP; 1187 fbi->task_state = (u_char)-1; 1188 fbi->fb.fix.smem_len = inf->xres * inf->yres * 1189 inf->bpp / 8; 1190 fbi->inf = inf; 1191 1192 /* Copy the RGB bitfield overrides */ 1193 for (i = 0; i < NR_RGB; i++) 1194 if (inf->rgb[i]) 1195 fbi->rgb[i] = inf->rgb[i]; 1196 1197 init_waitqueue_head(&fbi->ctrlr_wait); 1198 INIT_WORK(&fbi->task, sa1100fb_task); 1199 mutex_init(&fbi->ctrlr_lock); 1200 1201 return fbi; 1202} 1203 1204static int sa1100fb_probe(struct platform_device *pdev) 1205{ 1206 struct sa1100fb_info *fbi; 1207 struct resource *res; 1208 int ret, irq; 1209 1210 if (!dev_get_platdata(&pdev->dev)) { 1211 dev_err(&pdev->dev, "no platform LCD data\n"); 1212 return -EINVAL; 1213 } 1214 1215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1216 irq = platform_get_irq(pdev, 0); 1217 if (irq < 0 || !res) 1218 return -EINVAL; 1219 1220 if (!request_mem_region(res->start, resource_size(res), "LCD")) 1221 return -EBUSY; 1222 1223 fbi = sa1100fb_init_fbinfo(&pdev->dev); 1224 ret = -ENOMEM; 1225 if (!fbi) 1226 goto failed; 1227 1228 fbi->base = ioremap(res->start, resource_size(res)); 1229 if (!fbi->base) 1230 goto failed; 1231 1232 /* Initialize video memory */ 1233 ret = sa1100fb_map_video_memory(fbi); 1234 if (ret) 1235 goto failed; 1236 1237 ret = request_irq(irq, sa1100fb_handle_irq, 0, "LCD", fbi); 1238 if (ret) { 1239 dev_err(&pdev->dev, "request_irq failed: %d\n", ret); 1240 goto failed; 1241 } 1242 1243 if (machine_is_shannon()) { 1244 ret = gpio_request_one(SHANNON_GPIO_DISP_EN, 1245 GPIOF_OUT_INIT_LOW, "display enable"); 1246 if (ret) 1247 goto err_free_irq; 1248 } 1249 1250 /* 1251 * This makes sure that our colour bitfield 1252 * descriptors are correctly initialised. 1253 */ 1254 sa1100fb_check_var(&fbi->fb.var, &fbi->fb); 1255 1256 platform_set_drvdata(pdev, fbi); 1257 1258 ret = register_framebuffer(&fbi->fb); 1259 if (ret < 0) 1260 goto err_reg_fb; 1261 1262#ifdef CONFIG_CPU_FREQ 1263 fbi->freq_transition.notifier_call = sa1100fb_freq_transition; 1264 fbi->freq_policy.notifier_call = sa1100fb_freq_policy; 1265 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); 1266 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER); 1267#endif 1268 1269 /* This driver cannot be unloaded at the moment */ 1270 return 0; 1271 1272 err_reg_fb: 1273 if (machine_is_shannon()) 1274 gpio_free(SHANNON_GPIO_DISP_EN); 1275 err_free_irq: 1276 free_irq(irq, fbi); 1277 failed: 1278 if (fbi) 1279 iounmap(fbi->base); 1280 kfree(fbi); 1281 release_mem_region(res->start, resource_size(res)); 1282 return ret; 1283} 1284 1285static struct platform_driver sa1100fb_driver = { 1286 .probe = sa1100fb_probe, 1287 .suspend = sa1100fb_suspend, 1288 .resume = sa1100fb_resume, 1289 .driver = { 1290 .name = "sa11x0-fb", 1291 .owner = THIS_MODULE, 1292 }, 1293}; 1294 1295int __init sa1100fb_init(void) 1296{ 1297 if (fb_get_options("sa1100fb", NULL)) 1298 return -ENODEV; 1299 1300 return platform_driver_register(&sa1100fb_driver); 1301} 1302 1303int __init sa1100fb_setup(char *options) 1304{ 1305#if 0 1306 char *this_opt; 1307 1308 if (!options || !*options) 1309 return 0; 1310 1311 while ((this_opt = strsep(&options, ",")) != NULL) { 1312 1313 if (!strncmp(this_opt, "bpp:", 4)) 1314 current_par.max_bpp = 1315 simple_strtoul(this_opt + 4, NULL, 0); 1316 1317 if (!strncmp(this_opt, "lccr0:", 6)) 1318 lcd_shadow.lccr0 = 1319 simple_strtoul(this_opt + 6, NULL, 0); 1320 if (!strncmp(this_opt, "lccr1:", 6)) { 1321 lcd_shadow.lccr1 = 1322 simple_strtoul(this_opt + 6, NULL, 0); 1323 current_par.max_xres = 1324 (lcd_shadow.lccr1 & 0x3ff) + 16; 1325 } 1326 if (!strncmp(this_opt, "lccr2:", 6)) { 1327 lcd_shadow.lccr2 = 1328 simple_strtoul(this_opt + 6, NULL, 0); 1329 current_par.max_yres = 1330 (lcd_shadow. 1331 lccr0 & LCCR0_SDS) ? ((lcd_shadow. 1332 lccr2 & 0x3ff) + 1333 1) * 1334 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1); 1335 } 1336 if (!strncmp(this_opt, "lccr3:", 6)) 1337 lcd_shadow.lccr3 = 1338 simple_strtoul(this_opt + 6, NULL, 0); 1339 } 1340#endif 1341 return 0; 1342} 1343 1344module_init(sa1100fb_init); 1345MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver"); 1346MODULE_LICENSE("GPL"); 1347