Lines Matching refs:pwm
83 static struct samsung_pwm_clocksource pwm;
96 reg = readl(pwm.base + REG_TCFG0);
99 writel(reg, pwm.base + REG_TCFG0);
111 bits = (fls(divisor) - 1) - pwm.variant.div_base;
115 reg = readl(pwm.base + REG_TCFG1);
118 writel(reg, pwm.base + REG_TCFG1);
133 tcon = __raw_readl(pwm.base + REG_TCON);
135 __raw_writel(tcon, pwm.base + REG_TCON);
151 tcon = __raw_readl(pwm.base + REG_TCON);
156 __raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
157 __raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
158 __raw_writel(tcon, pwm.base + REG_TCON);
173 tcon = __raw_readl(pwm.base + REG_TCON);
183 __raw_writel(tcon, pwm.base + REG_TCON);
204 samsung_time_setup(pwm.event_id, cycles);
205 samsung_time_start(pwm.event_id, false);
213 samsung_time_stop(pwm.event_id);
217 samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
218 samsung_time_start(pwm.event_id, true);
233 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
234 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
236 if (pwm.variant.has_tint_cstat) {
237 u32 mask = (1 << pwm.event_id);
238 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
255 if (pwm.variant.has_tint_cstat) {
256 u32 mask = (1 << pwm.event_id);
257 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
278 pclk = clk_get_rate(pwm.timerclk);
280 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
281 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
283 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
284 pwm.clock_count_per_tick = clock_rate / HZ;
288 clock_rate, 1, pwm.tcnt_max);
290 irq_number = pwm.irq[pwm.event_id];
293 if (pwm.variant.has_tint_cstat) {
294 u32 mask = (1 << pwm.event_id);
295 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
301 samsung_time_stop(pwm.source_id);
306 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
307 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
309 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
310 samsung_time_start(pwm.source_id, true);
315 return ~readl_relaxed(pwm.source_reg);
345 pclk = clk_get_rate(pwm.timerclk);
347 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
348 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
350 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
352 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
353 samsung_time_start(pwm.source_id, true);
355 if (pwm.source_id == 4)
356 pwm.source_reg = pwm.base + 0x40;
358 pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
361 pwm.variant.bits, clock_rate);
363 samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
371 clk_prepare_enable(pwm.timerclk);
373 pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
374 if (pwm.variant.bits == 16) {
375 pwm.tscaler_div = 25;
376 pwm.tdiv = 2;
378 pwm.tscaler_div = 2;
379 pwm.tdiv = 1;
391 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
395 pwm.source_id = channel;
401 pwm.event_id = channel;
411 pwm.base = base;
412 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
413 memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
415 pwm.timerclk = clk_get(NULL, "timers");
416 if (IS_ERR(pwm.timerclk))
431 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
433 pwm.irq[i] = irq_of_parse_and_map(np, i);
435 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
437 pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
441 pwm.variant.output_mask |= 1 << val;
444 pwm.base = of_iomap(np, 0);
445 if (!pwm.base) {
450 pwm.timerclk = of_clk_get_by_name(np, "timers");
451 if (IS_ERR(pwm.timerclk))
468 CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
481 CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
494 CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
507 CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);