Lines Matching refs:REG_READ
88 dspcntr = REG_READ(map->cntr);
120 REG_READ(map->base);
123 REG_READ(map->base);
125 REG_READ(map->surf);
226 temp = REG_READ(map->dpll);
229 REG_READ(map->dpll);
233 REG_READ(map->dpll);
237 REG_READ(map->dpll);
243 temp = REG_READ(map->cntr);
248 REG_WRITE(map->base, REG_READ(map->base));
254 temp = REG_READ(map->conf);
258 temp = REG_READ(map->status);
262 REG_READ(map->status);
290 temp = REG_READ(map->cntr);
295 REG_WRITE(map->base, REG_READ(map->base));
296 REG_READ(map->base);
300 temp = REG_READ(map->conf);
303 REG_READ(map->conf);
312 temp = REG_READ(map->dpll);
315 REG_READ(map->dpll);
570 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
571 crtc_state->savePIPECONF = REG_READ(map->conf);
572 crtc_state->savePIPESRC = REG_READ(map->src);
573 crtc_state->saveFP0 = REG_READ(map->fp0);
574 crtc_state->saveFP1 = REG_READ(map->fp1);
575 crtc_state->saveDPLL = REG_READ(map->dpll);
576 crtc_state->saveHTOTAL = REG_READ(map->htotal);
577 crtc_state->saveHBLANK = REG_READ(map->hblank);
578 crtc_state->saveHSYNC = REG_READ(map->hsync);
579 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
580 crtc_state->saveVBLANK = REG_READ(map->vblank);
581 crtc_state->saveVSYNC = REG_READ(map->vsync);
582 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
585 crtc_state->saveDSPSIZE = REG_READ(map->size);
586 crtc_state->saveDSPPOS = REG_READ(map->pos);
588 crtc_state->saveDSPBASE = REG_READ(map->base);
592 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
616 REG_READ(map->dpll);
621 REG_READ(map->fp0);
624 REG_READ(map->fp1);
627 REG_READ(map->dpll);
741 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
748 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==