Lines Matching refs:is
9 * This program is free software; you can redistribute it and/or modify
15 #include "fimc-is.h"
16 #include "fimc-is-command.h"
17 #include "fimc-is-regs.h"
18 #include "fimc-is-sensor.h"
20 void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr)
22 mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1);
25 void fimc_is_fw_clear_irq2(struct fimc_is *is)
27 u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);
28 mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);
31 void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is)
33 mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0);
36 int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)
42 cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
46 dev_warn(&is->pdev->dev, "%s timeout\n",
56 int fimc_is_hw_set_param(struct fimc_is *is)
58 struct chain_config *config = &is->config[is->config_index];
59 unsigned int param_count = __get_pending_param_count(is);
61 fimc_is_hw_wait_intmsr0_intmsd0(is);
63 mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0));
64 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
65 mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2));
67 mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3));
68 mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4));
69 mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5));
71 fimc_is_hw_set_intgr0_gd0(is);
75 static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is)
77 fimc_is_hw_wait_intmsr0_intmsd0(is);
79 mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0));
80 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
81 mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2));
83 fimc_is_hw_set_intgr0_gd0(is);
89 int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)
96 is->i2h_cmd.num_args = num_args;
100 is->i2h_cmd.args[i] = mcuctl_read(is,
103 is->i2h_cmd.args[i] = 0;
108 void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask)
111 dev_err(&is->pdev->dev, "%s(): not enough buffers (mask %#x)\n",
116 if (mcuctl_read(is, MCUCTL_REG_ISSR(23)) != 0)
117 dev_dbg(&is->pdev->dev, "non-zero DMA buffer mask\n");
119 mcuctl_write(mask, is, MCUCTL_REG_ISSR(23));
122 void fimc_is_hw_set_sensor_num(struct fimc_is *is)
124 pr_debug("setting sensor index to: %d\n", is->sensor_index);
126 mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0));
127 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
128 mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2));
129 mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3));
132 void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index)
134 if (is->sensor_index != index)
137 fimc_is_hw_wait_intmsr0_intmsd0(is);
138 mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0));
139 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
140 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2));
141 fimc_is_hw_set_intgr0_gd0(is);
144 void fimc_is_hw_get_setfile_addr(struct fimc_is *is)
146 fimc_is_hw_wait_intmsr0_intmsd0(is);
147 mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0));
148 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
149 fimc_is_hw_set_intgr0_gd0(is);
152 void fimc_is_hw_load_setfile(struct fimc_is *is)
154 fimc_is_hw_wait_intmsr0_intmsd0(is);
155 mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0));
156 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
157 fimc_is_hw_set_intgr0_gd0(is);
160 int fimc_is_hw_change_mode(struct fimc_is *is)
167 if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd)))
170 mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0));
171 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
172 mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2));
173 fimc_is_hw_set_intgr0_gd0(is);
177 void fimc_is_hw_stream_on(struct fimc_is *is)
179 fimc_is_hw_wait_intmsr0_intmsd0(is);
180 mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0));
181 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
182 mcuctl_write(0, is, MCUCTL_REG_ISSR(2));
183 fimc_is_hw_set_intgr0_gd0(is);
186 void fimc_is_hw_stream_off(struct fimc_is *is)
188 fimc_is_hw_wait_intmsr0_intmsd0(is);
189 mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0));
190 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
191 fimc_is_hw_set_intgr0_gd0(is);
194 void fimc_is_hw_subip_power_off(struct fimc_is *is)
196 fimc_is_hw_wait_intmsr0_intmsd0(is);
197 mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0));
198 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
199 fimc_is_hw_set_intgr0_gd0(is);
202 int fimc_is_itf_s_param(struct fimc_is *is, bool update)
207 __is_hw_update_params(is);
211 clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
212 fimc_is_hw_set_param(is);
213 ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,
216 dev_err(&is->pdev->dev, "%s() timeout\n", __func__);
221 int fimc_is_itf_mode_change(struct fimc_is *is)
225 clear_bit(IS_ST_CHANGE_MODE, &is->state);
226 fimc_is_hw_change_mode(is);
227 ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1,
230 dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n",
231 __func__, is->config_index);