/drivers/clk/ |
H A D | clk-si570.c | 232 u64 rfreq, rate; local 238 dev_err(&data->i2c_client->dev, "unable to recalc rate\n"); 243 rate = (data->fxtal * rfreq) >> 28; 245 return rate; 248 static long si570_round_rate(struct clk_hw *hw, unsigned long rate, argument 256 if (!rate) 259 if (div64_u64(abs(rate - data->frequency) * 10000LL, 261 rfreq = div64_u64((data->rfreq * rate) + 267 err = si570_calc_divs(rate, data, &rfreq, &n1, &hs_div); 270 "unable to round rate\ 341 si570_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument [all...] |
H A D | clk-conf.c | 85 u32 rate; local 87 of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { 88 if (rate) { 108 rc = clk_set_rate(clk, rate); 110 pr_err("clk: couldn't set %s clock rate: %d\n",
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H A D | clk-composite.c | 58 static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, argument 76 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate, 86 return rate_ops->round_rate(rate_hw, rate, 97 tmp_rate = rate_ops->round_rate(rate_hw, rate, 102 rate_diff = abs(rate - tmp_rate); 113 return rate; 119 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate, 122 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); 127 static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, argument 136 return rate_ops->round_rate(rate_hw, rate, prat 139 clk_composite_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument [all...] |
/drivers/clk/mxs/ |
H A D | clk-ref.c | 27 * clock has a gate control and a fractional * divider. The rate is calculated 28 * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35. 67 static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, argument 74 tmp = tmp * 18 + rate / 2; 75 do_div(tmp, rate); 90 static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, argument 99 tmp = tmp * 18 + rate / 2; 100 do_div(tmp, rate);
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H A D | clk-div.c | 50 static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, argument 55 return div->ops->round_rate(&div->divider.hw, rate, prate); 58 static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, argument 64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
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/drivers/clk/shmobile/ |
H A D | clk-div6.c | 75 static unsigned int cpg_div6_clock_calc_div(unsigned long rate, argument 80 div = DIV_ROUND_CLOSEST(parent_rate, rate); 84 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, argument 87 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); 92 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, argument 96 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
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/drivers/clocksource/ |
H A D | sun4i_timer.c | 148 unsigned long rate = 0; local 166 rate = clk_get_rate(clk); 173 sched_clock_register(sun4i_timer_sched_read, 32, rate); 175 rate, 350, 32, clocksource_mmio_readl_down); 177 ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); 188 clockevents_config_and_register(&sun4i_clockevent, rate,
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H A D | timer-sun5i.c | 148 unsigned long rate; local 165 rate = clk_get_rate(clk); 175 sched_clock_register(sun5i_timer_sched_read, 32, rate); 177 rate, 340, 32, clocksource_mmio_readl_down); 179 ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); 192 clockevents_config_and_register(&sun5i_clockevent, rate,
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H A D | nomadik-mtu.c | 197 unsigned long rate; local 205 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz 207 * Use a divide-by-16 counter if the tick rate is more than 32MHz. 212 rate = clk_get_rate(clk); 213 if (rate > 32000000) { 214 rate /= 16; 221 nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ); 228 rate, 200, 32, clocksource_mmio_readl_down)) 233 sched_clock_register(nomadik_read_sched_clock, 32, rate); 240 clockevents_config_and_register(&nmdk_clkevt, rate, [all...] |
/drivers/cpufreq/ |
H A D | tegra-cpufreq.c | 94 unsigned long rate = freq_table[index].frequency; local 102 if (rate >= 816000) 104 else if (rate >= 456000) 113 if (rate == ifreq) 116 ret = clk_set_rate(pll_x_clk, rate * 1000); 119 pr_err("Failed to change pll_x to %lu\n", rate);
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/drivers/net/wireless/brcm80211/brcmsmac/ |
H A D | rate.h | 34 /* phy rate in kbps [20Mhz] */ 36 /* phy rate in kbps [40Mhz] */ 38 /* phy rate in kbps [20Mhz] with SGI */ 40 /* phy rate in kbps [40Mhz] with SGI */ 42 /* phy ctl byte 3, code rate, modulation type, # of streams */ 44 /* matching legacy ofdm rate in 500bkps */ 75 #define BRCMS_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */ 78 * rate spec : holds rate and mode specific information required to generate a 84 /* rate spe 183 u32 rate = (ratespec & BRCMS_RATE_MASK); local [all...] |
/drivers/clk/st/ |
H A D | clk-flexgen.c | 98 clk_best_div(unsigned long parent_rate, unsigned long rate) argument 100 return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1); 103 static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate, argument 108 /* Round div according to exact prate and wished rate */ 109 div = clk_best_div(*prate, rate); 112 *prate = rate * div; 113 return rate; 135 static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate, argument [all...] |
/drivers/net/wan/ |
H A D | sbni.h | 49 u8 rate : 2; member in struct:sbni_csr1 53 u8 rate : 2; 126 u32 rate : 2; member in struct:sbni_flags
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/drivers/clk/berlin/ |
H A D | berlin2-pll.c | 65 u64 rate = parent_rate; local 84 rate *= fbdiv * map->mult; 85 do_div(rate, rfdiv * vcodiv); 87 return (unsigned long)rate;
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/drivers/clk/mvebu/ |
H A D | clk-cpu.c | 60 static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate, argument 66 div = *parent_rate / rate; 75 static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate, argument 83 div = parent_rate / rate; 109 static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate, argument 130 if (rate == 2 * cur_rate) 152 static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate, argument 156 return clk_cpu_on_set_rate(hwclk, rate, parent_rate); 158 return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
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/drivers/clk/qcom/ |
H A D | common.h | 32 unsigned long rate);
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H A D | clk-pll.c | 101 unsigned long rate; local 112 rate = parent_rate * l; 117 rate += tmp; 123 rate /= config + 1; 126 return rate; 130 struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate) argument 136 if (rate <= f->freq) 143 clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate, argument 149 f = find_freq(pll->freq_tbl, rate); 157 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigne argument [all...] |
/drivers/clk/at91/ |
H A D | clk-usb.c | 59 static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, argument 64 if (!rate) 67 if (rate >= *parent_rate) 70 div = DIV_ROUND_CLOSEST(*parent_rate, rate); 100 static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, argument 108 if (!rate) 111 div = DIV_ROUND_CLOSEST(parent_rate, rate); 238 static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, argument 255 tmp_parent_rate = rate * usb->divisors[i]; 258 if (tmprate < rate) 276 at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument [all...] |
H A D | clk-peripheral.c | 231 unsigned long rate, 252 if (rate >= cur_rate) 255 best_diff = cur_rate - rate; 259 if (cur_rate < rate) 260 cur_diff = rate - cur_rate; 262 cur_diff = cur_rate - rate; 269 if (!best_diff || cur_rate < rate) 277 unsigned long rate, 283 if (parent_rate == rate) 289 if (periph->range.max && rate > perip 230 clk_sam9x5_peripheral_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) argument 276 clk_sam9x5_peripheral_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument [all...] |
/drivers/clk/spear/ |
H A D | clk-vco-pll.c | 23 * VCO and PLL rate are derived from following equations: 39 * set_rate to vco. A single rate table exists for both the clocks, which 68 /* Calculates pll clk rate for specific value of mode, m, n and p */ 72 unsigned long rate = prate; local 76 rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n)); 79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; 81 return rate * 10000; 88 unsigned long prev_rate, vco_prev_rate, rate = 0; local 98 prev_rate = rate; [all...] |
/drivers/clk/sunxi/ |
H A D | clk-factors.h | 28 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); 36 void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
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/drivers/ide/ |
H A D | ide-xfer-mode.c | 240 * ide_set_xfer_rate - set transfer rate 242 * @rate: speed to attempt to set 249 int ide_set_xfer_rate(ide_drive_t *drive, u8 rate) argument 258 rate = ide_rate_filter(drive, rate); 260 BUG_ON(rate < XFER_PIO_0); 262 if (rate >= XFER_PIO_0 && rate <= XFER_PIO_6) 263 return ide_set_pio_mode(drive, rate); 265 return ide_set_dma_mode(drive, rate); [all...] |
/drivers/net/wireless/ti/wl1251/ |
H A D | tx.h | 118 * A bit mask that specifies the initial rate to be used 134 __le16 rate; member in struct:tx_double_buffer_desc 199 /* At which rate we got a ACK */ 200 u16 rate; member in struct:tx_result
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/drivers/pwm/ |
H A D | pwm-tegra.c | 71 unsigned long rate, hz; local 87 * cycles at the PWM clock rate will take period_ns nanoseconds. 89 rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; 92 rate = (rate + (hz / 2)) / hz; 99 if (rate > 0) 100 rate--; 103 * Make sure that the rate will fit in the register's frequency 106 if (rate >> PWM_SCALE_WIDTH) 109 val |= rate << PWM_SCALE_SHIF [all...] |
/drivers/watchdog/ |
H A D | sp805_wdt.c | 81 u64 load, rate; local 83 rate = clk_get_rate(wdt->clk); 91 load = div_u64(rate, 2) * timeout - 1; 99 wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); 109 u64 load, rate; local 111 rate = clk_get_rate(wdt->clk); 121 return div_u64(load, rate);
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