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Searched defs:dpcd (Results 1 - 9 of 9) sorted by relevance

/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c35 u8 *dpcd)
40 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
59 u8 *dpcd = nv_encoder->dp.dpcd; local
66 ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
70 nv_encoder->dp.link_bw = 27000 * dpcd[1];
71 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
73 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
74 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
87 nouveau_dp_probe_oui(dev, auxch, dpcd);
34 nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch, u8 *dpcd) argument
[all...]
H A Dnouveau_encoder.h58 u8 dpcd[8]; member in struct:nouveau_encoder::__anon907::__anon908
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Doutpdp.h17 u8 dpcd[16]; member in struct:nvkm_output_dp
/drivers/gpu/drm/
H A Ddrm_dp_helper.c310 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { argument
311 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
314 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
318 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { argument
319 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
322 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
/drivers/gpu/drm/radeon/
H A Datombios_dp.c298 u8 dpcd[DP_DPCD_SIZE])
303 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
305 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
315 u8 dpcd[DP_DPCD_SIZE],
319 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
320 int max_lane_num = drm_dp_max_lane_count(dpcd);
334 u8 dpcd[DP_DPCD_SIZE],
344 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
357 return radeon_dp_get_max_link_rate(connector, dpcd);
392 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUN
297 radeon_dp_get_max_link_rate(struct drm_connector *connector, u8 dpcd[DP_DPCD_SIZE]) argument
314 radeon_dp_get_dp_lane_number(struct drm_connector *connector, u8 dpcd[DP_DPCD_SIZE], int pix_clock) argument
333 radeon_dp_get_dp_link_clock(struct drm_connector *connector, u8 dpcd[DP_DPCD_SIZE], int pix_clock) argument
550 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:radeon_dp_link_train_info
[all...]
H A Dradeon_mode.h453 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:radeon_connector_atom_dig
/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c71 uint8_t dpcd[4]; member in struct:cdv_intel_dp
134 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
135 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
884 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
885 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
920 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1514 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1515 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
[all...]
/drivers/gpu/drm/i915/
H A Dintel_dp.c120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3481 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3505 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3585 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3985 uint8_t *dpcd = intel_dp->dpcd; local
[all...]
H A Dintel_drv.h558 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:intel_dp

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