| /drivers/gpu/drm/nouveau/ |
| H A D | nouveau_encoder.h | 60 int link_bw; member in struct:nouveau_encoder::__anon907::__anon908
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| /drivers/gpu/drm/nouveau/core/engine/disp/ |
| H A D | dport.c | 44 u32 link_bw; member in struct:dp_state
71 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
76 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
80 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
88 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
100 sink[0] = dp->link_bw / 27000;
344 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw)
345 outp->dpcd[1] = outp->base.info.dpconf.link_bw;
367 dp->link_bw = cfg->bw * 27000;
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| H A D | nvd0.c | 991 u32 datarate, link_nr, link_bw, bits; local
995 link_bw = (clksor & 0x007c0000) >> 18;
996 link_bw *= 27000;
1000 value = value * link_bw;
1007 value = value * link_bw;
1020 do_div(ratio, link_nr * link_bw);
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| H A D | nv50.c | 1651 u32 link_nr, link_bw, bits; local
1654 link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
1659 value = value * link_bw;
1666 value = value * link_bw;
1680 do_div(link_ratio, link_bw);
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| /drivers/gpu/drm/nouveau/core/include/subdev/bios/ |
| H A D | dcb.h | 50 int link_bw; member in struct:dcb_output::__anon837::__anon841
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| /drivers/gpu/drm/nouveau/core/subdev/i2c/ |
| H A D | anx9805.c | 34 anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) argument
40 DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh);
42 nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
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| /drivers/gpu/drm/ |
| H A D | drm_dp_helper.c | 340 int drm_dp_bw_code_to_link_rate(u8 link_bw) argument
342 switch (link_bw) {
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| /drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 69 uint8_t link_bw; member in struct:cdv_intel_dp
164 cdv_intel_dp_link_clock(uint8_t link_bw) argument
166 if (link_bw == DP_LINK_BW_2_7)
724 intel_dp->link_bw = bws[clock];
726 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
729 intel_dp->link_bw, intel_dp->lane_count,
738 intel_dp->link_bw = bws[max_clock];
739 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
742 intel_dp->link_bw, intel_dp->lane_count,
878 intel_dp->link_configuration[0] = intel_dp->link_bw;
[all...] |
| /drivers/gpu/drm/i915/ |
| H A D | intel_dp.c | 44 int link_bw; member in struct:dp_link_dpll
966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) argument
968 switch (link_bw) {
983 struct intel_crtc_config *pipe_config, int link_bw)
1005 if (link_bw == divisor[i].link_bw) {
1117 intel_dp->link_bw = bws[clock];
1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1123 intel_dp->link_bw, intel_dp->lane_count,
1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
982 intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config, int link_bw) argument
[all...] |
| H A D | intel_drv.h | 556 uint8_t link_bw; member in struct:intel_dp
848 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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| H A D | intel_display.c | 5274 int lane, link_bw, fdi_dotclock; local
5285 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5289 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5295 link_bw, &pipe_config->fdi_m_n);
7101 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) argument
7109 return DIV_ROUND_UP(bps, link_bw * 8);
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