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Searched refs:WRITE_BYTE (Results 1 - 7 of 7) sorted by relevance

/drivers/isdn/hardware/eicon/
H A Ds_pri.c93 WRITE_BYTE(p, _MP_RISC_RESET | _MP_LED1 | _MP_LED2);
95 WRITE_BYTE(p, 0x00);
122 WRITE_BYTE(p, _MP_RISC_RESET | _MP_LED1 | _MP_LED2);
H A Dos_pri.c425 WRITE_BYTE(mem++, *data++);
779 WRITE_BYTE(&config[0xc3c], c); /* Base Address enable register */
781 WRITE_BYTE(&config[LOW_BOOTCS_DREG], 0x00);
782 WRITE_BYTE(&config[HI_BOOTCS_DREG], 0xFF);
795 WRITE_BYTE(&config[LOW_BOOTCS_DREG], 0xFC); /* Disable FLASH EPROM access */
796 WRITE_BYTE(&config[HI_BOOTCS_DREG], 0xFF);
979 WRITE_BYTE(p, _MP_RISC_RESET | _MP_DSP_RESET);
1006 WRITE_BYTE(p, _MP_RISC_RESET | _MP_LED1 | _MP_LED2);
H A Ds_4bri.c169 WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
423 WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
H A Dos_4bri.c427 WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
925 WRITE_BYTE(mem++, *data++);
1022 WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
1050 WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
H A Dplatform.h319 #define WRITE_BYTE(addr, v) writeb(v, addr) macro
H A Dio.c629 WRITE_BYTE(Base + (unsigned long)addr, data);
658 WRITE_BYTE(Base + (unsigned long)addr, x + 1);
/drivers/video/fbdev/
H A Dstifb.c159 # define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)) macro
165 # define WRITE_BYTE(value,fb,reg) do { if (debug_on) \ macro
166 printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
229 WRITE_BYTE(1, fb, REG_16b1);

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