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Searched refs:clock_type (Results 1 - 16 of 16) sorted by relevance

/drivers/net/wan/
H A Dc101.c158 switch(port->settings.clock_type) {
265 if (new_line.clock_type != CLOCK_EXT &&
266 new_line.clock_type != CLOCK_TXFROMRX &&
267 new_line.clock_type != CLOCK_INT &&
268 new_line.clock_type != CLOCK_TXINT)
380 card->settings.clock_type = CLOCK_EXT;
H A Dpci200syn.c129 switch(port->settings.clock_type) {
221 if (new_line.clock_type != CLOCK_EXT &&
222 new_line.clock_type != CLOCK_TXFROMRX &&
223 new_line.clock_type != CLOCK_INT &&
224 new_line.clock_type != CLOCK_TXINT)
398 port->settings.clock_type = CLOCK_EXT;
H A Dn2.c176 switch(port->settings.clock_type) {
283 if (new_line.clock_type != CLOCK_EXT &&
284 new_line.clock_type != CLOCK_TXFROMRX &&
285 new_line.clock_type != CLOCK_INT &&
286 new_line.clock_type != CLOCK_TXINT)
473 port->settings.clock_type = CLOCK_EXT;
H A Dpc300too.c130 switch(port->settings.clock_type) {
246 if (new_line.clock_type != CLOCK_EXT &&
247 new_line.clock_type != CLOCK_TXFROMRX &&
248 new_line.clock_type != CLOCK_INT &&
249 new_line.clock_type != CLOCK_TXINT)
458 port->settings.clock_type = CLOCK_EXT;
H A Dixp4xx_hss.c266 unsigned int clock_type, clock_rate, loopback; member in struct:port
403 if (port->clock_type == CLOCK_INT)
1265 new_line.clock_type = port->clock_type;
1279 clk = new_line.clock_type;
1289 port->clock_type = clk; /* Update settings */
1355 port->clock_type = CLOCK_EXT;
H A Dwanxl.c62 unsigned int clock_type; member in struct:port
359 line.clock_type = get_status(port)->clocking;
377 if (line.clock_type != CLOCK_EXT &&
378 line.clock_type != CLOCK_TXFROMRX)
384 get_status(port)->clocking = line.clock_type;
H A Dfarsync.c1910 switch (sync.clock_type) {
1969 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
H A Ddscc4.c998 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
/drivers/video/fbdev/
H A Dsm501fb.c437 unsigned int clock_type; local
448 clock_type = SM501_CLOCK_V2XCLK;
454 clock_type = SM501_CLOCK_P2XCLK;
461 clock_type = 0;
507 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
/drivers/char/pcmcia/
H A Dsynclink_cs.c4138 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4139 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4140 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4141 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4142 default: new_line.clock_type = CLOCK_DEFAULT;
4159 switch (new_line.clock_type)
/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c2791 u8 clock_type,
2809 args.v1.ucAction = clock_type;
2823 args.v2.ucAction = clock_type;
2838 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2839 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2857 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2888 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2790 radeon_atom_get_clock_dividers(struct radeon_device *rdev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) argument
H A Dradeon.h285 u8 clock_type,
/drivers/staging/octeon-usb/
H A Docteon-hcd.c3734 const char *clock_type; local
3767 "refclk-type", &clock_type);
3769 if (!i && strcmp("crystal", clock_type) == 0)
/drivers/tty/
H A Dsynclink.c7867 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7868 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7870 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7871 default: new_line.clock_type = CLOCK_DEFAULT;
7888 switch (new_line.clock_type)
H A Dsynclink_gt.c1655 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1656 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1657 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1658 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1659 default: new_line.clock_type = CLOCK_DEFAULT;
1676 switch (new_line.clock_type)
H A Dsynclinkmp.c1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1775 default: new_line.clock_type = CLOCK_DEFAULT;
1792 switch (new_line.clock_type)

Completed in 336 milliseconds