Searched refs:fbc (Results 1 - 9 of 9) sorted by relevance
/drivers/video/fbdev/ |
H A D | cg6.c | 257 struct cg6_fbc __iomem *fbc; member in struct:cg6_par 271 struct cg6_fbc __iomem *fbc = par->fbc; local 275 if (!(sbus_readl(&fbc->s) & 0x10000000)) 319 struct cg6_fbc __iomem *fbc = par->fbc; local 329 sbus_writel(rect->color, &fbc->fg); 330 sbus_writel(~(u32)0, &fbc->pixelm); 331 sbus_writel(0xea80ff00, &fbc->alu); 332 sbus_writel(0, &fbc 358 struct cg6_fbc __iomem *fbc = par->fbc; local 396 struct cg6_fbc __iomem *fbc = par->fbc; local 670 struct cg6_fbc __iomem *fbc = par->fbc; local [all...] |
H A D | ffb.c | 241 u32 fbc; member in struct:ffb_fbc 353 struct ffb_fbc __iomem *fbc; member in struct:ffb_par 377 struct ffb_fbc __iomem *fbc; local 381 fbc = par->fbc; 383 cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK); 392 struct ffb_fbc __iomem *fbc; local 395 fbc = par->fbc; 397 if ((upa_readl(&fbc 425 struct ffb_fbc __iomem *fbc = par->fbc; local 478 struct ffb_fbc __iomem *fbc = par->fbc; local 518 struct ffb_fbc __iomem *fbc = par->fbc; local 552 struct ffb_fbc __iomem *fbc = par->fbc; local 899 struct ffb_fbc __iomem *fbc; local [all...] |
/drivers/gpu/drm/i915/ |
H A D | i915_gem_stolen.c | 197 ret = find_compression_threshold(dev, &dev_priv->fbc.compressed_fb, 206 dev_priv->fbc.threshold = ret; 209 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 211 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 222 dev_priv->fbc.compressed_llb = compressed_llb; 225 dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); 230 dev_priv->fbc.size = size / dev_priv->fbc.threshold; 239 drm_mm_remove_node(&dev_priv->fbc.compressed_fb); 252 if (size < dev_priv->fbc [all...] |
H A D | intel_pm.c | 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 229 dev_priv->fbc.threshold++; 231 switch (dev_priv->fbc.threshold) { 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 295 dev_priv->fbc.threshold++; 297 switch (dev_priv->fbc.threshold) { 312 if (dev_priv->fbc.false_color) 335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 367 if (work == dev_priv->fbc 1931 uint16_t fbc; member in struct:ilk_wm_maximums [all...] |
H A D | intel_sprite.c | 757 if (dev_priv->fbc.plane == intel_crtc->plane)
|
H A D | i915_debugfs.c | 1421 switch (dev_priv->fbc.no_fbc_reason) { 1475 *val = dev_priv->fbc.false_color; 1493 dev_priv->fbc.false_color = val;
|
H A D | i915_drv.h | 679 FBC_BAD_PLANE, /* fbc not supported on plane */ 1503 struct i915_fbc fbc; member in struct:drm_i915_private
|
H A D | i915_reg.h | 4103 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4105 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
|
H A D | intel_display.c | 4074 if (dev_priv->fbc.plane == plane) 9164 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must 9220 * FIXME: Unconditional fbc flushing here is a rather gross hack and 11943 * FIXME: This is redundant with the fbc update done in 11949 dev_priv->fbc.plane == intel_crtc->plane && 12162 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
|
Completed in 716 milliseconds