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Searched refs:irq_mask (Results 1 - 25 of 231) sorted by relevance

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/drivers/mfd/
H A Dtps65912-irq.c44 u32 irq_mask; local
59 irq_mask = reg;
61 irq_mask |= reg << 8;
63 irq_mask |= reg << 16;
65 irq_mask |= reg << 24;
67 irq_sts &= ~irq_mask;
120 if (tps65912->irq_mask != reg_mask) {
121 reg = tps65912->irq_mask & 0xFF;
123 reg = tps65912->irq_mask >> 8 & 0xFF;
125 reg = tps65912->irq_mask >> 1
[all...]
H A Ducb1x00-core.c306 ucb->irq_mask);
309 ucb->irq_mask);
323 ucb->irq_mask &= ~mask;
334 ucb->irq_mask |= mask;
354 if (ucb->irq_mask & mask) {
356 ucb->irq_mask);
358 ucb->irq_mask);
387 .irq_mask = ucb1x00_irq_mask,
722 ucb->irq_mask);
724 ucb->irq_mask);
[all...]
/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_irq.c41 masked_status = status & dev_priv->irq_mask;
194 dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE;
195 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
208 dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE;
209 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
225 dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL;
226 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
239 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL;
240 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
/drivers/video/fbdev/omap2/dss/
H A Ddispc-compat.c525 u32 irq_mask; local
536 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
540 irq_mask);
542 DSSERR("failed to register %x isr\n", irq_mask);
553 irq_mask);
555 DSSERR("failed to unregister %x isr\n", irq_mask);
562 u32 irq_mask; local
573 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
576 if (!irq_mask) {
582 irq_mask
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/drivers/ide/
H A Dcmd64x.c191 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : local
196 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
205 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : local
211 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
218 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : local
222 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
223 hwif->name, mrdmode, irq_mask);
225 return (mrdmode & irq_mask) ? 1 : 0;
232 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : local
238 pr_debug("%s: irq_stat: 0x%02x irq_mask
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/drivers/irqchip/
H A Dexynos-combiner.c34 unsigned int irq_mask; member in struct:combiner_chip_data
75 status &= chip_data->irq_mask;
109 .irq_mask = combiner_mask_irq,
130 combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
134 __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
H A Dirq-or1k-pic.c73 .irq_mask = or1k_pic_mask,
84 .irq_mask = or1k_pic_mask,
96 .irq_mask = or1k_pic_mask,
H A Dirq-dw-apb-ictl.c129 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
134 gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
H A Dirq-mxs.c71 .irq_mask = icoll_mask_irq,
H A Dirq-nvic.c95 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
H A Dirq-xtensa-pic.c84 .irq_mask = xtensa_irq_mask,
H A Dirq-metag-ext.c161 data->chip->irq_mask(data);
542 .irq_mask = meta_intc_mask_irq,
553 .irq_mask = meta_intc_mask_irq,
801 meta_intc_edge_chip.irq_mask = meta_intc_mask_irq_nomask;
803 meta_intc_level_chip.irq_mask = meta_intc_mask_irq_nomask;
/drivers/mtd/nand/
H A Ddenali.c106 uint32_t irq_mask);
165 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; local
171 irq_status = wait_for_irq(denali, irq_mask);
622 uint32_t irq_mask)
628 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
692 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) argument
704 if (intr_status & irq_mask) {
705 denali->irq_status &= ~irq_mask;
721 intr_status, irq_mask);
756 uint32_t addr, cmd, irq_status, irq_mask; local
621 clear_interrupt(struct denali_nand_info *denali, uint32_t irq_mask) argument
866 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | local
894 uint32_t irq_mask = INTR_STATUS__LOAD_COMP; local
1061 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | local
1159 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | local
1208 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; local
[all...]
/drivers/crypto/qat/qat_common/
H A Dadf_transport_internal.h83 uint16_t irq_mask; member in struct:adf_etr_bank_data
/drivers/gpu/drm/radeon/
H A Dradeon_irq.c136 u32 irq_mask = RADEON_SW_INT_TEST; local
154 irq_mask |= R500_DISPLAY_INT_STATUS;
156 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
158 irqs &= irq_mask;
/drivers/gpio/
H A Dgpio-adp5588.c42 uint8_t irq_mask[3]; member in struct:adp5588_gpio
181 if (dev->int_en[i] ^ dev->irq_mask[i]) {
182 dev->int_en[i] = dev->irq_mask[i];
195 dev->irq_mask[ADP5588_BANK(gpio)] &= ~ADP5588_BIT(gpio);
203 dev->irq_mask[ADP5588_BANK(gpio)] |= ADP5588_BIT(gpio);
237 .irq_mask = adp5588_irq_mask,
268 pending = dev->irq_stat[bank] & dev->irq_mask[bank];
H A Dgpio-max732x.c137 uint8_t irq_mask; member in struct:max732x_chip
297 if (chip->irq_mask == chip->irq_mask_cur)
300 chip->irq_mask = chip->irq_mask_cur;
309 msg = (chip->irq_mask << 8) | chip->reg_out[0];
314 msg = chip->irq_mask | chip->reg_out[0];
349 chip->irq_mask_cur = chip->irq_mask;
393 .irq_mask = max732x_irq_mask,
414 trigger &= chip->irq_mask;
420 cur_stat &= chip->irq_mask;
H A Dgpio-pxa.c75 unsigned long irq_mask; member in struct:pxa_gpio_chip
336 * bits are set in c->irq_mask
342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
344 grer |= c->irq_edge_rise & c->irq_mask;
345 gfer |= c->irq_edge_fall & c->irq_mask;
411 gedr = gedr & c->irq_mask;
439 c->irq_mask &= ~GPIO_bit(gpio);
463 c->irq_mask |= GPIO_bit(gpio);
470 .irq_mask
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/drivers/media/pci/solo6x10/
H A Dsolo6x10.h201 u32 irq_mask; member in struct:solo_dev
319 dev->irq_mask |= mask;
320 solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
325 dev->irq_mask &= ~mask;
326 solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
/drivers/i2c/busses/
H A Di2c-nomadik.c450 u32 mcr, irq_mask; local
466 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
470 irq_mask |= I2C_IT_MTD;
472 irq_mask |= I2C_IT_MTDWS;
474 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
476 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
519 u32 mcr, irq_mask; local
536 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
542 irq_mask |
[all...]
/drivers/ata/
H A Dpata_cmd64x.c241 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; local
248 return irq_stat & irq_mask;
281 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; local
284 return mrdmode & irq_mask;
298 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; local
306 outb(mrdmode | irq_mask, base + 1);
/drivers/acpi/acpica/
H A Drsirq.c64 AML_OFFSET(irq.irq_mask),
118 AML_OFFSET(irq.irq_mask),
/drivers/message/i2o/
H A Dpci.c169 c->irq_mask = c->base.virt + I2O_IRQ_MASK;
183 c->irq_mask += I2O_MOTOROLA_PORT_OFFSET;
274 writel(0xffffffff, c->irq_mask);
286 writel(0x00000000, c->irq_mask);
301 writel(0xffffffff, c->irq_mask);
/drivers/hid/
H A Dhid-rmi.c52 unsigned long irq_mask; /* mask of the interrupts member in struct:rmi_function
323 if (!(irq & hdata->f11.irq_mask) || size <= 0)
359 if (!(irq & hdata->f30.irq_mask))
382 unsigned long irq_mask = 0; local
388 irq_mask |= hdata->f11.irq_mask;
389 irq_mask |= hdata->f30.irq_mask;
391 if (data[1] & ~irq_mask)
393 data[1] & ~irq_mask, __FILE_
[all...]
/drivers/sn/
H A Dioc3.c423 && (pending & ioc3_submodules[id]->irq_mask)
425 write_ireg(idd, ioc3_submodules[id]->irq_mask,
428 idd, pending & ioc3_submodules[id]->irq_mask))
429 pending &= ~ioc3_submodules[id]->irq_mask;
431 write_ireg(idd, ioc3_submodules[id]->irq_mask,
464 write_ireg(idd, irqs & is->irq_mask, IOC3_W_IES);
470 writel(irqs & is->irq_mask, &idd->vma->sio_ir);
476 write_ireg(idd, irqs & is->irq_mask, IOC3_W_IEC);
568 if(is->irq_mask)
569 write_ireg(idd, is->irq_mask, IOC3_W_IE
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