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Searched refs:min_n (Results 1 - 7 of 7) sorted by relevance

/drivers/gpu/drm/nouveau/core/include/subdev/bios/
H A Dpll.h72 u8 min_n; member in struct:nvbios_pll::__anon848
/drivers/gpu/drm/nouveau/core/subdev/bios/
H A Dpll.c262 info->vco1.min_n = 0x5;
265 info->vco1.min_n = 0x1;
278 info->vco2.min_n = 0x4;
301 info->vco1.min_n = nv_ro08(bios, data + 20);
305 info->vco2.min_n = nv_ro08(bios, data + 24);
330 info->vco1.min_n = nv_ro08(bios, data + 16);
334 info->vco2.min_n = nv_ro08(bios, data + 20);
352 info->vco1.min_n = nv_ro08(bios, data + 10);
391 info->vco1.min_n = 0x1;
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dpllnva3.c64 if (N < info->vco1.min_n)
H A Dpllnv04.c44 int minN = info->vco1.min_n, maxN = info->vco1.max_n;
146 int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n;
148 int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n;
H A Dgk20a.c107 u32 min_n, max_n; member in struct:gk20a_clk_pllg_params
115 .min_n = 8, .max_n = 255,
170 best_n = priv->params->min_n;
222 if (n < priv->params->min_n)
/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c267 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
275 pv.N1 = pll_lim.vco1.min_n;
/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c43 int min_m2, max_m2, min_n, max_n; member in struct:pll_min_max
970 n = pll->min_n;

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