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Searched refs:spll (Results 1 - 21 of 21) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c37 struct radeon_pll *spll = &rdev->clock.spll; local
43 fb_div *= spll->reference_freq;
106 struct radeon_pll *spll = &rdev->clock.spll; local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
146 spll->reference_div = mpll->reference_div =
181 struct radeon_pll *spll = &rdev->clock.spll; local
209 if (spll
350 struct radeon_pll *spll = &rdev->clock.spll; local
[all...]
H A Dradeon_combios.c736 struct radeon_pll *spll = &rdev->clock.spll; local
763 spll->reference_freq = RBIOS16(pll_info + 0x1a);
764 spll->reference_div = RBIOS16(pll_info + 0x1c);
765 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
766 spll->pll_out_max = RBIOS32(pll_info + 0x22);
769 spll->pll_in_min = RBIOS32(pll_info + 0x48);
770 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
773 spll->pll_in_min = 40;
774 spll
[all...]
H A Dradeon_atombios.c1123 struct radeon_pll *spll = &rdev->clock.spll; local
1176 spll->reference_freq =
1179 spll->reference_freq =
1181 spll->reference_div = 0;
1183 spll->pll_out_min =
1185 spll->pll_out_max =
1189 if (spll->pll_out_min == 0) {
1191 spll->pll_out_min = 64800;
1193 spll
[all...]
H A Drv740_dpm.c132 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Drv6xx_dpm.c164 u32 ref_clk = rdev->clock.spll.reference_freq;
429 u32 ref_clk = rdev->clock.spll.reference_freq;
552 u32 ref_clk = rdev->clock.spll.reference_freq;
841 u32 ref_clk = rdev->clock.spll.reference_freq;
H A Drv730_dpm.c52 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Dradeon_kms.c322 *value = rdev->clock.spll.reference_freq * 10;
H A Dradeon_uvd.c878 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
H A Drs780_dpm.c990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
H A Dr600.c120 return rdev->clock.spll.reference_freq;
147 if (rdev->clock.spll.reference_freq == 10000)
H A Dci_dpm.c1540 u32 ref_clock = rdev->clock.spll.reference_freq;
2532 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2691 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Drv770.c791 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Drv770_dpm.c499 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Dradeon.h262 struct radeon_pll spll; member in struct:radeon_clock
H A Dni_dpm.c2012 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Dsi.c1279 u32 reference_clock = rdev->clock.spll.reference_freq;
4034 /* powerdown spll */
H A Dcik.c1652 u32 reference_clock = rdev->clock.spll.reference_freq;
H A Dsi_dpm.c4675 u32 reference_clock = rdev->clock.spll.reference_freq;
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dnv40.c36 u32 spll; member in struct:nv40_clock_priv
180 priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
183 priv->spll = 0x00000000;
197 nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
H A Dnv50.c459 /* shader: tie to nvclk if possible, otherwise use spll. have to be
466 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
473 clk_mask(hwsq, spll[0], 0xc03f0100,
475 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
/drivers/clk/samsung/
H A Dclk-exynos5420.c147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator in enum:exynos5x_plls
1236 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,

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