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Searched refs:pclk (Results 1 - 25 of 72) sorted by relevance

123

/drivers/clk/pxa/
H A Dclk-pxa.c34 struct pxa_clk_cken *pclk = to_pxa_clk(hw); local
37 if (!pclk->is_in_low_power || pclk->is_in_low_power())
38 fix = &pclk->lp;
40 fix = &pclk->hp;
51 struct pxa_clk_cken *pclk = to_pxa_clk(hw); local
53 if (!pclk->is_in_low_power)
55 return pclk->is_in_low_power() ? 0 : 1;
75 struct pxa_clk_cken *pclk; local
79 pclk
[all...]
/drivers/clk/
H A Dclk-xgene.c222 struct xgene_clk *pclk = to_xgene_clk(hw); local
226 if (pclk->lock)
227 spin_lock_irqsave(pclk->lock, flags);
229 if (pclk->param.csr_reg != NULL) {
230 pr_debug("%s clock enabled\n", pclk->name);
232 data = xgene_clk_read(pclk->param.csr_reg +
233 pclk->param.reg_clk_offset);
234 data |= pclk->param.reg_clk_mask;
235 xgene_clk_write(data, pclk->param.csr_reg +
236 pclk
262 struct xgene_clk *pclk = to_xgene_clk(hw); local
292 struct xgene_clk *pclk = to_xgene_clk(hw); local
312 struct xgene_clk *pclk = to_xgene_clk(hw); local
334 struct xgene_clk *pclk = to_xgene_clk(hw); local
373 struct xgene_clk *pclk = to_xgene_clk(hw); local
[all...]
H A Dclk-conf.c22 struct clk *clk, *pclk; local
42 pclk = of_clk_get_by_clkspec(&clkspec);
43 if (IS_ERR(pclk)) {
46 return PTR_ERR(pclk);
65 rc = clk_set_parent(clk, pclk);
68 __clk_get_name(clk), __clk_get_name(pclk), rc);
70 clk_put(pclk);
74 clk_put(pclk);
/drivers/video/fbdev/omap2/dss/
H A Dhdmi_common.c52 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) argument
75 if (pclk == 27027000 || pclk == 74250000)
78 if (pclk == 27027000)
85 if (pclk == 27027000)
146 *cts = (pclk/1000) * (*n / 128) * deep_color / (sample_freq / 10);
H A Dhdmi_phy.c153 /* DCOCLK/10 is pixel clock, compare pclk with DCOCLK_MIN/10 */
155 u32 pclk = cfg->timings.pixelclock; local
157 if (pclk < dco_min)
159 else if ((pclk >= dco_min) && (pclk < phy_feat->max_phy))
/drivers/cpufreq/
H A Ds3c2410-cpufreq.c48 unsigned long hclk, fclk, pclk; local
68 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
69 pclk = hclk / pdiv;
71 if (pclk > cfg->max.pclk) {
72 s3c_freq_dbg("%s: pclk too big\n", __func__);
89 .pclk = 50000000,
142 s3c2410_cpufreq_info.max.pclk = 66500000;
H A Dspear-cpufreq.c37 int pclk; local
54 pclk = 0; /* src is sys_syn_clk */
56 pclk = 3; /* src is pll3_clk */
58 pclk = 1; /* src is pll1_clk */
63 sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
65 pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
H A Ds3c2412-cpufreq.c61 cfg->freq.hclk, cfg->freq.pclk);
91 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
93 if ((hclk / pdiv) > cfg->max.pclk)
96 cfg->freq.pclk = hclk / pdiv;
172 .pclk = 50000000,
217 s3c2412_cpufreq_info.max.pclk = 66000000;
/drivers/clk/versatile/
H A Dclk-impd1.c24 struct clk *pclk; member in struct:impd1_clk
91 struct clk *pclk; local
101 imc->pclkname = kasprintf(GFP_KERNEL, "lm%x-pclk", id);
102 pclk = clk_register_fixed_rate(NULL, imc->pclkname, NULL,
104 imc->pclk = pclk;
110 imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id);
120 imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id);
128 imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id);
130 imc->clks[6] = clkdev_alloc(pclk, "apb_pcl
[all...]
/drivers/input/serio/
H A Dat32psif.c97 struct clk *pclk; member in struct:psif
160 retval = clk_enable(psif->pclk);
181 clk_disable(psif->pclk);
187 unsigned long rate = clk_get_rate(psif->pclk);
194 dev_dbg(&psif->pdev->dev, "pclk too fast, "
198 clk_enable(psif->pclk);
200 clk_disable(psif->pclk);
208 struct clk *pclk; local
242 pclk = clk_get(&pdev->dev, "pclk");
[all...]
/drivers/clocksource/
H A Ddw_apb_timer_of.c30 struct clk *pclk; local
41 pclk = of_clk_get_by_name(np, "pclk");
42 if (!IS_ERR(pclk))
43 if (clk_prepare_enable(pclk))
44 pr_warn("pclk for %s is present, but could not be activated\n",
H A Dmoxart_timer.c122 unsigned long pclk; local
141 pclk = clk_get_rate(clk);
144 "moxart_timer", pclk, 200, 32,
148 clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
162 clockevents_config_and_register(&moxart_clockevent, pclk,
H A Dnomadik-mtu.c195 struct clk *pclk, struct clk *clk)
201 BUG_ON(clk_prepare_enable(pclk));
249 struct clk *pclk; local
258 pclk = of_clk_get_by_name(node, "apb_pclk");
259 if (IS_ERR(pclk))
270 nmdk_timer_init(base, irq, pclk, clk);
194 nmdk_timer_init(void __iomem *base, int irq, struct clk *pclk, struct clk *clk) argument
/drivers/iio/adc/
H A Drockchip_saradc.c46 struct clk *pclk; member in struct:rockchip_saradc
175 info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
176 if (IS_ERR(info->pclk)) {
177 dev_err(&pdev->dev, "failed to get pclk\n");
178 return PTR_ERR(info->pclk);
210 ret = clk_prepare_enable(info->pclk);
212 dev_err(&pdev->dev, "failed to enable pclk\n");
242 clk_disable_unprepare(info->pclk);
255 clk_disable_unprepare(info->pclk);
268 clk_disable_unprepare(info->pclk);
[all...]
/drivers/iommu/
H A Dmsm_iommu.h77 * @pclk: The clock for the IOMMU bus interconnect
87 struct clk *pclk; member in struct:msm_iommu_drvdata
H A Dmsm_iommu_dev.c216 drvdata->pclk = iommu_pclk;
257 clk_unprepare(drv->pclk);
258 clk_put(drv->pclk);
289 ret = clk_prepare_enable(drvdata->pclk);
296 clk_disable_unprepare(drvdata->pclk);
328 clk_disable(drvdata->pclk);
/drivers/gpu/drm/tegra/
H A Dhdmi.c21 unsigned int pclk; member in struct:tmds_config
101 unsigned int pclk; member in struct:tegra_hdmi_audio_config
165 .pclk = 27000000,
180 .pclk = UINT_MAX,
198 .pclk = 27000000,
212 .pclk = 74250000,
226 .pclk = UINT_MAX,
244 .pclk = 27000000,
262 .pclk = 74250000,
281 .pclk
401 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) argument
475 tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk) argument
778 unsigned int pulse_start, div82, pclk; local
1059 tegra_output_hdmi_setup_clock(struct tegra_output *output, struct clk *clk, unsigned long pclk, unsigned int *div) argument
1087 unsigned long pclk = mode->clock * 1000; local
[all...]
/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c137 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) argument
158 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
235 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
326 u32 dsi_clock, pclk; local
375 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
377 return pclk;
H A Dintel_dsi_panel_vbt.c274 u32 pclk, computed_ddr; local
300 pclk = mode->clock;
309 (pclk * bits_per_pixel) / intel_dsi->lane_count;
321 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
330 intel_dsi->pclk = pclk;
332 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
/drivers/spi/
H A Dspi-cadence.c105 * @pclk: Pointer to the APB clock
117 struct clk *pclk; member in struct:cdns_spi
493 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
494 if (IS_ERR(xspi->pclk)) {
495 dev_err(&pdev->dev, "pclk clock not found.\n");
496 ret = PTR_ERR(xspi->pclk);
507 ret = clk_prepare_enable(xspi->pclk);
574 clk_disable_unprepare(xspi->pclk);
599 clk_disable_unprepare(xspi->pclk);
[all...]
/drivers/tty/serial/8250/
H A D8250_dw.c63 struct clk *pclk; member in struct:dw8250_data
378 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
383 if (!IS_ERR(data->pclk)) {
384 err = clk_prepare_enable(data->pclk);
439 if (!IS_ERR(data->pclk))
440 clk_disable_unprepare(data->pclk);
460 if (!IS_ERR(data->pclk))
461 clk_disable_unprepare(data->pclk);
500 if (!IS_ERR(data->pclk))
501 clk_disable_unprepare(data->pclk);
[all...]
/drivers/net/ethernet/cadence/
H A Dat91_ether.c338 lp->pclk = devm_clk_get(&pdev->dev, "ether_clk");
339 if (IS_ERR(lp->pclk)) {
340 res = PTR_ERR(lp->pclk);
343 clk_enable(lp->pclk);
409 clk_disable(lp->pclk);
427 clk_disable(lp->pclk);
443 clk_disable(lp->pclk);
454 clk_enable(lp->pclk);
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Dnvd0.c873 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) argument
899 if (pclk >= 165000)
916 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
966 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; local
967 if (pclk)
968 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
982 const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; local
1001 do_div(value, pclk);
1008 do_div(value, pclk);
1016 datarate = (pclk * bit
1037 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; local
1078 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; local
[all...]
/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_kms.c177 if (mdp4_kms->pclk)
178 clk_disable_unprepare(mdp4_kms->pclk);
191 if (mdp4_kms->pclk)
192 clk_prepare_enable(mdp4_kms->pclk);
403 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
404 if (IS_ERR(mdp4_kms->pclk))
405 mdp4_kms->pclk = NULL;
/drivers/input/keyboard/
H A Dnomadik-ske-keypad.c70 struct clk *pclk; member in struct:ske_keypad
276 keypad->pclk = clk_get(&pdev->dev, "apb_pclk");
277 if (IS_ERR(keypad->pclk)) {
278 dev_err(&pdev->dev, "failed to get pclk\n");
279 error = PTR_ERR(keypad->pclk);
306 error = clk_prepare_enable(keypad->pclk);
308 dev_err(&pdev->dev, "Failed to prepare/enable pclk\n");
355 clk_disable_unprepare(keypad->pclk);
359 clk_put(keypad->pclk);

Completed in 372 milliseconds

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