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Searched refs:pll_prediv (Results 1 - 10 of 10) sorted by relevance

/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c225 .pll_prediv = 1,
391 .pll_prediv = 1,
661 .pll_prediv = 1,
953 .pll_prediv = 1,
1179 .pll_prediv = 1,
1518 .pll_prediv = 1,
1609 .io.pll_prediv = 1,
1939 .pll_prediv = 1,
1986 .io.pll_prediv = 3,
2017 u32 pll_prediv; /* Ne member in struct:dibx090p_adc
2023 u32 pll_prediv; member in struct:dibx090p_best_adc
[all...]
H A Ddib0700_core.c366 u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv,
380 st->buf[2] = (pll_prediv >> 8) & 0xff; /* MSB */
381 st->buf[3] = pll_prediv & 0xff; /* LSB */
365 dib0700_set_clock(struct dvb_usb_device *d, u8 en_pll, u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv, u16 pll_loopdiv, u16 free_div, u16 dsuScaler) argument
H A Dcxusb.c1145 .pll_prediv = 1,
/drivers/media/dvb-frontends/
H A Ddib0090.h23 u8 pll_prediv:6; member in struct:dib0090_io_config
H A Ddibx000_common.h120 u8 pll_prediv; member in struct:dibx000_bandwidth_config
H A Ddib8000.c696 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
727 (pll->pll_prediv));
746 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
753 if ((pll == NULL) || (pll->pll_prediv == prediv &&
757 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
766 (pll->pll_prediv & 0x3f));
772 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
792 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
794 if (state->cfg.pll->pll_prediv != oldprediv) {
798 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, stat
[all...]
H A Ddib7000p.c449 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
463 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
496 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
497 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
502 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
507 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
H A Ddib0090.c549 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
561 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
621 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
632 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
H A Ddib7000m.c411 reg_910 |= (bw->pll_prediv << 5);
427 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
/drivers/media/pci/cx23885/
H A Dcx23885-dvb.c903 .pll_prediv = 1,

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