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Searched refs:read_pll (Results 1 - 5 of 5) sorted by relevance

/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dnvc0.c59 read_pll(struct nvc0_clock_priv *priv, u32 pll) function
132 sclk = read_pll(priv, 0x137000 + (clk * 0x20));
134 sclk = read_pll(priv, 0x1370e0);
159 return read_pll(priv, 0x00e800);
161 return read_pll(priv, 0x00e820);
166 return read_pll(priv, 0x132020);
168 return read_pll(priv, 0x132000);
H A Dnv50.c154 read_pll(struct nv50_clock_priv *priv, u32 base) function
219 case 0x00000002: return read_pll(priv, 0x004020) >> P;
220 case 0x00000003: return read_pll(priv, 0x004028) >> P;
231 case 0x00000020: return read_pll(priv, 0x004028) >> P;
232 case 0x00000030: return read_pll(priv, 0x004020) >> P;
246 return read_pll(priv, 0x004008) >> P;
267 return read_pll(priv, 0x004028) >> P;
268 return read_pll(priv, 0x004030) >> P;
291 return read_pll(priv, 0x00e810) >> 2;
395 out = read_pll(pri
[all...]
H A Dnve0.c47 static u32 read_pll(struct nve0_clock_priv *, u32);
54 return read_pll(priv, 0x00e800);
55 return read_pll(priv, 0x00e820);
59 read_pll(struct nve0_clock_priv *priv, u32 pll) function
79 sclk = read_pll(priv, 0x132020);
133 case 1: return read_pll(priv, 0x132020);
134 case 2: return read_pll(priv, 0x132000);
149 sclk = read_pll(priv, 0x137000 + (clk * 0x20));
161 sclk = read_pll(priv, 0x1370e0);
H A Dnva3.c41 static u32 read_pll(struct nva3_clock_priv *, int, u32);
52 return read_pll(priv, 0x41, 0x00e820);
54 return read_pll(priv, 0x42, 0x00e8a0);
107 read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) function
147 return read_pll(priv, 0x00, 0x4200);
149 return read_pll(priv, 0x01, 0x4220);
151 return read_pll(priv, 0x02, 0x4000);
H A Dnvaa.c50 read_pll(struct nouveau_clock *clk, u32 base) function
111 case 0x00000003: return read_pll(clk, 0x004028) >> P;
135 case 0x00000020: return read_pll(clk, 0x004028) >> P;
136 case 0x00000030: return read_pll(clk, 0x004020) >> P;

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