STAC Report: New STAC-T0 results with an Exegy/AMD FPGA solution

Exegy and AMD demonstrate 40-49% lower maximum latency at all ingress rates than previous record.

25 June 2024

AMD asked STAC to test the performance of the AMD Alveo™ UL3524 FPGA Accelerator, its new fintech accelerator specifically designed for ultra-low latency electronic trading applications, using STAC-T0 benchmarks.

The stack consisted of the Exegy nxFramework and Exegy IP Core nxTCP-UDP-10g-ULL on an AMD Alveo™ UL3524 FPGA Accelerator in a Dell PowerEdge R7525 server with AMD EPYC™ 7313 processors.

STAC-T0 evaluates the tick-to-trade network-I/O latency of any trading platform extremely accurately, whether the platform involves CPUs and software, FPGAs, or other hardware. The key metric in STAC-T0 is Actionable Latency, which is the time from the last bit of inbound data needed to make a trading decision to the first bit of the simulated outbound order.

AMD and Exegy chose to highlight the following about Actionable Latency:

• For 507-byte frames at all ingress rates
• Minimum of 13.9 nanoseconds (STAC-T0.β1.*.A.ACTIONABLE.MIN)
• Minimum latency was lower than the previous record (SUT ID XLX200514) by 50% and maxes lower by 40-42% (STAC-T0.β1.*.A.ACTIONABLE.MAX)
• For 68-byte frames at all ingress rates
• Minimum of 14.1 nanoseconds (STAC-T0.β1.*.B.ACTIONABLE.MIN)
• Minimum latency was lower than the previous record (SUT ID XLX200514) by 42% and maxes lower by 43-49% (STAC-T0.β1.*.B.ACTIONABLE.MAX)

For details, please see the report at the link above. Premium subscribers have access to the code used in this project as well as the micro-detailed configuration information for the solution. To learn about subscription options, please contact us.