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IP-XACT, also known as IEEE 1685,^[1] is an XML format that defines and describes individual, re-usable electronic circuit designs (individual pieces of intellectual property, or IPs) to facilitate their use in creating integrated circuits (i.e. microchips). IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through tools^[2] and evolving into an IEEE standard.

The goals of the standard are

to ensure delivery of compatible component descriptions, such as IPs, from multiple component vendors,
to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),
to describe configurable components using metadata, and
to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators).

Approved as IEEE 1685-2009 on December 9, 2009, published on February 18, 2010.^[3] Superseded by IEEE 1685-2014. IEEE 1685-2009 was adopted as IEC 62014-4:2015. In June 2023, the supplemental material for standard IEEE 1685-2022 IP-XACT was approved by Accellera.^[4]

Overview[edit]

Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.

All documents will have the following basic titular attributes spirit:vendor, spirit:library, spirit:name, spirit:version.

A document typically represents one of:

bus specification, giving its signals and protocol etc.;
leaf IP block data sheet;
or a hierarchic component wiring diagram that describes a sub-system by connecting up or abstracting other components made up of spirit:componentInstance and spirit:interconnection elements.

For each port of a component there will be a spirit:busInterface element in the document. This may have a spirit:signalMap that gives the mapping of the formal net names in the interface to the names used in a corresponding formal specification of the port. A simple wiring tool will use the signal map to know which net on one interface to connect to which net on another instance of the same formal port on another component.

There may be various versions of a component referenced in the document, each as a spirit:view element, relating to different versions of a design: typical levels are gate-level, RTL and TLM. Each view typically contains a list of filenames as a spirit:fileSet that implement the design at that level of abstraction in appropriate language, like Verilog, C++ or PSL.

Non-functional data present includes the programmer's view with a list of spirit:register declarations inside a spirit:memoryMap or spirit:addressBlock.

Supporting companies and software[edit]

Arteris ^[5]- Magillem Connectivity,^[6] Magillem Registers,^[7] CSRCompiler^[8] and FlexNoC5^[9]
Cadence - JasperGold ^[10] and Interconnect Workbench (IWB) ^[11]
Synopsys, Inc ^[12]
Agnisys ^[13]
Defacto Technologies ^[14]
EDAUtils ^[15]
Magillem (now part of Arteris) ^[16]
Semifore (now part of Arteris) ^[17]
Xilinx (now part of AMD)
Lattice

References[edit]

^ "IEEE Standards Association". IEEE Standards Association. Retrieved 2023-10-27.
^ IP-XACT Working Group
^ IEEE 1685-2009, ISBN 978-0-7381-6160-0
^ "IP-XACT". www.accellera.org. Retrieved 2023-10-27.
^ "Arteris". Retrieved 2023-10-27.
^ "Magillem Connectivity – Arteris". Retrieved 2023-10-27.
^ "Magillem Registers – Arteris". Retrieved 2023-10-27.
^ "CSRCompiler – Arteris". Retrieved 2023-10-27.
^ "FlexNoC 5 Interconnect IP – Arteris". Retrieved 2023-10-27.
^ Cadence's JasperGold Control and Status Register App
^ Cadence Interconnect Workbench
^ Synopsys, Inc
^ Agnisys IDesignSpec
^ Defacto SoC Compiler
^ EDAUtils
^ Magillem Design Services
^ Semifore, Inc

1685-2022 - IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2023. doi:10.1109/IEEESTD.2023.10054520. ISBN 978-1-5044-9448-9.
1685-2014 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2014. doi:10.1109/IEEESTD.2014.6898803. ISBN 978-0-7381-9226-0.
1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows. 2010. doi:10.1109/IEEESTD.2010.5417309. ISBN 978-0-7381-6160-0.
- IEEE/IEC International Standard - IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2015. doi:10.1109/IEEESTD.2015.7066223. ISBN 978-2-8322-2265-2.

External links[edit]

IEEE 1685-2022
IP-XACT at Accellera
- XML Schema at Accellera
- BusDefs at Accellera

[1] "IEEE Standards Association". IEEE Standards Association. Retrieved 2023-10-27.

[2] IP-XACT Working Group

[3] IEEE 1685-2009, ISBN 978-0-7381-6160-0

[4] "IP-XACT". www.accellera.org. Retrieved 2023-10-27.

[5] "Arteris". Retrieved 2023-10-27.

[6] "Magillem Connectivity – Arteris". Retrieved 2023-10-27.

[7] "Magillem Registers – Arteris". Retrieved 2023-10-27.

[8] "CSRCompiler – Arteris". Retrieved 2023-10-27.

[9] "FlexNoC 5 Interconnect IP – Arteris". Retrieved 2023-10-27.

[10] Cadence's JasperGold Control and Status Register App

[11] Cadence Interconnect Workbench

[12] Synopsys, Inc

[13] Agnisys IDesignSpec

[14] Defacto SoC Compiler

[15] EDAUtils

[16] Magillem Design Services

[17] Semifore, Inc

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@@ Line 1: / Line 1: @@
+{{Short description|XML-based standard covering electronic components}}
-'''IP-XACT''' is an [[XML]] format that defines and describes [[electronic components]] and their [[Circuit design|designs]]. IP-XACT was created by the [[SPIRIT Consortium]] as a standard to enable automated configuration and integration through tools.<ref>[http://accellera.org/activities/working-groups/ip-xact/ IP-XACT Working Group]</ref>
+{{more footnotes|date=January 2019}}
+'''IP-XACT''', also known as IEEE 1685,<ref>{{Cite web |title=IEEE Standards Association |url=https://standards.ieee.org/ |access-date=2023-10-27 |website=IEEE Standards Association |language=en}}</ref> is an [[XML]] format that defines and describes individual, re-usable [[circuit design|electronic circuit design]]s (individual pieces of intellectual property, or IPs) to facilitate their use in creating [[integrated circuits]] (i.e. ''microchips''). IP-XACT was created by the [[SPIRIT Consortium]] as a standard to enable automated configuration and integration through tools<ref>[http://accellera.org/activities/working-groups/ip-xact/ IP-XACT Working Group]</ref> and evolving into an IEEE standard.
 The goals of the standard are
-* to ensure delivery of compatible component descriptions from multiple component vendors,
+* to ensure delivery of compatible component descriptions, such as IPs, from multiple component vendors,
 * to enable exchanging complex component libraries between [[electronic design automation]] (EDA) tools for [[System-on-a-chip|SoC]] design (design environments),
 * to describe configurable components using [[metadata]], and
 * to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators).
-Approved as [[IEEE]] 1685-2009 on December 9, 2009, published on February 18, 2010.<ref>IEEE 1685-2009, ISBN 978-0-7381-6160-0</ref>
+Approved as [[IEEE]] 1685-2009 on December 9, 2009, published on February 18, 2010.<ref>IEEE 1685-2009, {{ISBN|978-0-7381-6160-0}}</ref>
-Superseded by [[IEEE]] 1685-2014. IEEE 1685-2009 was adopted as IEC 62014-4:2015.
+Superseded by [[IEEE]] 1685-2014. IEEE 1685-2009 was adopted as IEC 62014-4:2015.  In June 2023, the supplemental material for standard IEEE 1685-2022 IP-XACT was approved by Accellera.<ref>{{Cite web |title=IP-XACT |url=https://www.accellera.org/activities/working-groups/ip-xact |access-date=2023-10-27 |website=www.accellera.org}}</ref>
-== Tools ==
+== Overview ==
-* [http://www.arm.com/products/system-ip/index.php ARM Socrates System IP Tooling]
+Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.
-* [http://www.magillem.com/eda/ Magillem, Industrial IP-XACT Solution for a complete RTL and ESL front end capture]
-* [http://scineric.csir.co.za/ Scineric Workspace IP-XACT based IDE]
+All documents will have the following basic titular attributes spirit:vendor, spirit:library, spirit:name, spirit:version.
-* [http://sourceforge.net/projects/kactus2/ Kactus2 open source IP-XACT design environment]
-* [http://www.edautils.com/ip-xact.html Free IP-XACT 1685 platform available in GUI and command line for Component packaging, Register and Memory specification, C and UVM Model generators, import and export into XLS, translators like verilog2ipxact, ipxact2verilog, vhdl2ipxact, ipxact2vhdl ... ] & [http://www.edautils.com/Baya.html Baya- SoC Platform Assembly Tool]
+A document typically represents one of:
-* [http://www.atrenta.com/products/gensys-assembly.htm5 Atrenta gensys assembly]
+* bus specification, giving its signals and protocol etc.;
-* [[Xilinx]]'s Vivado tool supports IP-XACT component by way of a Xilinx Core Instance (XCI) files.  The XCI file represents an IP-XACT component XML file that records the values of project options, customization parameters, and port parameters used to create the IP. Most of the IP in the Vivado IP catalog uses the IP-XACT standard format (based on IEEE Std 1685-2009).
+* leaf IP block data sheet;
+* or a hierarchic component wiring diagram that describes a sub-system by connecting up or abstracting other components made up of spirit:componentInstance and spirit:interconnection elements.
+For each port of a component there will be a spirit:busInterface element in the document.  This may have a spirit:signalMap
+that gives the mapping of the formal net names in the interface to the names used in a corresponding formal specification of the port.
+A simple wiring tool will use the signal map to know which net on one interface to connect to which net on another instance
+of the same formal port on another component.
+There may be various versions of a component referenced in the document, each as a spirit:view element, relating to different versions of a design: typical levels are gate-level, RTL and TLM.
+Each view typically contains a list of filenames as a spirit:fileSet that implement the design at that level of abstraction in appropriate language, like Verilog,
+C++ or PSL.
+Non-functional data present includes the programmer's view with a list of spirit:register declarations inside a spirit:memoryMap or spirit:addressBlock.
+== Supporting companies and software ==
+*Arteris <ref>{{Cite web |title=Arteris |url=https://www.arteris.com/ |access-date=2023-10-27 |language=en-US}}</ref>- Magillem Connectivity,<ref>{{Cite web |title=Magillem Connectivity – Arteris |url=https://www.arteris.com/products/soc-connectivity/magillem-connectivity/ |access-date=2023-10-27 |language=en-US}}</ref> Magillem Registers,<ref>{{Cite web |title=Magillem Registers – Arteris |url=https://www.arteris.com/products/hardware-software-interface/magillem-registers/ |access-date=2023-10-27 |language=en-US}}</ref> CSRCompiler<ref>{{Cite web |title=CSRCompiler – Arteris |url=https://www.arteris.com/products/hardware-software-interface/csrcompiler/ |access-date=2023-10-27 |language=en-US}}</ref> and FlexNoC5<ref>{{Cite web |title=FlexNoC 5 Interconnect IP – Arteris |url=https://www.arteris.com/products/non-coherent-noc-ip/flexnoc/ |access-date=2023-10-27 |language=en-US}}</ref>
+*Cadence - JasperGold <ref>[https://www.cadence.com/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/jaspergold-control-and-status-register-app.html Cadence's JasperGold Control and Status Register App]</ref> and Interconnect Workbench (IWB) <ref>[https://community.arm.com/developer/ip-products/system/b/soc-design-blog/posts/the-future-of-tooling-from-ip-configuration-to-soc-verification Cadence Interconnect Workbench]</ref>
+*Synopsys, Inc <ref>[https://www.synopsys.com/designware-ip/ip-reuse-tool.html Synopsys, Inc]</ref>
+*Agnisys <ref>[https://www.agnisys.com/products/idesignspec-uvm-register-generator/ Agnisys  IDesignSpec]</ref>
+*Defacto Technologies <ref>[https://www.defactotech.com/products-solutions/soc-integration-at-rtl/ Defacto SoC Compiler]</ref>
+*EDAUtils <ref>[http://www.edautils.com/ip-xact.html EDAUtils]</ref>
+*Magillem (now part of Arteris) <ref>[http://www.magillem.com/ip-xact-ieee-1685/ Magillem Design Services]</ref>
+*Semifore (now part of Arteris) <ref>[http://www.semifore.com/standards-support/ Semifore, Inc]</ref>
+*Xilinx (now part of AMD)
+*Lattice
 == See also ==
@@ Line 25: / Line 52: @@
 {{Reflist}}
 {{refbegin}}
+*{{Cite book | doi = 10.1109/IEEESTD.2023.10054520| title = 1685-2022 - IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows| year = 2023| isbn = 978-1-5044-9448-9}}
-*{{cite doi|10.1109/IEEESTD.2014.6898803}}
+*{{Cite book | doi = 10.1109/IEEESTD.2014.6898803| title = 1685-2014 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows| year = 2014| isbn = 978-0-7381-9226-0}}
-*{{cite doi|10.1109/IEEESTD.2010.5417309}}
+*{{Cite book| title = 1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows| doi = 10.1109/IEEESTD.2010.5417309| year = 2010| isbn = 978-0-7381-6160-0}}
-**{{cite doi|10.1109/IEEESTD.2015.7066223}}
+**{{Cite book | doi = 10.1109/IEEESTD.2015.7066223| year = 2015| isbn = 978-2-8322-2265-2| title = IEEE/IEC International Standard - IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows}}
 {{refend}}
 == Further reading==
 * [http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform]
+* {{Cite journal | doi = 10.1109/MDT.2006.104| title = Standards: The P1685 IP-XACT IP Metadata Standard| journal = IEEE Design & Test of Computers| volume = 23| issue = 4| pages = 316–317| date = April 2006| last1 = Berman | first1 = V.| s2cid = 206459094}}
-* {{cite doi|10.1109/MDT.2006.104}}
+* {{Cite conference | doi = 10.1145/1403375.1403386| title = Industrial IP integration flows based on IP-XACT™ standards| work = Proceedings of the conference on Design, automation and test in Europe| conference = [[Design Automation and Test in Europe|DATE]]'08| pages = 32–37| year = 2008| last1 = Kruijtzer | first1 = W. | last2 = Vaumorin | first2 = E. | last3 = Van Der Wolf | first3 = P. | last4 = De Kock | first4 = E. | last5 = Stuyt | first5 = J. | last6 = Ecker | first6 = W. | last7 = Mayer | first7 = A. | last8 = Hustin | first8 = S. | last9 = Amerijckx | first9 = C. | last10 = De Paoli | first10 = S. | isbn = 978-3-9810801-3-1| citeseerx = 10.1.1.455.8801 }}
-* {{cite doi|10.1145/1403375.1403386}}
 == External links ==
+* [https://standards.ieee.org/ieee/1685/10583/ IEEE 1685-2022]
 * [http://www.accellera.org/downloads/standards/ip-xact IP-XACT] at [[Accellera]]
 ** [http://www.accellera.org/XMLSchema/ XML Schema] at [[Accellera]]
 ** [http://www.accellera.org/busdefs BusDefs] at [[Accellera]]
+{{List of International Electrotechnical Commission standards}}
-* [http://standards.ieee.org/getieee/1685/download/1685-2014.pdf IEEE 1685-2014] - free download of the standard.
 {{IEEE standards}}
 {{DEFAULTSORT:Ip-Xact}}
 [[Category:Electronic engineering]]
 [[Category:IEEE DASC standards]]
-[[Category:IEC standards|#62014-4]]
+[[Category:IEC standards]]

v t e IEC standards
IEC	60027 60034 60038 60062 60063 60068 60112 60228 60269 60297 60309 60320 60364 60446 60559 60601 60870 60870-5 60870-6 60906-1 60908 60929 60958 61030 61131 61131-3 61131-9 61158 61162 61334 61355 61360 61400 61499 61508 61511 61784 61850 61851 61883 61960 61968 61970 62014-4 62026 62056 62061 62196 62262 62264 62304 62325 62351 62365 62366 62379 62386 62455 62680 62682 62700 63110 63119 63382
ISO/IEC	646 1989 2022 4909 5218 6429 6523 7810 7811 7812 7813 7816 7942 8613 8632 8652 8859 9126 9293 9496 9529 9592 9593 9899 9945 9995 10021 10116 10165 10179 10279 10646 10967 11172 11179 11404 11544 11801 12207 13250 13346 13522-5 13568 13816 13818 14443 14496 14651 14882 15288 15291 15408 15444 15445 15504 15511 15693 15897 15938 16262 16485 17024 17025 18004 18014 18181 19752 19757 19770 19788 20000 20802 21000 21827 22275 22537 23000 23003 23008 23270 23360 24707 24727 24744 24752 26300 27000 27000-series 27002 27040 29110 29119 33001 38500 39075 42010 80000 81346
Related	International Electrotechnical Commission