Programmed input–output: Difference between revisions
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'''Programmed input/output''' ('''PIO''') is a method of transferring data between the [[Central processing unit|CPU]] and a peripheral, such as a network adapter or an [[AT Attachment|ATA]] storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in [[Direct Memory Access]] (DMA) operations, the CPU is not involved in the data transfer. |
<span lang="hi">'''Programmed input/output''' ('''PIO''') is a method of transferring data between the [[Central processing unit|CPU]] and a peripheral, such as a network adapter or an [[AT Attachment|ATA]] storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in [[Direct Memory Access]] (DMA) operations, the CPU is not involved in the data transfer.</span> |
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The term ''Programmed I/O'' can refer to either [[Memory-mapped I/O|Memory-mapped I/O (MMIO) or Port-mapped I/O (PMIO)]]. PMIO refers to transfers using a special [[address space]] outside of normal memory, usually accessed with dedicated instructions, such as IN and OUT in [[x86]] architectures. MMIO<ref>Computer Organization and Architecture 9th Edition. Stallings, William. Pearson, 2012</ref> refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices. |
<span lang="hi">The term ''Programmed I/O'' can refer to either [[Memory-mapped I/O|Memory-mapped I/O (MMIO) or Port-mapped I/O (PMIO)]]. PMIO refers to transfers using a special [[address space]] outside of normal memory, usually accessed with dedicated instructions, such as IN and OUT in [[x86]] architectures. MMIO<ref>Computer Organization and Architecture 9th Edition. Stallings, William. Pearson, 2012</ref> refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.</span> |
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The best known example of a PC device that uses programmed I/O is the [[AT Attachment|ATA]] interface; however, this interface can also be operated in any of several [[Direct Memory Access|DMA]] modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, the PS/2 keyboard and mouse ports, legacy MIDI and joystick ports, the interval timer, and older network interfaces. |
<span lang="hi">The best known example of a PC device that uses programmed I/O is the [[AT Attachment|ATA]] interface; however, this interface can also be operated in any of several [[Direct Memory Access|DMA]] modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, the PS/2 keyboard and mouse ports, legacy MIDI and joystick ports, the interval timer, and older network interfaces.</span> |
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== PIO mode in the ATA interface |
==<span lang="hi">PIO mode in the ATA interface</span>== |
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The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance. |
<span lang="hi">The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.</span> |
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The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the [[Direct memory access|DMA]] (and eventually [[UDMA]]) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with [[Field-programmable gate array|FPGA]] chips where PIO mode can be used without significant performance loss. |
<span lang="hi">The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the [[Direct memory access|DMA]] (and eventually [[UDMA]]) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with [[Field-programmable gate array|FPGA]] chips where PIO mode can be used without significant performance loss.</span> |
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Two additional Advanced Timing modes have been defined in the [[CompactFlash]] specification 2.0. Those are PIO mode 5 and PIO mode 6. They are specific to CompactFlash. |
<span lang="hi">Two additional Advanced Timing modes have been defined in the [[CompactFlash]] specification 2.0. Those are PIO mode 5 and PIO mode 6. They are specific to CompactFlash.</span> |
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Revision as of 20:40, 17 December 2018
 | This article needs additional citations for verification. (June 2013) |
Programmed input/output (PIO) is a method of transferring data between the CPU and a peripheral, such as a network adapter or an ATA storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in Direct Memory Access (DMA) operations, the CPU is not involved in the data transfer.
The term Programmed I/O can refer to either Memory-mapped I/O (MMIO) or Port-mapped I/O (PMIO). PMIO refers to transfers using a special address space outside of normal memory, usually accessed with dedicated instructions, such as IN and OUT in x86 architectures. MMIO[1] refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.
The best known example of a PC device that uses programmed I/O is the ATA interface; however, this interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, the PS/2 keyboard and mouse ports, legacy MIDI and joystick ports, the interval timer, and older network interfaces.
PIO mode in the ATA interface
The PIO interface is grouped into different modes that correspond to different transfer rates. The electrical signaling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually UDMA) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are not required like in embedded systems, or with FPGA chips where PIO mode can be used without significant performance loss.
Two additional Advanced Timing modes have been defined in the CompactFlash specification 2.0. Those are PIO mode 5 and PIO mode 6. They are specific to CompactFlash.
| Mode | Maximum transfer rate (MB/s) | Minimum cycle time | Standard where spec is defined |
|---|---|---|---|
| Mode 0 | 3.3 | 600 ns | ATA-1 |
| Mode 1 | 5.2 | 383 ns | ATA-1 |
| Mode 2 | 8.3 | 240 ns | ATA-1 |
| Mode 3 | 11.1 | 180 ns | ATA-2 |
| Mode 4 | 16.7 | 120 ns | ATA-2 |
| Mode 5 | 20 | 100 ns | CompactFlash 2.0 |
| Mode 6 | 25 | 80 ns | CompactFlash 2.0 |
PIO Mode 5
A PIO Mode 5 was proposed[2] with operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and the DMA standard ultimately obviated it. While no hard drives were ever manufactured to support this mode, some motherboard manufacturers preemptively provided BIOS support for it. PIO Mode 5 can be used with CompactFlash cards connected to IDE via CF-to-IDE adapters.
See also
- WDMA - Single/Multiword DMA
- ATA - ATA specification
- Input/output
- Interrupt
- List of device bandwidths
- CompactFlash
References
- ^ Computer Organization and Architecture 9th Edition. Stallings, William. Pearson, 2012
- ^ Proposed 22 MByte/Sec ATA Timing Extension For ATA-3, January 1995, ATA-3 Extension Proposal[permanent dead link]