Programmed input–output: Difference between revisions
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The '''programmed input/output''' ('''PIO''') interface was the original method used to transfer data between the [[Central processing unit|CPU]] (through the [[Advanced Technology Attachment|ATA]] [[controller (computing)|controller]]) and an [[Advanced Technology Attachment|ATA]] device. The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar -- only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode -- Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance. |
The '''programmed input/output''' ('''PIO''') interface was the original method used to transfer data between the [[Central processing unit|CPU]] (through the [[Advanced Technology Attachment|ATA]] [[controller (computing)|controller]]) and an [[Advanced Technology Attachment|ATA]] device. The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar -- only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode -- Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance. |
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Revision as of 16:18, 10 December 2006
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The programmed input/output (PIO) interface was the original method used to transfer data between the CPU (through the ATA controller) and an ATA device. The PIO interface is grouped into different modes that correspond to different transfer rates. The electrical signaling among the different modes is similar -- only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode -- Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.
The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually UDMA) interface was created to increase performance. The simple digital logic required to implement a PIO transfer still makes this transfer method useful today (especially if high transfer rates are not required).
The modes are given below:
| Mode | Maximum Transfer Rate (MB/s) | Standard Where Spec Was Defined |
|---|---|---|
| Mode 0 | 3.3 | ATA-1 |
| Mode 1 | 5.2 | ATA-1 |
| Mode 2 | 8.3 | ATA-1 |
| Mode 3 | 11.1 | ATA-2 |
| Mode 4 | 16.7 | ATA-2 |
It may be worthwhile to mention that there was talk about a PIO 5 which would have operated at 22 MB/s, but it was never implemented in light of the DMA standard and that CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings. While no hard drives were ever manufactured to support this mode, some motherboard manufacturers preemptively provided BIOS support for it.
See also
- WDMA - Single/Multiword DMA
- ATA - ATA specification
- Input/output
- Interrupt