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{{New unreviewed article|source=ArticleWizard|date=August 2010}}


'''STD Bus''' is a computer bus popular with industrial control applications but has also been used in computing applications. The STD Bus has been called "STD-80" as well, this has head a popular confusion that the bus contains 80 pins, however its in reference to its bus being related to the [[Zilog_Z80]] series processors in practical use.
'''STD Bus''' is a computer bus popular with industrial control applications but has also been used in computing applications. The STD Bus has been called "STD-80" as well, this has head a popular confusion that the bus contains 80 pins, however its in reference to its bus being related to the [[Zilog Z80]] series processors in practical use.


== STD Bus Configuration ==
== STD Bus Configuration ==

Revision as of 00:01, 21 August 2010

Template:New unreviewed article

STD Bus is a computer bus popular with industrial control applications but has also been used in computing applications. The STD Bus has been called "STD-80" as well, this has head a popular confusion that the bus contains 80 pins, however its in reference to its bus being related to the Zilog Z80 series processors in practical use.

STD Bus Configuration

The STD Bus pin configuration is as follows (Flow is relative using a STD Bus Processor Card)[1].

Pin Mnemonic Signal Flow Description Pin Mnemonic Signal Flow Description
1 +5V In Logic Power 2 +5V In Logic Power
3 GND In Logic Ground 4 GND In Logic Ground
5 -5V In Negative Logic Power 6 -5V In Negative Logic Power
7 D3 In/Out Data Bus 8 D7(A23) In/Out Data Bus
9 D2 In/Out Data Bus 10 D6(A22) In/Out Data Bus
11 D1 In/Out Data Bus 12 D5(A21) In/Out Data Bus
13 D0 In/Out Data Bus 14 D7(A20) In/Out Data Bus
15 A7 Out Address Bus 16 A15 Out Address Bus
17 A6 Out Address Bus 18 A14 Out Address Bus
19 A5 Out Address Bus 20 A13 Out Address Bus
21 A4 Out Address Bus 22 A12 Out Address Bus
23 A3 Out Address Bus 24 A11 Out Address Bus
25 A2 Out Address Bus 26 A10 Out Address Bus
27 A1 Out Address Bus 28 A9 Out Address Bus
29 A0 Out Address Bus 30 A8 Out Address Bus
31 WR Out Write to Memory or I/O 32 RD Out Read to Memory or I/O
33 IORQ Out I/O Address Select 34 MEMRQ Out Memory Address Select
35 IOEX Out I/O Expansion 36 MEMEX Out Memory Expansion
37 REFRESH Out Refresh Timing 38 MCSYNC Out CPU Machine Cycle Sync
39 STATUS 1 Out CPU Status 40 STATUS 0 Out CPU Status
41 BUSAK Out Bus Acknowledge 42 BUSRQ In Bus Request
43 INTAK Out Interrupt Acknowledge 44 INTRQ In Interrupt Request
45 WAITRQ In Wait Request 46 NMIRQ In Non-Maskable Interrupt
47 SYSRESET Out System Reset 48 PBRESET In Push Button Reset
49 CLK Out Clock from Processor 50 CNTRL In Aux Timing
51 PCO Out Priority Chain Out 52 PCI In Priority Chain In
53 AUX GND In AUX Ground 54 AUX GND In AUX Ground
55 AUX +12V In AUX Positive 56 AUX -12V In AUX Negative

STD-32

The STD-32 is a pin compatible STD interface that allows the co-existence of both 8-bit and 32-bit systems on a single bus. This is accomplished by the addition of pins between the normal pins that do not connect, nor do they interfere with the original specification. This allows with the proper STD-32 backplane the ability to run legacy cards used for specific applications on the same bus without having to upgrade the complete system.

References

  1. ^ Prolog 7801 8085A Processor Card Specifications September 1981